TWI835564B - Semiconductor structure and method of forming the same - Google Patents

Abstract

The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate including active regions arranged in an array, an isolation structure extending from a surface of the substrate into the substrate to define the active regions, and word line structures buried in the substrate, extending through the active regions in a first direction, and arranged in a second direction different from the first direction. Each of the word line structures include a body portion and extension portions extending from opposite sidewalls of the body portion into the isolation structure between two adjacent active regions.

Description

Semiconductor structures and methods of forming them

The present invention relates to a semiconductor structure and a method of forming the same, and in particular, to a semiconductor structure for a memory element and a method of forming the same.

Memory can be divided into non-volatile memory and volatile memory. Dynamic random access memory (DRAM) is a type of volatile memory commonly found in electronic devices. memory. Generally speaking, DRAM is composed of a large number of memory cells, and each memory cell can include a capacitor and a transistor (1T1C), where the word line (word line) is connected to The gate of the transistor; the bit line is connected to the source of the transistor; and the capacitor is connected to the drain of the transistor.

As the size of electronic devices continues to shrink and users' requirements for the performance of electronic devices continue to increase, those skilled in the art continue to improve the performance of memory components while taking the component size into consideration.

The present invention provides a semiconductor structure and a method for forming the same. Each of the plurality of word line structures includes a main body and a plurality of extension parts, and the plurality of extension parts extend from opposite side walls of the main body part to two adjacent adjacent ones. In the isolation structure between two active areas, this can increase the area covered by the word line structure in the active area, thereby improving the gate's ability to control the channel, so that the semiconductor structure has a good subthreshold swing.

An embodiment of the present invention provides a semiconductor structure, which includes a substrate, an isolation structure and a plurality of word line structures. The substrate includes a plurality of active areas arranged in an array. The isolation structure extends from the surface of the substrate into the substrate to define a plurality of active regions. A plurality of word line structures are embedded in the substrate, extend through a plurality of active areas in a first direction, and are arranged in a second direction different from the first direction. Each of the plurality of word line structures includes a main body and a plurality of extension portions, wherein the plurality of extension portions extend from opposite side walls of the main body into an isolation structure between two adjacent active regions.

In some embodiments, the plurality of extensions are aligned in the first direction.

In some embodiments, each of the plurality of active regions includes a long side extending in a third direction, the third direction is inclined to the first direction and the second direction, and the word line structures have different widths in the third direction. .

In some embodiments, the plurality of extensions cover portions of the plurality of active regions.

In some embodiments, the substrate includes a plurality of word line trenches with a plurality of word line structures disposed therein, and the plurality of word line trenches includes a plurality of recesses with a plurality of extensions disposed therein.

An embodiment of the present invention provides a method for forming a semiconductor structure, which includes: forming an isolation structure defining a plurality of active regions in a substrate, wherein the plurality of active regions are arranged in an array in the substrate; forming a plurality of word line trenches in the substrate , wherein the plurality of word line trenches extend through the plurality of active regions in a first direction and are arranged in a second direction different from the first direction; removing a portion of the isolation structure exposed by the plurality of word line trenches, to form a plurality of recesses; and to form a plurality of word line structures in a plurality of word line trenches, wherein each of the plurality of word line structures includes a main body portion and a plurality of extension portions formed in the plurality of recesses. .

In some embodiments, the plurality of recesses are formed by a wet etching process to remove portions of the isolation structure exposed by the plurality of word line trenches.

In some embodiments, each of the plurality of active regions includes a long side extending in a third direction, the third direction is inclined to the first direction and the second direction, and the word line structures have different widths in the third direction. .

In some embodiments, a plurality of recesses are recessed in the isolation structure between two adjacent active regions in a third direction.

In some embodiments, the plurality of extensions cover portions of the plurality of active regions.

Based on the above, in the above-mentioned semiconductor structure and its forming method, since each of the plurality of word line structures is designed to include a main body part and a plurality of extension parts, and the plurality of extension parts are designed to be from opposite side walls of the main body part. Extending into the isolation structure between two adjacent active areas, in this way, the area covered by the word line structure in the active area can be increased to improve the gate's ability to control the channel, making the semiconductor structure have good sub-criticality Swing (subthreshold swing).

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention may also be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar components, and will not be repeated one by one in the following paragraphs.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connection" may refer to a physical and/or electrical connection, and "electrical connection" or "coupling" may refer to the presence of other components between two components. "Electrical connection" as used herein may include physical connections (such as wired connections) and physical disconnections (such as wireless connections).

As used herein, "about," "approximately" or "substantially" includes the recited value and the average within an acceptable range of deviations from the specific value that a person with ordinary skill in the art can determine, taking into account the Discuss the measurement and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" used in this article can be used to select a more acceptable deviation range or standard deviation based on optical properties, etching properties or other properties, and one standard deviation does not apply to all properties. .

The terminology used herein is used only to describe illustrative embodiments and does not limit the disclosure. In such cases, the singular form includes the plural form unless the context dictates otherwise.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. FIG. 2 and FIG. 3 are schematic cross-sectional views of a method for forming a semiconductor structure according to an embodiment of the present invention. The cross-sections shown in (a) of FIG. 2 and FIG. 3 correspond to the schematic cross-sectional view taken along the line A-A' of FIG. 1. The cross-sections shown in (b) of FIG. 2 and FIG. 3 correspond to the schematic cross-sectional view taken along the line B-B' of FIG. 1.

Referring to FIG. 1 , the semiconductor structure 10 includes a substrate 100 , an isolation structure STI and a plurality of word line structures WL.

The substrate 100 includes a plurality of active areas AA arranged in an array. The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include element semiconductor, alloy semiconductor or compound semiconductor. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, III-V semiconductor materials, or II-VI semiconductor materials. Group III-V semiconductor materials may include GaN, GaP, GaAs, AIN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type that is complementary to the first conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type.

The isolation structure STI extends from the surface of the substrate 100 into the substrate to define a plurality of active areas AA. The isolation structure STI may include materials such as oxides for isolation structures.

The word line structure WL is embedded in the substrate 100, extends through the plurality of active areas AA in a first direction D1, and is arranged in a second direction D2 different from the first direction D1. In some embodiments, the first direction D1 may be perpendicular to the second direction D2. Each of the word line structures WL includes a main body portion BP and a plurality of extension portions EP. A plurality of extension portions EP extend from opposite side walls of the main body portion BP to the isolation structure STI between two adjacent active areas AA. In this way, the area covered by the word line structure WL in the active area AA can be increased to improve the ability of the gate in the word line structure WL to control the channel (not shown) in the active area AA, so that the semiconductor structure 10 has Good subthreshold swing.

In some embodiments, the word line structure WL may include a gate (not shown) and a gate dielectric layer (not shown) surrounding the gate. The gate may include conductive materials such as Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, etc. The gate dielectric layer may include at least one of the following: a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide/nitride/oxide (ONO) layer, and a high dielectric constant higher than the silicon oxide layer. Dielectric constant layer. In some embodiments, the gate dielectric layer may include, for example, hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), or lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide At least one material selected from the group consisting of BaSrTiO, barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO) and lead scandium tantalum oxide (PbScTaO). For example, the gate dielectric layer may include HfO ₂ , Al ₂ O ₃ , HfAlO ₃ , Ta ₂ O ₃ or TiO ₂ .

In some embodiments, the extending portions EP of the word line structures WL may be aligned in the first direction D1. In some embodiments, each of the plurality of active areas AA may include a long side extending in the third direction D3. The third direction D3 may be inclined to the first direction D1 and the second direction D2. The word line structure WL may have different widths in the third direction D3. For example, the width of the word line structure WL in the portion including the extension EP (width W1 in FIG. 2 ) is greater than the width of the word line structure WL in the portion not including the extension EP (width W1 in FIG. 3 ). Width W3).

In some embodiments, the substrate 100 may include a plurality of word line trenches (such as the word line trench WLT2 of FIG. 3 ) in which a plurality of word line structures WL are disposed, and the plurality of word line trenches may include a plurality of word line trenches disposed therein. There are multiple recesses with multiple extensions EP (recess R1 in Figure 3). In some embodiments, the extension EP of the word line structure WL may cover a portion of the active area AA. For example, since the extension EP extends from the opposite side walls of the main body BP (for example, the opposite side walls in the second direction D2) to the isolation structure STI between the two adjacent active areas AA, the character The extension EP of the line structure WL may cover the portion of the active area AA exposed by the recess R1.

In some embodiments, multiple word line trenches (word line trenches WLT2 in FIG. 3 ) provided with multiple word line structures WL may be formed in the following manner.

First, please refer to FIGS. 1 and 2 . After forming the isolation structure STI defining a plurality of array-arranged active areas AA in the substrate 100 , a plurality of preliminary word line trenches WLT1 are formed in the substrate 100 , wherein the preliminary word line trenches WLT1 are formed in the substrate 100 . WLT1 extends through the plurality of active areas AA in a first direction D1 and is arranged in a second direction D2 different from the first direction D1. In some embodiments, the mask M can be etched by removing the exposed portion of the mask M to form a first portion T1 (as shown in (a) of Figure 2) and a second portion T2 (as shown in (a) of Figure 2). b)) Preliminary word line trench WLT1. The first part T1 and the second part T2 of the preliminary word line trench WLT1 have approximately the same width in the third direction D3. In some embodiments, the mask M may include at least one of a photoresist layer, a hard mask, and an anti-reflective layer.

Next, please refer to FIGS. 1 and 3 . After the preliminary word line trench WLT1 is formed, a portion of the isolation structure STI exposed by the preliminary word line trench WLT1 can be removed to form a plurality of recesses R1 , so that the zigzag formed The element line trench WLT2 includes a first part T1, a second part T2 and a recess R1. In some embodiments, the portion of the isolation structure STI exposed by the preliminary word line trench WLT1 may be removed by a wet etching process to form the recess R1. In some embodiments, the width of the word line trench WLT2 in the second portion T2 including the recess R1 (width W3 as shown in FIG. 3(b) ) is larger than that of the word line trench WLT2 when the recess R1 is not included. The width of the first part T1 (the width W1 shown in (a) of Figure 3).

Hereinafter, a method of forming the semiconductor structure 10 will be illustrated with reference to FIGS. 1 to 3 .

First, please refer to FIGS. 1 and 2 , an isolation structure STI defining a plurality of active areas AA arranged in an array is formed in the substrate 100 . Next, a plurality of word line trenches (such as the preliminary word line trench WLT1 shown in FIG. 2 ) are formed in the substrate 100 . The plurality of word line trenches extend through the plurality of active areas AA in the first direction D1 and are arranged in a second direction D2 different from the first direction D1.

Then, referring to FIGS. 1 and 3 , a portion of the isolation structure STI exposed by the plurality of word line trenches is removed to form a plurality of recesses R1 . Afterwards, a plurality of word line structures WL are formed in a plurality of word line trenches (such as the word line trench WLT2 shown in FIG. 3 ), wherein each of the plurality of word line structures WL includes a main body portion BP and a plurality of extension portions EP formed in a plurality of recesses R1. In some embodiments, the recesses R1 are formed by a wet etching process to remove the portions of the isolation structures STI exposed by the word line trenches WLT2. In some embodiments, a plurality of recesses R1 are recessed in the isolation structure STI between two adjacent active areas AA in the third direction D3.

To sum up, in the semiconductor structure and the forming method of the above embodiments, since each of the plurality of word line structures is designed to include a main body and a plurality of extensions, and the plurality of extensions are designed to be independent of the main body. The opposite side walls of the portion extend into the isolation structure between two adjacent active areas, so the area covered by the word line structure in the active area can be increased to improve the gate's ability to control the channel, making the semiconductor structure have good Subthreshold swing.

10: Semiconductor structure 100:Base AA: active area BP: main body EP:Extension D1: first direction D2: second direction D3: Third direction M:mask R1: depression STI: isolation structure T1:Part one T2:Part Two WL: word line structure WLT1: Preliminary word line trench WLT2: Word Line Trench W1, W2, W3: Width

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. 2 and 3 are schematic cross-sectional views of a method of forming a semiconductor structure according to an embodiment of the present invention.

10: Semiconductor structure

100:Base

AA: active area

BP: main body

EP:Extension

D1: first direction

D2: second direction

D3: Third direction

STI: isolation structure

WL: word line structure

Claims (10)

A semiconductor structure, including: a substrate including a plurality of active regions arranged in an array; an isolation structure extending from a surface of the substrate into the substrate to define a plurality of the active regions; and a plurality of word line structures, buried extending through a plurality of the active regions in a first direction in the substrate and arranged in a second direction different from the first direction, wherein each of a plurality of the word line structures It includes a main body part and a plurality of extension parts, and the plurality of extension parts extend from opposite side walls of the main body part to the isolation structure between two adjacent active areas. The semiconductor structure of claim 1, wherein a plurality of the extending portions are arranged in the first direction. The semiconductor structure of claim 1, wherein each of the plurality of active regions includes a long side extending in a third direction, the third direction being inclined to the first direction and the second direction. , the word line structure has different widths in the third direction. The semiconductor structure of claim 1, wherein a plurality of the extension portions cover a portion of a plurality of the active regions in the first direction. The semiconductor structure of claim 1, wherein the substrate includes a plurality of word line trenches in which a plurality of the word line structures are disposed, and the plurality of word line trenches include a plurality of the word line trenches in which a plurality of the word line structures are disposed. A plurality of depressions in the extension part. A method of forming a semiconductor structure, including: forming an isolation structure defining a plurality of active regions in a substrate, the plurality of active regions being arranged in an array in the substrate; forming a plurality of word line trenches in the substrate, Each of the word line trenches extends through a plurality of the active regions in a first direction and is arranged in a second direction different from the first direction; removing the plurality of word line trenches exposed by a portion of the isolation structure to form a plurality of recesses; and forming a plurality of word line structures in a plurality of the word line trenches, wherein each of the plurality of word line structures includes a body portion and A plurality of extensions formed in a plurality of said depressions. The method of claim 6, wherein the plurality of recesses are formed by removing the portions of the isolation structure exposed by the plurality of word line trenches through a wet etching process. The method of claim 6, wherein each of a plurality of said active areas includes a long side extending in a third direction, said third direction being inclined to said first direction and said second direction, The word line structures have different widths in the third direction. The method of claim 8, wherein a plurality of the recesses are recessed in the isolation structure between two adjacent active areas in the third direction. The method of claim 6, wherein a plurality of the extension portions cover a portion of a plurality of the active areas in the first direction.

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