CN110838496B - Memory element and manufacturing method thereof - Google Patents
Memory element and manufacturing method thereof Download PDFInfo
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- CN110838496B CN110838496B CN201810940188.6A CN201810940188A CN110838496B CN 110838496 B CN110838496 B CN 110838496B CN 201810940188 A CN201810940188 A CN 201810940188A CN 110838496 B CN110838496 B CN 110838496B
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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Abstract
The embodiment of the invention provides a memory element and a manufacturing method thereof. The memory element comprises a pair of laminated structures, a charge storage layer and a channel layer. A pair of stacked structures is disposed on the substrate. Each stacked structure comprises a plurality of gate layers and a plurality of insulating layers which are alternately stacked on the substrate, and comprises a top cover layer positioned on the plurality of gate layers and the plurality of insulating layers. The charge storage layer is disposed on sidewalls of the pair of stacked structures facing each other. The channel layer covers the charge storage layer. The channel layer has a top portion, a body portion, and a bottom portion. The top portion covers sidewalls of the cap layers of the pair of stacked structures. The bottom portion covers a portion of the substrate between the pair of stacked structures. The main body part is connected between the top part and the bottom part. The dopant concentration of the top and bottom portions is respectively higher than that of the main body portion.
Description
Technical Field
The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to memory devices and methods of fabricating the same.
Background
Flash memory (flash memory) is a type of nonvolatile memory, and has become one of the mainstream technologies of storage media in recent years. Flash memory may be classified into NAND (NAND) flash memory and exclusive or (NOR) flash memory. The nand flash memory cell array can have a high density and can be applied to the storage of a large amount of data.
The NAND flash memory comprises a plurality of memory cells, and a gap is formed between adjacent memory cells. The semiconductor layer is formed on the bottom surface and the side wall of the gaps to be used as a channel layer of each memory cell. In the process of forming such voids, it is difficult to precisely control the depth of all voids. The voids with greater depth result in a higher height of the channel layer formed on the surface thereof, so that the corresponding memory cell has a longer channel length (i.e., a higher resistance value), thereby reducing the operating current. In addition, when the channel length is too long, the open circuit problem of the memory cell is more likely to be caused.
Disclosure of Invention
The invention provides a memory element and a manufacturing method thereof, which can keep the working current of a memory cell and avoid the problem of open circuit.
The memory element comprises a pair of laminated structures, a charge storage layer and a channel layer. A pair of stacked structures is disposed on the substrate. Each of the stacked structures includes a plurality of gate layers and a plurality of insulating layers alternately stacked on the substrate, and includes a cap layer over the plurality of gate layers and the plurality of insulating layers. The charge storage layer is disposed on the sidewalls of the pair of stacked structures facing each other. The channel layer covers the charge storage layer. The channel layer has a top portion, a body portion, and a bottom portion. The top portion covers sidewalls of the cap layers of the pair of stacked structures facing each other. The bottom portion covers a portion of the substrate between the pair of stacked structures. The main body part is connected between the top part and the bottom part. The dopant concentration of the top and bottom portions is respectively higher than that of the main body portion.
In some embodiments, the ratio of the dopant concentration at the top and bottom of the channel layer to the dopant concentration of the main body of the channel layer may be 10 17 Atoms (atoms)/cm 3 To 10 21 atoms/cm 3 。
In some embodiments, the capping layer comprises a top gate layer.
In some embodiments, the top of the channel layer also covers the top surface of the cap layer.
In some embodiments, the stacked structure further comprises a bottom gate layer. The bottom gate layer is located on the substrate, and the gate layers and the insulating layers are located on the bottom gate layer.
In some embodiments, the memory element further comprises an isolation structure. The isolation structure is disposed on a portion of the substrate between the pair of stacked structures. The channel layer is located on the side wall and the bottom surface of the isolation structure.
In some embodiments, the material of the cap layer comprises an insulating material.
In some embodiments, the memory element further comprises an epitaxial layer. The epitaxial layer is disposed on a portion of the substrate between the pair of stacked structures. The bottom of the channel layer covers the epitaxial layer.
In some embodiments, the dopant concentration of the epitaxial layer is greater than the dopant concentration of the body portion of the channel layer.
In some embodiments, the memory device further includes an isolation structure and an upper pad. The isolation structure and the upper pad are filled on the part of the substrate between the adjacent laminated structures. The isolation structure is located between the substrate and the upper pad. The top of the channel layer is located on the sidewall of the upper pad. The main body part of the channel layer is positioned on the side wall of the isolation structure, and the isolation structure covers the bottom of the channel layer.
The manufacturing method of the memory element of the invention comprises the following steps: forming a pair of stacked structures on a substrate, wherein each stacked structure comprises a plurality of first material layers and a plurality of second material layers which are alternately stacked on the substrate, and comprises a top cover layer positioned above the plurality of first material layers and the plurality of second material layers; forming a charge storage layer on sidewalls facing each other of a pair of stacked structures; and forming a channel layer on the charge storage layer, wherein the channel layer has a top portion, a body portion and a bottom portion, the top portion covers the mutually-facing sidewalls of the capping layers of the pair of stacked structures, the bottom portion covers a portion of the substrate located between the pair of stacked structures, the body portion is connected between the top portion and the bottom portion, and the dopant concentrations of the top portion and the bottom portion are respectively higher than the dopant concentration of the body portion.
In some embodiments, a method of forming a channel layer includes: forming a channel material layer and a barrier layer on the charge storage layer in sequence; patterning the barrier layer such that the patterned barrier layer exposes a portion of the channel material layer between the pair of layered structures and substantially parallel to the major surface of the substrate and exposes another portion of the channel material layer overlying the cap layer; forming a doped layer on the patterned barrier layer and the exposed portion of the channel material layer; performing heat treatment to make the dopant in the doped layer enter the exposed part of the channel material layer so as to form a channel layer; and removing the doped layer and the patterned barrier layer.
In some embodiments, a method of patterning a barrier layer includes anisotropic etching.
In some embodiments, each first material layer is a gate layer, each second material layer is an insulating layer, and the capping layer comprises a top gate layer.
In some embodiments, each stacked structure further comprises a bottom gate layer. The bottom gate layer is located on the substrate, and the plurality of first material layers and the plurality of second material layers are formed on the bottom gate layer.
In some embodiments, after forming the channel layer, further comprising: an isolation structure is formed between a pair of stacked structures.
In some embodiments, the first material layers and the second material layers are all insulating materials and have an etching selection ratio with respect to each other.
In some embodiments, before forming the charge storage layer, further comprising: an epitaxial layer is formed. The epitaxial layer is disposed on a portion of the substrate between the pair of stacked structures.
In some embodiments, after forming the channel layer, further comprising: an isolation structure and an upper pad are sequentially formed between the pair of stacked structures. The top of the channel layer is located on the sidewall of the upper pad, and the main body and the bottom of the channel layer are located on the sidewall and the bottom surface of the isolation structure, respectively.
In some embodiments, after forming the channel layer, further comprising: the plurality of second material layers is replaced by a plurality of gate layers.
Based on the above, the channel layer of the memory device in the embodiment of the invention has the top and the bottom with high dopant concentration, and the body portion with much lower dopant concentration than the top and the bottom. By doping the top and bottom of the channel layer with high dopant concentration, the overall resistance of the channel layer can be effectively reduced. Therefore, even if the recess between some laminated structures has an excessive depth, the working current of the channel layer can still be maintained. In addition, in some embodiments, the problem of open circuit of the channel layer corresponding to the stacked structures can be avoided. Furthermore, since the top of the channel layer has a high dopant concentration (i.e., a low resistance), the contact resistance between the channel layer and the conductive plug formed thereon can be reduced. On the other hand, when doping the top and bottom of the channel layer, the patterned barrier layer prevents the diffusion of dopants into the body portion of the channel layer, so that the body portion of the channel layer that covers the sidewalls of the memory cells remains relatively low in dopant concentration. Therefore, when the memory element operates, the situation that the dopant in the main body part of the channel layer diffuses to the memory unit can be reduced. Therefore, the reliability of the memory element can be prevented from being influenced.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a flow chart of a method of fabricating a memory device according to some embodiments of the invention.
Fig. 2A to 2H are schematic cross-sectional views of the structure at various stages of the method for manufacturing the memory device shown in fig. 1.
Fig. 3 is a flow chart of a method of manufacturing a memory device according to some embodiments of the invention.
Fig. 4A to 4I are schematic cross-sectional views of structures at various stages of the method of manufacturing the memory device shown in fig. 3.
[ notation ] to show
10. 20: memory element
100. 200: substrate
102: semiconductor substrate
104: insulating layer
110. 210: initial laminated structure
110a, 210a: laminated structure
111: bottom gate layer
112. 212: a first material layer
114. 214: second material layer
116. 216: top cover layer
118: protective layer
120. 220, and (2) a step of: charge storage layer
122. 222: layer of channel material
122-1, 222-1: channel layer
122-1a, 222-1a: top part
122-1b, 222-1b: main body part
122-1c, 222-1c: bottom part
124. 224: barrier layer
124a, 224a: top part
124b, 224b: main body part
124c, 224c: bottom part
126. 226: doping layer
130. 230: isolation structure
132. 232: dielectric layer
140. 240: plug opening
142. 242: conductive plug
144. 244: signal line
EP: epitaxial layer
GL: grid layer
H: height
MU: memory cell
R: recesses
S100, S102, S104, S106, S108, S110, S112, S114, S116, S118, S200, S202, S204, S205, S206, S208, S210, S212, S214, S215, S216, S217, S218: step (ii) of
TP: upper connecting pad
W: width of
Detailed Description
Fig. 1 is a flow chart of a method of manufacturing a memory element 10 according to some embodiments of the invention. Fig. 2A to 2H are schematic cross-sectional views of the structure at various stages of the manufacturing method of the memory device 10 shown in fig. 1.
Referring to fig. 1 and fig. 2A, a step S100 is performed to provide a substrate 100. In some embodiments, the substrate 100 includes a semiconductor substrate 102 and an insulating layer 104. The material of the semiconductor substrate 102 may include an elemental semiconductor or a compound semiconductor. The elemental semiconductor may comprise Si or Ge, for example. The compound semiconductor may comprise SiGe, siC, siGeC, a group III-V semiconductor material, or a group II-VI semiconductor material. The III-V semiconductor material may include GaN, gaP, gaAs, alN, alP, alAs, inN, inP, inAs, gaNP, gaNAs, gaGaAs, alNP, alNAs, alPAs, inNP, inNAs, inPAs, gaAlNP, gaAlNAs, gaAlPAs, gaInNP, gaInNAs, gaInPAs, inInInNP, inAlNAs, or InAlPAs. The II-VI semiconductor material can include CdS, cdSe, cdTe, znS, znSe, znTe, hgS, hgSe, hgTe, cdSeS, cdSeTe, cdSeS, znSeS, znSeTe, znSTe, hgSeS, hgSeTe, cdZnS, cdZnSe, cdZnTe, cdHgS, cdHgSe, cdHgTe, hgZnS, hgZnSe, hgZnTe, cdZnSeS, cdZnSeTe, cdZnSTe, cdHgSeS, cdHgSeTe, cdHSTgZnSeS, hgZnSeTe, or HgZnSTe. In addition, the semiconductor substrate 102 may be doped to a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type can be N-type, and the second conductivity type can be P-type. On the other hand, the material of the insulating layer 104 may be silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
Step S102 is performed to form an initial stacked structure 110 on the substrate 100. The initial stacked structure 110 includes a plurality of first material layers 112 and second material layers 114 stacked alternately. One skilled in the art can adjust the number of the first material layer 112 and the second material layer 114 according to design requirements, and the invention is not limited thereto. In some embodiments, the first material layer 112 is a conductive layer and the second material layer 114 is an insulating layer. In such embodiments, the first material layer 112 may serve as a gate layer (or a word line), and the second material layer 114 may serve as an inter-gate insulating layer. For example, the material of the first material layer 112 may include polysilicon, tungsten, or other conductive materials. The material of the second material layer 114 may include silicon oxide, silicon nitride, silicon oxynitride, organic insulating material, or the like. In some embodiments, the thickness of the first material layer 112 ranges from 10nm to 40nm. On the other hand, the thickness of the second material layer 114 may range from 25nm to 65nm. In addition, the initial stacked structure 110 further includes a cap layer 116 located on the first material layer 112 and the second material layer 114. In some embodiments, the topmost second material layer 114 may be located between the cap layer 116 and the topmost first material layer 112. In some embodiments, cap layer 116 is composed of the same material as first material layer 112, except that cap layer 116 has a greater thickness. For example, the cap layer 116 may have a thickness ranging from 50nm to 250nm. In such embodiments, the cap layer 116 may serve as a top gate layer or a select gate (selection gate) layer.
In some embodiments, the initial stacked structure 110 further includes a protective layer 118. Protective layer 118 is located on top of cap layer 116. In addition, the protection layer 118 and the second material layer 114 may be made of the same material and may have substantially the same thickness. In some embodiments, the initial stacked structure 110 further comprises a bottom gate layer 111. The bottom gate layer 111 is disposed on the substrate 100, and the first material layer 112 and the second material layer 114 are disposed on the bottom gate layer 111. In some embodiments, the bottommost second material layer 114 is located between the bottom gate layer 111 and the bottommost first material layer 112. Furthermore, in some embodiments, the bottom gate layer 111 is composed of the same material as the first material layer 112, but the bottom gate layer 111 has a larger thickness. For example, the thickness of the bottom gate layer 111 may be 150nm to 350nm. In such embodiments, the bottom gate layer 111 may serve as an inversion gate (inversion gate) layer. In some embodiments, the layers of the initial stacked structure 110 may be formed by chemical vapor deposition.
Referring to fig. 1 and fig. 2B, step S104 is performed to pattern the initial stacked structure 110. In this way, a plurality of stacked structures 110a are formed. In some embodiments, a plurality of stacked structures 110a may be arranged on the substrate 100 in an array. The first material layers 112 and the second material layers 114 alternately stacked in each stack structure 110a can be used as the memory units MU. Memory unit MU is located between bottom gate layer 111 and top cap layer 116. A pair of adjacent stacked structures 110a has a recess R therebetween. In some embodiments, the recess R may extend into the insulating layer 104 of the substrate 100. In some embodiments, the height H of the recess R may range from 1.5um to 3.5um. The width W of the recess R (i.e., the spacing between the adjacent pair of stacked structures 110 a) may be 50nm to 150nm. In some embodiments, the method of patterning the initial stacked structure 110 to form the plurality of stacked structures 110a may include performing a photolithography process and an etching process. The sidewalls of the recess R (i.e., the sidewalls of the stacked structure 110 a) may be substantially perpendicular to the main surface of the substrate 100, or may sandwich 0 ° to 30 ° from the normal direction of the main surface of the substrate 100.
Referring to fig. 1 and fig. 2C, step S106 is performed to sequentially form a charge storage layer 120, a channel material layer 122 and a barrier layer 124 on the stacked structure 110a. In other words, the channel material layer 122 is located between the charge storage layer 120 and the barrier layer 124. In some embodiments, the charge storage layer 120, the channel material layer 122, and the barrier layer 124 may be conformally formed on the structure shown in fig. 2B. As a result, as shown in fig. 2C, the charge storage layer 120, the channel material layer 122 and the barrier layer 124 cover the sidewalls of the adjacent stacked structures 110a facing each other, and cover the top surface of the stacked structures 110a and the portion of the substrate 100 between the adjacent stacked structures 110a. In some embodiments, the material of the charge storage layer 120 includes silicon oxide, silicon nitride, or a combination thereof. For example, the charge storage layer 120 includes a multi-layer structure of silicon oxide/silicon nitride/silicon oxide. The material of the channel material layer 122 includes polysilicon or other semiconductor material, and is an undoped intrinsic material. The material of barrier layer 124 may include silicon nitride. In some embodiments, the thickness of the charge storage layer 120 may range from 15nm to 25nm. The thickness of the channel material layer 122 may range from 5nm to 15nm. The barrier layer 124 may have a thickness in the range of 5nm to 20nm. In addition, the charge storage layer 120, the channel material layer 122 and the barrier layer 124 may be formed by, for example, a furnace growth method.
Referring to fig. 1 and fig. 2D, step S108 is performed to pattern the barrier layer 124. In some embodiments, the method of patterning the barrier layer 124 includes performing an anisotropic etch, such as a dry etch. During the anisotropic etching process, some portions of the barrier layer 124 are removed and other portions of the barrier layer 124 remain based on the difference in the angle of arrival (arrival angle) corresponding to each portion of the barrier layer 124. Specifically, the top 124a and the bottom 124c of the barrier layer 124 may be removed in step S108, while the main body portion 124b of the barrier layer 124 may remain. In some embodiments, the top 124a of the barrier layer 124 covers the top surface of the stack 110a (e.g., the top surface of the protection layer 118) and extends to the sidewalls of the protection layer 118 and the cap layer 116 before removal. The bottom 124c of the barrier layer 124 covers the portion of the substrate 100 between the adjacent stacked structures 110a without being removed, and may extend onto the sidewalls of the bottom gate layer 111 in some embodiments. The body portion 124b of the barrier layer 124 is connected between the top portion 124a and the bottom portion 124b. In other words, the main body portion 124b of the barrier layer 124 covers the sidewalls of the memory unit MU, and may extend to the sidewalls of the bottom gate layer 111 and the cap layer 116. After patterning the barrier layer 124, only the main portion 124b of the barrier layer 124 is left, and a plurality of longitudinal line segments covering the plurality of memory units MU are formed. As such, a portion of the top surface of the cover stack structure 110a (e.g., the top surface of the cover protection layer 118) of the channel material layer 122 is exposed, and another portion of the cover substrate 100, which is located between the adjacent stack structures 110a and substantially parallel to the main surface of the substrate 100, of the channel material layer 122 is exposed. In addition, as can be seen from the above, the exposed portions of the channel material layer 122 overlap the top 124a and the bottom 124c of the barrier layer 124.
Referring to fig. 1 and 2E, step S110 is performed to form a doped layer 126 on the main body portion 124b of the barrier layer 124 and the exposed portion of the channel material layer 122. A doped layer 126 may be conformally formed on the structure shown in fig. 2D, contacting the body portion 124b of the barrier layer 124 and the exposed portion of the channel material layer 122. In some embodiments, the doped layer 126 may have a dopant of a first conductivity type (dopant), or a dopant of a second conductivity type. For example, the material of doped layer 126 may include phosphosilicate glass (PSG), tetraethoxysilane (TEOS), boron-silicate glass (BSG), triethoxyborose (TEB), triethyl phosphate (TEPO), or a combination thereof. In addition, the doped layer 126 can be formed by, for example, chemical vapor deposition or furnace growth.
Referring to fig. 1 and fig. 2F, step S112 is performed to perform a heat treatment. As such, the dopants in the doped layer 126 may diffuse into the exposed portion of the channel material layer 122, thereby doping the exposed portion of the channel material layer 122. In some embodiments, the method of performing a heat treatment may include an annealing process. The temperature range of the heat treatment may be 600 to 1000 ℃, and the heat treatment may be performed in an atmosphere of an inert gas (e.g., nitrogen). The doped channel material layer 122 may be referred to as a channel layer 122-1. The top 122-1a and bottom 122-1c of the channel layer 122-1 are doped in step S112. On the other hand, the body portion 124b of the barrier layer 124 covers the body portion 122-1b of the channel layer 122-1, and blocks diffusion of dopants into the body portion 122-1b of the channel layer 122-1. Therefore, the body portion 122-1b of the channel layer 122-1 is not doped in step S112.
The top 122-1a, bottom 122-1c, and body portion 122-1b of the channel layer 122-1 shown in FIG. 2F overlap the top 124a, bottom 124c, and body portion 124b, respectively, of the barrier layer 124 shown in FIG. 2D. In other words, the top portion 122-1a of the channel layer 122-1 covers the top surface of the stack structure 110a and extends to the sidewalls of the passivation layer 118 and the cap layer 116. The bottom portion 122-1c of the channel layer 122-1 covers a portion of the substrate 100 between adjacent stacked structures 110a, and may extend onto sidewalls of the bottom gate layer 111 in some embodiments. The main body portion 122-1b of the channel layer 122-1 is connected between the top portion 122-1a and the bottom portion 122-1c, covering the sidewalls of the memory units MU, and may extend longitudinally onto the sidewalls of the bottom gate layer 111 and the cap layer 116.
Based on the top portion 122-1a and the bottom portion 122-1c of the channel layer 122-1 being further doped in step S112, the dopant concentration (dopant concentration) of the top portion 122-1a and the bottom portion 122-1c of the channel layer 122-1 may be respectively higher than that of the body portion 122-1b. In some embodiments, the dopant concentration ranges of the top portion 122-1a and the bottom portion 122-1c of the channel layer 122-1 may be 10 respectively 17 atoms/cm 3 To 10 21 atoms/cm 3 . On the other hand, the body portion 122-1b remains undoped intrinsic material.
Referring to fig. 1 and fig. 2G, step S114 is performed to remove the doped layer 126 and the main body portion 124b of the barrier layer 124. As such, portions of the channel layer 122-1 may be exposed. In some embodiments, the method of removing the doped layer 126 and the body portion 124b of the barrier layer 124 may include anisotropic etching, such as wet etching.
Referring to fig. 1 and fig. 2H, in some embodiments, a step S116 may be performed to form an isolation structure 130 between adjacent stacked structures 110a. In some embodiments, the isolation structure 130 may also extend onto the top surface of the stacked structure 110a. The material of the isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The method of forming the isolation structure 130 may include a chemical vapor deposition method.
Subsequently, step S118 may be performed to form the conductive plug 142 and the signal line 144. The dielectric layer 132 may be formed on the isolation structure 130 prior to forming the electrical plugs 142 and the signal lines 144. For example, the dielectric layer 132 may be a multi-layer structure including one or more layers of dielectric material. The material of the dielectric layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The method of forming the dielectric layer 132 may include a chemical vapor deposition method. In addition, the isolation structure 130 and the dielectric layer 132 may be patterned to form a plug opening 140 exposing the top portion 122-1a of the channel layer 122-1. Next, a conductive plug 142 may be formed in the plug opening 140, and a signal line 144 may be formed on the dielectric layer 132. In some embodiments, the material of conductive plug 142 may include polysilicon or other conductive material. The material of the signal line 144 may include copper or other conductive material. The method of forming the conductive plug 142 and the signal line 144 may include a physical vapor deposition method, a plating process (plating process), or a combination thereof. Although fig. 2H only illustrates a single layer of signal lines 144, in practice, the signal lines 144 may include source lines and bit lines located in different layers. In addition, an interlayer dielectric layer (not shown) may be formed between the source lines and the bit lines. In some embodiments, a plurality of stacked structures 110a arranged in a direction parallel to the surface of the substrate 100 may be alternately electrically connected to the source lines and the bit lines through the top portion 122-1a of the channel layer 122-1. In some embodiments, at least one of the word line (e.g., the first material layer 112), the bit line, and the source line may extend in a direction different from or perpendicular to the other two.
Thus, the fabrication of the memory device 10 of the embodiment of the present invention has been completed. Based on the above, the channel layer 122-1 of the memory device 10 has the top portion 122-1a and the bottom portion 122-1c with high dopant concentration, and has the body portion 112-1b with much lower dopant concentration than the top portion 122-1a and the bottom portion 122-1 c. By providing the top portion 122-1a and the bottom portion 122-1c of the channel layer 122-1 with high dopant concentrations, the overall resistance of the channel layer 122-1 may be effectively reduced. Thus, even if the depth of the recess R between some of the stacked structures 110a is too large, the operating current of the channel layer 122-1 can be maintained. In addition, in some embodiments, the problem of open circuit of the channel layer 122-1 corresponding to the stacked structures 110a can be avoided. Furthermore, since the top portion 122-1a of the channel layer 122-1 has a high dopant concentration (i.e., a low resistance), the contact resistance between the channel layer 122-1 and the conductive plug 142 formed thereon can be reduced. On the other hand, when doping the top portion 122-1a and the bottom portion 122-1c of channel layer 122-1, the remaining portions of barrier layer 124 (i.e., body portion 124b of barrier layer 124) may prevent dopants from diffusing into body portion 122-1b of channel layer 122-1, so that body portion 122-1b of channel layer 122-1 may be maintained at a relatively low dopant concentration. Accordingly, the diffusion of the dopants in the main body portion 122-1b of the channel layer 122-1 into the memory unit MU can be reduced during the operation of the memory device 10. In this way, the reliability of the memory device 10 is prevented from being affected.
Fig. 3 is a flow chart of a method of manufacturing memory element 20 according to some embodiments of the invention. Fig. 4A to 4I are schematic cross-sectional views of the structure at various stages of the method of manufacturing the memory device 20 shown in fig. 3. The manufacturing method of the memory device 20 is similar to the manufacturing method of the memory device 10 shown in fig. 1 and fig. 2A to 2H, and only the differences between the two will be described below, and the same or similar parts will not be repeated. Further, the same or similar reference numerals denote the same or similar components.
Referring to fig. 3 and fig. 4A, step S200 is performed to provide a substrate 200. In some embodiments, the substrate 200 may be a semiconductor substrate or a Semiconductor On Insulator (SOI) substrate. The semiconductor material in the substrate 200 is the same as or different from the semiconductor substrate 102 shown in fig. 2A. In some embodiments, one or more doped regions (not shown) may also be formed in the substrate 200. In addition, the conductive type of the doped region may be the same as or different from that of the substrate 200.
Step S202 is performed to form an initial stacked structure 210 on the substrate 200. The initial stacked structure includes a plurality of first material layers 212 and second material layers 214 stacked alternately. In some embodiments, the first material layer 212 and the second material layer 214 are both insulating materials and have an etching selectivity ratio with respect to each other. For example, the first material layer 212 may be silicon oxide and the second material layer may be silicon nitride. In some embodiments, the initial stacked structure 210 may further include a cap layer 216 over the first material layer 212 and the second material layer 214. In some embodiments, the topmost first material layer 212 may be located between the cap layer 216 and the topmost second material layer 214. In some embodiments, the material of the cap layer 216 may comprise an insulating material, such as the same material as the first material layer 212. In addition, in such embodiments, the initial stack structure 210 may not include the protection layer 118 and the bottom gate layer 111 as shown in fig. 2A.
Referring to fig. 3 and fig. 4B, step S204 is performed to pattern the initial stacked structure 210. In this way, a plurality of stacked structures 210a are formed. The plurality of stacked structures 210a may be arranged in an array on the substrate 200. A recess R is provided between an adjacent pair of the laminated structures.
In some embodiments, after patterning the initial stacked structure 210, step S205 may be further performed to form an epitaxial layer EP on the substrate 200 exposed by the recess R. In other words, the epitaxial layer EP is disposed on a portion of the substrate 200 between the adjacent pair of the stacked structures 210a. In some embodiments, the epitaxial layer EP extends further up to cover the sidewalls of the lowermost first material layer 212. The material of the epitaxial layer EP comprises silicon, for example. The method of forming the epitaxial layer EP may include an epitaxial process.
Referring to fig. 3 and fig. 4C, in step S206, a charge storage layer 220, a channel material layer 222 and a barrier layer 224 are sequentially formed on the stacked structure 210a. In some embodiments, the charge storage layer 220 is formed to cover the sidewalls of the stacked structure 210a, but not to extend to the top surface of the stacked structure 210. Furthermore, in some embodiments, the charge storage layer 220 covers only a portion of the top surface of the epitaxial layer EP. As a result, the charge storage layers on opposite sides of the epitaxial layer EP are not connected to each other. In some embodiments, the channel material layer 222 and the barrier layer 224 may be sequentially formed conformally on the present structure. In other words, as shown in fig. 4C, the channel material layer 222 and the barrier layer 224 cover the surface of the charge storage layer 220, and cover the top surface of the stacked structure 210a and the top surface of the epitaxial layer EP.
Referring to fig. 3 and 4D, step S208 is performed to pattern the barrier layer 224. The top portion 224a and the bottom portion 224c of the barrier layer 224 may be removed in step S208, while the main portion 224b of the barrier layer 224 may remain. A top portion 224a of the barrier layer 224 covers a top surface of the stack 210a (e.g., a top surface of the cap layer 216) and extends onto sidewalls of the cap layer 216 before removal. The bottom 224c of the barrier layer 224 covers the top surface of the epitaxial layer EP before removal and may, in some embodiments, extend up onto the sidewalls of the bottommost first material layer 212 (or onto the sidewalls of the bottommost first material layer 212 and the bottommost second material layer 214). The body portion 224b of the barrier layer 224 is connected between the top portion 224a and the bottom portion 224b. After patterning barrier layer 224, only a main body portion 224b of barrier layer 224 remains. As such, a portion of the top surface of the channel material layer 222 covering the stack structure 210a (e.g., the top surface of the capping layer 216) is exposed, and another portion of the channel material layer 222 covering the epitaxial layer EP is exposed. In addition, as can be seen from the above, the exposed portions of the channel material layer 222 overlap the top 224a and the bottom 224c of the barrier layer 224.
Referring to fig. 3 and 4E, step S210 is performed to form a doped layer 226 on the main body portion 224b of the barrier layer 224 and the exposed portion of the channel material layer 222. The doped layer 226 may be conformally formed on the structure shown in fig. 4D, contacting the main portion 224b of the barrier layer 224 and the exposed portion of the channel material layer 222.
Referring to fig. 3 and 4F, step S212 is performed to perform a heat treatment. As such, dopants in the doped layer 226 may diffuse into the exposed portion of the channel material layer 222, which may dope the exposed portion of the channel material layer 222. The doped channel material layer 222 may be referred to as a channel layer 222-1. The top 222-1a and bottom 222-1c of the channel layer 222-1 are doped in step S212. In some embodiments, the dopants in the doped layer 226 may also diffuse into the epitaxial layer EP through the bottom 222-1c of the channel layer 222-1, such that at least a portion of the epitaxial layer EP is doped (as shown by the dashed region of the epitaxial layer EP in fig. 4F). In other embodiments, the dopants in doped layer 226 diffuse into epitaxial layer EP, leaving the entire epitaxial layer EP doped. On the other hand, the body portion 224b of the barrier layer 224 covers the body portion 222-1b of the channel layer 222-1, thereby blocking the diffusion of dopants into the body portion 222-1b of the channel layer 222-1. Therefore, the body portion 222-1b of the channel layer 222-1 is not doped in step S212. It can be seen that the dopant concentration at the top 222-1a and the bottom 222-1c of the channel layer 222-1 may be respectively higher than the dopant concentration at the body portion 222-1b. In some embodiments, dopants of epitaxial layer EPThe concentration may be similar to the dopant concentration at the top 222-1a and bottom 222-1c of the channel layer 222-1, but may also be greater than the dopant concentration at the body portion 222-1b of the channel layer 222-1. For example, the dopant concentration of the epitaxial layer EP may be in the range of 10 17 atoms/cm 3 To 10 21 atoms/cm 3 。
The top 222-1a, bottom 222-1c, and body portion 222-1b of the channel layer 222-1 shown in FIG. 4F overlap the top 224a, bottom 224c, and body portion 224b, respectively, of the barrier layer 224 shown in FIG. 4D. In other words, the top 222-1a of the channel layer 222-1 covers the top surface of the stack 210a and may extend to the sidewall of the cap layer 216. The bottom 222-1c of the via layer 222-1 covers the top surface of the epitaxial layer EP and may in some embodiments extend up to the sidewalls of the bottommost first material layer 212 (or to the bottommost first material layer 212 and the bottommost second material layer 214). The body portion 222-1b of the channel layer 222-1 is connected between the top portion 222-1a and the bottom portion 222-1 c.
Referring to fig. 3 and 4G, step S214 is performed to remove the doped layer 226 and the main body portion 224b of the barrier layer 224. As such, portions of the channel layer 222-1 may be exposed.
Referring to fig. 3 and fig. 4H, in some embodiments, step S215 may be performed to replace the plurality of second material layers 214 with a plurality of gate layers GL. In some embodiments, the method of replacing the second material layer 214 with the gate layer GL includes removing the second material layer 214. For example, the second material layer 214 may be removed by isotropic etching. Since the second material layer 214 has an etching selectivity with respect to the first material layer 212, the first material layer 212 may remain when the second material layer 214 is removed. Next, a gate layer GL is formed at the original position of the second material layer 214 (i.e. between the adjacent first material layers 212). The material of the gate layer GL may include a metal material, such as tungsten. In addition, in some embodiments, a work function layer (not shown) may be formed in the original position of the second material layer 214, and then the gate layer GL is formed. The method of forming the work function layer and the gate layer GL may include a chemical vapor deposition method.
In addition, in some embodiments, step S216 may be performed to sequentially form the isolation structure 230 and the top pad TP between the adjacent stacked structures 210a. In some embodiments, the top surface of the isolation structure 230 may be lower than the top surface of the stack structure 210a (e.g., the top surface of the cap layer 216). The upper pad TP is disposed on the isolation structure 230. In some embodiments, the top pad TP may also extend to the top surface of the stacked structure 210a to cover the top 222-1a of the channel layer 222-1. In some embodiments, the material of the top pad TP may be the same as the material of the channel layer 222-1. In addition, the dopant concentration of the top pad TP may be substantially equal to the dopant concentration of the channel layer 222-1. The method of forming the isolation structure 230 and the upper pad TP may include a chemical vapor deposition method.
In some embodiments, step S215 may be performed first, and then step S216 may be performed. In other embodiments, step S216 may be performed first, and then step S215 may be performed. The present embodiment is not limited to the order of step S215 and step S216.
Referring to fig. 4I, step S217 is performed to perform a planarization process. In step S217, a portion of the top pad TP and a portion of the top 222-1a of the channel layer 222-1 are removed by a planarization process to expose a top surface of the stacked structure 210a (e.g., a top surface of the cap layer 216). As a result, the top surface of the top portion 222-1a of the remaining top pad TP and the channel layer 222-1 may be substantially flush with the top surface of the stack 210a (e.g., the top surface of the cap layer 216). In some embodiments, the planarization process is, for example, a chemical mechanical polishing process.
Subsequently, step S218 may be performed to form the conductive plugs 242 and the signal lines 244. Before forming the conductive plugs 242 and the signal lines 244, a dielectric layer 232 may be formed on the stacked structure 210a and the upper pads TP. For example, the dielectric layer 232 may be a single layer or a multi-layer structure, including one or more layers of dielectric material. In addition, the dielectric layer 232 may be patterned to form a plug opening 240 exposing the upper pad TP. Next, conductive plugs 242 may be formed in the plug openings 240, and signal lines 244 may be formed on the dielectric layer 232. Although fig. 4I only shows a single layer of signal lines 244, in practice, the signal lines 244 may include source lines and bit lines in different layers. In addition, an interlayer dielectric layer (not shown) may be formed between the source lines and the bit lines. In some embodiments, a plurality of stacked structures 210a arranged in a direction parallel to the surface of the substrate 200 may be alternately electrically connected to the source lines and the bit lines through the top 222-1a of the channel layer 222-1. In some embodiments, at least one of the word line (e.g., the gate layer GL), the bit line, and the source line may extend in a direction different from or perpendicular to the other two. Thus, the manufacturing of the memory device 20 of the embodiment of the present invention has been completed.
In summary, the channel layer of the memory device of the embodiments of the invention has a top portion and a bottom portion with high dopant concentration, and has a body portion with a dopant concentration much lower than the top portion and the bottom portion. The top and the bottom of the channel layer are doped with high dopant concentration, so that the overall resistance value of the channel layer can be effectively reduced. Therefore, even if the recesses between some of the stacked structures have too large a depth, the operating current of the channel layer can be maintained. In addition, in some embodiments, the problem of open circuit of the channel layer corresponding to the laminated structures can be avoided. Furthermore, since the top of the channel layer has a high dopant concentration (i.e., a low resistance), the contact resistance between the channel layer and the conductive plug formed thereon can be reduced. On the other hand, when doping the top and bottom of the channel layer, the remaining portions of the barrier layer (i.e., the body portions of the barrier layer) prevent the dopants from diffusing into the body portions of the channel layer, so that the body portions of the channel layer that cover the sidewalls of the memory cells remain at a relatively low dopant concentration. Therefore, when the memory element operates, the situation that the dopant in the main body part of the channel layer diffuses to the memory unit can be reduced. Therefore, the reliability of the memory element can be prevented from being influenced.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A memory element, comprising:
a pair of stacked structures disposed on a substrate, wherein each stacked structure comprises a plurality of gate layers and a plurality of insulating layers alternately stacked on the substrate, and a cap layer disposed on the plurality of gate layers and the plurality of insulating layers;
a charge storage layer disposed on sidewalls of the pair of stacked structures facing each other; and
a channel layer covering the charge storage layer, wherein the channel layer has a top portion covering sidewalls of the cap layers of the pair of stacked structures facing each other, a body portion connected between the top portion and the bottom portion, and a bottom portion covering a portion of the substrate between the pair of stacked structures, and the top portion and the bottom portion have a dopant concentration higher than a dopant concentration of the body portion, respectively, and the charge storage layer continuously extends below the bottom portion of the channel layer.
2. The memory element of claim 1, wherein the cap layer comprises a top gate layer.
3. The memory element of claim 2, wherein the top of the channel layer further covers a top surface of the cap layer.
4. The memory element of claim 2, wherein the stack structure further comprises a bottom gate layer on the substrate, and the plurality of gate layers and the plurality of insulating layers are on the bottom gate layer.
5. The memory element defined in claim 1, wherein the material of the cap layer comprises an insulating material.
6. The memory element of claim 5, further comprising an epitaxial layer, wherein the epitaxial layer is disposed on a portion of the substrate between the pair of stacked structures, and the bottom of the channel layer covers the epitaxial layer.
7. A method of manufacturing a memory element, comprising:
forming a pair of stacked structures on a substrate, wherein each stacked structure comprises a plurality of first material layers and a plurality of second material layers which are alternately stacked on the substrate, and comprises a top cover layer positioned on the plurality of first material layers and the plurality of second material layers;
forming a charge storage layer on sidewalls of the pair of stacked structures facing each other; and
forming a channel layer on the charge storage layer, wherein the channel layer has a top portion, a body portion and a bottom portion, the top portion covers the sidewalls of the cap layers of the pair of stacked structures facing each other, the bottom portion covers a portion of the substrate between the pair of stacked structures, the body portion is connected between the top portion and the bottom portion, and the dopant concentrations of the top portion and the bottom portion are respectively higher than the dopant concentration of the body portion;
forming a channel material layer and a barrier layer on the charge storage layer in sequence; patterning the barrier layer such that the patterned barrier layer exposes a portion of the channel material layer between the pair of layered structures and substantially parallel to a major surface of the substrate and exposes another portion of the channel material layer overlying the cap layer; doping the exposed portion of the channel material layer to form a channel layer; and removing the patterned barrier layer.
8. The method of manufacturing a memory element according to claim 7, wherein the method of doping the channel material layer comprises:
forming a doped layer on the patterned barrier layer and exposed portions of the channel material layer;
performing a heat treatment to make dopants in the doped layer enter the exposed part of the channel material layer, thereby forming the channel layer; and
removing the doped layer.
9. The method of claim 7, wherein each first material layer is a gate layer, each second material layer is an insulating layer, and the capping layer comprises a top gate layer.
10. The method of manufacturing a memory element according to claim 7, further comprising, before forming the charge storage layer: forming an epitaxial layer, wherein the epitaxial layer is disposed on a portion of the substrate between the pair of stacked structures.
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| CN105097812A (en) * | 2014-05-09 | 2015-11-25 | 旺宏电子股份有限公司 | Storage unit and manufacture method thereof |
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| US20150380428A1 (en) * | 2014-06-27 | 2015-12-31 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing same |
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| CN102751334A (en) * | 2011-04-18 | 2012-10-24 | 力晶科技股份有限公司 | Non-volatile memory device and method of manufacturing the same |
| CN104769721A (en) * | 2012-07-01 | 2015-07-08 | 赛普拉斯半导体公司 | SONOS ONO stack scaling |
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