CN104769721A - SONOS ONO stack scaling - Google Patents

SONOS ONO stack scaling Download PDF

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Publication number
CN104769721A
CN104769721A CN201380032545.4A CN201380032545A CN104769721A CN 104769721 A CN104769721 A CN 104769721A CN 201380032545 A CN201380032545 A CN 201380032545A CN 104769721 A CN104769721 A CN 104769721A
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China
Prior art keywords
layer
electric charge
tunnel
oxide
substrate
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CN201380032545.4A
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Inventor
斐德列克·杰能
赛格·利维
克里希纳斯瓦米·库马尔
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Longitudinal Flash Storage Solutions Co., Ltd.
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Cypress Semiconductor Corp
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Priority claimed from US13/539,461 external-priority patent/US9299568B2/en
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Publication of CN104769721A publication Critical patent/CN104769721A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Description

SONOS ONO lamination improves
The cross reference of related application
The application is the Application U.S. Serial No 11/904 of the common unexamined that on September 26th, 2007 submits to, the homologous series continuation application of 506, sequence number 11/904,506 require according to 35 U.S.C.119 (e) the U.S. Provisional Patent Application sequence number 60/940 that on May 25th, 2007 submits to, the benefit of priority of 384, these two applications are merged in herein all by reference.
Technical field
Embodiments of the present invention relate to electronic equipment manufacturing industry, and relate more specifically to the non-volatile manufacture being captured charge accumulator equipment.
Background
Fig. 1 is the partial cross-sectional views of the intermediate structure of the semiconductor equipment 100 with Semiconductor Oxide-Nitride Oxide-semiconductor (SONOS) gate stack 102, and Semiconductor Oxide-Nitride Oxide-semiconductor (SONOS) gate stack 102 comprises conventional oxide-Nitride Oxide (ONO) lamination 104 formed above the surface 106 of Semiconductor substrate 108 according to conventional methods.Equipment 100 aligns and one or more diffusion regions 110 of being separated by channel region 112 with gate stack general also comprising, such as source area and drain region.SONOS gate stack 102 is included on ONO lamination 104 and is formed and polysilicon (poly) grid layer 114 contacted with ONO lamination 104.Polysilicon gate 114 is separated or electric isolution by ONO lamination 104 and substrate 108.ONO lamination 104 generally includes siliconoxide tunnel layer 116, as the charge storage of equipment 100 or the silicon nitride charge capture layer 118 of memory layer and the silica barrier layer 120 that covers above electric charge capture layer 118.
Such SONOS transistor npn npn is useful to nonvolatile memory (NVM).Electric charge capture layer stored charge is to provide non-volatile.In order to n raceway groove SONOS type device programming (that is, writing n raceway groove SONOS type equipment), positive voltage is applied to control gate (Vcg), and source electrode, main body and grounded drain.Depict the energy band diagram of the conventional n raceway groove SONOS equipment during programming with raceway groove 212, oxide tunnel layer 216, nitride memory layer 218 and barrier oxide layers 220 in fig. 2, be captured CHARGE DISTRIBUTION and trap density distribution.As shown, positive Vcg produces the electric field through SONOS lamination, causes some negative electrical charges at the conduction level place in the buried channel of silicon substrate raceway groove to experience passing through tunnel layer and the Fowler-Nordheim tunnelling (FNT) entered in electric charge capture layer.Electronic saving having in the trap of middle forbidden band energy level in charge trapping silicon nitride thing.As shown, trap density is distributed in is in fact uniform in whole electric charge capture layer.As further shown, under bias voltage, be captured CHARGE DISTRIBUTION and make major part be captured electric charge in the part of the electric charge capture layer (that is, memory layer) close to barrier oxide.In order to wipe n raceway groove SONOS equipment, negative voltage is applied to control gate 314.Depict the energy band diagram that raceway groove 312, oxide tunnel layer 316, nitride memory layer 318 and barrier oxide layers 320 are shown in figure 3.As shown, negative Vcg produces the electric field through SONOS lamination, its attract to pass through tunnel layer tunnel, the hole electric charge entered in electric charge capture layer.
High-density storage for such as embedded NVM is applied, and SONOS type equipment receives an acclaim day by day.Known to programming and erasing in the industry, uniform channel Fowler-Nordheim tunnelling (FNT) and/or directly tunnelling (DT) produce the reliability being better than the raising of other method.FNT and DT is combined in referred here and is called as the Fowler-Nordheim tunnelling (MFNT) of improvement.At present, conventional SONOS operates in 10V scope for MFNT.But the advantage that SONOS is better than other NVM equipment is voltage scalability.It is theorized, uses correct proportional zoom, there is the possibility realizing exercisable memory technology within the scope of 5 volts of (V) scopes instead of the 10V scope of conventional SONOS-type equipment or the 12V-15V of conventional flash memories technology in SONOS.Under low-voltage (close to 5V), exercisable SONOS type equipment is advantageously compatible with low voltage cmos.Alternatively, for the equipment improving (scaled), programming faster or erasing may be possible under specific voltage.But the successful improvement (scaling) of SONOS type equipment is valuable.Such as, Fig. 4 describes programming and the erasing time of the conventional SONOS equipment using the conventional ONO lamination be made up of 10nm thick silicon dioxide barrier layer, 7nm thick silicon nitride electric charge capture layer and 3nm thick silicon dioxide tunnel layer.As shown, when Vcg reduces in proportion, the program/erase time obviously increases.Usually, the program/erase time being less than 1 millisecond (ms) is desirable for in-line memory application.But such 1ms program/erase time only could realize when using the Vcg of +/-10V in conventional SONOS lamination.When Vcg is reduced to about +/-9v, conventional SONOS program/erase time lengthening is to 100ms or longer.
In addition, the reduction that program voltage causes erasing or program window (that is, memory window) is reduced.If this is because equivalent oxide thickness (EOT) not to scale (NTS) of whole ONO lamination reduces when voltage reduces, then the electric field through ONO lamination will reduce.It is valuable for reducing the EOT of lamination, because reduce tunnel layer thickness to allow the unfavorable increase that can cause in erasing and programming attenuation rate in the identical initial erase level at lower applied voltage (Vcg) place.Similarly, if charge trapping layer thickness reduces, then charge centroid is placed comparatively close to substrate, adds the charge loss to substrate.Finally, when barrier oxide thickness reduces in proportion, the electronics inverse injection from control gate increases, and causes the damage to ONO lamination and data maintenance loss.Inverse injection is as being shown of illustrating further in the diagram, and wherein FNT erasing reaches " saturated ".This appear at electronics from grid flow to backward memory layer internal ratio they can through tunnel oxide hole transport be eliminated faster time.Therefore, still exist and improve the needs of the ONO lamination of SONOS in the mode of exercisable equipment under can being provided in lower program/erase voltage.
Brief description of drawings
Embodiments of the present invention as an example instead of limit shown in the drawings, wherein:
Fig. 1 illustrates the viewgraph of cross-section of the intermediate structure of conventional SONOS equipment.
During Fig. 2 is depicted in programming conventional SONOS equipment energy band diagram, be captured CHARGE DISTRIBUTION and trap density distribution.
Fig. 3 describes the energy band diagram of conventional SONOS equipment in the erase period.
Fig. 4 describes programming and the erasing time of the conventional SONOS equipment using conventional ONO lamination.
Fig. 5 illustrate according to the embodiment of the present invention there is the non-volatile cross-sectional side view being captured a part for charge accumulator equipment of improvement of ONO structure of improvement comprising nitride-oxide tunnel layer, multilayer charge trapping oxynitride and highly dense barrier layer.
Fig. 6 illustrates the nitrogen concentration profile roughly of nitride-oxide tunnel layer according to the embodiment of the present invention.
Fig. 7 A illustrates the curve of description simulation according to the embodiment of the present invention, and this simulation illustrates the reduction of the program voltage being attributable to nitride-oxide tunnel layer.
Fig. 7 B illustrates the comparison of two kinds of concentration profiles of hydrogen, nitrogen, oxygen and silicon in the barrier layer of two kinds of different SONOS type equipment, electric charge capture layer and tunnel layer.
Fig. 8 A describes the Holdover mode energy band diagram of the SONOS type equipment of improvement according to the embodiment of the present invention.
During Fig. 8 B is depicted in programming the SONOS type equipment of improvement according to the embodiment of the present invention energy band diagram, be captured CHARGE DISTRIBUTION and trap density distribution.
Fig. 9 is that manufacture according to the embodiment of the present invention comprises nitride-oxide tunnel layer, multilayer electric charge capture layer and reoxidizes the flow chart of SONOS scaling method of ONO structure of improvement on barrier layer.
Figure 10 is the flow chart that the SONOS forming nitride-oxide tunnel layer improves one's methods.
Figure 11 A and 11B illustrate according to the embodiment of the present invention there is the non-volatile cross-sectional side view being captured a part for charge accumulator equipment of improvement of ONO structure of improvement comprising nitride-oxide tunnel layer, multilayer electric charge capture layer and highly dense barrier layer.
Figure 12 is that formation according to the embodiment of the present invention has the non-volatile flow chart being captured the method for charge accumulator equipment of improvement of ONO structure of improvement comprising nitride-oxide tunnel layer, the multilayer electric charge capture layer separated and highly dense barrier layer.
Figure 13 A illustrates the many gate device of on-plane surface comprising nitride-oxide tunnel layer, the multilayer electric charge capture layer separated and highly dense barrier layer according to the embodiment of the present invention.
Figure 13 B illustrates the viewgraph of cross-section of the many gate device of the on-plane surface of Figure 13 A.
Figure 14 A and 14B illustrates the many gate device of on-plane surface comprising nitride-oxide tunnel layer, the multilayer electric charge capture layer separated, highly dense barrier layer and horizontal nano wire channel according to the embodiment of the present invention.
Figure 14 C illustrates the viewgraph of cross-section of the vertical string of the many gate device of the on-plane surface of Figure 14 A.
Figure 15 A and 15B illustrates the many gate device of on-plane surface comprising nitride-oxide tunnel layer, the multilayer electric charge capture layer separated, highly dense barrier layer and vertical nanowires wire channel.
Figure 16 A to 16F illustrates the grid scheme at first of the many gate device of on-plane surface for the manufacture of Figure 15 A.
Figure 17 A to 17F illustrates the grid final solution of the many gate device of on-plane surface for the manufacture of Figure 15 A.
Describe in detail
The non-volatile execution mode being captured charge accumulator equipment of improvement has been described with reference to the drawings herein.But, can to implement specific execution mode when not have in these specific detail one or more or in conjunction with other known method, material and device.In the following description, set forth a lot of specific details, such as specific material, size and technological parameter etc., to provide thorough understanding of the present invention.In other example, do not describe known semiconductor design and manufacturing technology especially in detail, to avoid unnecessarily making indigestion of the present invention.In whole specification, mentioning of " execution mode " is meaned that specific feature, structure, material or the characteristic described in conjunction with execution mode is included at least one execution mode of the present invention.Therefore, phrase " in embodiments " different local appearance in this specification whole might not refer to same execution mode of the present invention.In addition, specific feature, structure, material or characteristic can combine in any suitable manner in one or more execution mode.
Some execution mode of the present invention comprises the SONOS type equipment of improvement.In particular implementation of the present invention, tunnel layer, electric charge capture layer and barrier layer are modified to improve SONOS type equipment.In specific execution mode, the SONOS equipment of improvement can operate under lower than the programming of +/-10V and erasing voltage.In the execution mode that some is such, the SONOS equipment improved operates with the erasing voltage between-5V and-9V and preferably between-5V and-7V, to provide the initial erase voltage threshold level (VTE) of-1 to-3V and preferably-2 to-3 after lms-10ms pulse when operating at the temperature between-40 to 95 degrees Celsius (DEG C).In other specific execution mode, be used in 5V and 9V and the program voltage preferably between 5V and 7V to operate SONOS type equipment, to provide 1 to the initial programming voltage threshold level (VTP) of 3V, preferably 2V to 3V after lms to 10ms, preferably 5ms programming pulse.The SONOS equipment of these example improvement to be provided at 85 DEG C and end-of-life (EOL) memory window and at least 10 more than 20 years between 1V and 2V, 000 write/erase circulation, is preferably 100,000 circulation.
In some embodiments, conventional pure oxygen (oxide) the tunnel layer nitride-oxide with specific nitrogen concentration profile replaces to reduce the equivalent oxide thickness of tunnel layer relative to pure oxygen tunnel layer, keeps low interface trap density simultaneously.Program/erase voltage that this can reduce (reducing in proportion), provides the equipment do not improved with routine equally good or compare the better erase voltage threshold level (VTPNTE) of the conventional equipment do not improved simultaneously.In other execution mode specific, replace the conventional charge capture layer of nitride with the multilayer oxynitride with at least different stoichiometric top layers and bottom.In such execution mode, multilayer oxynitride comprises Silicon-rich, oxygen deprivation top layer to locate and to limit the barycenter of the electric charge away from tunnel oxide, thus is increased in the trap density in electric charge capture layer partly.In other execution mode specific, replace the conventional barrier layers of high-temperature oxide (HTO) to increase the density of barrier oxide with reoxidizing barrier layer, and thus reduce in proportion to store attenuation rate.Such execution mode provides enough net charges for enough memory windows, also reduces trap simultaneously and assists tunnelling to improve when SONOS equipment operates under the program/erase voltage reduced or to maintain programming and erase threshold voltage (VTPNTE).
Term as used herein " ... top ", " ... below ", " ... between " and " ... on " refer to the relative position of one deck relative to other layer.Therefore, such as to deposit or the one deck be arranged in above or below another layer directly can contact with another layer and maybe can have one or more intermediate layer.And deposition or layout one deck between layers can directly contact with those layers maybe can have one or more intermediate layer.On the contrary, the second layer " on " ground floor contact with this second layer.In addition, assuming that provide one deck relative to the relative position of other layer relative to starting substrates operation deposition, amendment and removal film, and the absolute orientation of substrate is not considered.
According to an embodiment of the invention, the non-volatile charge accumulator equipment that is captured is SONOS type equipment, and wherein electric charge capture layer is insulator layer, such as nitride.In another embodiment, the non-volatile charge accumulator equipment that is captured is flash-type equipment, and wherein electric charge capture layer is conductor layer or semiconductor layer, such as polysilicon.Use the non-volatile charge accumulator equipment that is captured of nitride-oxide tunnel layer can realize lower programming or erasing voltage, provide and conventional equipment equally good or erase voltage threshold level (VTPNTE) more better than conventional equipment simultaneously.
Fig. 5 illustrates the cross-sectional side view with the intermediate structure of the SONOS type equipment 500 of the ONO lamination of improvement according to the embodiment of the present invention.It should be understood that other SONOS execution mode various disclosed herein also can be used to produce outside the particular implementation described in Figure 5 but still the ONO lamination of also exercisable improvement under the program/erase voltage reduced.Therefore, although the feature of Fig. 5 can be mentioned in whole description, the present invention is not limited to this specific execution mode.
In the particular implementation shown in Fig. 5, SONOS type equipment 500 comprises SONOS gate stack 502, and it is included in the ONO lamination 504 formed above the surface 506 of substrate 508.SONOS type equipment 500 also comprises and aliging and one or more source area of being separated by channel region 512 and drain region 510 with gate stack 502.Usually, formed on the ONO lamination 504 that the SONOS gate stack 502 of improvement is included in improvement and a part for the grid layer 514 contacted with the ONO lamination 504 improved and substrate 508.Grid layer 514 is separated or electric isolution with substrate 508 by the ONO lamination 504 improved.
In one embodiment, substrate 508 is by the bulk substrate that can include but not limited to silicon, germanium, the monocrystalline of material of silicon-germanium or III-V compound semi-conducting material forms.In another embodiment, substrate 508 is made up of the integral layer with top epitaxial layer.In specific execution mode, integral layer by can include but not limited to silicon, germanium, silicon/germanium, III-V compound semi-conducting material and quartz the monocrystalline of material form, and top epitaxial layer by silicon, germanium can be included but not limited to, the single crystalline layer of silicon/germanium and III-V compound semi-conducting material forms.In another embodiment, substrate 508 is made up of the top epitaxial layer on intermediate insulator layer, and intermediate insulator layer is above lower integral layer.Top epitaxial layer by silicon (that is, to form silicon-on-insulator (SOI) Semiconductor substrate) can be included but not limited to, the single crystalline layer of germanium, silicon/germanium and III-V compound semi-conducting material forms.Insulator layer is by including but not limited to that the material of silicon dioxide, silicon nitride and silicon oxynitride forms.Lower integral layer by can include but not limited to silicon, germanium, silicon/germanium, III-V compound semi-conducting material and quartz the monocrystalline of material form.Substrate 508 and channel region 512 therefore between source area and drain region 510 can comprise dopant impurities atom.In specific execution mode, channel region is the doping of P type, and in alternative embodiments, channel region is N-type doping.
Source area in substrate 508 and drain region 510 can be any districts with the conductivity contrary with channel region 512.Such as, according to the embodiment of the present invention, source area and drain region 510 are N-type doping, and channel region 512 is the doping of P type.In one embodiment, substrate 508 is by having concentration at 1 x 10 15-1 x 10 19atom/cm 3scope in boron carry out boron doped monocrystalline silicon composition.Source area and drain region 510 are by having concentration at 5 x 10 16-5 x 10 19atom/cm 3scope in the phosphorus of N-type dopant or arsenic doping district composition.In specific execution mode, source area and drain region 510 have the degree of depth in the scope of 80-200 nanometer in substrate 508.According to optional execution mode of the present invention, source area and drain region 510 are the doping of P type, and the channel region of substrate 508 is N-type doping.SONOS type equipment 500 is also included in the gate stack 502 above channel region 512, and it comprises ONO lamination 504, grid layer 514 and gate cap 525.ONO lamination 504 also comprises tunnel layer 516, electric charge capture layer 518 and barrier layer 500.
In embodiments, tunnel layer 516 comprises nitride-oxide.Because programming and erasing voltage produce the large electric field of about 10MV/cm of the layer that passes through tunnel, program/erase tunnel current is not the function of tunnel layer thickness, the function of tunnel layer barrier height especially.But, in maintenance (retention) period, there is no electric field, and therefore the loss of electric charge is not the function of barrier height, the function of tunnel layer thickness especially.Do not sacrifice electric charge to improve tunnel current for the operating voltage reduced to keep, in specific execution mode, tunnel layer 516 is nitride-oxides.Nitrogenize is by being incorporated into nitrogen otherwise pure silicon dioxide film and add relative permittivity or the dielectric constant (ε) of tunnel layer.In some embodiments, the tunnel layer 516 of nitride-oxide has the physical thickness identical with using the conventional SONOS-type equipment of pure oxygen tunnel oxide.In specific execution mode, nitrogenize provides the tunnel layer (under normal temperature) of the effective ε had between 4.75 and 5.25, preferably between 4.90 and 5.1.In such execution mode, nitrogenize has the tunnel layer of effective ε of 5.07 under being provided in normal temperature.
In some embodiments, the nitridated tunnel oxides thing of the SONOS equipment of improvement has the physical thickness identical with the SONOS equipment using the routine of pure oxygen tunnel oxide not improve.Usually, the high permittivity of nitridated tunnel oxides thing cause memory layer to charge faster.In such execution mode, electric charge capture layer 518 charges faster than the pure oxygen tunnel oxide with that thickness during program/erase, because reduce (the relatively high permittivity due to nitridated tunnel oxides thing) from the nitridated tunnel oxides thing that relatively least partially penetrates of the large electric field of control gate.These execution modes allow SONOS type equipment 500 with the program/erase voltage reduced operation, still realize the program/erase voltage threshold level (VTPNTE) identical with conventional SONOS-type equipment simultaneously.In specific execution mode, SONOS type equipment 500 uses has the tunnel layer 516 of nitridated tunnel oxides thing, and nitridated tunnel oxides thing has at 1.5nm and 3.0nm and physical thickness preferably between 1.9nm and 2.2nm.
In another embodiment, tunnel layer 516 is kept to reduce improving electric charge at the trap density at substrate interface place by nitrogenize in a particular manner.Nitride-oxide tunnel layer is improved to the execution mode of the physical thickness identical with pure oxygen tunnel oxide, electric charge maintenance can be similar to identical with the pure oxygen tunnel oxide of same thickness.With reference to figure 6, depict the nitrogen concentration profile roughly in an execution mode of tunnel layer 616, nitrogen concentration 614 reduces to limit the silicon nitride (Si contacted with substrate 612 fast towards substrate interface 613 2n 4) formation.The silicon nitride layer comprising polar molecule obviously increases trap density, if existed, is positioned at substrate interface 613 place, thus reduces electric charge maintenance via trap to trap tunnelling.Therefore, by regulating the nitrogen concentration in nitridated tunnel oxides thing, program/erase Vcg can reduce, and the remarkable reduction not in the electric charge of the SONOS equipment improved keeps.As shown in Figure 4 further, close to the tunnel layer 416 at interface 413 thickness 25% be less than about 5 x 10 by nitrogenize to have 21nitrogen-atoms/cm 3nitrogen concentration 414, and close to the tunnel layer 416 of electric charge capture layer 420 thickness 25% by nitrogenize to have at least 5 x 10 21nitrogen-atoms/cm 3.
In one embodiment, the nitrogenize of the oxide in tunnel layer reduces its energy barrier relative to pure-oxide tunnel layer and increases dielectric constant.As shown in Figure 5, tunnel layer 516 is explained in order to illustration purpose center line 517.Fig. 6 describes similar center line 617, and a half thickness of tunnel layer 616 is close to substrate 612, and a half thickness of tunnel layer 616 is close to electric charge capture layer 620.In specific execution mode, nitrogen concentration 614 in whole front 25% thickness of tunnel layer 616 lower than 5 x 10 21atom/cm 3, and reach about 5 x 10 at 50% thickness place of tunnel layer 616 or in centerline 21atom/cm 3.In another embodiment, nitrogen concentration 614 in last 25% thickness of the tunnel layer 616 close to electric charge capture layer 618 higher than 5 x 10 21atom/cm 3.In exemplary realization, for 2.2nm tunnel layer, nitrogen concentration 614 before the tunnel layer close to substrate 612 in 0.6nm lower than 5 x 10 21atom/cm 3, and be at least 5 x 10 at the 1.1nm place of the thickness of tunnel layer 616 21atom/cm 3.By this way, the electric capacity of tunnel layer can increase, and the obvious reduction in the maintenance of the electric charge of the SONOS type equipment do not improved.
Fig. 7 illustrates the curve of description description simulation according to the embodiment of the present invention, and this simulation illustrates the reduction of the program voltage being attributable to nitride-oxide tunnel layer.As shown, exist pure-oxide tunnel layer and the leakage current at the maintenance voltage place of nitride charge trapping layer equals nitride-oxide tunnel layer and electric charge capture layer nitride, and the charging current of nitride-oxide tunnel layer under program voltage is greater than the charging current of pure-oxide tunnel layer.Therefore, under the programming or erasing voltage of 9.1V, nitride-oxide tunnel layer according to the present invention can provide the identical program erase level using 10V programming or erasing voltage to realize with conventional pure-oxide tunnel layer.
Refer back to Fig. 5, the electric charge capture layer 518 of SONOS type equipment 500 also can comprise any usually known charge trapping material, and has any thickness of the threshold voltage being suitable for stored charge and conditioning equipment.In some embodiments, electric charge capture layer 518 is silicon nitride (SiN 4), silicon-rich silicon nitride or silicon rich silicon oxynitride.Silicon-rich film comprises suspension silicon key (draggling silicon bond).In a specific execution mode, electric charge capture layer 518 has uneven stoichiometry in the whole thickness of electric charge capture layer.Such as, electric charge capture layer 518 also can comprise at least two oxynitride layers of the difference composition with silicon, oxygen and nitrogen.Such composition inhomogeneities in electric charge capture layer has a lot of feature performance benefits of the conventional SONOS electric charge capture layer being better than having uniform in fact composition.Such as, the thickness reducing conventional SONOS electric charge capture layer adds trap to trap tunneling rate, causes the loss that data keep.But when the stoichiometry of electric charge capture layer is modified according to the embodiment of the present invention, the thickness of electric charge capture layer can reduce in proportion, still keep good data to keep simultaneously.
In specific execution mode, bottom oxynitride layer 518A is provided in the partial zones in the electric charge capture layer with relatively low-density trapping state, thus the trap density reduced in tunnel oxide interface assists tunnelling with the trap reduced in the SONOS equipment improved.This causes the stored charge loss of the reduction of given charge trapping layer thickness to realize the improvement of electric charge capture layer, for the improvement of ONO lamination EOT.In such execution mode, bottom oxynitride 518A forms to provide the oxynitride of oxygen enrichment by first with high silicon concentration, high oxygen concentration and low nitrogen concentration.This first oxynitride can have the physical thickness between 2.5nm and 4.0nm, and it is corresponding to the EOT between 1.5nm and 5.0nm.In a specific execution mode, bottom oxynitride layer 518A has the effective dielectric constant (ε) of about 6.
In another embodiment, top oxygen nitride layer 518B is provided in the partial zones in the electric charge capture layer with relatively highdensity trapping state.Trapping state this relatively high density enable the electric charge capture layer of the thickness of reduction provide enough to be captured electric charge, it is enough for making memory window keep being captured electric charge in the ONO lamination improved.Therefore, the higher density of trapping state has and is increased in difference between the programming of memory devices and erasing voltage for specific charge trapping layer thickness, allows charge trapping layer thickness to reduce and thus reduces the effect of the EOT of the ONO lamination in the SONOS equipment improved.In specific execution mode, the composition of top oxygen nitride layer has high silicon concentration and high nitrogen concentration and low oxygen concentration to produce the oxynitride of Silicon-rich, oxygen deprivation.Usually, the silicone content of top oxygen nitride is higher, the density of the trapping state provided by top oxygen nitride is higher, and the thickness of top oxygen nitride layer just can reduce more (thus reducing charge trapping layer thickness to realize lower voltage operation).In addition, silicone content is higher, and permittivity is larger and EOT that is top oxygen nitride layer is lower.This reduction of EOT can depart from the increase of the EOT of oxynitride bottom oxygen enrichment greatly, for relative to the clean reduction of EOT of electric charge capture layer of conventional charge trapping oxynitride with in fact uniform composition.In such execution mode, top oxygen nitride has the effective dielectric constant of about 7.
Fig. 7 B describes exemplary secondary ion massspectrum (SIMS) distribution curve that instruction is the concentration of the silicon (Si) of unit, nitrogen (N), oxygen (O) and hydrogen (H) with atom/cm3 after the deposition (having deposited) on tunnel layer, electric charge capture layer and barrier layer.Base condition (" BL ") and dual-layer oxynitride condition (" the bilayer ") overlap as the condition described in Figure 5.Base condition is by having the conventional charge capture layer evenly formed.X-axis represents the degree of depth, and it is 0nm at the exposed top surface place on barrier layer and is passed down through lamination from top to advance, and ends in substrate.As shown, the oxygen concentration of Bilayer condition in the degree of depth district between about 5nm and 10nm of the part corresponding to electric charge capture layer completely lower than l.0 x l0 22atom/cm 3.On the contrary, base condition is presented at and is greater than l.0 x 10 in this same district 22oxygen concentration higher in fact.As further shown, base condition has the oxygen concentration constant in fact between 6nm and 10nm mark, and the Bilayer condition ratio 6nm be presented near 10nm mark marks more in fact oxygen.The transition of this inhomogeneities representative in Bilayer condition bottom oxygen deprivation top oxygen nitride and oxygen enrichment between oxynitride of oxygen concentration.
In some embodiments, the ratio of bottom oxynitride layer thickness and top oxygen nitride layer thickness is between 1:6 and 6:1, and more preferably, bottom oxynitride thickness and the ratio of top oxygen nitride thickness are at least 1:4.Have in the exemplary realization of the physical thickness between 2.5nm and 4.0nm at the first oxynitride, electric charge capture layer 518, second oxynitride 518B for the clean physical thickness had between 7.5nm and 10.0nm has the physical thickness between 5.0nm and 6.0nm.In a specific execution mode, use has the bottom oxynitride of physical thickness, for having the electric charge capture layer of improvement of clean physical thickness, top oxygen nitride has physical thickness.
In these specific execution modes, composition heterogeneity is used for locating trap and be restricted to the embedded location (that is, concentrating trap) at the electric charge capture layer from segment distance place, tunnel layer interface one.Fig. 8 A also illustrate according to the embodiment of the present invention comprise nitridated tunnel oxides thing 816, multilayer electric charge capture oxynitride 818 and the highly dense barrier layer 820 between substrate 812 and control gate 814 improvement SONOS equipment maintenance during energy band diagram.As depicted, the heterogeneity valence band of impact bottom the Silicon-rich top oxygen nitride 818B and oxygen enrichment of electric charge capture layer between oxynitride 818A in the composition of electric charge capture layer 818 and conduction band.As shown in Figure 8 B, electric charge capture layer is according to the embodiment of the present invention provided in the adjustment in the band of the interface of oxygen enrichment in electric charge capture layer 818 and silicon-rich oxy-nitride layer.This band-gap tuning is used for being captured the center coordination of electric charge in top oxygen nitride layer, for given charge trapping layer thickness substrate further away from each other.Conduction band adjustment between oxynitride layer also can be used to reduction and backflows.
As illustrated further in fig. 8 a, in specific execution mode, a part of Silicon-rich top oxygen nitride 818B is oxidized or reoxidize.Relative to such as in order to the pre-oxidation band gap that illustration purpose is depicted as a dotted line in fig. 8 a, such oxidation of Silicon-rich top region can produce the graded bandgap (graded band gap) close to barrier layer 820.In embodiments, only about half of being reoxidized of top oxygen nitride layer 818B has the higher oxygen concentration towards the interface with barrier layer 820.In another embodiment, all in fact top oxygen nitride layer 818B are reoxidized to have the higher oxygen concentration than having deposited.In one embodiment, reoxidize the oxygen concentration in top oxygen nitride layer 818B is added about 0.25 x 10 21-0.35 x 10 21atom/cm.Use such execution mode of reoxidized charge trapping layer can prevent the trap migration at the interface between electric charge capture layer and barrier layer, thus allow charge trapping layer thickness to reduce and do not cause and keep losing to making the thinning relevant electric charge of electric charge capture layer in fact evenly formed.Prevent charge migration from also reducing in the erase period through the electric field of barrier oxide to barrier oxidation nitride layer, this reduce backflowing of electronics, or allow scaled barrier oxide, the electronics simultaneously maintaining phase same level backflows.That the district measured by the different chemical in electric charge capture layer provides and in certain embodiments as the part with electric charge capture layer reoxidize further combined with trap locate and limits and can enable to operate with the erasing time under the voltage reduced or to programme faster according to the SONOS equipment of improvement of the present invention, maintain good memory maintenance simultaneously.
Although be depicted as in the accompanying drawings and in other place herein and only have two oxynitride layers, namely, top layer and bottom, but the present invention is not necessarily so limited, and plurality of charge storage layers can comprise the oxynitride layer of any quantity n, its any or all there is the difference composition of oxygen, nitrogen and/or silicon.Particularly, the plurality of charge storage layers with nearly five oxynitride layers of different composition has been produced and has been tested.
As described further in Figure 5, the barrier layer 520 of ONO lamination 504 is included in approximately approximately between layer of silicon dioxide.The improvement on the barrier layer 520 in the ONO lamination of SONOS type equipment is valuable, because if completed improperly, adversely can be increased in some bias condition download stream backflowing from control gate.In the execution mode comprising part reoxidized charge trapping layer, barrier layer 520 is high-temperature oxides (HTO) larger than the relative density deposited.Highly dense oxide has end hydrogen or the hydroxyl bond of lower percentage.Such as, hydrogen or water have from the removal of HTO oxide increases film density and the effect improving the quality of HTO oxide.The oxide of better quality enables layer improve on thickness.In one embodiment, hydrogen concentration is greater than 2.5 x 10 deposited 20atom/cm 3, and be reduced in highly dense film lower than 8.0 x 10 19atom/cm 3.In the exemplary embodiment, the thickness of HTO oxide between 2.5nm and 10.0nm deposited, and Anywhere when densification thinning about 10% to 30%.
In alternative embodiments, barrier oxidation nitride layer is modified to comprise nitrogen further.In such execution mode, nitrogen is involved on the whole thickness of barrier oxidation nitride layer with the form of ONO lamination.Such sandwich replaces conventional pure oxygen barrier layer, and the EOT desirably reducing the whole lamination between raceway groove and control gate and the adjustment realizing band skew are to reduce the anti-injection of charge carrier.ONO barrier layer can then merge with nitrogenize tunnel oxide and the electric charge capture layer comprising bottom oxynitride layer and top oxygen nitride layer.
Is grid layer 514 above ONO lamination 504.Grid layer 514 can be any conductor or semi-conducting material.In such execution mode, grid layer 514 is polysilicon (poly).In another embodiment, grid layer 514 comprises metal, such as but not limited to hafnium, zirconium, titanium, tantalum, aluminium, ruthenium, palladium, platinum, cobalt and nickel and silicide, its nitride and its carbide.In a specific execution mode, grid layer 514 is the polysilicons of the physical thickness had between 70nm and 250nm.
As illustrated further in Figure 5, SONOS type equipment 500 comprises pole adjacent to the gate cap 525 of grid layer 514 to be had and grid layer 514 and the approximately uniform critical dimension of ONO lamination 504 (critical dimension).In some embodiments, gate cap 525 forms the top layer of gate stack 502, and provides hard mask during the patterning of grid layer 514 and ONO lamination 504.In some embodiments, gate cap 525 is convenient to autoregistration contact (SAC) and is formed into SONOS equipment.Gate cap 525 can form by providing etch process subsequently necessary optionally any material (such as but not limited to silicon dioxide, silicon nitride and silicon oxynitride).
In a specific execution mode, SONOS type equipment use ONO lamination, it comprises and has corresponding to approximately physical thickness eOT nitridated tunnel oxides thing, comprise and have corresponding to approximately physical thickness eOT bottom oxynitride layer and have corresponding to approximately physical thickness eOT top oxygen nitride layer electric charge capture layer and deposit to and arrived by densification barrier oxidation nitride layer.Such SONOS type equipment can operate at the voltage range place of about 9V, to provide the initial erase voltage threshold level (VTE) of-2V after 1ms to 10ms pulse.
Fig. 9 describes for the manufacture of comprising nitride-oxide tunnel layer as above, by the flow chart of the method for the SONOS of the improvement of the SONOS such as described in Figure 5 of the multilayer electric charge capture oxynitride that partly reoxidizes and highly dense barrier oxidation nitride layer.The manufacture method of Fig. 9 starts to form nitride-oxide tunnel layer in operation 900 in the siliceous surface of substrate.Figure 10 describes the flow chart for the formation of the ad hoc approach of the nitride-oxide of the operation 900 in Fig. 9.
In the execution mode described in Fig. 10, multi-step nitrogenize and method for oxidation is used to realize the adjustment (tailoring) of the nitrogen distribution curve in the nitridated tunnel oxides thing of SONOS type equipment.In operation 1001, thin thermal oxide is formed by the silicon-containing layer on the surface of the substrate of the substrate 508 at such as Fig. 5.Because be necessary with the good interface of substrate, the formation of chemical oxide can before thermal oxidation.In specific execution mode, therefore chemical oxide exists (contrary with performing routine " HF is last " prerinse) during thermal oxidation.In such execution mode, chemical oxide is along with the aquatic length of ozonisation is to form the chemical oxide layer with the thickness of about 1.0nm.
Thermal oxide is formed into the thickness between about 1.0nm and 1.8nm.In specific execution mode, thermal oxide is formed into the thickness between 1.0nm and 1.2nm.Therefore, in the execution mode existed during the thermal oxidation of operation 501 at 1.0nm chemical oxide, the thickness of oxide on surface does not increase in fact, but the quality of oxide but improves.In another embodiment, oxide has relatively low density so that subsequently in conjunction with the nitrogen of quite a lot of wt%.But the too many nitrogen that too low film density will cause at silicon substrate interface place.The formation of the silicon dioxide layer in operation 501 is further as the means that the Heat Treatment subsequently discussed further below stops extra liner oxide to be formed.In one embodiment, atmospheric pressure vertical thermal reactor (VTR) is at oxidizing gas such as oxygen (O 2), nitrogen dioxide (N 2o), nitric oxide (NO), ozone (O 3) and steam (H 2grow under making the temperature of thermal oxide between 680 DEG C and 800 DEG C when O) existing.According to selected oxidant, the oxidation of operation 1001 can from 3.5 minutes to 20 minutes on the duration.In an air execution mode, the one period processing time of oxygen between 7 minutes and 20 minutes at the temperature between 700 DEG C and 750 DEG C, is used to define the silicon dioxide film of about 1.0nm.
In another embodiment, use commercially performs oxidation operation 1001 from the commercially available sub-atmospheric pressure processor of the AVIZA technology company of California Scotts Valley such as premium vertical processor (AVP).AVP can above-described for the temperature range of VTR execution mode in and 1 holder (T) and atmospheric pressure between pressure under operate.According to operating pressure, the oxidization time forming the hot titanium dioxide SiClx film of thickness between about 1.0nm and 1.8nm can extend to almost one hour, as determined by those skilled in the art.
Then, operation 1002 place in the polyoxygenated nitriding method execution mode described in Fig. 10, operation 1001 formed thermal oxide by nitrogenize.Usually, in operation 1002, n2 annealing is performed to increase dielectric constant (K) and the fixed charge reducing thermal oxide layer.In one embodiment, n2 annealing uses nitrogen (N 2) or hydrogenated nitrogen source such as ammonia (NH 3).In another embodiment, n2 annealing uses deuterate nitrogenous source, such as ammonia, deuterated (ND 3).In a specific execution mode, at the temperature of n2 annealing between 700 DEG C and 850 DEG C, be executed at a period of time between 3.5 minutes and 30 minutes.In another specific execution mode, at the temperature of n2 annealing between 725 DEG C and 775 DEG C, be executed at a period of time between 3.5 minutes and 30 minutes.In such execution mode, NH 3the a period of time between 3.5 minutes and 30 minutes is introduced at temperature at atmosheric pressure between 725 DEG C and 775 DEG C.In alternative embodiments, sub-atmospheric pressure NH 3annealing in the processor of such as AVP 800 DEG C to 900 DEG C at be executed at a period of time of 5 minutes to 30 minutes.In other execution mode other, perform usually known nitrogen plasma and thermal annealing combination.
After operation 1002, perform in operation 1004 and reoxidize.In one embodiment, during reoxidizing process, oxidizing gas by thermal spalling to provide the oxygen radical close to film surface.Oxygen radical eliminates nitrogen and hydrogen is captured electric charge.Reoxidation operation 1002 also makes to grow at the extra oxide at substrate interface place to be provided in the physical deflection between the nitrogen concentration in substrate and tunnel layer.Such as, refer back to Fig. 5, reoxidize and help to separate substrate interface 513 and the nitrogen concentration in tunnel layer 516.As specifically illustrated in figure 6, for a realization, be starkly lower than 5 x 10 at the nitrogen concentration 614 at substrate interface 613 place in tunnel layer 616 21atom/cm 3, and can be 5 x 10 20atom/cm 3magnitude.The maintenance that improve SONOS type equipment is offset with this nitrogen of substrate interface.In one embodiment, be limited between 1.2nm and 3.0nm at the thickness of the oxide of substrate interface 613 place growth.In operation 1004, reoxidize process condition and selected, make the oxidation outside the thickness that the thickness of the thermal oxide of operation 1001 formation prevents from exceeding about 3.0nm, it can cause tunnel layer to lack any favourable nitrogen concentration.Usually known oxidant can be used for reoxidizing process, such as but not limited to NO, N 2o, O 2, O 3and steam.The known annealer operated under can being used in the temperature between 800 DEG C and 850 DEG C introduces any such oxidant.According to operating parameter, the time of reoxidizing can be about 5 minutes to 40 minutes.In specific execution mode, use in the atmospheric pressure reacting furnace operated at the temperature between 800 DEG C and 850 DEG C NO one period of processing time of about 15 minutes with formed on a silicon substrate on thickness for the nitride-oxide film of about 2.2nm.In such execution mode, what 2.2nm was thick reoxidize film formed close to and the district between 0.5nm and 0.8nm at interface of silicon substrate, this district has lower than 5 x 10 21atom/cm 3nitrogen concentration.
After the reoxidizing of operation 1004, perform the second n2 annealing to make tunnel layer nitrogenize again in operation 1006.Second n2 annealing is used for the dielectric constant of increase tunnel layer further and adversely introduces a large amount of hydrogen or nitrogen trap at substrate interface place.In one embodiment, the second n2 annealing of the condition executable operations 1006 identical with the annealing performed in operation 1002 is used.In another embodiment, at the temperature that the first n2 annealing than operation 1002 is higher second n2 annealing of executable operations 1006 so that extra nitrogen is introduced in tunnel layer.In one embodiment, n2 annealing uses hydrogenated nitrogen source, such as NH 3.In another embodiment, n2 annealing uses deuterate nitrogenous source, such as ND 3.In specific execution mode, the n2 annealing of operation 1006 uses NH under atmospheric pressure and the temperature between 750 DEG C and 950 DEG C 3one period of processing time between 3.5 minutes and 30 minutes.In another specific execution mode, NH 3anneal at the temperature of atmospheric pressure between 800 DEG C and 850 DEG C, to be executed at a period of time between 5 minutes and 10 minutes.
As described, the operation 1001 to 1006 described in Fig. 10 provides two oxidation operation and two nitridation operations.The increase that the specific adjusted that the oxidation of the repetition described, nitridation scheme realize the nitrogen concentration in tunnel layer keeps with the memory of the increase of the reduction or program speed that realize program voltage and SONOS type equipment.Oxidation, nitrogenize, reoxidize, again the Continuous property of nitridation operations 1001-1006 realize the estimable nitrogen concentration that is less than in the thick tunnel layer of 3.0nm, the interface between tunnel layer and substrate with considerably less nitrogen and hydrogen trap is provided simultaneously.Independently oxidation, nitrogenize, reoxidize, the degree of freedom larger when nitridation operations 1001-1006 enables the first and second oxidations and the first and second nitrogenize be performed to be provided in the nitrogen concentration profile in adjustment tunnel layer with the condition designed separately again.In a favourable execution mode, operation 1001,1002,1004 and 1006 is continuously performed in single annealer, and between operations not from processor moving substrate.In such execution mode, processing pressure keeps under atmospheric pressure operation 1001-1006.First, oxidation operation 1001 is performed at the temperature between 700 DEG C and 750 DEG C.Gas flow being modified with the n2 annealing of executable operations 1002 at the temperature between 725 DEG C and 755 DEG C then as regulation.Then reacting furnace temperature climbs between 800 DEG C and 850 DEG C, and gas flow is modified reoxidizing with executable operations 1004 again.Finally, when being remained between 800 DEG C and 850 DEG C by reacting furnace, gas flow is modified the second nitrogenize annealing with executable operations 1006 again.
When the nitride-oxide tunnel layer 516 of Fig. 5 completes in fact, the manufacture of ONO lamination continues by the method that turns back to Fig. 9 and describe.In one embodiment, in low pressure chemical vapor deposition process, such as silane (SiH is used in operation 902 and 904 4), dichlorosilane (SiH 2cl 4), silicon tetrachloride (SiCl 4) or the silicon source of BisTertiaryButylAmino silane (BTBAS); Such as N 2, NH 3, N 2o or nitrogen peroxide (NO 3) nitrogenous source; And such as O 2and N 2the oxygen-containing gas of O forms multiple nitride or charge trapping oxynitride.Alternatively, can use gas, wherein hydrogen is replaced by deuterated, comprises such as ND 3replace NH 3.The deuterated silicon dangling bonds passivation advantageously making at substrate interface place for hydrogen, thus increase NBTI (Negative Bias Temperature Instability) life-span of SONOS type equipment.
In an exemplary realization, in operation 902, charge trapping oxynitride (comprises N by be placed on by substrate in settling chamber and to introduce process gas 2o, NH 3and DCS) be deposited on above tunnel layer, settling chamber to be maintained from about 5 millitorrs (mT) to the pressure of about 500mT simultaneously and substrate is maintained from about 700 DEG C to about 850 DEG C and a period of time more preferably continued the temperature of at least about 780 DEG C from 2.5 minutes to about 20 minutes.In another embodiment, process gas and can comprise the N mixed with the ratio from about 8:1 to about 1:8 2o and NH 3the first admixture of gas and the SiH that mixes with the ratio from about 1:7 to about 7:1 2cl 2and NH 3the second admixture of gas, and can be introduced under the flow rate of about 200 standard cubic centimeters (sccm) from per minute about 5.Find, produce under these conditions or the oxynitride layer generation Silicon-rich of deposition, the oxynitride layer of oxygen enrichment, the electric charge capture layer 518A such as described in Figure 5.The formation of electric charge capture layer also can relate to the CVD technique in operation 904, and it is used in the N mixed with the ratio from about 8:1 to about 1:8 be introduced into the flow rate of about 20sccm from about 5sccm 2o and NH 3the first admixture of gas and the SiH that mixes with the ratio from about 1:7 to about 7:1 2cl 2and NH 3the second admixture of gas produce the oxynitride layer of Silicon-rich, oxygen enrichment and oxygen deprivation, the electric charge capture layer 518B such as described in Figure 5.
In one embodiment, be sequentially performed in the same place grooming tool being formed in for the formation of tunnel layer of the electric charge capture layer in operation 902 and 904 and between operation 901 and 904, substrate do not unloaded from settling chamber.In specific execution mode, electric charge capture layer is deposited, and does not change substrate during the second n2 annealing of the operation 1006 of Figure 10 by temperature during heating.In one embodiment, by amendment NH 3the flow rate of gas also introduces N 2o and SiH 2cl 2expect that gas is than to produce Silicon-rich and oxygen-rich layer, Silicon-rich and rich nitrogen oxynitride layer in realizing at bilayer or this two layers come sequentially and and then charge trapping layer after the nitrogenize of the tunnel layer of operation 901 to provide.
After operation 904, form barrier layer by any suitable means (comprise such as thermal oxidation or use the deposition of CVD technology) in operation 906.In a preferred embodiment, high temperature CVD process is used to form barrier layer.Usually, depositing operation relates to is providing such as SiH from about 50mT in settling chamber under the pressure of about 1000mT 4, SiH 2cl or SiCl 4silicon source and such as O 2or N 2the oxygen-containing gas of O, carries out a period of time from about 10 minutes to about 120 minutes, is maintained by substrate from the temperature of about 650 DEG C to about 850 DEG C simultaneously.Preferably, sequentially deposited barrier layer in the same place grooming tool for forming electric charge capture layer in operation 902 and 904.More preferably, in the handling implement all identical with tunnel layer with electric charge capture layer, barrier layer is formed and not moving substrate between operations.
In the execution mode that Fig. 9 describes, the barrier layer deposited in operation 906 is reoxidized to make barrier layer oxide closely knit in operation 908.As herein other is locally discussed, operation 908 can be oxidized further or part or all (the electric charge capture layer 518B such as shown in Fig. 5 part or all) of reoxidized charge trapping layer to realize the graded bandgap such as described in fig. 8 a.Usually, such as oxygen (O can be there is 2), nitrous oxide (N 2o), nitric oxide (NO), ozone (O 3) and steam (H 2perform when oxidizing gas O) and reoxidize.In one embodiment, perform at the temperature that the temperature when being deposited than barrier layer is high and reoxidize process.Reoxidizing after the deposition on barrier layer is oxidized or reoxidizes thin electric charge capture layer with making the more controlled diffusion-controllable of oxidant.In particularly advantageous execution mode, use dilution wet oxidation.Dilution wet oxidation is different from wet oxidation, because H 2: O 2than between 1 and 1:3.In a specific execution mode, at the temperature between 800 DEG C and 900 DEG C, perform the H with about 1:2 2: O 2the dilution oxidation of ratio.In another embodiment, the duration of dilution oxidation can be enough to grow the silicon dioxide between 5.0nm and 12.5nm on a silicon substrate.In such execution mode, the silicon dioxide layer of duration to about 10nm to 1.1nm is on a silicon substrate enough.Such dilution oxidizing process for reoxidizing the barrier layer oxide of deposition, and can be oxidized further or the part of reoxidized charge trapping layer to give band structure, as the band structure described in Fig. 8 A or 8B.In another embodiment, reoxidizing of operation 908 can be used for being formed in the gate oxide in non-SONS type battery limits (such as, for complementary metal oxide silicon (CMOS) field-effect transistor (FET) on the substrate identical with SONOS type equipment) further.In another embodiment, reoxidizing of operation 908 can be used for being diffused into by deuterium in the electric charge capture layer of SONOS type equipment or the part on barrier layer further.
As described in fig .9, method can then terminate with the formation of the grid layer 514 of grid layer such as Fig. 5 in operation 910.In some embodiments, the formation that 910 also can comprise the gate cap 525 that gate cap is such as described in Figure 5 is operated.When gate stack manufacture terminates, further can there is the manufacture terminating SONOS type equipment 300 in process as known in the art.
Although with architectural feature and/or method action distinctive language description the present invention, should be understood that the present invention defined in the following claims might not be limited to described special characteristic or action.Disclosed special characteristic and action should be understood to the realization of the appropriateness especially of advocated invention, to illustrate instead of restriction the present invention.
Realize and possibility
Figure 11 illustrates the cross-sectional side view of intermediate structure of SONOS type equipment 1100 of ONO structure of improvement having and comprise nitride-oxide tunnel layer, multilayer electric charge capture layer and highly dense barrier layer.It should be understood that other SONOS execution mode various disclosed herein also can be used for producing ONO lamination that is outside the particular implementation described in fig. 11 but still also exercisable improvement under the program/erase voltage reduced.Therefore, although the feature of Figure 11 can be mentioned in whole description, the invention is not restricted to this specific execution mode.
In the particular implementation shown in Figure 11, SONOS type memory devices 1100 comprises SONOS gate stack 1102, and it is included in the ONO lamination 1104 formed above the surface 1106 of substrate 1108.SONOS type memory devices 1100 also comprises and aliging and the one or more source area be electrically connected by channel region 1112 and drain region 1110 with gate stack 1102.Usually, formed on the ONO lamination 1104 that the SONOS gate stack 1102 of improvement is also included in improvement and the grid layer 1114 contacted with the ONO lamination 1104 improved and the gate cap 1125 above grid layer 1114.Grid layer 1114 is separated or electric isolution with substrate 1108 by the ONO lamination 1104 improved.
In one embodiment, substrate 1108 is by the bulk substrate that can include but not limited to silicon, germanium, the monocrystalline of material of silicon-germanium or III-V compound semi-conducting material forms.In another embodiment, substrate 1108 is made up of the integral layer with top epitaxial layer.In specific execution mode, integral layer by can include but not limited to silicon, germanium, silicon/germanium, III-V compound semi-conducting material and quartz the monocrystalline of material form, and top epitaxial layer by silicon, germanium can be included but not limited to, the single crystalline layer of silicon/germanium and III-V compound semi-conducting material forms.In another embodiment, substrate 1108 is made up of the top epitaxial layer on intermediate insulator layer, and intermediate insulator layer is above lower integral layer.Top epitaxial layer by silicon (that is, to form silicon-on-insulator (SOI) Semiconductor substrate) can be included but not limited to, the single crystalline layer of germanium, silicon/germanium and III-V compound semi-conducting material forms.Insulator layer is by including but not limited to that the material of silicon dioxide, silicon nitride and silicon oxynitride forms.Lower integral layer by can include but not limited to silicon, germanium, silicon/germanium, III-V compound semi-conducting material and quartz monocrystalline form.Substrate 1108 and channel region 1112 therefore between source area and drain region 1110 can comprise dopant impurities atom.Channel region 1112 can comprise the polysilicon of polysilicon or recrystallization to form monocrystalline channel region.Comprise in channel region 1112 in the specific execution mode of monocrystalline silicon, channel region can be formed the <100> surface crystal orientation of the major axis had relative to channel region.
Source area in substrate 1108 and drain region 1110 can be any districts with the conductivity contrary with channel region 1112.Such as, according to the embodiment of the present invention, source area and drain region 1110 are N-type doping, and channel region 1112 is the doping of P type.In one embodiment, substrate 1108 is by having at 1 x 10 15-1 x 10 19atom/cm 3scope in boron concentration boron doped single crystal silicon composition.Source area and drain region 1110 are by having at 5 x 10 16-5 x 10 19atom/cm 3scope in the phosphorus of concentration of N-type dopant or arsenic doping district composition.In specific execution mode, source area and drain region 1110 have the degree of depth in the scope of 80-200 nanometer in substrate 1108.According to optional execution mode of the present invention, source area and drain region 1110 are the doping of P type, and the channel region of substrate 1108 is N-type doping.
ONO lamination 1104 comprises tunnel layer 1116, multilayer electric charge capture layer 1118 and barrier layer 1120.
In one embodiment, tunnel layer 1116 is the nitride-oxide tunnel layers comprising nitride-oxide.Because programming and erasing voltage produce the large electric field of the 10MV/cm magnitude of the layer that passes through tunnel, program/erase tunnel current is not only the function of tunnel layer thickness, especially the function of tunnel layer barrier height.But, during keeping, there is no large electric field, and therefore the function of barrier height is not only in the loss of electric charge, especially the function of tunnel layer thickness.Nitrogenize increases relative permittivity or the dielectric constant (ε) of tunnel layer, and this improves tunnel current for the operating voltage reduced.In specific execution mode, nitrogenize provides (under normal temperature) has the tunnel layer 1116 of the effective ε between 4.75 and 5.25 and preferably between 4.90 and 5.1.In such execution mode, nitrogenize has the tunnel layer of effective ε of 5.07 under being provided in normal temperature.
In such execution mode, multilayer electric charge capture layer 1118 charges faster than the pure-oxide tunnel layer with that thickness during program/erase, because reduce (the relatively high permittivity due to nitridated tunnel oxides thing) from the nitride-oxide tunnel layer that relatively least partially penetrates of the large electric field of control gate.These execution modes allow SONOS type memory devices 1100 with the program/erase voltage reduced operation, still realize the program/erase voltage threshold level (VTPNTE) identical with conventional SONOS-type equipment simultaneously.
In some embodiments, nitride-oxide tunnel layer has the physical thickness identical with using the conventional SONOS equipment of pure-oxide tunnel layer, does not sacrifice electric charge keep to improve tunnel current for the operating voltage reduced.In some embodiments, SONOS type memory devices 1100 uses the nitride-oxide tunnel layer 1116 of the thickness had between 1.5nm and 3.0nm and more preferably between 1.9nm and 2.2nm.In the particular implementation shown in Figure 11 B, nitride-oxide tunnel layer 1116 comprises having and is less than about 5 x 10 21nitrogen-atoms/cm 3nitrogen concentration the first district 1116A close to channel region 1112 and there are at least 5 x 10 21nitrogen-atoms/cm 3the second district 1116B close to multilayer electric charge capture layer 1118 of nitrogen concentration.In the execution mode of shown in Figure 11 B, the firstth district of nitride-oxide tunnel layer 1116 and the secondth district each comprise no more than about 25% tunnel layer thickness.
In another embodiment, multilayer electric charge capture layer 1118 comprises at least two-layer multilayer electric charge capture layer 1118, this two-layer difference composition with silicon, oxygen and nitrogen.In one embodiment, multilayer charge trapping region comprises oxygen enrichment ground floor 1118A and oxygen deprivation second layer 1118B, oxygen enrichment ground floor 1118A comprise in fact without trap, Silicon-rich, oxygen enrichment nitride, oxygen deprivation second layer 1118B comprise trap intensive, Silicon-rich, rich nitrogen and oxygen deprivation nitride.Find, oxygen enrichment ground floor 1118A reduces charge loss rate after programming and after an erase, and this is illustrated in small voltage drift in Holdover mode.Oxygen deprivation second layer 1118B improves speed and adds the initial difference between programming and erasing voltage, and the charge loss rate of the memory devices that the execution mode not endangering use silicon-oxide-oxynitride-oxide-silicon structure manufactures, thus extend the operation lifetime of equipment.
In another embodiment, multilayer electric charge capture layer 1118 is multilayer electric charge capture layers separately, and it comprises intermidate oxide further or comprises the anti-tunnel layer 1118C of the oxide separated by oxygen enrichment ground floor 1118A and oxygen deprivation second layer 1118B.Between the erasing period of memory devices 1100, hole is moved towards barrier layer 1120, but most of trap hole charge is formed in oxygen deprivation second layer 1118B.Electron charge accumulates in the boundary of oxygen deprivation second layer 1118B after programming, and therefore has less charge buildup at the lower boundary place of oxygen enrichment ground floor 1118A.In addition, due to anti-tunnel layer 1118C, the probability of the tunnelling caused by the trapped electron electric charge in oxygen deprivation second layer 1118B substantially reduces.This can cause the leakage current low relative to conventional memory devices.
Although be shown above and be described as that there are two nitride layers, namely, ground floor and the second layer, but the present invention is not necessarily so limited, and multilayer electric charge capture layer 1118 can comprise oxide, nitride or oxynitride layer that quantity is n, its any or all can have the different chemical metering composition of oxygen, nitrogen and/or silicon.Particularly, with each nearly five and may the multilayer charge storage structure of more nitride layer be conceived to different chemical metering composition.At least some in these layers is separated by the oxide skin(coating) of one or more relative thin and other layer.But, as those of skill in the art will recognize, utilize the least possible layer normally desirable to realize expected result, decrease the necessary treatment step of production equipment, and thus provide manufacture process that is simpler and more robust.And, utilize the least possible layer also to cause higher output because control the stoichiometric composition of less layer and size simpler.
In another embodiment, barrier layer 1120 comprises the high-temperature oxide (HTO) larger than the relative density deposited.Highly dense HTO oxide has end hydrogen or the hydroxyl bond of lower percentage.Such as, hydrogen or water have from the removal of HTO oxide increases film density and the effect improving the quality of HTO oxide.The oxide of better quality enables layer improve on thickness.In one embodiment, hydrogen concentration is greater than 2.5 x 10 deposited 20atom/cm 3, and be reduced in highly dense film lower than 8.0 x 10 19atom/cm 3.In the exemplary embodiment, the thickness comprising the barrier layer 1120 of highly dense HTO oxide be deposited between 2.5nm and 10.0nm, and when densification in each place all thinning about 10% to 30%.
In alternative embodiments, barrier layer 1120 is modified further in conjunction with nitrogen.In such execution mode, nitrogen is combined in the whole thickness on barrier layer 1120 with the form of ONO lamination.Such sandwich replaces conventional pure oxygen barrier layer desirably reduce the EOT of the whole lamination between channel region 1112 and control gate 1114 and realize being with the adjustment of skew to reduce the anti-injection of charge carrier.ONO lamination barrier layer 1120 can then be combined with nitride-oxide tunnel layer 1116 and the multilayer electric charge capture layer 1118 separated comprising oxygen enrichment ground floor 1118A and oxygen deprivation second layer 1118B and anti-tunnel layer 1118C.
Flow chart referring now to Figure 12 describes the method for memory devices comprising nitride-oxide tunnel layer, the multilayer electric charge capture layer separated and highly dense barrier layer according to the formation of an execution mode or manufacture.
With reference to Figure 12, the method starts with the channel region forming the polysilicon be included in the surface of substrate or on surface in operation 1200, the source area in channel region electrical connection substrate and drain region.As mentioned above, channel region can comprise P type or N-type dopant impurity atoms.In specific execution mode, channel region is doped, and in alternative embodiments, channel region is doped.Can adulterate with the dopant impurities atom contrary with channel region type in source electrode and drain region.Such as, according to a specific execution mode, source area and drain region are used in 5 x 10 16-5 x 10 19atom/cm 3scope in the phosphorus of N-type doping of concentration or arsenic doping district, and channel region is used in 1 x 10 15-1 x 10 19atom/cm 3scope in the boron of concentration carry out the doping of P type.
In operation 1202, the substrate of the tunnel layer comprising nitride-oxide side is over the channel region formed.Usually, comprise the tunnel layer of nitride-oxide by making substrate thermal oxidation to form oxidation film, after be make oxidation film nitrogenize.Because be necessary with the good interface of substrate, so can be the formation of chemical oxide before the formation of thermal oxidation.In specific execution mode, chemical oxide utilizes the water of ozonisation and grows to be formed the chemical oxide layer of the thickness with about 1.0nm.Then thermal oxide is formed into the thickness between about 1.0nm and 1.8nm.Preferably, oxide has relatively low density so that subsequently in conjunction with the nitrogen of quite a lot of wt%.But the too many nitrogen that too low film density will cause at silicon substrate interface place.In one embodiment, atmospheric pressure vertical thermal reactor (VTR) is at oxidizing gas such as oxygen (O 2), nitrous oxide (N 2o), nitric oxide (NO), ozone (O 3) and steam (H 2grow under making the temperature of thermal oxide between 680 DEG C and 800 DEG C when O) existing.According to selected oxidant, the oxidation of operation 1001 can from 3.5 minutes to 20 minutes on the duration.In an atmospheric execution mode, at the temperature between 700 DEG C and 750 DEG C, use O 2the one period processing time of gas between 7 minutes and 20 minutes defines the silicon dioxide film of about 1.0nm.
In another embodiment, use commercially forms thermal oxide from the commercially available sub-atmospheric pressure processor of the AVIZA technology company of California Scotts Valley such as premium vertical processor (AVP).AVP can above to VTR execution mode describe temperature range in and 1 holder (T) and atmospheric pressure between pressure under operate.According to operating pressure, the oxidization time being formed in the thermal silicon dioxide film on thickness between about 1.0nm and 1.8nm can extend to close to one hour always, as determined by those skilled in the art.
Then, n2 annealing is performed to make tropical resources to increase dielectric constant (K) and to reduce the fixed charge of thermal oxide layer.In one embodiment, n2 annealing uses nitrogen (N 2) or hydrogenated nitrogen source such as ammonia (NH 3).In another embodiment, n2 annealing uses deuterate nitrogenous source, such as ammonia, deuterated (ND 3).In a specific execution mode, at the temperature of n2 annealing between 700 DEG C and 850 DEG C, be executed at a period of time between 3.5 minutes and 30 minutes.In another specific execution mode, at the temperature of n2 annealing between 725 DEG C and 775 DEG C, be executed at a period of time between 3.5 minutes and 30 minutes.In such execution mode, NH 3the a period of time between 3.5 minutes and 30 minutes is introduced at temperature at atmosheric pressure between 725 DEG C and 775 DEG C.In alternative embodiments, sub-atmospheric pressure NH 3annealing in the processor of such as AVP 800 DEG C to 900 DEG C at be executed at a period of time of 5 minutes to 30 minutes.In other execution mode other, perform usually known nitrogen plasma and thermal annealing combination.
Alternatively, form nitride-oxide tunnel layer also to comprise by substrate is exposed to O 2oxide is reoxidized, and by substrate, nitride-oxide film are exposed to NO to make the nitride-oxide nitrogenize again reoxidized.In one embodiment, during reoxidizing process, oxidizing gas by thermal spalling to provide the oxygen radical close to film surface.Oxygen radical eliminates nitrogen and hydrogen trap electric charge.The process that reoxidizes also makes the extra oxide growth of the interface between substrate and tunnel layer to be provided in the physical deflection between the nitrogen concentration in substrate and tunnel layer.Such as, refer back to Figure 11 A and 11B, in one embodiment, the nitrogen concentration in tunnel layer 1116A is starkly lower than the nitrogen concentration in tunnel layer 1116B.The maintenance that improve SONOS type equipment is offset with this nitrogen of substrate interface.In one embodiment, be limited between 1.2nm and 3.0nm at the thickness of the oxide of substrate interface place growth.Reoxidizing in process, condition is selected, and makes the thickness of the thermal oxide formed in operation 1001 prevent the oxidation exceeded outside the thickness of about 3.0nm, and it can cause tunnel layer to lack any favourable nitrogen concentration.Usually known oxidant can be used for reoxidizing process, such as but not limited to NO, N 2o, O 2, O 3and steam.The known annealer operated under can being used in the temperature between 800 DEG C and 850 DEG C introduces any such oxidant.According to operating parameter, the time of reoxidizing can be about 5 minutes to any time in 40 minutes.In specific execution mode, in the atmospheric pressure reacting furnace operated at the temperature between 800 DEG C and 850 DEG C, use NO one period of processing time of about 15 minutes to form the nitride-oxide film that thickness is about 2.2nm on a silicon substrate.In such execution mode, what 2.2nm was thick reoxidize film formed close to and the district between 0.5nm and 0.8nm at interface of silicon substrate, this district has lower than 5 x 10 21atom/cm 3nitrogen concentration.
After reoxidation operation, perform the second n2 annealing and reoxidize to make tunnel layer.Second n2 annealing is used for the dielectric constant of increase tunnel layer further and adversely introduces a large amount of hydrogen or nitrogen trap at substrate interface place.In one embodiment, use performs the second n2 annealing with initial or that the first n2 annealing is identical condition.In another embodiment, at the temperature higher than the first n2 annealing, the second n2 annealing of nitridation operations is performed again to be introduced in tunnel layer by extra nitrogen.In one embodiment, n2 annealing uses hydrogenated nitrogen source, such as NH 3.In another embodiment, n2 annealing uses deuterate nitrogenous source, such as ND 3.In specific execution mode, the second n2 annealing uses NH under atmospheric pressure and the temperature between 750 DEG C and 950 DEG C 3one period of processing time between 3.5 minutes and 30 minutes.In another specific execution mode, NH 3anneal at the temperature of atmospheric pressure between 800 DEG C and 850 DEG C, to be executed at a period of time between 5 minutes and 10 minutes.
As described, operate 1202 and reoxidize and again nitrogenize two oxidation operation and two nitridation operations are provided.The increase that the specific adjusted that the oxidation of the repetition described, nitridation scheme realize the nitrogen concentration in tunnel layer keeps with the storage of the increase of the reduction or program speed that realize program voltage and SONOS type memory devices.Oxidation, nitrogenize, reoxidize, again the Continuous property of nitridation operations realize the estimable nitrogen concentration that is less than in the thick tunnel layer of 3.0nm, the interface between tunnel layer and substrate with considerably less nitrogen and hydrogen trap is provided simultaneously.Independently oxidation, nitrogenize, reoxidize, the degree of freedom larger when nitridation operations enables the first and second oxidations and the first and second nitrogenize be performed to be provided in the nitrogen concentration profile in adjustment tunnel layer with the condition designed separately again.In a favourable execution mode, operate in single annealer and be continuously performed, and between operations not from processor moving substrate.In such execution mode, processing pressure remains on atmospheric pressure place.First, the first oxidation operation is performed at the temperature between 700 DEG C and 750 DEG C.Gas flow being modified with operation at the temperature between 725 DEG C and 755 DEG C thus performing n2 annealing then as regulation.Then reacting furnace temperature climbs between 800 DEG C and 850 DEG C, and gas flow is modified to perform reoxidation operation again.Finally, when being remained between 800 DEG C and 850 DEG C by reacting furnace, gas flow is modified to perform the second nitrogenize annealing operation again.
In operation 1204, multilayer electric charge capture layer is formed on nitride-oxide tunnel layer.Usually, multilayer electric charge capture layer comprise in fact without trap, the oxygen deprivation second layer that Silicon-rich, oxygen enrichment ground floor and trap are intensive.In some embodiments, multilayer electric charge capture layer is the multilayer electric charge capture layer separated comprising anti-tunnel layer further, and anti-tunnel layer comprises oxide ground floor and the second layer separated.
In specific execution mode, in low pressure chemical vapor deposition process, use such as silane (SiH 4), chlorosilane (SiH3Cl), dichlorosilane or DCS (SiH 2cl 2), silicon tetrachloride (SiCl 4) or the silicon source of BisTertiaryButylAmino silane (BTBAS); Such as nitrogen (N 2), ammonia (NH 3) or nitrogen peroxide (NO 3) or nitrous oxide (N 2o) nitrogenous source; And such as oxygen (O 2) or N 2the oxygen-containing gas of O forms oxygen enrichment ground floor.Such as, oxygen enrichment ground floor (comprises N by be placed on by substrate in settling chamber and to introduce process gas 2o, NH 3and DCS) be deposited on above the first deuterated layer, settling chamber to be maintained from about 5 millitorrs (mT) to the pressure of about 500mT simultaneously and substrate is maintained from about 700 DEG C to about 850 DEG C and in some embodiments the temperature of at least about 760 DEG C from one period of 2.5 minutes to about 20 minutes.Particularly, process gas and can comprise the N mixed with the ratio from about 8:1 to about 1:8 2o and NH 3the first admixture of gas and DCS and NH that mix with the ratio from about 1:7 to about 7:1 3the second admixture of gas, and can be introduced under the flow rate of about 200 standard cubic centimeters (sccm) from per minute about 5.Find, the oxynitride layer producing under these conditions or deposit produces Silicon-rich, oxygen enrichment ground floor.
Alternatively, can use gas, wherein hydrogen is replaced by deuterated, comprises such as ND 3replace NH 3.The deuterated silicon dangling bonds passivation advantageously making at silicon-oxide interface place for hydrogen, thus increase NBTI (Negative Bias Temperature Instability) life-span of equipment.
Then formed on the surface of oxygen enrichment ground floor or deposit anti-tunnel layer.Form or deposit anti-tunnel layer by any suitable means (comprise plasma oxygen metallization processes, original position water vapour produces (ISSG) or free-radical oxidation technique).In one embodiment, free-radical oxidation technique relates to and makes hydrogen (H 2) and oxygen (O 2) growth of anti-tunnel layer is realized in gas flow to batch processing instrument or reacting furnace with the oxidation consumption of the part by oxygen enrichment ground floor.
Then the oxygen deprivation second layer of multilayer charge trapping region is formed on the surface of anti-tunnel layer.The oxygen deprivation second layer can use process gas (to comprise N in CVD process 2o, NH 3and DCS) be deposited on above anti-tunnel layer under the chamber pressure of about 500mT and under the underlayer temperature of about 700 DEG C to about 850 DEG C and in some embodiments continuing a period of time from about 2.5 minutes to about 20 minutes at least about 760 DEG C from about 5mT.Particularly, process gas and can comprise the N mixed with the ratio from about 8:1 to about 1:8 2o and NH 3the first admixture of gas and DCS and NH that mix with the ratio from about 1:7 to about 7:1 3the second admixture of gas, and can be introduced under the flow rate of about 5 to about 20sccm per minute.Find, the oxynitride layer producing under these conditions or deposit produces Silicon-rich, rich nitrogen and the oxygen deprivation second layer.
In some embodiments, the oxygen deprivation second layer BTBAS that the ratio comprised from about 7:1 to about 1:7 can be used to mix and ammonia (NH 3) process gas be deposited in CVD process above anti-tunnel layer to comprise the concentration of the carbon of the quantity being selected to increase trap wherein further.The selected concentration of the carbon in the second oxynitride layer can comprise the concentration of carbon of from about 5% to about 15%.
Then, in operation 1206, barrier layer is formed on multilayer electric charge capture layer or the multilayer electric charge capture layer that separates.Barrier layer is formed by any suitable means (comprise such as thermal oxidation or use the deposition of CVD technology).In a preferred embodiment, high temperature CVD process is used to form barrier layer.Usually, depositing operation relates to is providing such as SiH from about 50mT in settling chamber under the pressure of about 1000mT 4, SiH 2cl or SiCl 4silicon source and containing such as O 2or N 2substrate, from a period of time of about 10 minutes to about 120 minutes, maintains from the temperature of about 650 DEG C to about 850 DEG C by the carrier of oxygen of O simultaneously.Preferably, sequentially deposited barrier layer in for the formation of the same place grooming tool of multilayer electric charge capture layer.More preferably, in the handling implement all identical with tunnel layer with multilayer electric charge capture layer, barrier layer is formed and not moving substrate between operations.
In the execution mode that Figure 12 describes, the barrier layer deposited in operation 1206 is reoxidized to make barrier layer oxide closely knit in operation 1208.As in other local discussion herein, operate 1208 and can be oxidized or reoxidize parts of the second district 1116B of multilayer electric charge capture layer 1116 further to realize the graded bandgap such as described in fig. 8 a.Usually, oxidizing gas such as oxygen (O can be there is 2), nitrous oxide (N 2o), nitric oxide (NO), ozone (O 3) and steam (H 2o) perform when and reoxidize.In one embodiment, perform at the temperature that the temperature when being deposited than barrier layer is high and reoxidize process.Reoxidizing after the deposition on barrier layer is oxidized or reoxidizes a part of the second district 1116B with making the more controlled diffusion-controllable of oxidant.In particularly advantageous execution mode, use dilution wet oxidation.Dilution wet oxidation is different from wet oxidation, because H 2: O 2than between 1 and 1.3.In a specific execution mode, at the temperature between 800 DEG C and 900 DEG C, perform the H with about 1.2 2: O 2the dilution oxidation of ratio.
In another embodiment, the duration of dilution oxidation can be enough to grow the silicon dioxide between 5.0nm and 12.5nm on a silicon substrate.In such execution mode, such duration is enough to about 10nm to 1.1nm silicon dioxide layer on a silicon substrate.Such dilution oxidizing process for reoxidizing the barrier layer oxide of deposition, and can be oxidized further or the part of reoxidized charge trapping layer to give band structure, as the band structure described in Fig. 8 A or 8B.
In another embodiment, operate 1208 reoxidize can be used for further on the substrate identical with SONOS type equipment such as complementary metal oxide silicon (CMOS) field-effect transistor (FET) non-SONS type battery limits in form gate oxide.In another embodiment, reoxidizing of operation 1208 can be used for being diffused into by deuterium in the multilayer electric charge capture layer of SONOS type equipment or the part on barrier layer further.
The method can then to form the grid layer of the grid layer 1114 of such as Figure 11 A and to form the gate cap of the gate cap 1125 such as described in Figure 11 A in some embodiments and terminate.When gate stack manufacture terminates, further can there is the manufacture terminating SONOS type memory devices 300 in process as known in the art.
In another aspect, disclosure object is also to comprise covering on a surface of the substrate or the multiple-grid pole of the multilayer electric charge capture layer of two or more sides of channel region that formed, top or multiple-grid pole memory surface equipment and manufacture its method.Many gate device comprise plane and on-plane surface equipment simultaneously.Plane many gate device (not shown) generally includes bigrid planar device, and wherein multiple ground floor is deposited to form first grid under the channel region formed subsequently, and multiple second layer side of being deposited thereon is to form second grid.Formed above the surface that the many gate device of on-plane surface are usually included in substrate and on three sides or more side by grid around level or vertical channel region.
Figure 13 A and 13B illustrates an execution mode of the on-plane surface multiple-grid pole memory devices comprising multilayer electric charge capture layer.With reference to figure 13A, the memory devices 1300 being commonly called finFET comprises the channel region 1302 formed by the film of the silicon of the material comprised on the surface 1304 that covers on substrate 1306 or layer, the source area 1308 of its connected storage equipment and drain region 1310.Channel region 1302 is surrounded by the fin of the grid 1312 of forming device on three sides.As above-described execution mode, channel region 1302 can comprise the polysilicon of polysilicon or recrystallization to form monocrystalline channel region.Alternatively, comprise the occasion of monocrystalline silicon in channel region 1112, channel region can be formed the <100> surface crystal orientation of the major axis had relative to channel region.
The thickness (measuring on the direction from source area to drain region) of grid 1312 determines the length of effective channel of memory devices.
According to the disclosure, the on-plane surface multiple-grid pole memory devices 1300 of Figure 13 A can comprise multilayer electric charge capture layer, nitride-oxide tunnel layer and highly dense barrier layer.Figure 13 B is the viewgraph of cross-section of the many gate device of on-plane surface of Figure 13 A comprising the part of substrate 1306, channel region 1302 and grid 1312, and it illustrates multilayer electric charge capture layer 1314, nitride-oxide tunnel layer 1316 and highly dense barrier layer 1318.Grid 1312 also comprises the metal gate layers 1320 of covering barrier layer to form the control gate of memory devices 1300.In some embodiments, can depositing doped polysilicon instead of metal to provide polycrystalline silicon gate layer.The buried oxide layer that can directly such as be formed at substrate or types of flexure on substrate 1306 or at insulation or dielectric layer 1322 forms channel region 1302 and grid 1312.
With reference to figure 13B, tunnel layer 1316 is nitride-oxide tunnel layer 1316 in some execution mode (routine as directed execution mode), and comprises having and be less than about 5 x 10 21nitrogen-atoms/cm 3nitrogen concentration the first district 1316A close to channel region 1302 and there are at least 5 x 10 21nitrogen-atoms/cm 3the second district 1316B close to multilayer electric charge capture layer 1314 of nitrogen concentration.In one embodiment, be similar to disclosed execution mode in fig. 11, the firstth district of nitride-oxide tunnel layer 1316 and the secondth district each comprise no more than about 25% tunnel layer thickness.
Multilayer electric charge capture layer 1314 comprises and comprising comparatively close at least one oxygen enrichment ground floor 1314A of the nitride of the tunnel layer 1316 and oxygen deprivation second layer 1314B of covering oxygen enrichment ground floor.Usually, oxygen deprivation second layer 1314B comprises Silicon-rich, oxygen deprivation nitride layer comprise the most of charge trap be distributed in multilayer electric charge capture layer 1314, and oxygen enrichment ground floor 1314A comprises oxygen enrichment nitride or silicon oxynitride, and be the quantity to reduce charge trap wherein of oxygen enrichment relative to the oxygen deprivation second layer.So-called oxygen enrichment is meant to the concentration from about 15 to about 40% of the oxygen wherein in oxygen enrichment ground floor 1314A, and the concentration of oxygen in oxygen deprivation second layer 1314B is less than about 5%.
In some embodiment example execution mode as shown in Figure 11 B, multilayer electric charge capture layer 1314 also comprises at least one thin centre or anti-tunnel layer 1314C, and it comprises the dielectric such as oxide that oxygen deprivation second layer 1314B and oxygen enrichment ground floor 1314A is separated.As mentioned above, the electron charge tunnelling that anti-tunnel layer 1314C reduces in fact the boundary accumulating in oxygen deprivation second layer 1314B during programming enters the probability of oxygen enrichment ground floor 1314A.
As above-described execution mode, any one or two in oxygen enrichment ground floor 1314 and oxygen deprivation second layer 1314B can comprise silicon nitride or silicon oxynitride, and can such as by comprising the N by ratio 2o/NH 3and DCS/NH 3the CVD technique of admixture of gas and be adjusted to the flow rate of the oxynitride layer of Silicon-rich and oxygen enrichment is provided under formed.Then the oxygen deprivation second layer of multilayer charge storage structure is formed on intermediate oxide layer.Oxygen deprivation second layer 1314B has the stoichiometric composition of the oxygen of the composition being different from bottom oxygen enrichment ground floor 1314A, nitrogen and/or silicon, and also by using the N comprised by ratio 2o/NH 3and DCS/NH 3the CVD technique of admixture of gas and being formed or deposition being adjusted under the flow rate providing Silicon-rich, oxygen deprivation top nitride layer.
In those execution modes comprising oxidiferous centre or anti-tunnel layer 1314C, anti-tunnel layer uses free-radical oxidation to be formed into the selected degree of depth by the oxidation of oxygen enrichment ground floor 1314A.Such as can use single wafer tools at the temperature of 1000-1100 DEG C or at 800-900 DEG C, use batch reactor instrument to perform free-radical oxidation.The time using single gas phase instrument to use single wafer tools to continue 1-2 minute under the pressure that can hold in the palm at 300-500 for batch process or under 10-15 holder or the time using batch process to continue 30 minutes-1 hour use H 2and O 2the mixture of gas.
The suitable thickness of oxygen enrichment ground floor 1314A can from approximately to about (certain deviation allows, such as ), wherein approximately anti-tunnel layer 1314C can be formed by free-radical oxidation consumption.The suitable thickness of oxygen deprivation second layer 1314B can be at least in some embodiments, oxygen deprivation second layer 1314B can be formed nearly thick, wherein barrier layer 1318 can be formed by free-radical oxidation consumption.The ratio of the thickness between oxygen enrichment ground floor 1314A and oxygen deprivation second layer 1314B is about 1:1 in some embodiments, although other is than being also possible.
Barrier layer 1318 comprises high-temperature oxide (HTO), and it is larger than the relative density deposited.Highly dense HTO oxide has end hydrogen base key or the hydroxyl bond of lower percentage.Such as, hydrogen or water have from the removal of HTO oxide increases film density and the effect improving the quality of HTO oxide.The oxide of better quality enables layer improve on thickness.In one embodiment, hydrogen concentration is greater than the 2.5 x 1020 atoms/cm deposited 3, and be reduced in highly dense film lower than 8.0 x 10 19atom/cm 3.In the exemplary embodiment, comprise the thickness on the barrier layer 1318 of highly dense HTO oxide between 2.5nm and 10.0nm deposited, and when densification in each place thinning about 10% to 30%.
In alternative embodiments, barrier layer 1318 is modified further in conjunction with nitrogen.In such execution mode, nitrogen is combined in the whole thickness on barrier layer 1318 with the form of ONO lamination.Such sandwich replaces conventional pure oxygen barrier layer desirably reduce the EOT of the whole lamination between channel region 1302 and control gate 1320 and realize being with the adjustment of skew to reduce the anti-injection of charge carrier.ONO lamination barrier layer 1318 can then be combined with nitride-oxide tunnel layer 1316 and the multilayer electric charge capture layer 1114 separated comprising oxygen enrichment ground floor 1314A and oxygen deprivation second layer 1314B and anti-tunnel layer 1314C.
In another execution mode shown in Figure 14 A and 14B, memory devices can comprise the nanowire channel district formed by the film of the semi-conducting material on the surface covering substrate, the source area of its connected storage equipment and drain region.So-called nanowire channel district refers to the conducting channel district formed in the sheet of crystalline silicon material, and it has about 10 nanometers (nm) or less and be more preferably less than the cross-sectional dimension of about 6 nm.Alternatively, channel region can be formed the <100> surface crystal orientation of the major axis had relative to channel region.
With reference to figure 14A, memory devices comprises by the surface of substrate 1406 or cover the film of semi-conducting material on surface of substrate 1406 or thin layer is formed and the source area 1408 of connected storage equipment and the horizontal nanowire channel region 1402 of drain region 1410.In the illustrated embodiment, equipment has grid loopful around (GAA) structure, and wherein nanowire channel district 1402 is surrounded by the grid 1412 of equipment on all sides.The thickness (measuring on the direction from source area to drain region) of grid 1412 determines the length of effective channel of memory devices.As above-described execution mode, nanowire channel district 1402 can comprise the polysilicon of polysilicon or recrystallization to form monocrystalline channel region.Alternatively, comprise the occasion of monocrystalline silicon in channel region 1402, channel region can be formed the <100> surface crystal orientation of the major axis had relative to channel region.
According to the disclosure, the on-plane surface multiple-grid pole memory devices 1400 of Figure 14 A can comprise multilayer electric charge capture layer, nitride-oxide tunnel layer and highly dense barrier layer.Figure 14 B is the viewgraph of cross-section of a part of the many gate device of on-plane surface of Figure 14 A comprising the part of substrate 1406, nanowire channel district 1402 and grid 1412.With reference to figure 14B, grid 1412 comprises nitride-oxide tunnel layer 1414, multilayer electric charge capture layer 1416 and highly dense barrier layer 1418.Grid 1412 also comprises the grid layer 1420 of covering barrier layer to form the control gate of memory devices 1400.Grid layer 1420 can comprise metal or doped polycrystalline silicon.
Tunnel layer 1414 is nitride-oxide tunnel layer 1414 in the as directed execution mode of some embodiment example, and it comprises having and is less than about 5 x 10 21nitrogen-atoms/cm 3nitrogen concentration the first district 1414A close to channel region 1402 and there are at least 5 x 10 21nitrogen-atoms/cm 3the second district 1414B close to multilayer electric charge capture layer 1416 of nitrogen concentration.In one embodiment, be similar to execution mode disclosed in Figure 11 B, the firstth district of nitride-oxide tunnel layer 1414 and the secondth district each comprise no more than about 25% tunnel layer thickness.
Multilayer electric charge capture layer 1416 comprise comprise comparatively close to the nitride of tunnel layer 1414 at least one in oxygen enrichment ground floor 1416A and cover the outer oxygen deprivation second layer 1416B of oxygen enrichment ground floor.Usually, oxygen deprivation second layer 1416B comprises Silicon-rich, oxygen deprivation nitride layer comprise the most of charge trap be distributed in multilayer electric charge capture layer 1416, and oxygen enrichment ground floor 1416A comprises oxygen enrichment nitride or silicon oxynitride, and be the quantity to reduce charge trap wherein of oxygen enrichment relative to the oxygen deprivation second layer.The so-called oxygen enrichment meaning refers to the concentration from about 15% to about 40% of the oxygen wherein in oxygen enrichment ground floor 1416A, and the concentration of oxygen in oxygen deprivation second layer 1416B is less than about 5%.
In some embodiment example execution mode as shown in Figure 14B, multilayer electric charge capture layer 1416 also comprises at least one thin centre or anti-tunnel layer 1416C, and it comprises the dielectric (such as oxide) that oxygen deprivation second layer 1416B and oxygen enrichment ground floor 1416A is separated.As mentioned above, the electron charge tunnelling that anti-tunnel layer 1416C reduces in fact the boundary accumulating in oxygen deprivation second layer 1416B during programming enters the probability of oxygen enrichment ground floor 1416A.
As above-described execution mode, any one or two in oxygen enrichment ground floor 1416A and oxygen deprivation second layer 1416B can comprise silicon nitride or silicon oxynitride, and can such as by comprising into the N of ratio 2o/NH 3and DCS/NH 3the CVD technique of admixture of gas and being formed under the flow rate being adjusted to the oxynitride layer that Silicon-rich and oxygen enrichment are provided.Then the oxygen deprivation second layer of multilayer charge storage structure is formed on intermediate oxide layer.Oxygen deprivation second layer 1416B has the stoichiometric composition of the oxygen of the composition being different from bottom oxygen enrichment ground floor 1416A, nitrogen and/or silicon, and also by using the N comprising into ratio 2o/NH 3and DCS/NH 3the CVD technique of admixture of gas and be suitable for being formed under the flow rate that Silicon-rich, oxygen deprivation top nitride layer are provided or deposition.
In those execution modes comprising oxidiferous centre or anti-tunnel layer 1314C, anti-tunnel layer uses free-radical oxidation to be formed into the selected degree of depth by the oxidation of oxygen enrichment ground floor 1416A.Such as, single wafer tools can be used at the temperature of 1000-1100 DEG C or at 800-900 DEG C, use batch reactor instrument to perform free-radical oxidation.The time using single gas phase instrument to use single wafer tools to continue 1-2 minute under the pressure that can hold in the palm at 300-500 for batch process or under 10-15 holder or the time using batch process to continue 30 minutes-1 hour use H 2and O 2the mixture of gas.
The suitable thickness of oxygen enrichment ground floor 1416A can from approximately to about (certain deviation allows, such as ± ), wherein approximately anti-tunnel layer 1416C can be formed by free-radical oxidation consumption.The suitable thickness of oxygen deprivation second layer 1416B can be at least in some embodiments, oxygen deprivation second layer 1416B can be formed nearly thick, wherein barrier layer 1418 can be formed by free-radical oxidation consumption.The ratio of the thickness between oxygen enrichment ground floor 1416A and oxygen deprivation second layer 1416B is about 1:1 in some embodiments, although other is than being also possible.
Barrier layer 1418 comprises high-temperature oxide (HTO), and it is larger than the relative density deposited.Highly dense HTO oxide has end hydrogen base key or the hydroxyl bond of lower percentage.Such as, hydrogen or water have from the removal of HTO oxide increases film density and the effect improving the quality of HTO oxide.The oxide of better quality enables layer improve on thickness.In one embodiment, hydrogen concentration is greater than 2.5 x 10 deposited 20atom/cm 3, and be reduced in highly dense film lower than 8.0 x 10 19atom/cm 3.In the exemplary embodiment, comprise the thickness on the barrier layer 1418 of highly dense HTO oxide between 2.5nm and 10.0nm deposited, and when densification in each place thinning about 10% to 30%.
In alternative embodiments, barrier layer 1418 is modified further in conjunction with nitrogen.In such execution mode, nitrogen is combined in the whole thickness on barrier layer 1418 with the form of ONO lamination.Such sandwich replaces conventional pure oxygen barrier layer desirably reduce the EOT of the whole lamination between channel region 1402 and grid layer 1420 and realize being with the adjustment of skew to reduce the anti-injection of charge carrier.ONO lamination barrier layer 1418 can then be combined with nitride-oxide tunnel layer 1414 and the multilayer electric charge capture layer 1416 separated comprising oxygen enrichment ground floor 1416A and oxygen deprivation second layer 1416B and anti-tunnel layer 1416C.
Figure 14 C illustrates the viewgraph of cross-section of the vertical string of the many gate device of on-plane surface 1400 of Figure 14 A be arranged in bit cost easily extensible or BiCS architecture 1422.Architecture 1422 is made up of the vertical string of the many gate device of on-plane surface 1400 or lamination, wherein each equipment or unit comprise channel region 1402, channel region 1402 covers substrate 1406 and the source area of connected storage equipment and drain region (not shown in this drawing), and there is grid loopful around (GAA) structure, wherein nanowire channel district 1402 is surrounded by grid 1412 on all sides.Compare with the simple stacking of layer, BiCS architecture decreases the quantity of important lithography step, causes the cost of the every memory bits reduced.
In another embodiment, memory devices is or comprises on-plane surface equipment, it vertical nano-wire channel region comprising in a semiconductor material or formed by semi-conducting material, gives prominence to above its multiple conductive semiconductor layer on substrate or from the multiple conductive semiconductor layer substrate.With in this execution mode shown in cutaway view version in Figure 15 A, memory devices 1500 is included in the vertical nano-wire channel region 1502 formed in the cylinder of semi-conducting material, the source area 1504 of its connection device and drain region 1506.Channel region 1502 by tunnel layer 1508, multilayer electric charge capture layer 1510, barrier layer 1512 and covering barrier layer with the grid layer 1514 forming the control gate of memory devices 1500 around.Channel region 1502 can be included in the annulus in the skin of the solid body cylinders in fact of semi-conducting material, maybe can be included in the annulate lamella formed above the cylinder of dielectric filler material.As above-described horizontal nanowire, channel region 1502 can comprise the polysilicon of polysilicon or recrystallization to form monocrystalline channel region.Alternatively, comprise the occasion of monocrystalline silicon in channel region 1502, channel region can be formed the <100> surface crystal orientation of the major axis had relative to channel region.
At some execution modes such as in the execution mode shown in Figure 15 B, tunnel layer 1508 is nitride-oxide tunnel layers, comprises having being less than about 5 x 10 21nitrogen-atoms/cm 3nitrogen concentration the first district 1508A close to channel region 1502 and there are at least 5 x 10 21nitrogen-atoms/cm 3the second district 1508B close to multilayer electric charge capture layer 1510 of nitrogen concentration.In one embodiment, be similar to execution mode disclosed in Figure 11 B, the firstth district of nitride-oxide tunnel layer 1508 and the secondth district each comprise no more than about 25% tunnel layer thickness.
Multilayer electric charge capture layer 1510 be comprise further comprise comparatively close to the nitride of tunnel layer 1508 at least one in oxygen enrichment ground floor 1510A and cover the multilayer electric charge capture layer separated of outer oxygen deprivation second layer 1510B of oxygen enrichment ground floor.Usually, oxygen deprivation second layer 1510B comprises Silicon-rich, oxygen deprivation nitride layer comprise the most of charge trap be distributed in multilayer electric charge capture layer 1510, and oxygen enrichment ground floor 1510A comprises oxygen enrichment nitride or silicon oxynitride, and be the quantity to reduce charge trap wherein of oxygen enrichment relative to the oxygen deprivation second layer.The so-called oxygen enrichment meaning refers to the concentration from about 15% to about 40% of the oxygen wherein in oxygen enrichment ground floor 1510A, and the concentration of oxygen in oxygen deprivation second layer 1510B is less than about 5%.
In some embodiment example execution mode as shown in fig. 15b, multilayer electric charge capture layer 1510 separately also comprises at least one thin centre or anti-tunnel layer 1510C, and it comprises the dielectric (such as oxide) that oxygen deprivation second layer 1510B and oxygen enrichment ground floor 1510A is separated.As mentioned above, the electron charge tunnelling that anti-tunnel layer 1510C reduces in fact the boundary accumulating in oxygen deprivation second layer 1510B during programming enters the probability of oxygen enrichment ground floor 1510A.
As above-described execution mode, any one or two in oxygen enrichment ground floor 1510A and oxygen deprivation second layer 1510B can comprise silicon nitride or silicon oxynitride, and can such as by comprising into the N of ratio 2o/NH 3and DCS/NH 3the CVD technique of admixture of gas and being formed under the flow rate being adjusted to the oxynitride layer that Silicon-rich and oxygen enrichment are provided.Then the oxygen deprivation second layer of multilayer charge storage structure is formed on intermediate oxide layer.Oxygen deprivation second layer 1510B has the stoichiometric composition of the oxygen of the composition being different from bottom oxygen enrichment ground floor 1510A, nitrogen and/or silicon, and also by using the N comprising into ratio 2o/NH3 and DCS/NH 3the CVD technique of admixture of gas and being formed or deposition being adjusted under the flow rate providing Silicon-rich, oxygen deprivation top nitride layer.
In those execution modes comprising oxidiferous centre or anti-tunnel layer 1510C, anti-tunnel layer uses free-radical oxidation to be formed into the selected degree of depth by the oxidation of oxygen enrichment ground floor 1510A.Such as can use single wafer tools at the temperature of 1000-1100 DEG C or at 800-900 DEG C, use batch reactor instrument to perform free-radical oxidation.Under the pressure that can hold in the palm at 300-500 for batch process or the time using single gas phase instrument to use single wafer tools to continue 1-2 minute under 10-15 backing pressure power or time of using batch process to continue 30 minutes-1 hour use H 2and O 2the mixture of gas.
The suitable thickness of oxygen enrichment ground floor 1510A can from approximately to about (certain deviation allows, such as ), wherein approximately anti-tunnel layer 1510C can be formed by free-radical oxidation consumption.The suitable thickness of oxygen deprivation second layer 1510B can be at least in some embodiments, oxygen deprivation second layer 1510B can be formed nearly thick, wherein barrier layer 1512 can be formed by free-radical oxidation consumption.The ratio of the thickness between oxygen enrichment ground floor 1510A and oxygen deprivation second layer 1510B is about 1:1 in some embodiments, although other is than being also possible.
Barrier layer 1418 comprises high-temperature oxide (HTO), and it is larger than the relative density deposited.Highly dense HTO oxide has end hydrogen base key or the hydroxyl bond of lower percentage.Such as, hydrogen or water have from the removal of HTO oxide increases film density and the effect improving the quality of HTO oxide.The oxide of better quality enables layer improve on thickness.In one embodiment, hydrogen concentration is greater than 2.5 x 10 deposited 20atom/cm 3, and be reduced in highly dense film lower than 8.0 x 10 19atom/cm 3.In the exemplary embodiment, comprise the thickness on the barrier layer 1512 of highly dense HTO oxide between 2.5nm and 10.0nm deposited, and when densification thinning about 10% to 30%.
In alternative embodiments, barrier layer 1512 is modified further in conjunction with nitrogen.In such execution mode, nitrogen is combined in the whole thickness on barrier layer 1512 with the form of ONO lamination.Such sandwich replaces conventional pure oxygen barrier layer desirably reduce the EOT of the whole lamination between channel region 1502 and grid layer 1514 and realize being with the adjustment of skew to reduce the anti-injection of charge carrier.ONO lamination barrier layer 1512 can then merge with nitride-oxide tunnel layer 1508 and the multilayer electric charge capture layer 1510 separated comprising oxygen enrichment ground floor 1510A and oxygen deprivation second layer 1510B and anti-tunnel layer 1510C.
The memory devices 1500 of first grid or post tensioned unbonded prestressed concrete scheme shop drawings 15A can be used.Figure 16 A-F illustrates the first gate scheme of the many gate device of on-plane surface for the manufacture of Figure 15 A.Figure 17 A-F illustrates the post tensioned unbonded prestressed concrete scheme of the many gate device of on-plane surface for the manufacture of Figure 15 A.
With reference to figure 16A, in first gate scheme, first or first the doped diffusion region 1604 such as source area or drain region of lower dielectric layer 1602 in substrate 1606 above formed.Grid layer 1608 is deposited on the control gate of forming device above the first dielectric layer 1602, and second or upper dielectric layer 1610 formed above it.As above-described execution mode, deposit by CVD, free-radical oxidation or form the first and second dielectric layers 1602,1610 by the oxidation of a part for layer below or substrate.The metal that grid layer 1608 can comprise deposition or the doped polycrystalline silicon deposited by CVD.Usually, the thickness of grid layer 1608 is from approximately extremely and the first and second dielectric layers 1602,1610 are from approximately extremely
With reference to figure 16B, the first opening 1612 is etched to the diffusion region 1604 in substrate 1606 through the second dielectric layer 1610, grid layer 1608 and the first dielectric layer 1602.Then, multiple layer or barrier layer 1614, multilayer electric charge capture layer 1616 and tunnel layer 1618 sequentially deposit in the opening, and the surface plane of upper dielectric layer 1610 is to produce the intermediate structure shown in Figure 16 C.
In execution mode as described above, barrier layer 1614 can be the highly dense barrier layer comprising the highly dense HTO oxide relatively higher than the density deposited, and has end hydrogen or the hydroxyl bond of lower percentage.
Although not shown, to understand, in above-described execution mode, multilayer electric charge capture layer 1616 can comprise and comprising comparatively close to highly dense barrier layer 1614 or the outer oxygen deprivation second layer be deposited on highly dense barrier layer 1614 and deposition or the multilayer electric charge capture layer separated being formed in oxygen enrichment ground floor on the oxygen deprivation second layer.Usually, the oxygen deprivation second layer comprises Silicon-rich oxygen deprivation nitride layer and comprises the most of charge trap be distributed in multilayer electric charge capture layer, and oxygen enrichment ground floor comprises oxygen enrichment nitride or silicon oxynitride, and be the quantity to reduce charge trap wherein of oxygen enrichment relative to the oxygen deprivation second layer.In some embodiments, multilayer electric charge capture layer is the multilayer electric charge capture layer separated comprising at least one thin centre or anti-tunnel layer further, and it comprises makes the outer oxygen deprivation second layer and the closely spaced dielectric (such as oxide) of interior oxygen enrichment ground floor.
To recognize further, tunnel layer 1618 is nitride-oxide tunnel layers, and can comprise having and be less than about 5 x 10 21nitrogen-atoms/cm 3the firstth district of nitrogen concentration, its covering has at least 5 x 10 21nitrogen-atoms/cm 3secondth district close to multilayer electric charge capture layer 1616 of nitrogen concentration.
Then, with reference to figure 16D, second or pass through tunnel layer 1618, multilayer electric charge capture layer 1616 and barrier layer 1614 of raceway groove opening 1620 be anisotropically etched the part of the diffusion region 1604 be exposed in substrate 1606.With reference to figure 16E, semi-conducting material 1622 is deposited in raceway groove opening to form vertical channel region 1624 wherein.Vertical channel region 1624 can be included in the annulus in the skin of the solid body cylinders in fact of semi-conducting material, or as shown in Figure 16 E, can comprise the cylindrical layer semi-conducting material 1622 separately around packing material 1626.
With reference to figure 16F, the surface of upper dielectric layer 1610 is flattened, and the layer of semiconductor material 1628 being included in the second the doped diffusion region 1630 such as source area or drain region wherein formed is deposited on above upper dielectric layer to form shown equipment.
With reference to figure 17A, in post tensioned unbonded prestressed concrete scheme, formed above the sacrifice layer 1704 on dielectric layer 1702 (such as oxide) surface on substrate 1706, the opening through dielectric layer and sacrifice layer and vertical channel region 1708 etching is formed wherein.As above-described execution mode, vertical channel region 1708 can be included in the annulus in the skin of the solid body cylinders in fact of semi-conducting material 1710 (such as polysilicon or monocrystalline silicon), maybe can comprise the cylindrical layer semi-conducting material separately around dielectric filler material (not shown).Dielectric layer 1702 can comprise any suitable dielectric substance of the grid layer formed subsequently and covering electroactive layer or another memory devices electric isolution that can make at memory devices 1500, such as silica.Sacrifice layer 1704 can comprise any suitable material that can be etched with high selectivity or remove relative to the material of dielectric layer 1702, substrate 1706 and vertical channel region 1708.
With reference to figure 17B, the second opening 1712 is etched to substrate 1706 through dielectric layer and sacrifice layer 1702,1704, and sacrifice layer 1704 is etched at least in part or removes.Sacrifice layer 1704 can comprise any suitable material that can be etched with high selectivity or remove relative to the material of dielectric layer 1702, substrate 1706 and vertical channel region 1708.In one embodiment, sacrifice layer 1704 comprises the layer removed by buffer oxide etch (BOE etching).
With reference to figure 17C and 17D, comprise nitride-oxide, the layer of tunnel layer 1714A-B on multilayer electric charge capture layer 1716A-C and barrier layer 1718 sequentially deposits in the opening, and the surface plane of dielectric layer 1702 is to produce the intermediate structure shown in Figure 17 C.In execution mode as described above, barrier layer 1718 can be the highly dense barrier layer comprising the highly dense HTO oxide relatively higher than the density deposited, and has end hydrogen or the hydroxyl bond of lower percentage.
In some embodiment example execution mode as shown in figure 17d, nitride-oxide tunnel layer comprises having and is less than about 5 x 10 21nitrogen-atoms/cm 3nitrogen concentration the first district 1714A close to semi-conducting material 1710 and there are at least 5 x 10 21nitrogen-atoms/cm 3the second district 1714B close to multilayer electric charge capture layer 1716A-C of nitrogen concentration.
Multilayer electric charge capture layer 1716A-C be comprise close to nitride-oxide tunnel layer 1714 at least one in the multilayer electric charge capture layer separated of oxygen enrichment ground floor 1716A and outer oxygen deprivation second layer 1716B.Alternatively, the first and second electric charge capture layers can be separated by intermidate oxide or anti-tunnel layer 1716C.
Then, grid layer 1722 is deposited in the second opening 1712, and the surface plane of upper dielectric layer 1702 is to produce the intermediate structure shown in Figure 17 E.As above-described execution mode, grid layer 1722 can comprise deposited metal or the polysilicon of doping.Finally, opening 1724 is etched with through grid layer 1722 control gate forming independent memory devices 1726A and 1726B.
Therefore, the method for the manufacture of non-volatile charge trap memory equipment is disclosed.According to the embodiment of the present invention, substrate experiences the first free-radical oxidation process to form the first dielectric layer in first process chamber of Automatic Combined instrument (cluster tool).Electric charge capture layer can then be deposited on above the first dielectric layer in the second process chamber of Automatic Combined instrument.In one embodiment, then electric charge capture layer experiences the second free-radical oxidation process to be formed in the second dielectric layer above electric charge capture layer by a part for oxidation charge capture layer in the first process chamber of Automatic Combined instrument.By forming all layers of oxidenitride oxide (ONO) in Automatic Combined instrument, the interface failure between corresponding layer can be reduced.Therefore, according to the embodiment of the present invention, ONO is stacked in Automatic Combined instrument manufactured to protect the original interface between each layer in ONO lamination in one way.In specific execution mode, Automatic Combined instrument is single-chip Automatic Combined instrument.

Claims (20)

1. manufacture the non-volatile method being captured charge accumulator equipment, comprising:
Form the channel region of electrical connection source area and drain region in the substrate, wherein said channel region comprises polysilicon;
Above described channel region, in described substrate, form tunnel layer, wherein form described tunnel layer and comprise and make described liner oxidation to form oxidation film and to make described oxidation film nitrogenize;
The described tunnel layer comprising oxygen enrichment ground floor and the oxygen deprivation second layer forms multilayer electric charge capture layer; And
Described multilayer electric charge capture layer forms barrier layer.
2. the method for claim 1, also comprise and use oxidizing annealing to make described barrier layer closely knit, wherein said oxidizing annealing makes the oxidation at least partially of the described oxygen deprivation second layer of the described multilayer electric charge capture layer close to described barrier layer.
3. the method for claim 1, wherein form described multilayer electric charge capture layer and also comprise the anti-tunnel layer of formation, described anti-tunnel layer comprises the oxide that described ground floor and the described second layer are separated.
4. method as claimed in claim 3, wherein forms described channel region and comprises and make described polysilicon recrystallization.
5. the method for claim 1, wherein forms described channel region and is included in the protrusion of the material comprising silicon and forms described channel region, and described material covers the surface of described substrate and the described source area be electrically connected in described substrate and described drain region.
6. the method for claim 1, also comprise and use oxidizing annealing to make described barrier layer closely knit, wherein said oxidizing annealing makes a part for the described oxygen deprivation second layer of the described multilayer electric charge capture layer close to described barrier layer be oxidized.
7. method as claimed in claim 6, wherein forms described tunnel layer and also comprises by described substrate is exposed to O 2the oxidation film of institute's nitrogenize is reoxidized, and by the oxidation film of described substrate, institute's nitrogenize being exposed to NO to make the nitride-oxide film nitrogenize again reoxidized.
8. manufacture the non-volatile method being captured charge accumulator equipment, comprising:
Form the channel region of electrical connection source area and drain region in the substrate, wherein said channel region comprises polysilicon;
Above described channel region, in described substrate, form tunnel layer, wherein form described tunnel layer and comprise and make described liner oxidation to form oxidation film and to make described oxidation film nitrogenize;
The described tunnel layer comprising oxygen enrichment ground floor, the oxygen deprivation second layer and anti-tunnel layer is formed multilayer electric charge capture layer separately; And
The described multilayer electric charge capture layer separated forms barrier layer.
9. method as claimed in claim 8, also comprise and use oxidizing annealing to make described barrier layer closely knit, wherein said oxidizing annealing makes the oxidation at least partially of the described oxygen deprivation second layer of the described multilayer electric charge capture layer separated close to described barrier layer.
10. method as claimed in claim 9, wherein uses oxidizing annealing to make the closely knit part oxidation comprising the only about half of described oxygen deprivation second layer making to equal the described oxygen deprivation second layer in described barrier layer.
11. methods as claimed in claim 8, also comprise and use oxidizing annealing to make described barrier layer closely knit, wherein said oxidizing annealing makes a part for the described oxygen deprivation second layer of the described multilayer electric charge capture layer close to described barrier layer be oxidized.
12. methods as claimed in claim 8, wherein form described tunnel layer and also comprise by described substrate is exposed to O 2the oxidation film of institute's nitrogenize is reoxidized, and by the oxidation film of described substrate, institute's nitrogenize being exposed to NO to make the nitride-oxide film nitrogenize again reoxidized.
13. methods as claimed in claim 8, the multilayer electric charge capture layer separated described in wherein being formed also comprises the anti-tunnel layer of formation, and described anti-tunnel layer comprises the oxide that described ground floor and the described second layer are separated.
14. methods as claimed in claim 8, wherein form described channel region and are included in the protrusion of the material comprising silicon and form described channel region, and described material covers the surface of described substrate and the described source area be electrically connected in described substrate and described drain region.
15. 1 kinds non-volatile is captured charge accumulator equipment, comprising:
Channel region, it comprises silicon;
Tunnel layer, it covers described channel region;
Multilayer electric charge capture layer, it covers the described tunnel layer comprising oxygen enrichment ground floor and the oxygen deprivation second layer; And
Barrier layer, it covers described multilayer electric charge capture layer;
Wherein said tunnel layer comprises nitride-oxide, and comprises firstth district close to described channel region of the nitrogen concentration had lower than the secondth district close to described multilayer electric charge capture layer.
16. memory devices as claimed in claim 15, wherein said channel region comprises polysilicon.
17. memory devices as claimed in claim 15, wherein said multilayer electric charge capture layer is the multilayer electric charge capture layer separated also comprising anti-tunnel layer, and described anti-tunnel layer comprises the oxide that described ground floor and the described second layer are separated.
18. memory devices as claimed in claim 17, wherein said channel region comprises the polysilicon of recrystallization.
19. memory devices as claimed in claim 16, wherein said channel region comprises the surface the protrusion being connected electrically in the semi-conducting material of source area and the drain region formed in described substrate that cover substrate.
20. memory devices as claimed in claim 16, wherein said channel region comprises the vertical-channel formed by the protrusion of semi-conducting material, described vertical-channel extends to the second diffusion region formed in the described surface of described substrate from the first diffusion region formed on a surface of the substrate, described first diffusion region is electrically connected to described second diffusion region by described vertical-channel.
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