TW201405717A - SONOS ONO stack scaling - Google Patents

Abstract

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Description

Semiconductor-Oxide-Nitride-Oxide-Semiconductor Oxide-Nitride-Oxide Stacking Scaling

Embodiments of the present invention relate to the electronics manufacturing industry and, more particularly, to the fabrication of non-volatile charge trapping memory components.

Related application cross-reference

This application is a continuation of the US application Serial No. 11/904,506, filed on September 26, 2007, which is based on 35 USC 119(e) claiming the United States as claimed on May 25, 2007. The priority benefit of the provisional patent application Serial No. 60/940,384 is hereby incorporated by reference in its entirety.

1 is a cross-sectional view of an intermediate portion of a semiconductor device 100 having a semiconductor-oxide comprising a conventional oxide-nitride-oxide (ONO) stack 104 formed over a surface 106 of a semiconductor substrate 108 in accordance with a conventional method. A nitride-oxide-semiconductor (SONOS) gate stack 102. The element 100 typically includes one or more diffusion regions 110, such as source and drain regions, that are aligned with the gate stack and separated by a channel region 112. The semiconductor-oxide-nitride-oxide-semiconductor gate stack 102 includes a poly gate layer 114 formed thereon and contacting the oxide-nitride-oxide stack 104. The polysilicon gate layer 114 and the substrate 108 are electrically isolated via the oxide-nitride-oxide stack 104. The oxide-nitride The oxide stack 104 generally comprises a hafnium oxide tunneling layer 106A, a tantalum nitride charge trapping layer 118 that acts as a charge storage or memory layer for the device 100, and a hafnium oxide barrier layer over the charge trapping layer 118. 120.

Such semiconductor-oxide-nitride-oxide-semiconductor type transistors are useful for non-volatile memory (NVM). The charge trap layer stores charge to provide non-volatility. In order to program (ie, write) the n-channel semiconductor-oxide-nitride-oxide-semiconductor type element, a positive voltage is applied to the control gate (Vcg), and the source, body and The bungee is grounded. Capture charge distribution of a conventional n-channel semiconductor-oxide-nitride-oxide-semiconductor type device having a channel 212, an oxide tunneling layer 216, a nitride memory layer 218, and an oxide barrier during stylization The band diagram of the trap density distribution is shown in Figure 2. As shown, the positive voltage Vcg creates an electric field across the semiconductor-oxide-nitride-oxide-semiconductor stack, resulting in some of the buried-channels of the germanium substrate channel being at the energy level of the conduction band. The negative charge is subjected to Fuller-Nordheim tunneling (FNT) through the tunneling layer into the charge trapping layer. The electrons are stored in a trap having an intermediate gap energy level in the charge trap layer. As shown, the trap density profile is substantially evenly distributed throughout the charge trapping layer. As further shown, under bias, the trapped charge distribution is such that a majority of the trapped charge is a portion of the charge trapping layer (ie, the memory layer) that is proximate to the blocking oxide. To erase the via semiconductor-oxide-nitride-oxide-semiconductor component, a negative voltage is applied to the control gate 314. An energy band diagram showing channel 312, oxide tunneling layer 316, nitride memory layer 318, and oxide barrier layer 320 during erase is shown in FIG. As shown, the negative voltage Vcg produces an electric field across the semiconductor-oxide-nitride-oxide-semiconductor stack, and the attracting tunnel tunneling charges pass through the tunneling layer into the charge trapping layer.

Semiconductor-oxide-nitride-oxide-semiconductor-type components are becoming popular in high-density memory applications such as in-line non-volatile memory. Uniform channel Fuller-Nordheim tunneling (FNT) and/or direct tunneling (DT) for stylization and erasing is known in the industry to produce improved reliability results over other methods. The Fuller-Nordheim tunneling and direct tunneling system is referred to herein as a modified Fuller-Nordheim tunneling effect (MFNT). Currently, conventional semiconductor-oxide-nitride-oxide-semiconductor elements for modified Fuller-Nordheim tunneling operate within the 10 volt range. However, semiconductor-oxide-nitride-oxide-semiconductor advantages over other non-volatile memory components are voltage tunability. The established theory is to use the correct scaling, existing in the semiconductor-oxide-nitride-oxide-semiconductor, to achieve memory technology operating in the 5 volt range, rather than the traditional semiconductor-oxide- The 10 volt range of nitride-oxide-semiconductor type components or the 12 volts to 15 volt range of conventional flash memory technology. A semiconductor-oxide-nitride-oxide-semiconductor type device that is operable at a low voltage (nearly 5 volts) is advantageously compatible with a low voltage complementary metal oxide semiconductor. Alternatively, faster stylization or erasing is possible for scaling components at a particular voltage. However, successful scaling of semiconductor-oxide-nitride-oxide-semiconductor type components is not common. For example, Figure 4 illustrates the stylization and erasing time of a conventional semiconductor-oxide-nitride-oxide-semiconductor component using a conventional oxide-nitride-oxide stack that is oxidized by a 10 nm thick layer. The ruthenium barrier layer, a 7 nm thick tantalum nitride charge trap layer and a 3 nm thick ruthenium dioxide tunnel layer are formed. As shown, this stylization/erase time is dramatically increased as the voltage Vcg is reduced. In general, stylized and erase times of less than 1 millisecond (ms) are satisfactory for in-line memory applications. However, such 1 millisecond programming and erasing times are only available in conventional semiconductor-oxide-nitride-oxide-semiconductor stacks having a Vcg voltage of +/- 10 volts. When the voltage Vcg drops to about At +/- 9 volts, the conventional semiconductor-oxide-nitride-oxide-semiconductor stylization/erase time is extended to 100 mm.

Further, lowering the stylized voltage causes the erased or stylized window (ie, the memory window) to drop. This is because the effective oxide thickness (EOT) of the entire oxide-nitride-oxide stack is not reduced as the voltage drops, the electric field across the oxide-nitride-oxide stack is reduced. . Reducing the thickness of the tunneling layer to allow the same initial erasing level at a lower applied voltage (Vcg) results in an unfavorable increase in the erase and stylized decay rate, thereby reducing the effective oxide thickness of the stack It is not ordinary. Similarly, if the charge trapping layer thickness is reduced, the charge mass center is placed closer to the substrate, increasing the charge loss to the substrate. Finally, as the barrier oxide thickness is reduced, the electron retro-injection from the control gate increases, causing damage to the oxide-nitride-oxide stack and data retention losses. The reverse injection system is further shown in Figure 4, wherein the Fuller-Nordheim tunneling erase achieves "saturation". This occurs when electrons are reflowed from the gate to the memory layer faster than they can be removed by transporting holes through the tunneling oxide. In view of this, the oxide-nitride-oxide of a semiconductor-oxide-nitride-oxide-semiconductor element is still scaled in such a way as to provide an element that can operate at a lower stylized/erasing voltage. Stacking is required.

According to one aspect of the invention, a method of fabricating a non-volatile charge trapping memory device includes forming a channel region electrically connected to a source region and a drain region in a substrate, wherein the channel region comprises polysilicon; Forming a tunneling layer over the channel region, wherein forming the tunneling layer comprises oxidizing the substrate to form an oxide film and nitriding the oxide film; forming an oxygen-containing first layer on the tunneling layer and a multilayered charge of a second layer of anoxic a trap layer; and forming a barrier layer on the multilayer charge trap layer.

According to another aspect of the present invention, a method of fabricating a non-volatile charge trapping memory device includes forming a channel region electrically connected to a source region and a drain region in a substrate, wherein the channel region includes a polysilicon; Forming a tunneling layer over the channel region of the substrate, wherein forming the tunneling layer comprises oxidizing the substrate to form an oxide film and nitriding the oxide film; forming an oxygen-containing first layer on the tunneling layer An oxygen-deficient second layer and a separate multilayer charge trapping layer comprising one of the anti-tunneling layers separating the oxide of the first layer and the second layer; and forming a barrier layer over the separated multilayer charge trap layer .

According to still another aspect of the present invention, a non-volatile charge trapping memory device includes: a channel region containing germanium; a tunneling layer positioned above the channel region; positioned above the tunneling layer and including an oxygen-containing layer a multilayer charge trapping layer of one layer and an anoxic second layer; and forming a barrier layer over the multilayer charge trap layer, wherein the tunneling layer comprises a nitrided oxide and comprises one of the regions adjacent to the channel a first region having a nitrogen concentration that is lower than a second region adjacent to one of the plurality of charge storage layers.

100‧‧‧Semiconductor components

500, 1100, 1300, 1400, 1500, 1726A, 1726B‧‧‧ memory components

102, 502, 1102‧‧‧Semiconductor-Oxide-Nitride-Oxide-Semiconductor Gate Stack

104, 504, 1104‧‧‧Oxide-nitride-oxide stack

106, 506, 1106, 1304‧‧‧ surface

108, 508, 612, 812, 1108, 1306, 1406, 1606, 1706‧‧‧ substrates

110, 1604, 1630‧‧‧Diffusion areas

112, 512, 1112, 1302, 1402, 1502, 1624, 1708‧‧‧ channel area

114, 514, 1114, 1320, 1420, 1514, 1608, 1722‧‧ ‧ gate layer

116, 216, 316, 416, 516, 616, 1116, 1316, 1414, 1508, 1618, 1714A-B‧‧‧ tunneling layer

118, 420, 518, 818, 1118, 1314, 1416, 1510, 1616, 1716 A-C‧‧‧ charge trapping layer

120, 220, 320, 520, 820, 1120, 1318, 1418, 1512, 1614, 1718‧‧ ‧ barrier

212, 312‧‧ channels

218, 318‧‧‧ memory layer

314, 814‧‧‧Control gate

413, 513, 613‧‧‧ interface

510, 1110‧‧‧ source and bungee regions

517, 617‧‧‧ center line

518A, 518B, 818A, 818B‧‧‧ NOx layer

525, 1125‧‧‧ gate cap layer

816‧‧‧Oxide

901-910, 1001-1006, 1200-1208‧‧‧ operations

1116A, 1118A, 1314A, 1316A, 1414A, 1416A, 1508A, 1510A‧‧‧ first area

1116B, 1118B, 1314B, 1316B, 1414B, 1416B, 1508B, 1510B‧‧‧ second area

1118C, 1314C, 1416C, 1510C‧‧‧ anti-through tunneling

1308, 1408, 1504‧‧‧ source area

1310, 1410, 1506‧‧‧ bungee area

1312, 1412‧‧ ‧ gate

1322, 1602, 1610, 1702‧ ‧ dielectric layer

1612, 1712‧‧

1622, 1628, 1710‧‧‧ semiconductor materials

1626‧‧‧Filling materials

1704‧‧‧ Sacrifice layer

The embodiments of the present invention are illustrative of the drawings, and are not limiting, wherein: FIG. 1 illustrates a cross-sectional view of an intermediate structure of a conventional semiconductor-oxide-nitride-oxide-semiconductor device.

Figure 2 illustrates an energy band diagram of the trapped charge distribution and trap density distribution of a conventional semiconductor-oxide-nitride-oxide-semiconductor element during stylization.

Figure 3 illustrates an energy band diagram of a conventional semiconductor-oxide-nitride-oxide-semiconductor device during erasing.

Figure 4 illustrates the stylization and erasing time of a conventional semiconductor-oxide-nitride-oxide-semiconductor component using a conventional oxide-nitride-oxide stack.

5 is a partial cross-sectional view showing a portion of a scaled non-volatile charge trapping memory device having a nitride oxide tunneling layer, a multilayered NOx charge trapping layer, and a dense barrier layer, in accordance with an embodiment of the invention. Scale the oxide-nitride-oxide structure.

FIG. 6 illustrates an approximate nitrogen concentration profile of the nitride oxide tunneling layer in accordance with an embodiment of the invention.

FIG. 7A is a schematic diagram showing a stylized voltage display showing a reduction in contribution to a nitride nitride tunneling layer, in accordance with an embodiment of the invention. FIG.

Figure 7B illustrates a comparison of the two rich profiles of hydrogen, nitrogen, oxygen and helium in the barrier layer, charge trapping layer and tunneling layer of two different semiconductor-oxide-nitride-oxide-semiconductor type elements.

8A illustrates a retention mode energy band diagram of a scaled semiconductor-oxide-nitride-oxide-semiconductor type device in accordance with an embodiment of the present invention.

8B illustrates an energy band diagram illustrating the trapped charge distribution and trap density distribution of a scaled semiconductor-oxide-nitride-oxide-semiconductor type device during stylization, in accordance with an embodiment of the present invention.

9 is a semiconductor-oxide-nitrogen of a scaled oxide-nitride-oxide structure comprising a nitride oxide tunneling layer, a multilayer charge trapping layer, and a reoxidation barrier layer, in accordance with an embodiment of the invention. Flowchart of a compound-oxide-semiconductor scaling method.

Figure 10 is a flow diagram of a semiconductor-oxide-nitride-oxide-semiconductor scaling method for forming a nitride oxide tunneling layer.

11A and 11B are partial cross-sectional views of a scaled non-volatile charge trapping memory device having a scale including a nitride oxide tunneling layer, a multilayer charge trapping layer, and a dense barrier layer, in accordance with an embodiment of the invention. Oxide-nitride-oxide structure.

12 is a flow chart illustrating a method of forming a scaled non-volatile charge trapping memory device having a nitride oxide tunneling layer, a multilayer charge trapping layer, and a dense barrier layer, in accordance with an embodiment of the invention. Scale the oxide-nitride-oxide structure.

FIG. 13A illustrates a non-planar multi-gate device including a nitride oxide tunneling layer, a separate multilayer charge trapping layer, and a dense barrier layer, in accordance with an embodiment of the invention.

Figure 13B illustrates a cross-sectional view of the non-planar multi-gate element of Figure 13A.

14A and 14B illustrate a non-planar multi-gate element comprising a nitride oxide tunneling layer, a separate multilayer charge trapping layer, a dense barrier layer, and a horizontal nanowire channel, in accordance with an embodiment of the invention.

Figure 14C illustrates a cross-sectional view of the vertical string of the non-planar multi-gate element of Figure 14A.

15A and 15B illustrate a non-planar multi-gate element comprising a nitride oxide tunneling layer, a separate multilayer charge trapping layer, a dense barrier layer, and a vertical nanowire channel.

16A through 16F illustrate a gate priority scheme for fabricating the non-planar multi-gate element of Fig. 15A.

17A through 17F illustrate a gate post-production scheme for fabricating the non-planar multi-gate element of Fig. 15A.

Embodiments for scaling a non-volatile charge trapping memory component are described herein with reference to the drawings. However, specific embodiments may be practiced without one or more of these specific details or in combination with known methods, materials, and devices. Numerous specific details are set forth in the following description, such as the specific materials, dimensions, and process parameters, to provide a thorough understanding of the invention. In other examples, well-known semiconductor design and fabrication techniques are not specifically described to avoid unnecessarily obscuring this invention. The reference to "an embodiment" in this specification means that the specific features, structures, materials or characteristics described in connection with the embodiments are included in at least one embodiment of the invention. Thus, appearances of the phrase "in an embodiment" Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner into one or more embodiments.

Some embodiments of the invention include a scaled semiconductor-oxide-nitride-oxide-semiconductor type component. In a particular embodiment of the invention, the tunneling layer, charge trapping layer, and barrier layer are altered to scale the semiconductor-oxide-nitride-oxide-semiconductor type element. In a particular embodiment, the scaled semiconductor-oxide-nitride-oxide-semiconductor component is operable to program and erase voltages below +/- 10 volts. In some such embodiments, the scaled semiconductor-oxide-nitride-oxide-semiconductor component operates at an erase voltage between -5 volts and -9 volts, and preferably between -5 Volt to -7 volts to provide an initial erase voltage critical level (VTE) of -1 to -3 volts, and between 1 and 10 milliseconds when operating between -40 and 95 degrees Celsius (°C) After the pulse, the erase voltage critical level is preferably -2 to -3 volts. In other particular embodiments, the semiconductor-oxide-nitride-oxide-semiconductor type device operates at a stylized voltage between 5 volts and 9 volts, and preferably between 5 volts and 7 volts. To provide an initial programmed voltage threshold (VTP) of 1 volt to 3 volts, and after 1 millisecond to 10 milliseconds of programmed pulse, preferably 5 milliseconds of programmed pulse, the programmed voltage threshold is 2 volts. Up to 3 volts. These exemplary scaled semiconductor-oxide-nitride-oxide-semiconductor elements provide between 1 volt and 2 volts after 20 years at 85 ° C and at least 10,000 write/erase cycles, preferably 100,000 cycles. End of Life (EOL) memory window.

In some embodiments, a conventional pure oxygen (oxide) tunneling layer has a The nitrided oxide of the nitrogen concentration change curve is substituted to reduce the effective oxide thickness of the tunneling layer to the pure oxygen tunneling layer while retaining the low interface trap density. This reduces (reduces) the stylized/erase voltage while providing a better or better erase voltage threshold level (VTPNTE) than a conventional unscaled component. In certain other embodiments, the conventional nitride charge trapping layer is replaced with a multilayer oxynitride film having at least one top and bottom different stoichiometric layers. In one such embodiment, the multilayer oxynitride comprises a ruthenium-containing and oxygen-deficient top layer to position and limit the charge mass center away from the tunnel oxide layer, thereby locally increasing trap density in the charge trap layer . In certain other embodiments, the conventional high temperature oxide barrier layer is replaced with a reoxidation barrier layer to increase the barrier oxide density and thereby reduce the rate of memory degradation associated with scaling. Such embodiments provide sufficient net charge to a suitable memory window while also reducing trap assist tunneling to operate the semiconductor-oxide-nitride-oxide-semiconductor component in a reduced stylization/erasing Improve or maintain the stylized and erased threshold voltage (VTPNTE) at voltage.

The terms "above", "below", "between" and "upper" are used herein to refer to the relative position of one layer to the other. Accordingly, for example, a layer deposited or placed over or under another layer may be in direct contact with the other layer or have one or more interposers. Even a layer deposited or placed between layers may be in direct contact with the layers or have one or more interposers. In contrast, the first layer on a second layer is in contact with that second layer. Moreover, the relative position of one layer provided relative to the other layers assumes that the deposition, modification, and removal operations of the film relative to the starting substrate do not take into account the absolute orientation of the substrate.

According to an embodiment of the invention, the non-volatile charge trapping memory component is a semiconductor-oxide-nitride-oxide-semiconductor type component, wherein a charge trapping layer is an insulator layer such as a nitride. In another embodiment, the non-volatile charge trapping memory component A flash memory type device, wherein the charge trap layer is a conductor layer or a semiconductor layer such as polysilicon. The non-volatile charge trapping memory component using the nitride oxide tunneling layer can enable a lower stylization or erase voltage and provide a good or better erase voltage critical level (VTPNTE) than a conventional component. .

5 is a partial cross-sectional view showing a portion of a scaled non-volatile charge trapping memory device having a nitride oxide tunneling layer, a multilayered NOx charge trapping layer, and a dense barrier layer, in accordance with an embodiment of the invention. Scale the oxide-nitride-oxide structure. It should be understood that various other semiconductor-oxide-nitride-oxide-semiconductor embodiments disclosed herein can also be utilized to produce a scaled oxide-nitride-oxide stack that exceeds the particular embodiment illustrated in FIG. However, it is also possible to operate at a reduced stylized/erased voltage. Accordingly, while the features of FIG. 5 may be referenced throughout the specification, the invention is not limited to this particular embodiment.

In the particular embodiment illustrated in FIG. 5, the semiconductor-oxide-nitride-oxide-semiconductor type device 500 includes a semiconductor-oxide-nitride-oxide-semiconductor gate stack 502, which is formed in a An oxide-nitride-oxide stack 504 over surface 506 of substrate 508. The semiconductor-oxide-nitride-oxide-semiconductor type component 500 further includes one or more source and drain regions 510 that are aligned to the gate stack 502 and separated by a channel region 512. In general, the scaled semiconductor-oxide-nitride-oxide-semiconductor gate stack 502 includes a gate layer 514 formed thereon that contacts the scaled oxide-nitride-oxide stack 504 and a portion of the substrate 508. . The gate layer 514 and the substrate 508 are separated or electrically isolated by the scaled oxide-nitride-oxide stack 504.

In one embodiment, the substrate 508 is a bulk substrate composed of a single crystalline material that may comprise yttrium, lanthanum, ytterbium, or a group III-V compound semiconductor material, but is not limited thereto. In another In an embodiment, the substrate 508 is comprised of a body layer having a top epitaxial layer. In a specific embodiment, the body layer is composed of a single crystalline material which may include yttrium, lanthanum, cerium/lanthanum, a III-V compound semiconductor material, and quartz, but is not limited thereto, and the top epitaxial layer is composed of It may be composed of a single crystal layer of ruthenium, rhodium, iridium/ruthenium and a group III-V compound semiconductor material, but is not limited thereto. In another embodiment, substrate 508 is comprised of a top epitaxial layer on an intermediate insulator layer over a lower body layer. The top epitaxial layer is composed of a single crystal layer which may include germanium (that is, a germanium-on-insulator (SOI) semiconductor substrate), germanium, germanium/tellurium, and a group III-V compound semiconductor material, but is not limited thereto. . The insulating layer is composed of a material which may include cerium oxide, cerium nitride, and cerium oxynitride, but is not limited thereto. The lower body layer is composed of a single crystal material which may include yttrium, lanthanum, cerium/lanthanum, a group III-V compound semiconductor material, and quartz, but is not limited thereto. Substrate 508 and thus channel region 512 formed between the source and drain regions 510 can include dopant impurity atoms. In a particular embodiment, the channel region is P-type doped, and in an alternative embodiment, the channel region is N-doped.

The source and drain regions 510 within the substrate 508 can be any region having opposite conductivity to the channel region 512. For example, in accordance with an embodiment of the invention, the source and drain regions 510 are N-doped while the channel region 512 is P-doped. In one embodiment, substrate 508 is comprised of a boron doped single crystal germanium having a boron concentration in the range of 1 x 10 ^{15 -} 1 x 10 ¹⁹ atoms per cubic centimeter. The source and drain regions 510 are comprised of phosphorous or arsenic doped regions having an N-type dopant concentration in the range of 5 x ^{10 16 -} 5 x ^{10 19} atoms per cubic centimeter. In a particular embodiment, the source and drain regions 510 have a depth in the range of 80-200 nm in the substrate 508. In accordance with an alternative embodiment of the present invention, the source and drain regions 510 are P-type doped while the channel region of the substrate 508 is N-type doped. The semiconductor-oxide-nitride-oxide-semiconductor type device 500 further includes a gate stack 502 over the channel region 512, including an oxide-nitride-oxide stack 504, a gate layer 514, and a Gate cap layer 525. The oxide-nitride-oxide stack 504 further includes a tunneling layer 516, a charge trap layer 518, and a barrier layer 520.

In an embodiment, the tunneling layer 516 comprises a nitrided oxide. Since the stylized and erase voltages generate a large electric field of 10 million volts/cm across a tunneling layer, the stylized/erased tunneling current is greater than the tunneling barrier height ratio than the tunneling layer thickness The function. However, during the retention period, no large electric field occurs, and therefore, the charge loss is greater than the thickness of the tunneling layer as a function of the height of the barrier. In order to improve the tunneling current for reducing the operating voltage without sacrificing charge retention, in a particular embodiment, the tunneling layer 516 is a nitrided oxide. Nitriding increases the relative permittivity or dielectric constant (ε) of the tunneling layer by attracting nitrogen to a different pure hafnium oxide film. In some embodiments, the nitrided oxide tunneling layer 516 has the same physical thickness as a conventional semiconductor-oxide-nitride-oxide-semiconductor type component that utilizes a pure oxygen tunneling oxide. In a particular embodiment, the nitridation provides a tunneling layer having a effective dielectric constant of 5.07 at standard temperature.

In some embodiments, the nitride tunneling layer of the scaled semiconductor-oxide-nitride-oxide-semiconductor component has the same conventional unscaled semiconductor-oxide-nitride as the pure oxygen tunneling oxide. The physical thickness of the oxide-semiconductor type element. In general, the higher dielectric constant of the nitride tunneling oxide allows the memory layer to charge faster. In such embodiments, since the large electric field from the control gate spans the nitride tunneling oxide (due to the relatively high dielectric constant of the nitride tunneling oxide), the reduction is relatively small, so The charge trapping layer 518 charges faster than that thickness of pure oxygen tunneling oxide during stylization/erasing. These embodiments allow the semiconductor-oxide-nitride-oxide-semiconductor type component 500 to operate with a reduced stylized/erased voltage The stylized/erasing voltage critical level (VTPNTE) is the same as that of a conventional semiconductor-oxide-nitride-oxide-semiconductor type component. In a particular embodiment, the semiconductor-oxide-nitride-oxide-semiconductor type component 500 utilizes a tunneling layer 516 having a range of between 1.5 nm and 3.0 nm, and preferably between 1.9 nm. A nitrided tunneling oxide of physical thickness between meters and 2.2 nm.

In a further embodiment, the tunneling layer 516 is nitrided in a particular manner to reduce the trap density at the substrate interface to improve charge retention. For a particular embodiment where the nitride oxide tunneling layer is scaled to the same physical thickness as a pure oxygen tunneling oxide, the charge retention can be about the same as the pure oxygen tunneling oxide of the same thickness. Referring to Figure 6, an approximate nitrogen concentration profile in an embodiment of the tunneling layer 616 is illustrated, the nitrogen concentration 614 to the substrate interface 613 is rapidly reduced to limit a tantalum nitride (Si) in contact with the substrate 612. ₂ N ₄ ) layer formation. If a trap occurs at the substrate interface 613, the tantalum nitride layer comprising polar molecules disadvantageously increases the trap density, thereby reducing charge retention through trap-to-trap tunneling. Therefore, by adjusting the nitrogen concentration in the nitride tunneling oxide, the stylized/erase voltage Vcg can be lowered without significantly reducing the charge of the scaled semiconductor-oxide-nitride-oxide-semiconductor component. Reserved. As further shown in FIG. 4, 25% of the thickness of the tunneling layer 416 near the interface 413 is nitrided to have a nitrogen concentration 414 of less than about 5 x 10 ²¹ nitrogen atoms per cubic centimeter, near the charge trapping layer 420. 25% of the thickness of the tunneling layer 416 is nitrided to have at least 5 x 10 ²¹ nitrogen atoms per cubic centimeter.

In one embodiment, the oxide nitridation within the tunneling layer reduces its energy barrier and increases the dielectric constant relative to a pure oxide tunneling layer. As shown in FIG. 5, the tunneling layer 516 is labeled with a centerline 517 for illustrative purposes. 6 illustrates a similar centerline having a half thickness of the tunneling layer 616 proximate to the substrate 612 and a half thickness of the tunneling layer 616 proximate to the charge trapping layer 620. In a particular embodiment, the first 25% nitrogen concentration 614 across the thickness of the tunneling layer 616 is less than 5 x 10 ²¹ atoms/cm 3 and is at or 50% of the thickness of the tunneling layer 616. Line 617 is approximately 5 x 10 ²¹ atoms/cm 3 . In a further embodiment, the nitrogen concentration 614 in the last 25% of the thickness of the tunneling layer 616 near the charge trapping layer 618 exceeds 5 x 10 ²¹ atoms per cubic centimeter. In an exemplary configuration, for a 2.2 nm tunneling layer, the nitrogen concentration 614 within the first 0.6 nm of the tunneling layer proximate to the substrate 612 is less than 5 x 10 ²¹ atoms/cm 3 and is The 1.1 nm thickness of the tunneling layer 616 is at least 5 x 10 ²¹ atoms/cm 3 . In this manner, the tunneling layer capacitance can be increased without significantly reducing the charge retention of a scaled semiconductor-oxide-nitride-oxide-semiconductor type component.

FIG. 7A is a schematic diagram showing a stylized voltage display showing a reduction in contribution to a nitride nitride tunneling layer, in accordance with an embodiment of the invention. FIG. As shown, the leakage current on the retention voltage of the 20 angstrom pure oxide tunneling layer and the 40 Å nitride charge trapping layer is equal to 20 Å nitriding oxide tunneling layer and 40 Å nitride charge trapping layer, but The charging current on the stylized voltage of the nitride oxide tunneling layer is greater than the one of the pure oxide tunneling layers. Thus, a nitrided oxide tunneling layer in accordance with the present invention can provide the same uniform thickness as a conventional pure oxide tunneling layer having a 10 volt stylized or erased voltage at a stylized or erase voltage of 9.1 volts. Stylize/erase level.

Referring back to FIG. 5, the charge trapping layer 518 of the semiconductor-oxide-nitride-oxide-semiconductor type component 500 can further comprise any generally known charge trapping material and have any suitable thickness to store charge and condition the element. Threshold voltage. In some embodiments, the charge trapping layer 518 is tantalum nitride (SiN ₄ ), germanium-containing tantalum nitride or hafnium niobium oxide. The ruthenium containing film comprises an interfacial 矽 free bond. In a particular embodiment, the charge trap layer 518 has a uniform stoichiometry across the thickness of the charge trap layer. For example, the charge trap layer 518 can further comprise at least a oxynitride layer having different cerium, oxygen, and nitrogen constituents. Such compositional heterogeneity within the charge trapping layer has some performance efficiency advantages over conventional semiconductor-oxide-nitride-oxide-semiconductor charge trapping layers having a substantially homogeneous composition. For example, reducing the thickness of the conventional semiconductor-oxide-nitride-oxide-semiconductor charge trap layer increases the trap to trap tunneling, resulting in loss of data retention. However, when the stoichiometry of the charge trap layer is modified in accordance with an embodiment of the present invention, the thickness of the charge trap layer can be reduced while still maintaining good data retention.

In a particular embodiment, the bottom oxynitride layer 518 provides a localized region within the charge trapping layer having a relatively low trap state density, thereby reducing trap density at the tunneling oxide interface to reduce the scaling Trap assisted tunneling in semiconductor-oxide-nitride-oxide-semiconductor elements. This results in a reduction in the stored charge loss imparted to the thickness of the charge trap layer to enable charge trap layer scaling for the oxide-nitride-oxide stack effective oxide thickness scaling. In one such embodiment, the bottom oxynitride 518A has a first composition comprising a high cerium concentration, a high oxygen concentration, and a low nitrogen concentration to provide an oxynitride. The effective oxide thickness of this first oxynitride corresponding to between 1.5 nm and 5.0 nm may have a physical thickness between 2.5 nm and 4.0 nm. In a particular embodiment, the bottom oxynitride layer 518A has an effective dielectric constant ([epsilon]) of about 6.

In a further embodiment, a top oxynitride layer 5181B provides a localized region within a charge trapping layer having a relatively high trap state density. The relatively high trap state density enables a reduced thickness of the charge trapping layer to provide sufficient trapped charge to maintain a memory window within the scaled oxide-nitride-oxide stack. Therefore, the higher trap state density has a stylized and erased voltage difference between the memory elements that increase the thickness of a particular charge trap layer. The thickness of the charge trap layer is allowed to decrease and thereby the effect of the effective oxide thickness of the oxide-nitride-oxide of the scaled semiconductor-oxide-nitride-oxide-semiconductor element is reduced. In a particular embodiment, the top oxynitride layer composition has a high cerium concentration and a high nitrogen concentration and a low oxygen concentration to produce a nitrogen-containing nitrogen oxide. In general, the higher the top oxynitride content, the higher the trap state density provided by the top oxynitride and the lower the top NOx that can be reduced (thus reducing the thickness of the charge trap layer to enable lower voltage operation) The more layer thickness. Further, the higher the niobium content, the larger the dielectric constant and the smaller the effective oxide thickness of the top oxynitride layer. The effective oxide thickness reduction may be greater than the effective oxide thickness increase of the oxygen-containing bottom oxynitride relative to the conventional oxynitride charge-trapping layer having a substantially homogeneous composition for the charge-trapping layer on the effective oxide thickness Net reduced displacement. In one such embodiment, the top oxynitride has an effective dielectric constant of about 7.

7B illustrates an exemplary second ion mass spectrum indicating the concentration of yttrium (Si), nitrogen (N), oxygen (O), and hydrogen (H) after tunneling, charge trapping, and barrier deposition (during deposition) ( SIMS) curve. A baseline condition ("BL") and a double layer NOx condition as described in Figure 5 ("Bilayer") are repeated. The baseline condition has a conventional charge trapping layer containing a homogeneous composition. The x-axis represents a depth of 0 nm at the exposed top surface of the barrier layer that begins with stacking from top to bottom and terminates within the substrate. As shown, the two-layer conditional oxygen concentration corresponding to a portion of the charge trap layer is, of course, less than 1.0 x 10 ²² atoms/cm 3 in a depth region between about 5 nm and 10 nm. In contrast, the baseline condition exhibits a higher oxygen concentration that is substantially greater than 1.0 x 10 ²² in this same region. As further shown, the baseline condition has a substantially constant oxygen concentration between the 6 nm to 10 nm mark, and the bilayer condition is near the 10 nm mark than the 6 nm mark It actually shows more oxygen. This oxygen concentration non-uniformity represents the transfer between the anoxic top nitrogen oxide and the oxygenated bottom nitrogen oxide in the bilayer condition.

In certain embodiments, the ratio of the thickness of the bottom oxynitride layer to the thickness of the top oxynitride layer is between 1:6 and 6:1, and more preferably the bottom NOx thickness is to the top. The ratio of the thickness of the oxynitride is at least 1:4. In an exemplary configuration in which the first oxynitride has a physical thickness between 2.5 nanometers and 4.0 nanometers, for a charge trapping layer 518 having a net physical thickness between 7.5 nanometers and 10.0 nanometers. The second oxynitride 518B has a net physical thickness of between 5.0 nm and 6.0 nm. In a particular embodiment utilizing a bottom oxynitride having a physical thickness of 30 angstroms, the top oxynitride has a physical thickness of 60 angstroms for a scaled charge trapping layer having a net physical thickness of 90 angstroms.

In these particular embodiments, compositional heterogeneity is utilized to both locate and trap traps into the charge trapping layer (i.e., to concentrate the traps) at an in-situ site at a distance from the tunneling layer interface. 8A further illustrates a band diagram of a scaled semiconductor-oxide-nitride-oxide-semiconductor device during retention, the device comprising a nitride tunneling oxide 816, a multilayer charge trapping nitrogen oxide, in accordance with an embodiment of the invention. The object 818 and a dense barrier layer 820 between a substrate 812 and a control gate 814. As described, the compositional heterogeneity of the charge trapping layer 818 affects the valence and conduction band between the yttrium-containing top oxynitride 818B and the oxygen-containing bottom oxynitride 818A of the charge trapping layer. As shown in FIG. 8B, a charge trapping layer in accordance with an embodiment of the present invention provides energy band adjustment at the interface of the oxygen-containing and germanium-containing oxynitride layers within the charge trapping layer 818. The bandgap adjustment is used to position a center of the trapped charge within the top oxynitride layer that is imparted to the thickness of the charge trap layer further away from the substrate. Conductive band adjustment between the oxynitride layers can also be used to reduce reflow.

As further shown in FIG. 8A, in a particular embodiment, the cerium-containing top oxynitride 818B is oxidized or reoxidized. This type of ruthenium containing top region oxidation can produce a graded band gap near the barrier layer 810 relative to the previous oxidized band gap as illustrated by the dashed line for illustration purposes in FIG. 8A. In one embodiment, approximately one half of the top oxynitride layer 818B is reoxidized to have a higher oxygen concentration at the interface toward the barrier layer 820. In another embodiment, virtually all of the top oxynitride layer 818B is reoxidized to have a higher oxygen concentration than when deposited. In one embodiment, the reoxidation increases the oxygen concentration of the top oxynitride layer 818B by about 0.25 x 10 ^{21 -} 0.35 x 10 ²¹ atoms / cm. Embodiments that employ a re-oxidation of the charge trapping layer can prevent traps from drifting to the interface between the charge trapping layer and the barrier layer, thereby allowing the charge trapping layer to be reduced in thickness without causing a thinning of a substantially homogeneous composition. The charge associated with the capture layer retains an unfavorable result. Preventing this charge from drifting to the barrier oxide layer also reduces the electric field across the barrier oxide during erasing, which reduces electron reflow, or allows the barrier oxide to be shrunk while maintaining the same level of electron reflow. Such trap locations and limitations provided by different stoichiometric regions within the charge trap layer and further recombined as part of the charge trap layer in a particular embodiment may enable scaling of the semiconductor-oxide-nitride in accordance with the present invention. - Oxide-semiconductor components operate at a reduced voltage or faster stylized and erased time while maintaining good memory retention.

Although only the oxynitride layer is described, that is, a top and a bottom layer are in the patterns and elsewhere, the invention is not limited thereto, and the multilayer charge storage layer may comprise any number of oxynitride layers n Any or all of them have different oxygen, nitrogen and/or bismuth compositions. In particular, multilayer charge storage layers having up to 5 different compositions of oxynitride layers have been produced and tested.

As further described in FIG. 5, the oxide-nitride-oxide stack barrier layer 520 comprises a ruthenium dioxide layer between about 30 angstroms and about 50 angstroms. Scaling the barrier layer 520 in the oxide-nitride-oxide stack of the semiconductor-oxide-nitride-oxide-semiconductor type device is not common because under certain bias conditions, if not performed correctly The carrier reflow from the control gate is disadvantageously increased. In an embodiment comprising a portion of the reoxidized charge trap layer, the barrier layer 520 is a relatively dense tungsten oxide (HTO) that is deposited more densely. A dense oxide has a lower terminal hydrogen or hydroxide bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x ^{10 20} atoms per centimeter and is reduced to less than 8.0 x ^{10 19} atoms per centimeter in the dense film. In an exemplary embodiment, the high temperature oxide thickness during deposition is between 2.5 nanometers and 10.0 nanometers, and is 10% to 30% thinner everywhere due to densification.

In an alternative embodiment, the barrier oxide layer is further altered to integrate nitrogen. In one such embodiment, the nitrogen is integrated in an oxide-nitride-oxide stack across the thickness of the barrier oxide layer. Such a sandwich structure that replaces the conventional pure oxygen barrier layer advantageously reduces the overall stack effective oxide thickness between the channel and the control gate and enables adjustment of the conduction band displacement to reduce carrier reflow. The oxide-nitride-oxide block layer can then be integrated with the nitride tunneling oxide and a charge trapping layer comprising a bottom oxynitride layer and a top oxynitride layer.

A gate layer 514 is applied over the oxide-nitride-oxide stack 504. The gate layer 514 can be any conductor or semiconductor material. In one such embodiment, the gate layer 514 is polycrystalline. In another embodiment, the gate layer 514 comprises a metal such as hafnium, zirconium, titanium, hafnium, aluminum, hafnium, palladium, platinum, cobalt, and nickel, their tellurides, their nitrides, and their Carbide, but not limited to this. In a particular embodiment, the gate layer 514 has a Polycrystalline germanium having a physical thickness between 70 nm and 250 nm.

As further described in FIG. 5, the semiconductor-oxide-nitride-oxide-semiconductor type device 500 includes a gate cap layer 525 adjacent to the gate layer 514 and has approximately the same gate layer. The critical dimensions of 514 and oxide-nitride-oxide stack 504. In some embodiments, the gate cap layer 525 forms the top layer of the gate stack 502 and provides a hard mask during patterning of the gate layer 514 and the oxide-nitride-oxide stack 504. In some embodiments, the gate cap layer 525 facilitates the formation of self-aligned contacts (SAC) for the semiconductor-oxide-nitride-oxide-semiconductor elements. The gate cap layer 525 may be formed of any material that is capable of providing a subsequent etching process, such as, for example, hafnium oxide, hafnium nitride, and hafnium oxynitride, but is not limited thereto.

In a particular embodiment, a semiconductor-oxide-nitride-oxide-semiconductor type device utilizes an oxide-nitride-oxide stack comprising a 14 angstrom effective oxidation corresponding to a physical thickness of about 18 angstroms. a nitride tunneling oxide having a thickness corresponding to a physical thickness of about 25 angstroms having a bottom oxynitride layer having an effective oxide thickness of 20 angstroms and a physical thickness corresponding to a thickness of about 60 angstroms. A charge trapping layer of the top oxynitride layer of effective oxide thickness, and a barrier oxide layer deposited to 40 angstroms and densed to 30 angstroms. Such a semiconductor-oxide-nitride-oxide-semiconductor type device can be operated in a voltage range of approximately 9 volts to provide a -2 volt initial erase voltage critical level (VTE) after 1 millisecond to 10 millisecond pulses. .

Figure 9 illustrates a flow chart of a method of fabricating a scaled semiconductor-oxide-nitride-oxide-semiconductor such as that described in Figure 5, which includes a nitridation oxidation as described above. The tunneling layer, a partially reoxidized multilayer charge trapping oxynitride and a dense barrier oxide layer. The manufacturing method of FIG. 9 begins at operation 900, and includes a 矽 table on the substrate A nitride oxide tunneling layer is formed over the surface. Figure 10 illustrates a flow chart of a particular method of forming the nitrided oxide of operation 900 of Figure 9.

In the embodiment illustrated in FIG. 10, the nitrogen variation curve in the nitride tunneling oxide of a semiconductor-oxide-nitride-oxide-semiconductor type device is tailored to a multi-step nitridation and oxidation method. Finished. In operation 1001, a thin thermal oxide is formed from a germanium-containing layer on the surface of the substrate, such as substrate 508 of FIG. Since a good interface with the substrate is required, a chemical oxide formation can be a prelude to the thermal oxidation. Thus, in a particular embodiment, a chemical oxide is present during the thermal oxidation (as opposed to performing a conventional "hydrofluoric acid final treatment" pre-cleaning). In one such embodiment, the chemical oxide is grown with ozone water to form a chemical oxide layer having a thickness of about 1.0 nanometer.

The thermal oxide is formed to a thickness of between about 1.0 nm and 1.8 nm. In a particular embodiment, the thermal oxide is formed to a thickness of between 1.0 nm and 1.2 nm. Thus, in the embodiment where a 1.0 nm chemical oxide occurs during the thermal oxidation of operation 501, the surface oxide thickness does not actually increase, however, the oxide quality is improved. In a further embodiment, the oxide is relatively low density, facilitating subsequent integration of nitrogen having a significant weight percentage. However, a film density that is too low will produce too much nitrogen at the interface of the germanium substrate. Forming the ruthenium dioxide layer under operation 501 further serves as a means of blocking the formation of additional substrate oxide during subsequent heat treatment as further described below. In one embodiment, an atmospheric pressure vertical thermal reactor (VTR) is employed to present, for example, oxygen (O ₂ ), nitrous oxide (N ₂ O), at temperatures between 680 ° C and 800 ° C. The thermal oxide is grown in an oxidizing gas of nitrogen oxide (NO), ozone (O ₃ ), and steam (H ₂ O). The oxidation operation 1001 can be from 3.5 minutes to 20 minutes duration depending on the selected oxidant. In the atmospheric pressure embodiment, oxygen is used to form a film of about 1.0 nm of cerium oxide at a temperature between 700 ° C and 750 ° C for a period of 7 minutes to 20 minutes.

In another embodiment, the oxidation operation 1001 is performed using, for example, a sub-atmospheric processor of an Advanced Vertical Processor (AVP) commercially available from AVIZA Technologies, Inc. of Scott Valley, California. The advanced vertical processor can be operated within the temperature range of the vertical thermal reactor and at a pressure between 1 Torr (T) and atmospheric pressure. Depending on the operating pressure, the oxidation time of the hot ruthenium dioxide film used to form a thickness between about 1.0 nm and 1.8 nm can be extended by up to nearly one hour as may be determined by those skilled in the art.

Next, at operation 1002, in the plurality of oxidation and nitridation method embodiments illustrated in FIG. 10, the thermal oxide formed by operation 1001 is nitrided. Generally, at operation 1002, a nitrogen temper is performed to increase the dielectric constant (K) and reduce the fixed charge of the thermal oxide layer. In one embodiment, the nitrogen use tempering nitrogen (N ₂₎ or ammonia, for example, (NH ₃₎ hydrogenation of a nitrogen source. In another embodiment, the use of nitrogen tempering nitrogen sources such as deuterium, deuterated ammonia (DH ₃₎ of. In a particular embodiment, the nitrogen tempering is performed at a temperature between 700 ° C and 850 ° C for a period of from 3.5 minutes to 30 minutes. In another particular embodiment, the nitrogen tempering is performed at a temperature between 725 ° C and 775 ° C for a period of between 3.5 minutes and 30 minutes. In one such embodiment, the ammonia is introduced at atmospheric pressure between 725 ° C and 775 ° C for between 3.5 minutes and 30 minutes. In an alternative embodiment, the primary atmospheric ammonia tempering is performed in a processor such as the advanced vertical processor, at 800 ° C to 900 ° C for 5 minutes to 30 minutes. In yet another embodiment, a combination of nitrogen plasma and thermal tempering is generally performed.

Following operation 1002, a re-oxidation is performed at operation 1004. In one embodiment, during the reoxidation process, the oxidizing gas is thermally cracked to provide an oxy group near the surface of the film. These oxy groups eliminate nitrogen and hydrogen trap charges. The reoxidation operation 1002 also grows an additional oxide at the substrate interface to provide a physical displacement between the substrate and the nitrogen concentration within the tunneling layer. For example, referring back to FIG. 5, the reoxidation helps to separate the nitrogen concentration in the substrate interface 513 and the tunneling layer 516. As specifically shown in FIG. 6, for a configuration, the nitrogen concentration 614 at the substrate interface 613 in the tunneling layer 616 is significantly less than 5 x 10 ²¹ nitrogen atoms per cubic centimeter and may be 5 x ^{10 20} nitrogen atoms per cubic centimeter. grade. The nitrogen displacement from the substrate interface improves the retention of a semiconductor-oxide-nitride-oxide-semiconductor type element. In one embodiment, the thickness of the oxide grown by the substrate interface 613 is defined to be between 1.2 nm and 3.0 nm. At operation 1004, the reoxidation process conditions are selected such that the thermal oxide thickness formed by operation 1001 prevents oxidation greater than about 3.0 nm thickness, which can provide a tunneling layer that lacks any favorable nitrogen concentration. Those generally referred to as oxidants can be used in the reoxidation process, for example, nitrogen oxide, nitrous oxide, oxygen, ozone, and steam, but are not limited thereto. Any such oxidant can be introduced using a known thermal processor operating at temperatures between 800 °C and 900 °C. Depending on the operating parameters, the reoxidation time can be anywhere between 5 minutes and 40 minutes. In a particular embodiment, the nitrogen oxide is used in a one-pressure furnace operating at a temperature between 800 ° C and 850 ° C for a period of about 15 minutes to form a thickness of about 2.2 nm on a substrate. A nitride oxide film. In one such embodiment, the 2.2 nm thick reoxidized film forms a region between 0.5 nm and 0.8 nm near the interface of the tantalum substrate, the region having less than 5 x 10 ²¹ nitrogen atoms per cubic centimeter. Nitrogen concentration.

After the reoxidation operation 1004, a second nitrogen tempering is performed at operation 1006 to re-nitridate the tunneling layer. A second nitrogen tempering is employed to further increase the dielectric constant of the tunneling layer without introducing a significant amount of hydrogen or nitrogen traps at the substrate interface. In one embodiment, the second nitrogen tempering operation 1006 utilizes the same mode as the tempering performed in operation 1002. Conditions to implement it. In another embodiment, the second nitrogen tempering operation 1006 is performed at a higher temperature than the first nitrogen tempering operation 1002 to introduce additional nitrogen into the tunneling layer. In one embodiment, the nitrogen tempering utilizes a source of hydrogenated nitrogen such as ammonia. In another embodiment, the nitrogen tempering utilizes a source of deuterated nitrogen such as deuterated ammonia. In a particular embodiment, the nitrogen tempering operation 1006 utilizes ammonia at atmospheric pressure for a process time between 3.5 minutes and 30 minutes at a temperature between 750 ° C and 950 ° C. In another particular embodiment, the nitrogen tempering is performed at atmospheric pressure between 800 ° C and 850 ° C for 5 minutes to 10 minutes.

As described, operations 1001 through 1006 of FIG. 10 provide a dioxide operation and a diazotization operation. The repetitive oxidation and nitridation scheme allows the concentration of nitrogen in the tunneling layer to be tailored to achieve a reduction in stylized voltage or an increase in stylized speed with a semiconductor-oxide-nitride-oxide - Increase in memory retention of semiconductor type components. The continuous nature of the oxidation, nitridation, reoxidation, and re-nitridation operations 1001-1006 allows a nitrogen concentration in the tunneling layer of less than 3.0 nm thickness to be estimated while providing an interface between the tunneling layer and the substrate. Very few nitrogen and hydrogen traps. The separate oxidation, nitridation, reoxidation, and re-nitridation operations 1001-1006 allow the first and second oxidations and the first and second nitridation to be performed under independent design conditions to provide a greater measure of freedom Customize the curve of nitrogen concentration in a tunnel. In an advantageous embodiment, operations 1001, 1002, 1004, and 1006 are performed continuously within a single thermal processor without removing the substrate from the processor between operations. In one such embodiment, the process pressure is maintained at atmospheric pressure used in operations 1001-1006. First, the oxidation operation 1001 is performed at a temperature between 700 ° C and 750 ° C. The gas flow is then varied as specified to perform the nitrogen tempering operation 1002 at a temperature between 725 °C and 775 °C. The furnace temperature is then ramped up to between 800 ° C and 850 ° C and the gas flow is changed to perform the reoxidation operation Make 1004. Finally, as the furnace is maintained between 800 ° C and 850 ° C, the gas flow is again altered to perform the second nitrogen tempering operation 1006.

As the nitride oxide tunneling layer 516 of FIG. 5 is truly completed, the oxide-nitride-oxide stack can be continued by returning to the method described in FIG. In one embodiment, a plurality of nitride or oxynitride-based layer on the charge trapping operation in 902 and 904 to a low pressure chemical vapor deposition process, including for example, using Silane (SiH _4), dichloro Silane (SiH ₂ Cl ₂ ) a source of ruthenium tetrachloride (SiCl ₄ ) or a double tertiary butylamino decane (BTBAS) such as nitrogen, ammonia, nitrous oxide or nitrogen trioxide (NO ₃ ) and such as oxygen or oxidation A process gas of a nitrogen-containing oxygen-containing gas is formed. Alternatively, use of hydrogen gas has been substituted by deuterium, deuterated ammonia, for example, comprise (ND ₃₎ Alternative ammonia. Replacing hydrogen with hydrazine advantageously passivates the ruthenium dangling bonds at the interface of the substrate, thereby increasing the NBTI (negative bias temperature instability) lifetime of the semiconductor-oxide-nitride-oxide-semiconductor type element.

In an exemplary configuration, at operation 902, an oxynitride charge trap layer can be maintained by placing the substrate in a deposition chamber and introducing a process gas comprising nitrous oxide, ammonia, and methylene chloride. The chamber is maintained at a temperature of from about 5 millitorr (mT) to 500 millitorr and maintains the substrate at a temperature of from about 700 degrees Celsius to 850 degrees Celsius, and preferably at least about 780 degrees Celsius, for a period of about 2.5 minutes. It is deposited over a tunneling layer for up to 20 minutes. In a further embodiment, the process gas can comprise a first gas mixture of nitrous oxide and ammonia mixed in a ratio of from about 8:1 to 1:8 and a dichloride mixed from about 1:7 to 7:1 ratio. A second gas mixture of decane and ammonia, and may be introduced at a flow rate of from about 5 to 200 standard cubic centimeters per minute (sccm). It has been discovered that the oxynitride layer produced or deposited under these conditions produces a ruthenium-containing and oxygen-containing oxynitride layer, such as charge trapping layer 518A as described in FIG. The formation of the charge trap layer may further involve the chemical vapor deposition process of operation 904, using from about 8:1 to a first gas mixture of 1:8 ratio mixed nitrous oxide and ammonia and a second gas mixture of dichlorosilane and ammonia mixed from about 1:7 to 7:1 ratio, about 5 to 20 standard cubic centimeters per minute The flow rate is introduced to produce a ruthenium-containing, nitrogen-containing, and oxygen-deficient oxynitride layer, such as charge trapping layer 518B as described in FIG.

In one embodiment, at operations 902 and 904, a charge trap layer formation is then performed in the same process tool used to form the tunneling layer, and the substrate is not deposited from between 901 and 904. Removed from the chamber. In a particular embodiment, the charge trapping layer is deposited without changing the temperature at which the substrate is heated during the second nitrogen tempering operation 1006 of FIG. In one embodiment, after nitriding the tunneling layer in operation 901, the charge trapping layer generates a desired gas ratio by changing the flow rate of the ammonia gas and introducing nitrous oxide and dichlorosilane. The tantalum and the oxygen-containing layer and a nitrogen-containing nitrogen-containing oxynitride layer or two of a two-layer configuration are sequentially and immediately deposited.

Following operation 904, a barrier layer can be formed at operation 906 via any suitable means including, for example, thermal oxidation or deposition with chemical vapor deposition techniques. In a preferred embodiment, the barrier layer is formed by a high temperature chemical vapor deposition process. In general, the deposition process involves providing a source of ruthenium such as decane, dichlorodecane or tetrachloromethane and an oxygen-containing gas such as oxygen or nitrous oxide at a pressure of from about 50 mTorr to about 1000 mTorr. In a deposition chamber, the period of time is from about 10 minutes to 120 minutes while maintaining the substrate at a temperature of 650 ° C to 850 ° C. Preferably, the barrier layer is deposited sequentially in the same manner as the process tools used to form the charge trap layer in operations 902 and 904. More preferably, the barrier layer is formed by a process tool identical to both the charge trapping layer (each layer) and the tunneling layer, and the substrate is not removed between operations.

In the embodiment illustrated in FIG. 9, the barrier layer deposited by operation 906 is reoxidized at operation 908 to increase the barrier oxide density. As described elsewhere herein, operation 908 may further oxidize or reoxidize a portion or all of the charge trapping layer, for example, a portion or all of charge trapping layer 518B of FIG. 5B to obtain a graded strip such as that depicted in FIG. 8A. Gap. In general, the reoxidation is carried out in the presence of an oxidizing gas such as oxygen (O ₂ ), nitrous oxide (N ₂ O), nitrogen oxide (NO), ozone (O ₃ ), and steam (H ₂ O). In one embodiment, the reoxidation process can be performed at a temperature that is higher than the barrier layer deposition temperature. Reoxidation after deposition of the barrier oxide causes the oxidant diffusion to be more controlled to controllably oxidize or reoxidize the thin charge trapping layer. In a particularly advantageous embodiment, a dilute wet oxidation is utilized. The dilution wet oxidation differs from a wet oxidation in that the hydrogen to oxygen ratio is between 1 and 1.3. In a particular embodiment, the dilute oxidation having a hydrogen to oxygen ratio of about 1.2 is carried out at a temperature between 800 ° C and 900 ° C. In a further embodiment, the dilution oxidation duration may be sufficient to grow cerium oxide between 5.0 nm and 12.5 nm on a substrate. In one such embodiment, the duration is sufficient to grow a layer of ceria having a thickness of from about 10 nm to about 1.1 nm on a substrate. Such a dilute oxidation process is used to reoxidize the deposition barrier oxide and may further oxidize or reoxidize a portion of the charge trap layer to impart a conduction band structure as described in FIG. 8A or 8B. In another embodiment, the reoxidation operation 908 can further be used to non-semiconductor-oxide-nitride-oxide-semiconductors on the same substrate as the semiconductor-oxide-nitride-oxide-semiconductor type device. A gate oxide, for example, for a complementary metal oxide semiconductor (CMOS) field effect transistor (FET) is formed in the type of device region. In another embodiment, the re-oxidation operation 908 can be further used to diffuse germanium into portions of the charge trapping layer or barrier layer of the semiconductor-oxide-nitride-oxide-semiconductor type element.

As illustrated in FIG. 9, the method can then be completed at operation 910 as, for example, the gate layer formation of gate layer 514 of FIG. In some embodiments, operation 910 can further include the formation of a gate cap layer, such as gate cap layer 525 of FIG. As the gate stack fabrication is completed, a further process can occur as is known in the art to terminate the fabrication of the semiconductor-oxide-nitride-oxide-semiconductor type component 300.

Although the present invention has been described in terms of structural features and/or methods, it is understood that the invention is not limited by the specific features or acts. The particular features and acts disclosed are intended to be illustrative of the particular embodiments of the invention.

Configuration method and alternatives

Figure 11A illustrates a cross-sectional view of an intermediate structure of a semiconductor-oxide-nitride-oxide-semiconductor type device 1100 having a nitride oxide tunneling layer, a multilayer charge trapping layer, and a dense barrier layer. The scaled oxide-nitride-oxide structure. It should be understood that various other semiconductor-oxide-nitride-oxide-semiconductor embodiments disclosed herein can also be utilized to produce a scaled oxide-nitride-oxide stack that extends beyond the particular embodiment illustrated in Figure 11A. However, it is also possible to operate at a reduced stylized/erased voltage. Accordingly, although the features of FIG. 11A may be referenced throughout the specification, the invention is not limited to this particular embodiment.

In the particular embodiment illustrated in FIG. 11A, the semiconductor-oxide-nitride-oxide-semiconductor type device 1100 includes a semiconductor-oxide-nitride-oxide-semiconductor gate stack 1102, which is formed in a An oxide-nitride-oxide stack 1104 over the surface 1106 of the substrate 1108. The semiconductor-oxide-nitride-oxide-semiconductor type component 1100 further includes one or more source and drain regions 1110 aligned to the gate stack 1102 and comprised of a channel region 1112 is electrically connected. In general, the scaled semiconductor-oxide-nitride-oxide-semiconductor gate stack 1102 further includes a gate layer 1114 formed thereon and contacting the scaled oxide-nitride-oxide stack 1104 and a A gate cap layer 1125 over the gate layer 1114. The gate layer 1114 and the substrate 1108 are separated or electrically isolated by the scaled oxide-nitride-oxide stack 1104.

In one embodiment, the substrate 1108 is a body substrate composed of a single crystalline material that may comprise yttrium, lanthanum, ytterbium, or a group III-V compound semiconductor material, but is not limited thereto. In another embodiment, substrate 1108 is comprised of a body layer having a top epitaxial layer. In a specific embodiment, the body layer is composed of a single crystalline material which may include yttrium, lanthanum, cerium/lanthanum, a III-V compound semiconductor material, and quartz, but is not limited thereto, and the top epitaxial layer It is composed of a single crystal layer which may include ytterbium, ytterbium, ytterbium/ytterbium and a group III-V compound semiconductor material, but is not limited thereto. In another embodiment, the substrate 1108 is comprised of a top epitaxial layer on an intermediate insulator layer over a lower body layer. The top epitaxial layer is composed of a single crystal layer which may comprise germanium (that is, to form a silicon-on-insulator (SOI) semiconductor substrate), germanium, germanium/tellurium, and a group III-V compound semiconductor material, but Not limited to this. The insulating layer is composed of a material which may include cerium oxide, cerium nitride, and cerium oxynitride, but is not limited thereto. The lower body layer is composed of a single crystal material which may include yttrium, lanthanum, cerium/lanthanum, a group III-V compound semiconductor material, and quartz, but is not limited thereto. The substrate 1108 and thus the channel region 1112 formed between the source and drain regions 1110 can include dopant impurity atoms. The channel region 1112 can comprise polycrystalline germanium or recrystallized polycrystalline germanium to form a single crystalline channel region. In a particular embodiment, the channel region 1112 includes a single crystalline germanium region that can be formed to have a <100> surface crystalline orientation relative to a long axis of the channel region.

The source and drain regions 1110 within the substrate 1108 can be any region having conductivity opposite the channel region 1112. For example, in accordance with an embodiment of the invention, the source and drain regions 1110 are N-doped while the channel region 1112 is P-doped. In one embodiment, the substrate 1108 is comprised of a boron doped monocrystalline germanium having a boron concentration in the range of 1 x 10 ^{15 -} 1 x 10 ¹⁹ atoms per cubic centimeter. The source and drain regions 1110 are comprised of phosphorous or arsenic doped regions having an N-type dopant concentration in the range of 5 x ^{10 16 -} 5 x ^{10 19} atoms per cubic centimeter. In a particular embodiment, the source and drain regions 1110 have a depth in the range of 80-200 nm within the substrate 508. In accordance with an alternative embodiment of the present invention, the source and drain regions 1110 are P-doped while the channel region of the substrate 1108 is N-doped.

The oxide-nitride-oxide stack 1104 includes a tunneling layer 1116, a multilayer charge trap layer 1118, and a barrier layer 1120.

In one embodiment, the tunneling layer 1116 comprises a nitrided oxide tunneling layer of nitrided oxide. Since the stylized and erase voltages generate a large electric field of 10 million volts/cm across a tunneling layer, the stylized/erased tunneling current is greater than the tunneling barrier height ratio than the tunneling layer thickness The function. However, during the retention period, no large electric field occurs, and therefore, the charge loss is greater than the thickness of the tunneling layer as a function of the height of the barrier. Nitriding increases the relative permittivity or dielectric constant (ε) of the tunneling layer to improve the tunneling current used to reduce the operating voltage. In a particular embodiment, the nitridation provides a tunneling layer 1116 having an effective dielectric constant between 4.75 and 5.25, and preferably between 4.90 and 5.1 (at standard temperature). In one such embodiment, the nitridation provides a tunneling layer having an effective dielectric constant of 5.07 at standard temperature.

In such embodiments, the reduced phase is due to the large electric field from the control gate spanning the nitride tunneling oxide (due to the relatively high dielectric constant of the nitride tunneling oxide). When less, the charge trapping layer 518 will charge faster during the stylization/erasing than the pure oxide tunneling layer of that thickness. These embodiments allow the semiconductor-oxide-nitride-oxide-semiconductor type device 1100 to operate with a reduced stylized/erase voltage while still achieving the same conventional semiconductor-oxide-nitride-oxidation Stylized/erased voltage critical level (VTPNTE) for semiconductor-semiconductor components.

In some embodiments, the nitride oxide tunneling layer has the same physical thickness as a conventional semiconductor-oxide-nitride-oxide-semiconductor type component using a pure oxide tunneling layer to improve the reduction. The tunneling current of the operating voltage without sacrificing charge retention. In some embodiments, the semiconductor-oxide-nitride-oxide-semiconductor type memory device 1100 utilizes a nitride oxide tunneling layer 1116 having a thickness between 1.5 nm and 3.0 nm, and more The good land is between 1.9 nm and 2.2 nm. In a particular embodiment illustrated in FIG. 11B, the nitride oxide tunneling layer 1116 includes a first region 1116A near the channel region 1112 having a nitrogen concentration of less than about 5 x 10 ²¹ nitrogen atoms per cubic centimeter and is adjacent to the multilayer A second region 1116B having a nitrogen concentration of at least 5 x 10 ²¹ nitrogen atoms per cubic centimeter at the charge trap layer 1118. In an embodiment illustrated in FIG. 11B, the first and second regions of the nitride oxide tunneling layer 1116 each comprise no more than about 25% of the thickness of the tunneling layer.

In a further embodiment, the multilayer charge trap layer 1118 comprises at least a dinitride layer having a different composition of germanium, oxygen, and nitrogen. In one embodiment, the multilayer charge trapping region comprises a substantially trap-free cerium-containing oxynitride-containing oxygen-containing first layer 1118A, and a dense trap containing cerium, nitrogen-containing, and oxynitride-containing Hypoxia second layer 1118B. It has been found that the oxygen-containing first layer 1118A reduces the charge loss rate after stylization and erasing, which exhibits a small voltage shift in the retention mode. The anoxic second layer 1118B improves the speed and increases stylization and The initial difference between the erase voltages is not compromised by the charge loss rate of the memory device fabricated using the bismuth-oxide-oxynitride-oxide-germanium structure embodiment, thus extending the operational life of the device.

In another embodiment, the multilayer charge trap layer 1118 is a separate multilayer charge trap layer further comprising an intermediate oxide having an oxide separating the oxygen-containing first layer 1118A and the oxygen-deficient second layer 1118B or Anti-pass tunnel layer 1118C. During the erasing of the memory element 1100, the holes drift toward the barrier layer 1120, but a majority of the trap hole charges are formed in the anoxic second layer 1118B. After stylization, electron charges accumulate at the interface of the anoxic second layer 1118B, thereby accumulating less charge at the interface below the oxygen-containing first layer 1118A. Further, because of the anti-tunneling layer 1118C, the electron charge tunneling probability trapped in the anoxic second layer 1118B is actually reduced. This can result in lower leakage results than these conventional memory components.

Although a dinitride layer is shown and described above, that is, a first and a second layer, the invention is not limited thereto, and the multilayer charge trap layer 1118 may comprise some oxide, nitride or oxynitride layer. n, any or all of which may have different oxygen, nitrogen and/or bismuth stoichiometric compositions. In particular, multilayer charge storage structures of up to 5 or even more nitride layers each having a different stoichiometric composition are taken into account. At least some of these layers are separated from the other layers by one or more relatively thin oxide layers. However, as will be appreciated by those skilled in the art, it is generally contemplated that a minimum number of layers can be utilized to accomplish a desired result to reduce the number of process steps required to produce the component and thereby provide a simpler and more robust process. . Even using as few layers as possible produces higher yields because it is easier to control the lesser stoichiometric composition and size.

In another embodiment, the barrier layer 1120 includes a relatively high temperature oxide (HTO) that is relatively denser when deposited. A dense high temperature oxide has a lower terminal hydrogen or hydroxide bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x ^{10 20} atoms per centimeter and is reduced to less than 8.0 x ^{10 19} atoms per centimeter in the dense film. In an exemplary embodiment, the thickness of the barrier layer 1120 containing a dense high temperature oxide during deposition is between 2.5 nm and 10.0 nm, and is 10% thinner to 10% due to densification. 30%.

In an alternative embodiment, the barrier layer 1120 is further altered to incorporate nitrogen. In one such embodiment, the nitrogen is integrated in an oxide-nitride-oxide stack across the thickness of the barrier layer 1120. Such a sandwich structure that replaces the conventional pure oxygen barrier layer advantageously reduces the effective oxide thickness of the entire stack between the channel region 1112 and the control gate 1114 and enables adjustment of the conduction band displacement to reduce carrier reflow. The oxide-nitride-oxide stack barrier layer 1120 can then be separated from the nitride oxide tunneling layer 1116 and including an oxygen-containing first layer 1118A, an oxygen-deficient second layer 1118B, and an anti-tunneling layer 1118C. The multi-layer charge trapping layer 1118 is integrated.

A method of forming or fabricating a memory device including a nitride oxide tunneling layer, a separate multilayer charge trapping layer, and a dense barrier layer will now be described with reference to the flow chart of FIG. 12 in accordance with an embodiment.

Referring to Figure 12, the method begins with an operation 1200 having a polysilicon-containing channel region formed in or on a substrate that is electrically coupled to a source region and a drain region within the substrate. As described above, the channel region may include P-type or N-type dopant impurity atoms. In a particular embodiment, the channel region is P-type doped, and in an alternative embodiment, the channel region is N-doped. The source and drain regions may be doped with dopant impurity atoms of the opposite type to the channel region. For example, in accordance with a particular embodiment, the source and drain regions are N-doped with a phosphorus or arsenic doped region having a concentration ranging from 5 x ^{10 16 to} 5 x ^{10 19} atoms per cubic centimeter, and the channel region is P-type. The doping contains boron having a concentration ranging from 1 x 10 ^{15 to} 1 x 10 ¹⁹ atoms/cm 3 .

At operation 1202, a tunneling layer comprising a nitrided oxide is formed over the channel region on the substrate. Generally, the tunneling layer including a nitride oxide is formed by thermally oxidizing the substrate to form an oxide film and then nitriding the oxide film. Because of a good interface with the substrate, a chemical oxide can be formed prior to the formation of the thermal oxide. In a particular embodiment, a chemical oxide is grown using ozone water to form a chemical oxide layer having a thickness of between about 1.0 nanometers. The thermal oxide is then formed to a thickness of between 1.0 nm and 1.8 nm. Preferably, the oxide is of a relatively low density to facilitate subsequent integration of nitrogen having a significant weight percentage. However, a film density that is too low will produce too much nitrogen at the interface of the germanium substrate. In one embodiment, an atmospheric pressure vertical thermal reactor (VTR) is employed at a temperature between 680 ° C and 800 ° C, such as oxygen (O ₂ ), nitrous oxide (N ₂ O), nitrogen oxides. When the oxidizing gas of (NO), ozone (O ₃ ), and steam (H ₂ O) is present, the thermal oxide is grown. The duration of the oxidation operation 1001 can range from 3.5 minutes to 20 minutes depending on the selected oxidant. In the atmospheric pressure embodiment, oxygen is used to form a film of about 1.0 nm of cerium oxide at a temperature between 700 ° C and 750 ° C for a period of from 7 minutes to 20 minutes.

In another embodiment, the thermal oxide is formed using, for example, a sub-atmospheric processor of an Advanced Vertical Processor (AVP) commercially available from AVIZA Technologies, Inc. of Scott Valley, California. The advanced vertical processor can be operated within the temperature range of the above-described vertical thermal reactor embodiment and at a pressure between 1 Torr (T) and atmospheric pressure. Oxidation of a thermal ruthenium dioxide film between about 1.0 nm and 1.8 nm thick depending on the operating pressure The time can be extended by up to nearly one hour as may be determined by a person familiar with the art.

Next, a nitrogen tempering is performed to nitride the thermal oxide layer to increase the dielectric constant (K) and reduce the fixed charge of the thermal oxide layer. In one embodiment, the nitrogen use tempering nitrogen (N ₂₎ or ammonia, for example, (NH ₃₎ hydrogenation of a nitrogen source. In another embodiment, the use of nitrogen tempering nitrogen sources such as deuterium, deuterated ammonia (DH ₃₎ of. In a particular embodiment, the nitrogen tempering is performed at a temperature between 700 ° C and 850 ° C for a period of time ranging from 3.5 minutes to 30 minutes. In another particular embodiment, the nitrogen tempering is performed at a temperature between 725 ° C and 775 ° C for a period of between 3.5 minutes and 30 minutes. In one such embodiment, ammonia is introduced at an atmospheric pressure between 725 ° C and 775 ° C for between 3.5 minutes and 30 minutes. In an alternative embodiment, the primary atmospheric ammonia tempering is performed in a processor such as the advanced vertical processor, at 800 ° C to 900 ° C for 5 minutes to 30 minutes. In yet another embodiment, a combination of nitrogen plasma and thermal tempering is generally performed.

Optionally, forming the nitride oxide tunneling layer further comprises reoxidizing the oxide film by exposing the substrate to oxygen, and re-nitriding the reoxidation by exposing the substrate to nitrogen oxide A nitrided oxide film. In one embodiment, during the reoxidation process, the oxidizing gas is thermally cracked to provide an oxy group near the surface of the film. These oxy groups eliminate nitrogen and hydrogen trap charges. The reoxidation operation also grows an additional oxide at the interface between the substrate and the tunneling layer to provide a physical displacement between the substrate and the nitrogen concentration within the tunneling layer. For example, referring back to FIGS. 11A and 11B, in one embodiment, the concentration of nitrogen within the tunneling layer 1116A is significantly less than the concentration of nitrogen within the tunneling layer 1116B. The nitrogen displacement from the substrate interface improves the retention of a semiconductor-oxide-nitride-oxide-semiconductor type element. In one embodiment, the thickness of the oxide grown at the substrate interface is defined to be between 1.2 nm and 3.0 nm. In the reoxidation process, conditions are selected such that the thickness of the thermal oxide formed by operation 1001 prevents oxidation of more than about 3.0 nanometers thick, which provides a tunneling layer that lacks any favorable nitrogen concentration. Those generally referred to as oxidants can be used in the reoxidation process, for example, nitrogen oxides, nitrous oxide, oxygen, ozone, and steam, but are not limited thereto. Any such oxidant can be introduced using a known thermal processor operating at temperatures between 800 °C and 900 °C. Depending on the operating parameters, the reoxidation time can be anywhere between 5 minutes and 40 minutes. In a particular embodiment, the nitrogen oxide is used in a one-pressure furnace operating at a temperature between 800 ° C and 850 ° C for a period of about 15 minutes to form a thickness of about 2.2 nm on a substrate. A nitride oxide film. In one such embodiment, the 2.2 nm thick reoxidized film forms a region between 0.5 nm and 0.8 nm near the interface of the germanium substrate, the region having less than 5 x 10 ²¹ nitrogen atoms per cubic centimeter. Nitrogen concentration.

After the reoxidation operation, a second nitrogen tempering is performed to re-nitridate the tunneling layer. A second nitrogen tempering is employed to further increase the dielectric constant of the tunneling layer without introducing a significant amount of hydrogen or nitrogen traps at the substrate interface. In one embodiment, the second nitrogen tempering operation 1006 is performed using the same conditions as the initial or first nitrogen tempering. In another embodiment, the second nitrogen tempering re-nitriding operation is performed at a higher temperature than the first nitrogen tempering to introduce additional nitrogen into the tunneling layer. In one embodiment, the nitrogen tempering utilizes a source of hydrogenated nitrogen such as ammonia. In another embodiment, the nitrogen tempering utilizes a source of deuterated nitrogen such as deuterated ammonia. In a particular embodiment, the nitrogen tempering operation 1006 utilizes ammonia at a temperature between 750 ° C and 950 ° C at a temperature between 750 ° C and 950 ° C for a process time between 3.5 minutes and 30 minutes. In another particular embodiment, the nitrogen tempering is performed at atmospheric pressure between 800 ° C and 850 ° C for 5 minutes to 10 minutes.

As described, operation 1202 and the reoxidation and renitridation provide a dioxide operation and a diazotization operation. The repetitive oxidation and nitridation scheme allows the concentration of nitrogen in the tunneling layer to be tailored to achieve a reduction in stylized voltage or an increase in stylized speed with a semiconductor-oxide-nitride-oxide - Increase in memory retention of semiconductor type components. The continuous nature of the oxidation, nitridation, reoxidation, and re-nitridation operations allows for a nitrogen concentration in the tunneling layer of less than 3.0 nm thickness to be estimated, while providing very little interface between the tunneling layer and the substrate. Nitrogen and hydrogen traps. The separate oxidation, nitridation, reoxidation, and re-nitridation operations allow the first and second oxidations and the first and second nitridation to be performed in accordance with independent design conditions to provide greater freedom A curve of nitrogen concentration in a tunnel is formed. In an advantageous embodiment, the operation is continuously performed within a single thermal processor without removing the substrate from the processor between operations. In one such embodiment, the process pressure is maintained at atmospheric pressure. The first oxidation operation is performed at a temperature between 700 ° C and 750 ° C. The gas flow is then varied as specified to perform the nitrogen tempering operation at a temperature between 725 ° C and 775 ° C. The furnace temperature is then ramped up to between 800 ° C and 850 ° C and the gas flow is changed to perform the reoxidation operation. Finally, as the furnace is maintained between 800 ° C and 850 ° C, the gas flow is again changed to perform the second nitrogen tempering operation.

In operation 1204, a multilayer charge trapping layer is formed over the nitride oxide tunneling layer. In general, the multilayer charge trapping layer comprises a substantially trap free oxygen-containing first layer and a trap-dense anoxic second layer. In certain embodiments, the multilayer charge trapping layer is a separate multilayer charge trapping layer further comprising an anti-tunneling layer having an oxide separating the first layer from the second layer.

In a particular embodiment, the oxygen-containing first layer is subjected to a low pressure chemical vapor deposition process using, for example, decane (SiH ₄ ), chlorodecane (SiH ₃ Cl), dichlorodecane or DCS (SiH ₂ Cl ₂ ). a source of ruthenium tetrachloromethane (SiCl ₄ ) or a double tertiary butylamino decane (BTBAS) such as nitrogen (H ₂ ), ammonia (NH ₃ ), nitrogen trioxide (NO ₃ ) or nitrous oxide (N _{2 )} A nitrogen source of the class O) and an oxygen-containing gas such as oxygen (O ₂ ) or nitrous oxide (N ₂ O) are formed or deposited. For example, the oxygen-containing first layer can be maintained in the chamber by about 5 mTorr by placing the substrate in a deposition chamber and introducing a process gas comprising nitrous oxide, ammonia, and methylene chloride. (mT) to 500 mTorr and maintaining the substrate at a temperature between about 700 ° C and 850 ° C, and in some embodiments at least about 760 ° C for a period of about 2.5 minutes to 20 minutes. The time is deposited above the first deuterated layer. In particular, the process gas may comprise a first gas mixture having a mixture of nitrous oxide and ammonia in a ratio of from about 8:1 to 1:8, and having a mixture of dichloromethane and ammonia at a ratio of from about 1:7 to about 7:1. The second gas mixture can be introduced at a flow rate in the range of about 5 to 200 standard cubic centimeters (sccm) per minute. It has been discovered that the oxynitride layer produced or deposited under these conditions produces a first layer containing ruthenium and oxygen.

Alternatively, a gas that has been replaced by deuterium may be used, including, for example, ammonia instead of ammonia (ND ₃ ). The substitution of hydrogen facilitates the passivation of the ruthenium dangling bonds at the ruthenium-oxide interface, thereby increasing the NBTI (negative bias temperature instability) lifetime of the components.

A primary tunneling layer is then formed or deposited on the surface of the oxygen-containing first layer. The anti-tunneling layer can be formed or deposited via any suitable means including a plasma oxidation process, an on-site steam generation technique (ISSG) or a base oxidation process. In one embodiment, the base oxidation process involves flowing hydrogen (H ₂ ) and oxygen (O ₂ ) into a batch of processing tools or furnaces to consume a portion of the oxygen-containing first layer via oxidation to cause the tunneling resistance. The growth of the layer.

An oxygen-deficient second layer of the multilayer charge trapping region is then formed in the anti-channeling On the surface of the layer (1506). The oxygen-deficient second layer can be subjected to a chemical vapor deposition process using a process gas comprising nitrous oxide, ammonia and methylene chloride, at a pressure of from about 5 mTorr to 500 mTorr, and at about 700 From °C to 850 ° C, and in some embodiments at a substrate temperature of at least about 760 ° C, for a period of time from about 2.5 minutes to 20 minutes, is deposited over the anti-tunneling layer. In particular, the process gas may comprise a first gas mixture of nitrous oxide and ammonia mixed at a ratio of from about 8:1 to 1:8 and a second mixture of dichloromethane and ammonia at a ratio of from about 1:7 to 7:1. The gas mixture can be introduced at a flow rate of about 5 to 20 standard cubic centimeters per minute. It has been discovered that the oxynitride layer produced or deposited under these conditions produces a second layer containing ruthenium, nitrogen and oxygen.

In some embodiments, the anoxic second layer can be subjected to a chemical vapor deposition process using a process gas comprising a mixture of two tertiary butyl amino decane and ammonia (NH ₃ ) at a ratio of from about 1:7 to about 7:1. Deposited over the anti-tunneling layer to further include a selected carbon concentration to increase the number of traps therein. The selected carbon concentration in the second oxynitride layer can comprise a carbon concentration of from about 5% to 15%.

Next, at operation 1206, a barrier layer is formed over the multilayer charge trap layer or the separate multilayer charge trap layer. The barrier layer can be formed via any suitable means including, for example, thermal oxidation or deposition with chemical vapor deposition techniques. In a preferred embodiment, the barrier layer is formed by a high temperature chemical vapor deposition process. In general, the deposition process involves providing a source of ruthenium such as decane, dichlorodecane or tetrachloromethane and an oxygen-containing gas such as oxygen or nitrous oxide at a pressure of from about 50 mTorr to about 1000 mTorr. In a deposition chamber, the period of time is from about 10 minutes to 120 minutes while maintaining the substrate at a temperature of 650 ° C to 850 ° C. Preferably, the barrier layer is deposited sequentially in the same manner as the process tool used to form the multilayer charge trap layer. More preferably, the barrier layer is the same as the multilayer charge trapping The process tool of both the layer and the tunneling layer is formed and the substrate is not removed between operations.

In the embodiment illustrated in FIG. 12, the barrier layer deposited by operation 1206 is subjected to operation 1208 for reoxidation to densify the barrier oxide. Operation 1208 can further oxidize or reoxidize a portion of second region 1116B of the plurality of charge trapping layers 1116 to obtain a graded band gap such as that depicted in FIG. 8A, as described elsewhere herein. In general, the reoxidation can be performed in the presence of an oxidizing gas such as oxygen (O ₂ ), nitrous oxide (N ₂ O), nitrogen oxide (NO), ozone (O ₃ ), and steam (H ₂ O). In one embodiment, the reoxidation process can be performed at a temperature that is higher than the barrier layer deposition temperature. The reoxidation after deposition of the barrier oxide causes the oxidant diffusion to be more controlled to controllably oxidize or reoxidize a portion of the second region 1116B. In a particularly advantageous embodiment, a dilute wet oxidation is utilized. The dilution wet oxidation differs from a wet oxidation in that the hydrogen to oxygen ratio is between 1 and 1.3. In a particular embodiment, the dilute oxidation having a hydrogen to oxygen ratio of about 1.2 is carried out at a temperature between 800 ° C and 900 ° C.

In a further embodiment, the dilution oxidation is for a duration sufficient to grow cerium oxide between 5.0 nm and 12.5 nm on a substrate. In one such embodiment, the duration is sufficient to grow a layer of ceria having a thickness of from about 10 nm to about 1.1 nm on a substrate. Such a dilute oxidation process is used to reoxidize the deposition barrier oxide and may further oxidize or reoxidize a portion of the charge trap layer to impart a conduction band structure as described in Figure 8A or 8B.

In another embodiment, the reoxidation operation 1208 can be further utilized for non-semiconductor-oxide-nitride-oxide-semiconductors on the same substrate as the semiconductor-oxide-nitride-oxide-semiconductor type device. A gate oxide, for example, for a complementary metal oxide semiconductor (CMOS) field effect transistor (FET) is formed in the type of device region. In another embodiment, the reoxidation Operation 1208 can be further used to diffuse germanium into portions of the multilayer charge trapping or barrier layer of the semiconductor-oxide-nitride-oxide-semiconductor type device.

The method can then be completed with the formation of a gate layer such as gate layer 1114 of FIG. 11A, and in some embodiments, with the gate cap layer of gate cap layer 1125 as described, for example, in FIG. 11A. Formed and completed. As the gate stack fabrication is completed, a further process can occur as is known in the art to terminate the fabrication of the semiconductor-oxide-nitride-oxide-semiconductor type component 300.

In another aspect, the present disclosure also refers to a multi-gate or multi-gate surface memory element comprising a plurality of charge trapping layers formed on two or more sides of a channel on or above a substrate surface, and a method of fabricating the same. Multiple gate elements include both planar and non-planar components. A planar multi-gate element (not shown) generally includes a dual gate planar element, wherein some first layers are deposited to form a first gate below the subsequently formed channel region, and some second layers It is deposited over it to form a second gate. A non-planar multi-gate element generally comprises a horizontal or vertical channel region formed on or above a substrate surface and surrounded by a gate on three or more sides.

13A and 13B illustrate an embodiment of a non-planar multi-gate memory device comprising a plurality of charge trapping layers. Referring to Figure 13A, the memory component 1300, commonly referred to as a fin field effect transistor, includes a surface 1304 over a substrate 1306 connected to a source region 1308 and a drain region 1310 of the memory device. A channel region 1302 formed by a thin film or thin layer of germanium material. The three sides of the channel region 1302 are enclosed by fins that form the gate 1312 of the component. As with the above embodiments, the channel region 1302 can comprise polycrystalline germanium or recrystallized polycrystalline germanium to form a single crystalline channel region. Optionally, the channel region 1302 includes a single crystal Wherein, the channel region can be formed to have a <100> surface crystal orientation with respect to a long axis of the channel region.

The thickness of the gate 1312 (estimated from the source to the drain) determines the effective channel length of the memory element.

According to the present disclosure, the non-planar multi-gate memory device 1300 of FIG. 13A can include a separate charge trapping layer, a nitride oxide tunneling layer, and a dense barrier layer. 13B is a partial cross-sectional view of a non-planar memory device of FIG. 13A, including a portion of substrate 1306, channel region 1302, and illustrating a multilayer charge trap layer 1314, a nitride oxide tunneling layer 1316, and a dense barrier layer 1318. The gate 1312. The gate 1312 further includes a metal gate layer 1320 positioned over the barrier layer to form a control gate of the memory device 1300. In some embodiments, a doped polysilicon instead of a metal can be deposited to replace the metal to provide a polysilicon gate layer. The channel region 1302 and the gate 1312 can be formed directly on the substrate 1306 or on an insulating or dielectric layer 1322 such as a buried oxide layer formed on or over the substrate.

Referring to Figure 13B, the tunneling layer 1316 in some embodiments, such as the one shown, is a nitrided oxide tunneling layer 1316 and includes a nitrogen atom of less than about 5 x 10 ²¹ at the channel region 1302. A first region 1316A of cubic centimeter nitrogen concentration and a second region 1316B near the multilayer charge trapping layer 1314 having a nitrogen concentration of at least 5 x 10 ²¹ nitrogen atoms per cubic centimeter. In one embodiment, similar to that disclosed in FIG. 11B, the first and second regions of the nitride oxide tunneling layer 1316 each comprise no more than about 25% of the thickness of the tunneling layer.

The multilayer charge trap layer 1314 includes at least one oxygen-containing first layer 1314A adjacent to the tunneling layer 1316 and an oxygen-deficient second layer 1314B positioned above the oxygen-containing first layer. In general, the anoxic second layer 1314B comprises a germanium-containing and anoxic nitride-containing layer and comprises a plurality of charge traps disposed within the multilayer charge trap layer 1314, and the oxygen-containing first layer 1314A comprises an oxynitride or bismuth oxynitride and is oxygen-containing relative to the oxygen-deficient second layer to reduce The number of charge traps. Oxygenation means that the oxygen concentration in the oxygen-containing first layer 1314A is from about 15 to 40%, and the oxygen concentration in the oxygen-deficient second layer 1314B is less than 5%.

In some embodiments, such as the one shown in FIG. 13B, the multi-layer charge storage layer 1314 further includes at least one thin intermediate or anti-tunneling layer 1314C containing a dielectric layer such as an oxide to deplete the oxygen-deficient second. Layer 1314B is separated from the oxygen-containing first layer 1314A. As described above, the anti-tunneling layer 1314C actually reduces the likelihood that electron charges accumulated at the interface of the anoxic second layer 1314B during tunneling will tunnel to the oxygen-containing first layer 1314A.

As with the above embodiments, either or both of the oxygen-containing first layer 1314A and the oxygen-deficient second layer 1314B may comprise tantalum nitride or hafnium oxynitride, and may, for example, comprise nitrous oxide/ammonia and dichloride. A chemical vapor deposition process of a decane/ammonia gas mixture is formed by providing a niobium-containing and oxygen-containing oxynitride layer at a tailored ratio and flow rate. An oxygen-deficient second layer of the multilayer charge storage structure is then formed on the intermediate oxide layer. The oxygen-deficient second layer 1314B has a stoichiometric composition of oxygen, nitrogen and/or bismuth different from the bottom oxygen-containing first layer 1314A, and may also be subjected to a chemical vapor deposition process using dichloromethane/ammonia and The process gas of the nitrous oxide/ammonia gas mixture is formed or deposited by providing a niobium-containing and oxygen-containing top nitride layer at a tailored ratio and flow rate.

In those embodiments comprising an intermediate or anti-tunneling layer 1314C, the anti-tunneling layer can be formed using a base oxidation to oxidize the oxygen-containing first layer 1314A to a selected depth. The base oxidation can be carried out using, for example, a single wafer tool at a temperature of 1000-1100 ° C or using a batch of reactor tools at a temperature of 800-900 ° C. a mixture of hydrogen and oxygen The material can be used in a batch process at 300-500 Torr or a single gas phase tool at 10-15 Torr, using a single wafer tool for 1-2 minutes, or using one The batch process lasts from 30 minutes to 1 hour.

A suitable thickness of the oxygen-containing first layer 1314A can range from about 30 angstroms to about 130 angstroms (with some variation, for example, ±10 angstroms), wherein a thickness of about 5-20 angstroms can be consumed via basal oxidation to form the Anti-pass tunnel layer 1314C. In some embodiments, the anoxic second layer 1314B can be formed up to 130 angstroms thick, wherein a thickness of 30-70 angstroms can be consumed via basal oxidation to form the barrier layer 1318. In some embodiments, the thickness ratio of the oxygen-containing first layer 1314A to the oxygen-deficient second layer 1314B is about 1:1, although other ratios are also possible.

The barrier layer 1318 includes a relatively high temperature oxide (HTO) that is relatively denser when deposited. A dense high temperature oxide has a lower terminal hydrogen or hydroxide bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x ^{10 20} atoms per centimeter and is reduced to less than 8.0 x ^{10 19} atoms per centimeter in the dense film. In an exemplary embodiment, the thickness of the barrier layer 1318 including a dense high temperature oxide is between 2.5 nm and 10.0 nm at the time of deposition, and is 10% thinner everywhere due to the densification. Up to 30%.

In an alternative embodiment, the barrier layer 1318 is further altered to integrate nitrogen. In one such embodiment, the nitrogen is integrated in an oxide-nitride-oxide stack across the thickness of the barrier layer 1318. Such a sandwich structure that replaces the conventional pure oxygen barrier layer advantageously reduces the effective oxide thickness of the entire stack between the channel region 1302 and the control gate 1320 and enables adjustment of the conduction band displacement to reduce carrier reflow. The oxide-nitride-oxide stack barrier layer 1318 can then be integrated with the nitride oxide tunneling layer 1316 and a separate multilayer charge trapping layer 1314 comprising an oxygen containing first layer 1314A, an oxygen deficient second layer 1314B, and an anti-tunneling layer 1314C.

In another embodiment shown in FIGS. 14A and 14B, the memory device can comprise a thin film of semiconductor material disposed over a surface of a substrate connected to a source region and a drain region of the memory device. Nano line channel area. The nanowire channel region means a conductive channel region formed in a thin strip of crystalline germanium material having a maximum cross-sectional dimension of about 10 nanometers (nm) or less, and preferably, less than about 6 nanometers. Meter. Optionally, the channel region can be formed to have a <100> surface crystal orientation relative to a long axis of the channel.

Referring to FIG. 14A, the memory device 1400 includes a thin film of semiconductor material or a thin layer formed on or above one surface of a substrate 1406 and connected to the source region 1408 and the drain region 1410 of the memory device. Line channel area 1402. In the illustrated embodiment, the component has a wound gate (GAA) structure in which all sides of the nanochannel region 1402 are enclosed by the gate 1412 of the component. The thickness of the gate 1412 (estimated from the source to the drain) determines the effective channel length of the component. As with the above embodiments, the nanowire channel region 1402 can comprise polycrystalline germanium or recrystallized polycrystalline germanium to form a single crystalline channel region. Optionally, the channel region 1402 includes a single crystalline germanium region that can be formed to have a <100> surface crystalline orientation relative to a long axis of the channel region.

In accordance with the present disclosure, the non-planar multi-gate memory device 1400 of FIG. 14A can include a separate charge trap layer, a nitride oxide tunneling layer, and a dense barrier layer. 14B is a partial cross-sectional view of a non-planar multi-gate element of FIG. 14A, including a portion of substrate 1406, a nanowire channel region 1402, and the gate 1412. Referring to FIG. 14B, the gate 1412 includes a nitrogen The oxide tunneling layer 1414, a multilayer charge trap layer 1416, and a dense barrier layer 1418. The gate 1412 further includes a gate layer 1420 positioned over the barrier layer to form a control gate of the memory device 1400. The gate layer 1420 can include a deposition metal or a doped polysilicon.

In some embodiments, such as the one shown, the tunneling layer 1414 is a nitride oxide tunneling layer 1414 comprising a nitrogen concentration near the channel region 1402 of less than about 5 x 10 ²¹ nitrogen atoms per cubic centimeter. The first region 1414A and the second region 1414B having a nitrogen concentration of at least 5 x 10 ²¹ nitrogen atoms per cubic centimeter at the multilayer charge trap layer 1416. In one embodiment, similar to the one disclosed in FIG. 11B, the first and second regions of the nitride oxide tunneling layer 1414 each comprise no more than about 25% of the thickness of the tunneling layer.

The multilayer charge trap layer 1416 includes at least one thin oxygen-containing first layer 1416A adjacent to the nitride-containing layer 1414 and an outer anoxic second layer 1416B positioned above the oxygen-containing first layer. In general, the anoxic second layer 1416B includes a germanium-containing and oxygen-deficient nitride layer and includes a plurality of charge traps dispersed within the plurality of charge trap layers 1416, and the oxygen-containing first layer 1416A includes an oxygen-containing nitride. Or a layer of oxynitride and oxygen containing relative to the second layer of oxygen deficiency to reduce the number of charge traps therein. Oxygenation means that the oxygen concentration in the oxygen-containing first layer 1416A is from about 15 to 40%, and the oxygen concentration in the anoxic second layer 1416B is less than 5%.

In some embodiments, as shown in FIG. 14B, the multi-layer charge trap layer 1416 further includes at least one thin intermediate or anti-tunneling layer 1416C containing a dielectric layer such as an oxide to provide the second oxygen-deficient layer. Layer 1416B is separated from the oxygen-containing first layer 1416A. As described above, the anti-tunneling layer 1416C actually reduces the likelihood that electron charges accumulated at the interface of the anoxic second layer 1416B during tunneling will tunnel to the oxygen-containing first layer 1416A.

Like the above embodiment, the oxygen-containing first layer 1416A and the oxygen-deficient second layer Any one or both of 1416B may include tantalum nitride or hafnium oxynitride, and may be tailored to the ratio, for example, via a chemical vapor deposition process comprising a mixture of nitrous oxide/ammonia and a dichloromethane/ammonia gas. And a flow rate to provide a layer of ruthenium-containing and oxygen-containing oxynitride. An oxygen-deficient second layer of the multilayer charge storage structure is then formed on the intermediate oxide layer. The anoxic second layer 1416B has a stoichiometric composition of oxygen, nitrogen and/or helium different from the oxygen-containing first layer 1416A, and may also be subjected to a chemical vapor deposition process using dichloromethane/ammonia and oxidation. The process gas of the nitrous/ammonia gas mixture is formed or deposited by providing a niobium- and oxygen-deficient top nitride layer at a tailored ratio and flow rate.

In those embodiments comprising an oxide-containing intermediate or anti-tunneling layer 1416C, the anti-tunneling layer can be formed using a base oxidation to oxidize the oxygen-containing first layer 1416A to a selected depth. The base oxidation can be carried out using, for example, a single wafer tool at a temperature of 1000-1100 ° C or using a batch of reactor tools at a temperature of 800-900 ° C. A hydrogen and oxygen mixture can be used in a batch process at 300-500 Torr or a single gas phase tool at 10-15 Torr, using a single wafer tool for 1-2 minutes. Alternatively, use a batch process for a period of 30 minutes to 1 hour.

A suitable thickness of the oxygen-containing first layer 1416A can range from about 30 angstroms to about 130 angstroms (with some variation, for example, ±10 angstroms), wherein a thickness of about 5-20 angstroms can be consumed via basal oxidation to form the Anti-through tunnel layer 1416C. The oxygen-deficient second layer 1416B has a suitable thickness of at least 30 angstroms. In certain embodiments, the anoxic second layer 1416B can be formed up to 130 angstroms thick, wherein a thickness of 30-70 angstroms can be consumed via basal oxidation to form the barrier layer 1418. In some embodiments, the thickness ratio of the oxygen-containing first layer 1416A to the anoxic second layer 1416B is about 1:1, although other ratios are also possible.

The barrier layer 1418 includes a relatively high temperature oxide (HTO) that is relatively denser when deposited. A dense high temperature oxide has a lower terminal hydrogen or hydroxide bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x ^{10 20} atoms per centimeter and is reduced to less than 8.0 x ^{10 19} atoms per centimeter in the dense film. In an exemplary embodiment, the thickness of the barrier layer 1418 including a dense high temperature oxide is between 2.5 nanometers and 10.0 nanometers at the time of deposition, and is 10% thinner everywhere due to densification. Up to 30%.

In an alternative embodiment, the barrier layer 1418 is further altered to incorporate nitrogen. In one such embodiment, the nitrogen is integrated in an oxide-nitride-oxide stack across the thickness of the barrier layer 1418. Such a sandwich structure that replaces the conventional pure oxygen barrier layer advantageously reduces the effective oxide thickness of the entire stack between the channel region 1402 and the gate layer 1420 and enables adjustment of the conduction band displacement to reduce carrier reflow. The oxide-nitride-oxide stack barrier layer 1418 can then be coupled to the nitride oxide tunneling layer 1414 and include an oxygen-containing first layer 1416A, an oxygen-deficient second layer 1416B, and an anti-tunneling layer 1416C. The split multilayer charge trap layer 1416 is integrated.

14C illustrates a cross-sectional view of a vertical string of non-planar multi-gate elements 1400 arranged in a bit cost adjustable or BiCS architecture 1422 of FIG. 14A. The structure 1422 is formed by a vertical string or stack of non-planar multi-gate elements 1400, wherein each element or cell includes a source region and a drain region above the substrate 1406 and connected to the memory device (not The channel region 1402, shown in the drawing, has a wound gate (GAA) structure in which all sides of the nanowire channel region 1402 are enclosed by a gate region 1412. Compared to a simple layer stack, the BiCS The architecture reduces the number of critical lithography imaging steps, resulting in a reduction in cost per memory bit.

In another embodiment, the memory component is or comprises a non-planar component containing one of the semiconductor materials formed in or on a semiconductor material overlying or partially on a substrate. Rice noodle channel. In the first embodiment of the embodiment shown in Fig. 15A, the memory device 1500 includes a vertical nanowire channel region 1502 formed by a semiconductor material cylinder connecting the source region 1504 and the drain region 1506 of the device. . The channel region 1502 is surrounded by a tunneling layer 1508, a multilayer charge trapping layer 1510, a barrier layer 1512, and a gate layer 1514 over the barrier layer to form a control gate of the memory device 1500. The channel region 1502 can comprise an annular region within an outer layer of a substantially solid cylindrical body of semiconductor material, or can comprise an annular layer formed over a cylinder of dielectric filler material. Like the horizontal nanowires described above, the channel region 1502 can include polysilicon or recrystallized polysilicon to form a single crystalline channel region. Optionally, the channel region 1502 includes a crystalline germanium that can be formed to have a <100> surface crystalline orientation relative to a long axis of the channel.

In some embodiments, such as that shown in FIG. 15B, the tunneling layer 1508 is a nitrided oxide tunneling layer comprising a nitrogen concentration near the channel region 1502 having a nitrogen concentration of less than about 5 x 10 ²¹ nitrogen atoms per cubic centimeter. The first region 1508A and the second region 1508B having a nitrogen concentration of at least 5 x 10 ²¹ nitrogen atoms per cubic centimeter at the multilayer charge trap layer 1510. In one embodiment, similar to the one disclosed in FIG. 11B, the first and second regions of the nitride oxide tunneling layer 1508 each comprise no more than about 25% of the thickness of the tunneling layer.

The multilayer charge trap layer 1510 is a separate multilayer charge trap layer further comprising at least one thin oxygen-containing first layer 1510A adjacent to the tunneling layer 1508 and located above the first oxygen-containing layer Externally anoxic second layer 1510B. In general, the second layer of oxygen deficiency 1510B includes a germanium-containing and oxygen-deficient nitride layer and includes a plurality of charge traps dispersed within the plurality of charge trap layers 1510, and the oxygen-containing first layer 1510A includes an oxynitride or bismuth oxynitride layer relative to the layer The second layer of oxygen deficient is oxygenated to reduce the number of charge traps therein. Oxygenation means that the oxygen concentration in the oxygen-containing first layer 1510A is from about 15 to 40%, and the oxygen concentration in the anoxic second layer 1510B is less than 5%.

In some embodiments, as shown in FIG. 15B, the split multilayer charge trap layer 1510 further includes at least one thin intermediate or anti-tunneling layer 1510C containing a dielectric layer such as an oxide to decompose the oxygen The second layer 1510B is separated from the oxygen-containing first layer 1510A. As described above, the anti-tunneling layer 1510C actually reduces the likelihood that electron charges accumulated at the interface of the anoxic second layer 1510B during tunneling will tunnel to the oxygen-containing first layer 1510A.

As with the above embodiments, either or both of the oxygen-containing first layer 1510A and the oxygen-deficient second layer 1510B may include tantalum nitride or hafnium oxynitride, and may include, for example, nitrous oxide/ammonia and dichloride. A chemical vapor deposition process of a decane/ammonia gas mixture is formed by providing a niobium-containing and oxygen-containing oxynitride layer at a tailored ratio and flow rate. An oxygen-deficient second layer of the multilayer charge storage structure is then formed on the intermediate oxide layer. The anoxic second layer 1510B has a stoichiometric composition of oxygen, nitrogen and/or helium different from the oxygen-containing first layer 1510A, and may also be subjected to a chemical vapor deposition process using dichloromethane/ammonia and oxidation. The process gas of the nitrous/ammonia gas mixture is formed or deposited by providing a niobium- and oxygen-deficient top nitride layer at a tailored ratio and flow rate.

In those embodiments comprising an intermediate or anti-tunneling layer 1510C, the anti-tunneling layer can be formed using a base oxidation to oxidize the oxygen-containing first layer 1510A to a selected depth. Base oxidation can be used at a temperature of, for example, 1000-1100 ° C using a single wafer tool Or use a batch of reactor tools to perform at 800-900 degrees Celsius. A hydrogen and oxygen mixture can be used in a batch process at 300-500 Torr or a single gas phase tool at 10-15 Torr, using a single wafer tool for 1-2 minutes, or , using a batch process for 30 minutes - 1 hour.

The oxygen-containing first layer 1510A may have a suitable thickness of from about 30 angstroms to about 130 angstroms (having some variation, for example, ±10 angstroms), wherein a thickness of about 5-20 angstroms may be consumed via basal oxidation to form the Anti-through tunnel layer 1510C. The oxygen-deficient second layer 1510B has a suitable thickness of at least 30 angstroms. In certain embodiments, the anoxic second layer 1510B can be formed up to 130 angstroms thick, wherein a thickness of 30-70 angstroms can be consumed via base oxidation to form the barrier layer 1512. In some embodiments, the thickness ratio of the oxygen-containing first layer 1510A to the oxygen-deficient second layer 1510B is about 1:1, although other ratios are also possible.

The barrier layer 1512 includes a relatively high temperature oxide (HTO) that is relatively denser when deposited. A dense high temperature oxide has a lower terminal hydrogen or hydroxide bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x ^{10 20} atoms per centimeter and is reduced to less than 8.0 x ^{10 19} atoms per centimeter in the dense film. In an exemplary embodiment, the thickness of the barrier layer 1512 including a dense high temperature oxide is between 2.5 nm and 10.0 nm at the time of deposition, and is 10% thinner everywhere due to the densification. Up to 30%.

In an alternative embodiment, the barrier layer 1512 is further altered to integrate nitrogen. In one such embodiment, the nitrogen is integrated in an oxide-nitride-oxide stack across the thickness of the barrier layer 1512. It is advantageous to replace such a sandwich structure of the conventional pure oxygen barrier layer. The effective oxide thickness of the entire stack between the channel region 1502 and the gate layer 1514 is reduced and the conduction band displacement is adjusted to reduce carrier reflow. The oxide-nitride-oxide stack barrier layer 1512 can then be coupled to the nitride oxide tunneling layer 1508 and include an oxygen-containing first layer 1510A, an oxygen-deficient second layer 1510B, and an anti-tunneling layer 1510C. The separate multilayer charge trap layer 1510 is integrated.

The memory component 1500 of Figure 15A is fabricated using either a gate priority or a gate post scheme. 16A-F illustrate a gate priority scheme for fabricating the non-planar multi-gate element of FIG. 15A. 17A-F illustrate a gate post-production scheme for fabricating the non-planar multi-gate element of FIG. 15A.

Referring to FIG. 16A, in a gate priority scheme, a first or lower dielectric layer 1602 is formed in a substrate 1906, such as a source region or a first doped diffusion region 1604 of a drain region. A gate layer 1608 is deposited over the first dielectric layer 1602 to form a control gate of the component, and a second or upper dielectric layer 1610 is formed thereover. As with the above embodiments, the first and second dielectric layers 1602, 1610 can be deposited via a chemical vapor deposition process, a base oxidation process, or via oxidation of a portion of the lower or lower substrate. The gate layer 1608 can include a metal or doped polysilicon deposited via a chemical vapor deposition process. Generally, the gate layer 1608 has a thickness of about 40-110 angstroms, and the first and second dielectric layers 1602, 1610 are about 20-80 angstroms.

Referring to FIG. 16B, a first opening 1612 is etched through the second dielectric layer 1610, the gate layer 1608, and the first dielectric layer 1602 to reach a diffusion region 1604 within the substrate 1606. Next, a barrier layer 1614, a plurality of layers of the charge trap layer 1616 and the tunneling layer 1618 are subsequently deposited in the opening, and the surface of the upper dielectric layer 1610 is planarized to produce the layer shown in FIG. 16C. The middle structure.

As with the above embodiments, the barrier layer 1614 can be a dense barrier layer comprising dense high temperature oxides that are relatively denser when deposited and have a lower terminal hydrogen or hydroxide bond fraction.

Although not shown, it will be appreciated that as with the above embodiments, the multilayer charge trapping layer 1616 can comprise a separate multilayer charge trapping layer comprising an outer anoxic second layer that is closer to or deposited on the dense barrier layer 1614 and Depositing or forming a first oxygen-containing first layer on the second layer of the anoxic layer. In general, the anoxic second layer comprises a germanium-containing and oxygen-deficient nitride layer and includes a plurality of charge traps interspersed among a plurality of charge trapping layers, and the oxygen-containing first layer comprises an oxynitride or nitrogen The cerium oxide is oxygen-containing relative to the top charge trapping layer to reduce the number of charge traps therein. In some embodiments, the multilayer charge trapping layer 1616 is a separate multilayer charge trapping layer, further comprising at least one thin intermediate or anti-tunneling layer, the thin layer comprising a dielectric such as an oxide to The outer anoxic second layer is separated from the inner oxygen containing first layer.

It is further understood that the tunneling layer 1618 is a nitrided oxide tunneling layer and can include a first region having a nitrogen concentration of less than about 5 x 10 ²¹ nitrogen atoms per cubic centimeter, located adjacent to the multilayer charge trapping layer 1616. Above the second region 1116B having a nitrogen concentration of at least 5 x 10 ²¹ nitrogen atoms per cubic centimeter.

Next, referring to FIG. 16D, a second or via opening 1620 is anisotropically etched through the tunneling layer 1618, the plurality of charge trapping layers 1616, and the barrier layer 1614 to expose a portion of the diffusion region 1604 within the substrate 1606. Referring to Figure 16E, a semiconductor material 1622 is deposited in the via opening to form a vertical via 1624 therein. The vertical channel 1624 can comprise an annular region within an outer layer of a substantially solid cylindrical body of semiconductor material, or as shown in Figure 16E. A separate layer of semiconductor material 1922 surrounding a cylinder of fill material 1626 can be included.

Referring to FIG. 16F, the surface of the upper dielectric layer 1610 is planarized, and a semiconductor material layer 1628 including a second doped diffusion region 1630 formed therein, for example, a source region or a drain region, is deposited on the upper dielectric layer. Above the electrical layer to form the components shown.

Referring to FIG. 17A, in a gate post-production scheme, for example, an oxide dielectric layer 1702 is formed over the sacrificial layer 1704 on the surface of a substrate 1706, and an opening etches through the dielectric and sacrificial layers. A vertical channel 1708 is formed therein. As with the above embodiments, the vertical channel 1708 can comprise an annular region within the outer cylindrical layer of the solid semiconductor material 1710, such as a polycrystalline germanium or a single crystalline germanium, or can comprise a cylindrical surrounding a dielectric fill material (not shown). A layer of independent semiconductor material. The dielectric layer 1702 can comprise any suitable dielectric material capable of electrically isolating a subsequently formed gate layer of the memory element 1500 from an upper electrically active layer or another memory element such as hafnium oxide. The sacrificial layer 1704 can comprise any suitable material that can be etched or removed with high selectivity relative to the material of the dielectric layer 1702, substrate 1706, and vertical channel 1708.

Referring to FIG. 17B, a second opening 1712 is etched through the dielectric and sacrificial layers 1702, 1704 to the substrate 1706, and the sacrificial layer 1704 is at least partially etched or removed. The sacrificial layer 1704 can comprise any suitable material that can be etched or removed with high selectivity relative to the material of the dielectric layer 1702, substrate 1706, and vertical channel region 1708. In an embodiment, the sacrificial layer 1704 includes being removable via a buffered oxide etch technique (BOE etch technique).

Referring to FIGS. 17C and 17D, a tunneling layer 1714A-B including a nitride oxide, a plurality of layers of charge trapping layers 1716A-C and a barrier layer 1718 are sequentially deposited in the opening, and the dielectric is dielectrically deposited. The surface of layer 1702 is planarized to create the intermediate structure shown in Figure 17C. As with the above embodiments, the barrier layer 1718 can be a dense barrier layer, including relatively more deposited than when deposited. Dense high temperature oxide dense and having a lower terminal hydrogen or hydroxide bond fraction.

In some embodiments, such as the one shown in FIG. 17D, the nitride oxide tunneling layer includes a first region 1714A near the semiconductor material 1710 having a nitrogen concentration of less than about 5 x 10 ²¹ nitrogen atoms per cubic centimeter and is close to the A second region 1714B having a nitrogen concentration of at least 5 x 10 ²¹ nitrogen atoms per cubic centimeter at the multilayer charge trap layer 1716A-C.

The multilayer charge trapping layer 1716A-C is a separate multilayer charge trapping layer containing at least one inner oxygen-containing first layer 1716A and an outer oxygen-deficient second layer 1716B closest to the tunneling oxide layer 1714. Optionally, the first and second charge trapping layers may be separated by an intermediate oxide or anti-tunneling layer 1716C.

Next, a gate layer 1722 is deposited into the second opening 1712, and the surface of the upper dielectric layer 1702 is planarized to produce the intermediate structure shown in FIG. 17E. As with the above embodiments, the gate layer 1722 can comprise a deposited metal or a doped polysilicon. Finally, an opening 1724 is etched through the gate layer 1722 to form control gates for the respective memory elements 1726A and 1726B.

Therefore, a method of manufacturing a non-volatile charge trapping memory element has been disclosed. According to an embodiment of the invention, a substrate is subjected to a first base oxidation process in a first process chamber of a cluster tool to form a first dielectric layer. A charge trap layer can then be deposited over the first dielectric layer in a second process chamber of the cluster tool. In one embodiment, the charge trap layer is then subjected to a second base oxidation process in the first process chamber of the cluster tool to form a second dielectric layer over the charge trap layer. By forming all of the oxide-nitride-oxide (ONO) stacks in a cluster tool, the interface damage between the layers can be reduced. Thus, in accordance with an embodiment of the invention, an oxide-nitride-oxide stack is fabricated in a cluster tool in a single operation to maintain an original interface between the oxide-nitride-oxide stack layers. In a In a particular embodiment, the cluster tool is a single wafer cluster tool.

500‧‧‧Semiconductor-Oxide-Nitride-Oxide-Semiconductor Type Components

502‧‧‧Semiconductor-Oxide-Nitride-Oxide-Semiconductor Gate Stack

504‧‧‧Oxide-nitride-oxide stack

506‧‧‧ surface

508‧‧‧Substrate

510‧‧‧Source and bungee regions

512‧‧‧Channel area

513‧‧‧ interface

514‧‧ ‧ gate layer

516‧‧‧ Tunneling

517‧‧‧ center line

518‧‧‧Charge trapping layer

518A‧‧‧ bottom oxynitride layer

518B‧‧‧Top oxynitride layer

520‧‧‧Block

525‧‧‧gate cap layer

Claims (20)

A method of fabricating a non-volatile charge trapping memory device, comprising: forming a channel region electrically connected to a source region and a drain region in a substrate, wherein the channel region comprises a polysilicon; above the channel region of the substrate Forming a tunneling layer, wherein forming the tunneling layer comprises oxidizing the substrate to form an oxide film and nitriding the oxide film; forming an oxygen-containing first layer and an anoxic layer on the tunneling layer a multilayer charge trapping layer; and forming a barrier layer on the multilayer charge trap layer. The method of claim 1, further comprising densifying the barrier layer by a oxidative tempering, wherein the oxidative tempering oxidizes the second layer of the oxygen-deficient second layer of at least a portion of the plurality of charge trapping layers of the barrier layer. The method of claim 1, wherein forming the multilayer charge trap layer further comprises forming an anti-tunneling layer containing an oxide separating the first layer from the second layer. The method of claim 3, wherein forming the channel region comprises recrystallizing the polysilicon. The method of claim 1, wherein the forming the channel region comprises forming the channel in a germanium-containing material protrusion over a surface of the substrate and electrically connected to the source region and the drain region in the substrate. region. The method of claim 1, further comprising densifying the barrier layer by a oxidative tempering, wherein the oxidative tempering oxidizes a portion of the oxygen-deficient second layer in the plurality of charge trapping layers of the barrier layer. The method of claim 6, wherein the forming the tunneling layer further comprises reoxidizing the nitride oxide film by exposing the substrate to oxygen, and exposing the substrate to nitrogen oxide by exposing the substrate to nitrogen oxide. The reoxidized nitride oxide film is again nitrided. A method of fabricating a non-volatile charge trapping memory device, comprising: forming a channel region electrically connected to a source region and a drain region in a substrate, wherein the channel region comprises a polysilicon; above the channel region of the substrate Forming a tunneling layer, wherein forming the tunneling layer comprises oxidizing the substrate to form an oxide film and nitriding the oxide film; forming an oxygen-containing first layer and an anoxic layer on the tunneling layer a second layer and a separate multilayer charge trapping layer comprising an anti-tunneling layer separating the oxides of the first layer and the second layer; and forming a barrier layer on the separate multilayer charge trap layer. The method of claim 8, further comprising densifying the barrier layer by oxidative tempering, wherein the oxidative tempering oxidizes at least a portion of the separated multilayer charge trapping layer of the barrier layer. Floor. The method of claim 9, wherein the densifying the barrier layer by oxidative tempering comprises oxidizing a portion of the oxygen-deficient second layer that is approximately equal to one half of the second layer of the anoxic. The method of claim 8, further comprising densifying the barrier layer by a oxidative tempering, wherein the oxidative tempering oxidizes a portion of the oxygen-deficient second layer in the plurality of charge trapping layers of the barrier layer. The method of claim 8, wherein the forming the tunneling layer further comprises reoxidizing the nitride oxide film by exposing the substrate to oxygen, and exposing the substrate to nitrogen oxide by exposing the substrate to nitrogen oxide. The reoxidized nitride oxide film is again nitrided. The method of claim 8, wherein the forming the multi-layered charge trapping layer further comprises forming an anti-tunneling layer comprising an oxide separating the first layer from the second layer. The method of claim 8, wherein the forming the channel region comprises forming the channel in a germanium-containing material protrusion over a surface of the substrate and electrically connected to the source region and the drain region in the substrate. region. A non-volatile charge trapping memory device comprising: a channel region containing germanium; a tunneling layer positioned above the channel region; a multilayer charge trapping layer positioned above the tunneling layer and including a a first layer of oxygen and an anoxic second layer; and a barrier layer overlying the plurality of charge trapping layers, wherein the tunneling layer comprises a nitrided oxide and comprises a first region proximate to the channel region The first region has a nitrogen concentration that is lower than a second region adjacent to one of the plurality of charge storage layers. The memory component of claim 15 wherein the channel region comprises polysilicon. The memory device of claim 15 wherein the multilayer charge trap layer is a separate multilayer charge trap layer further comprising an anti-tunneling layer having an oxide separating the layer from the second layer. The memory component of claim 17, wherein the channel region comprises a recrystallized polysilicon. The memory device of claim 16, wherein the channel region comprises a source region and a drain region formed over the surface of the substrate and electrically connected to the substrate. Conductor material projections. The memory device of claim 16, wherein the channel region comprises a vertical channel extending from a first diffusion region formed on a surface of the substrate to a semiconductor formed in the second diffusion region above the surface of the substrate A material protrusion is formed, and the vertical channel is electrically connected to the first diffusion region to the second diffusion region.