TWI604595B - Nonvolatile trapped-charged memory devices and manufacturing methods thereof - Google Patents

Nonvolatile trapped-charged memory devices and manufacturing methods thereof Download PDF

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TWI604595B
TWI604595B TW102123446A TW102123446A TWI604595B TW I604595 B TWI604595 B TW I604595B TW 102123446 A TW102123446 A TW 102123446A TW 102123446 A TW102123446 A TW 102123446A TW I604595 B TWI604595 B TW I604595B
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layer
oxide
tunneling
oxygen
nitride
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TW201405717A (en
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賽格 利維
斐德列克 傑能
克里希納斯瓦米 庫馬爾
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賽普拉斯半導體公司
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    • GPHYSICS
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    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
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    • GPHYSICS
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    • G11C16/00Erasable programmable read-only memories
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    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
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    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3468Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40117Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane

Description

非揮發性電荷捕獲記憶體元件以及其製造方法 Non-volatile charge trapping memory element and method of manufacturing same
本發明實施例關於電子製造工業,且更特別地,關於非揮發性電荷捕獲記憶體元件之製造。 Embodiments of the present invention relate to the electronics manufacturing industry and, more particularly, to the fabrication of non-volatile charge trapping memory components.
相關申請案交互參考 Related application cross-reference
本申請案係2007年9月26日所提申之共同申請之美國申請案序號11/904,506之部分接續案,其基於35 U.S.C.119(e)條款主張2007年5月25日所提申之美國臨時專利申請案序號60/940,384之優先權利益,在此將其兩者一併整合參考之。 This application is a continuation of the US application Serial No. 11/904,506, filed on September 26, 2007, which is based on 35 USC 119(e) claiming the United States as claimed on May 25, 2007. The priority benefit of the provisional patent application Serial No. 60/940,384 is hereby incorporated by reference in its entirety.
圖1係一半導體元件100的中間結構部分剖面圖,具有包含根據一傳統方法形成於一半導體基板108一表面106上方之傳統氧化物-氮化物-氧化物(ONO)堆疊104的半導體-氧化物-氮化物-氧化物-半導體(SONOS)閘極堆疊102。該元件100典型地包含對準該閘極堆疊並由一通道區域112分開之一或更多擴散區域110,例如,源極和汲極區域。該半導體-氧化物-氮化物-氧化物-半導體閘極堆疊102包含形成於其上並接觸該氧化物-氮化物-氧化物堆疊104之多晶矽(poly)閘極層114。該多晶矽閘極層114與該基 板108係經由該氧化物-氮化物-氧化物堆疊104電性隔離。該氧化物-氮化物-氧化物堆疊104大體上包含一氧化矽穿隧層106A,充當該元件100之電荷儲存或記憶體層之氮化矽電荷捕獲層118,及位在該電荷捕獲層118上方之一氧化矽阻擋層120。 1 is a cross-sectional view of an intermediate portion of a semiconductor device 100 having a semiconductor-oxide comprising a conventional oxide-nitride-oxide (ONO) stack 104 formed over a surface 106 of a semiconductor substrate 108 in accordance with a conventional method. A nitride-oxide-semiconductor (SONOS) gate stack 102. The element 100 typically includes one or more diffusion regions 110, such as source and drain regions, that are aligned with the gate stack and separated by a channel region 112. The semiconductor-oxide-nitride-oxide-semiconductor gate stack 102 includes a poly gate layer 114 formed thereon and contacting the oxide-nitride-oxide stack 104. The polysilicon gate layer 114 and the base The plates 108 are electrically isolated via the oxide-nitride-oxide stack 104. The oxide-nitride-oxide stack 104 generally includes a hafnium oxide tunneling layer 106A, a tantalum nitride charge trapping layer 118 that acts as a charge storage or memory layer for the device 100, and is positioned above the charge trapping layer 118. One of the ruthenium oxide barrier layers 120.
這類半導體-氧化物-氮化物-氧化物-半導體型電晶體對於非揮發性記憶體(NVM)而言係有用的。該電荷捕獲層儲存電荷以提供非揮發性。為了程式化(也就是,寫入)該n型通道半導體-氧化物-氮化物-氧化物-半導體型元件,一正電壓被施加至該控制閘(Vcg),同時,該源極、本體及汲極係接地的。在程式化期間,具有一通道212、氧化物穿隧層216、氮化物記憶體層218及氧化物阻擋層之傳統n型通道半導體-氧化物-氮化物-氧化物-半導體型元件之捕獲電荷分佈和陷阱密度分佈能帶圖係示於圖2。如所示地,該正電壓Vcg產生橫跨該半導體-氧化物-氮化物-氧化物-半導體堆疊之電場,導致該矽基板通道之埋入式通道內位於該傳導帶能量位準下之一些負電荷承受富勒-諾得漢穿隧(FNT)而透過該穿隧層進入該電荷捕獲層中。該些電子係儲存於該電荷捕獲層中之具有中間間隙能量位準的陷阱內。如所示地,該陷阱密度分佈實際上係均勻遍佈於該電荷捕獲層各處。如進一步所示地,在偏壓下,該捕獲電荷分佈係使得多數捕獲電荷為該電荷捕獲層(也就是記憶體層)中接近該阻擋氧化物之部分。為了抹除該通道半導體-氧化物-氮化物-氧化物-半導體元件,一負電壓被施加至該控制閘極314。顯示抹除期間之通道312、氧化物穿隧層316、氮化物記憶體層318及氧化物阻擋層320之能帶圖係示於圖3。如所示地,該負電壓Vcg產生一橫跨該半導體-氧化物-氮化物-氧化物-半導體堆疊之電場,吸引電洞穿隧電荷 透過該穿隧層進入該電荷捕獲層中。 Such semiconductor-oxide-nitride-oxide-semiconductor type transistors are useful for non-volatile memory (NVM). The charge trap layer stores charge to provide non-volatility. In order to program (ie, write) the n-channel semiconductor-oxide-nitride-oxide-semiconductor type element, a positive voltage is applied to the control gate (Vcg), and the source, body and The bungee is grounded. Capture charge distribution of a conventional n-channel semiconductor-oxide-nitride-oxide-semiconductor type device having a channel 212, an oxide tunneling layer 216, a nitride memory layer 218, and an oxide barrier during stylization The band diagram of the trap density distribution is shown in Figure 2. As shown, the positive voltage Vcg creates an electric field across the semiconductor-oxide-nitride-oxide-semiconductor stack, resulting in some of the buried-channels of the germanium substrate channel being at the energy level of the conduction band. The negative charge is subjected to Fuller-Nordheim tunneling (FNT) through the tunneling layer into the charge trapping layer. The electrons are stored in a trap having an intermediate gap energy level in the charge trap layer. As shown, the trap density profile is substantially evenly distributed throughout the charge trapping layer. As further shown, under bias, the trapped charge distribution is such that a majority of the trapped charge is a portion of the charge trapping layer (ie, the memory layer) that is proximate to the blocking oxide. To erase the via semiconductor-oxide-nitride-oxide-semiconductor component, a negative voltage is applied to the control gate 314. An energy band diagram showing channel 312, oxide tunneling layer 316, nitride memory layer 318, and oxide barrier layer 320 during erase is shown in FIG. As shown, the negative voltage Vcg produces an electric field across the semiconductor-oxide-nitride-oxide-semiconductor stack, attracting hole tunneling charges The tunneling layer enters the charge trap layer.
半導體-氧化物-氮化物-氧化物-半導體型元件係正普遍流行於例如內嵌式非揮發性記憶體之高密度記憶體應用中。在該工業中已知到用於程式化及抹除之均勻通道富勒-諾得漢穿隧(FNT)及/或直接穿隧(DT)產生超過其它方法之改善的可靠性結果。富勒-諾得漢穿隧及直接穿隧結合係在此參考之並稱之為修改式富勒-諾得漢穿隧效應(MFNT)。目前,用於修改式富勒-諾得漢穿隧之傳統半導體-氧化物-氮化物-氧化物-半導體元件操作於該10伏特範圍內。然而,超過其它非揮發性記憶體元件之半導體-氧化物-氮化物-氧化物-半導體優勢係電壓可調性。已建立的理論為利用正確的縮放,現存於半導體-氧化物-氮化物-氧化物-半導體內之電位,可取得操作於該5伏特範圍內之記憶體技術,而非傳統半導體-氧化物-氮化物-氧化物-半導體型元件之10伏特範圍或傳統快閃記憶體技術之12伏特-15伏特範圍。可操作於低電壓(接近5伏特)下之半導體-氧化物-氮化物-氧化物-半導體型元件係具優勢地相容於低電壓互補式金屬氧化物半導體。替代性地,較快程式化或抹除對於一特定電壓下之縮放元件係可行的。然而,成功的縮放半導體-氧化物-氮化物-氧化物-半導體型元件係不普通的。例如,圖4說明運用一傳統氧化物-氮化物-氧化物堆疊之傳統半導體-氧化物-氮化物-氧化物-半導體元件之程式化及抹除時間,該堆疊由一10奈米厚二氧化矽阻擋層、一7奈米厚氮化矽電荷捕獲層及一3奈米厚二氧化矽穿隧層所構成。如所示地,當電壓Vcg係縮小時,該程式化/抹除時間戲劇性地增加。大體上,小於1毫秒(ms)之程式化及抹除時間在內嵌式記憶體應用令人滿意。然而,這類1毫秒程式化及抹除時間只有在具有+/-10伏特Vcg電壓之傳統半 導體-氧化物-氮化物-氧化物-半導體堆疊內可取得。當電壓Vcg係下降至約+/-9伏特時,傳統半導體-氧化物-氮化物-氧化物-半導體程式化/抹除時間延長至100毫秒或更久。 Semiconductor-oxide-nitride-oxide-semiconductor-type components are becoming popular in high-density memory applications such as in-line non-volatile memory. Uniform channel Fuller-Nordheim tunneling (FNT) and/or direct tunneling (DT) for stylization and erasing is known in the industry to produce improved reliability results over other methods. The Fuller-Nordheim tunneling and direct tunneling system is referred to herein as a modified Fuller-Nordheim tunneling effect (MFNT). Currently, conventional semiconductor-oxide-nitride-oxide-semiconductor elements for modified Fuller-Nordheim tunneling operate within the 10 volt range. However, semiconductor-oxide-nitride-oxide-semiconductor advantages over other non-volatile memory components are voltage tunability. The established theory is to use the correct scaling, existing in the semiconductor-oxide-nitride-oxide-semiconductor, to achieve memory technology operating in the 5 volt range, rather than the traditional semiconductor-oxide- The 10 volt range of nitride-oxide-semiconductor type components or the 12 volts to 15 volt range of conventional flash memory technology. A semiconductor-oxide-nitride-oxide-semiconductor type device that is operable at a low voltage (nearly 5 volts) is advantageously compatible with a low voltage complementary metal oxide semiconductor. Alternatively, faster stylization or erasing is possible for scaling components at a particular voltage. However, successful scaling of semiconductor-oxide-nitride-oxide-semiconductor type components is not common. For example, Figure 4 illustrates the stylization and erasing time of a conventional semiconductor-oxide-nitride-oxide-semiconductor component using a conventional oxide-nitride-oxide stack that is oxidized by a 10 nm thick layer. The ruthenium barrier layer, a 7 nm thick tantalum nitride charge trap layer and a 3 nm thick ruthenium dioxide tunnel layer are formed. As shown, this stylization/erase time is dramatically increased as the voltage Vcg is reduced. In general, stylized and erase times of less than 1 millisecond (ms) are satisfactory for in-line memory applications. However, this 1 millisecond stylization and erasing time is only in the traditional half with a Vcg of +/-10 volts. Available in conductor-oxide-nitride-oxide-semiconductor stacks. When the voltage Vcg drops to about +/- 9 volts, the conventional semiconductor-oxide-nitride-oxide-semiconductor stylization/erase time is extended to 100 milliseconds or more.
更進一步,降低該程式化電壓導致該抹除或程式化視窗(也就是,記憶體視窗)下降。這個係因為假設該整個氧化物-氮化物-氧化物堆疊之有效氧化物厚度(EOT)未隨該電壓下降而縮小,則橫跨該氧化物-氮化物-氧化物堆疊之電場被降低之故。因為減少該穿隧層厚度以允許在一較低施加電壓(Vcg)下之相同初始抹除位準會導致該抹除及程式化衰退率不利的增增加,故減少該堆疊之有效氧化物厚度係不普通的。類似地,若該電荷捕獲層厚度被減少,則該電荷質量中心係置於較接近該基板,增加對該基板之電荷損失。最後,當該阻擋氧化物厚度被縮小,來自該控制閘極之電子逆向注入係增加,引起對該氧化物-氮化物-氧化物堆疊及資料保留損失之損害。逆向注入係如圖4所進一步顯示地證明之,其中,該富勒-諾得漢穿隧抹除達到“飽和”。這個發生於電子自該閘極回流至該記憶體層快於它們可透過運送跨越該穿隧氧化物之電洞來移除之時。有鑑於此,仍舊對以能夠提供可於一較低程式化/抹除電壓操作之元件的方式來縮放一半導體-氧化物-氮化物-氧化物-半導體元件之氧化物-氮化物-氧化物堆疊有所要求。 Further, lowering the stylized voltage causes the erased or stylized window (ie, the memory window) to drop. This is because the effective oxide thickness (EOT) of the entire oxide-nitride-oxide stack is not reduced as the voltage drops, the electric field across the oxide-nitride-oxide stack is reduced. . Reducing the thickness of the tunneling layer to allow the same initial erasing level at a lower applied voltage (Vcg) results in an unfavorable increase in the erase and stylized decay rate, thereby reducing the effective oxide thickness of the stack It is not ordinary. Similarly, if the charge trapping layer thickness is reduced, the charge mass center is placed closer to the substrate, increasing the charge loss to the substrate. Finally, as the barrier oxide thickness is reduced, the electron retro-injection from the control gate increases, causing damage to the oxide-nitride-oxide stack and data retention losses. The reverse injection system is further shown in Figure 4, wherein the Fuller-Nordheim tunneling erase achieves "saturation". This occurs when electrons are reflowed from the gate to the memory layer faster than they can be removed by transporting holes through the tunneling oxide. In view of this, the oxide-nitride-oxide of a semiconductor-oxide-nitride-oxide-semiconductor element is still scaled in such a way as to provide an element that can operate at a lower stylized/erasing voltage. Stacking is required.
根據本發明一觀點,一種非揮發性電荷捕獲記憶體元件之製造方法包括形成電性連接一基板內之源極區域和汲極區域之一通道區域,其中,該通道區域包括多晶矽;在該基板之通道區域上方形成一穿隧層,其中,形成該穿隧層包括氧化該基板以形成一氧化物薄膜並氮化該氧化物 薄膜;在該穿隧層上形成包含一富氧第一層和一貧氧第二層之一多層電荷捕獲層;及在該多層電荷捕獲層上形成一阻擋層。 According to one aspect of the invention, a method of fabricating a non-volatile charge trapping memory device includes forming a channel region electrically connected to a source region and a drain region in a substrate, wherein the channel region comprises polysilicon; Forming a tunneling layer over the channel region, wherein forming the tunneling layer comprises oxidizing the substrate to form an oxide film and nitriding the oxide a thin film; forming a multilayer charge trapping layer comprising an oxygen-rich first layer and an oxygen-poor second layer on the tunneling layer; and forming a barrier layer on the multilayer charge trap layer.
根據本發明另一觀點,一種非揮發性電荷捕獲記憶體元件之製造方法包括形成電性連接一基板內之源極區域和汲極區域之一通道區域,其中,該通道區域包括多晶矽;在該基板之通道區域上方形成一穿隧層,其中,形成該穿隧層包括氧化該基板以形成一氧化物薄膜並氮化該氧化物薄膜;在該穿隧層上形成包含一富氧第一層、一貧氧第二層和包括分開該第一層與該第二層之氧化物之抗穿隧層之一分離式多層電荷捕獲層;及在該分離式多層電荷捕獲層上方形成一阻擋層。 According to another aspect of the present invention, a method of fabricating a non-volatile charge trapping memory device includes forming a channel region electrically connected to a source region and a drain region in a substrate, wherein the channel region includes a polysilicon; Forming a tunneling layer over the channel region of the substrate, wherein forming the tunneling layer comprises oxidizing the substrate to form an oxide film and nitriding the oxide film; forming an oxygen-rich first layer on the tunneling layer An oxygen-depleted second layer and a separate multilayer charge trapping layer comprising a barrier layer separating the oxide of the first layer and the second layer; and forming a barrier layer over the separated multilayer charge trap layer .
根據本發明又一觀點,一種非揮發性電荷捕獲記憶體元件包括:一含矽之通道區域;位在該通道區域上方之一穿隧層;位在該穿隧層上方且包括一富氧第一層和一貧氧第二層之一多層電荷捕獲層;及在該多層電荷捕獲層上方形成一阻擋層,其中,該穿隧層包括一氮化氧化物並包含接近該通道區域之一第一區域,該第一區域具有低於接近該多層電荷儲存層之一第二區域之氮濃度。 According to still another aspect of the present invention, a non-volatile charge trapping memory device includes: a channel region containing germanium; a tunneling layer positioned above the channel region; positioned above the tunneling layer and including an oxygen-rich portion a multilayer charge trapping layer of one layer and an oxygen-lean second layer; and forming a barrier layer over the multilayer charge trap layer, wherein the tunneling layer comprises a nitride oxide and comprises one of the regions adjacent to the channel a first region having a nitrogen concentration that is lower than a second region adjacent to one of the plurality of charge storage layers.
100‧‧‧半導體元件 100‧‧‧Semiconductor components
500、1100、1300、1400、1500、1726A、1726B‧‧‧記憶體元件 500, 1100, 1300, 1400, 1500, 1726A, 1726B‧‧‧ memory components
102、502、1102‧‧‧半導體-氧化物-氮化物-氧化物-半導體閘極堆疊 102, 502, 1102‧‧‧Semiconductor-Oxide-Nitride-Oxide-Semiconductor Gate Stack
104、504、1104‧‧‧氧化物-氮化物-氧化物堆疊 104, 504, 1104‧‧‧Oxide-nitride-oxide stack
106、506、1106、1304‧‧‧表面 106, 506, 1106, 1304‧‧‧ surface
108、508、612、812、1108、1306、1406、1606、1706‧‧‧基板 108, 508, 612, 812, 1108, 1306, 1406, 1606, 1706‧‧‧ substrates
110、1604、1630‧‧‧擴散區域 110, 1604, 1630‧‧‧Diffusion areas
112、512、1112、1302、1402、1502、1624、1708‧‧‧通道區域 112, 512, 1112, 1302, 1402, 1502, 1624, 1708‧‧‧ channel area
114、514、1114、1320、1420、1514、1608、1722‧‧‧閘極層 114, 514, 1114, 1320, 1420, 1514, 1608, 1722‧‧ ‧ gate layer
614‧‧‧氮濃度 614‧‧‧ nitrogen concentration
116、216、316、516、616、1116、1316、1414、1508、1618、1714A-B‧‧‧穿隧層 116, 216, 316, 516, 616, 1116, 1316, 1414, 1508, 1618, 1714A-B‧‧‧ tunneling layer
118、518、618、818、1118、1314、1416、1510、1616、1716A-C‧‧‧電荷捕獲層 118, 518, 618, 818, 1118, 1314, 1416, 1510, 1616, 1716A-C‧‧‧ charge trapping layers
120、220、320、520、820、1120、1318、1418、1512、1614、1718‧‧‧阻擋層 120, 220, 320, 520, 820, 1120, 1318, 1418, 1512, 1614, 1718‧‧ ‧ barrier
212、312‧‧‧通道 212, 312‧‧ channels
218、318‧‧‧記憶體層 218, 318‧‧‧ memory layer
314、814‧‧‧控制閘極 314, 814‧‧‧Control gate
513、613‧‧‧界面 513, 613‧‧‧ interface
510、1110‧‧‧源極和汲極區域 510, 1110‧‧‧ source and bungee regions
517、617‧‧‧中心線 517, 617‧‧‧ center line
518A、518B、818A、818B‧‧‧氮氧化物層 518A, 518B, 818A, 818B‧‧‧ NOx layer
525、1125‧‧‧閘極帽蓋層 525, 1125‧‧‧ gate cap layer
816‧‧‧氧化物 816‧‧‧Oxide
901-910、1001-1006、1200-1208‧‧‧操作 901-910, 1001-1006, 1200-1208‧‧‧ operations
1116A、1118A、1314A、1316A、1414A、1416A、1508A、1510A‧‧‧第一區域 1116A, 1118A, 1314A, 1316A, 1414A, 1416A, 1508A, 1510A‧‧‧ first area
1116B、1118B、1314B、1316B、1414B、1416B、1508B、1510B‧‧‧第二區域 1116B, 1118B, 1314B, 1316B, 1414B, 1416B, 1508B, 1510B‧‧‧ second area
1118C、1314C、1416C、1510C‧‧‧抗穿隧層 1118C, 1314C, 1416C, 1510C‧‧‧ anti-through tunneling
1308、1408、1504‧‧‧源極區域 1308, 1408, 1504‧‧‧ source area
1310、1410、1506‧‧‧汲極區域 1310, 1410, 1506‧‧‧ bungee area
1312、1412‧‧‧閘極 1312, 1412‧‧ ‧ gate
1322、1602、1610、1702‧‧‧介電層 1322, 1602, 1610, 1702‧ ‧ dielectric layer
1612、1712‧‧‧開口 1612, 1712‧‧
1622、1628、1710‧‧‧半導體材料 1622, 1628, 1710‧‧‧ semiconductor materials
1626‧‧‧填充材料 1626‧‧‧Filling materials
1704‧‧‧犧牲層 1704‧‧‧ Sacrifice layer
本發明實施例係舉例說明附圖之圖形,並非限制,其中:圖1說明一傳統半導體-氧化物-氮化物-氧化物-半導體元件之中間結構剖面圖。 The embodiments of the present invention are illustrative of the drawings, and are not limiting, wherein: FIG. 1 illustrates a cross-sectional view of an intermediate structure of a conventional semiconductor-oxide-nitride-oxide-semiconductor device.
圖2說明程式化期間之傳統半導體-氧化物-氮化物-氧化物-半導體元件之捕獲電荷分佈及陷阱密度分佈之能帶圖。 Figure 2 illustrates an energy band diagram of the trapped charge distribution and trap density distribution of a conventional semiconductor-oxide-nitride-oxide-semiconductor element during stylization.
圖3說明抹除期間之傳統半導體-氧化物-氮化物-氧化物-半導體元件之 能帶圖。 Figure 3 illustrates a conventional semiconductor-oxide-nitride-oxide-semiconductor component during erasing Can bring a picture.
圖4說明運用一傳統氧化物-氮化物-氧化物堆疊之傳統半導體-氧化物-氮化物-氧化物-半導體元件之程式化及抹除時間。 Figure 4 illustrates the stylization and erasing time of a conventional semiconductor-oxide-nitride-oxide-semiconductor component using a conventional oxide-nitride-oxide stack.
圖5根據本發明一實施例說明一縮放非揮發性電荷捕獲記憶體元件之一部分剖面圖,具有包含一氮化氧化物穿隧層、一多層氮氧化物電荷捕獲層及一密集阻擋層之縮放氧化物-氮化物-氧化物結構。 5 is a partial cross-sectional view showing a portion of a scaled non-volatile charge trapping memory device having a nitride oxide tunneling layer, a multilayered NOx charge trapping layer, and a dense barrier layer, in accordance with an embodiment of the invention. Scale the oxide-nitride-oxide structure.
圖6根據本發明一實施例說明該氮化氧化物穿隧層之近似氮濃度輪廓。 FIG. 6 illustrates an approximate nitrogen concentration profile of the nitride oxide tunneling layer in accordance with an embodiment of the invention.
圖7A根據本發明一實施例說明顯示降低可貢獻至一氮化氧化物穿隧層之程式化電壓模擬示圖。 FIG. 7A is a schematic diagram showing a stylized voltage display showing a reduction in contribution to a nitride nitride tunneling layer, in accordance with an embodiment of the invention. FIG.
圖7B說明二不同半導體-氧化物-氮化物-氧化物-半導體型元件之阻擋層、電荷捕獲層及穿隧層內之氫、氮、氧及矽之二濃渡輪廓比較。 Figure 7B illustrates a comparison of the two rich profiles of hydrogen, nitrogen, oxygen and helium in the barrier layer, charge trapping layer and tunneling layer of two different semiconductor-oxide-nitride-oxide-semiconductor type elements.
圖8A根據本發明一實施例說明一縮放半導體-氧化物-氮化物-氧化物-半導體型元件之保留模式能帶圖。 8A illustrates a retention mode energy band diagram of a scaled semiconductor-oxide-nitride-oxide-semiconductor type device in accordance with an embodiment of the present invention.
圖8B圖根據本發明一實施例說明在程式化期間之縮放半導體-氧化物-氮化物-氧化物-半導體型元件之捕獲電荷分佈及陷阱密度分佈之能帶圖。 8B illustrates an energy band diagram illustrating the trapped charge distribution and trap density distribution of a scaled semiconductor-oxide-nitride-oxide-semiconductor type device during stylization, in accordance with an embodiment of the present invention.
圖9係根據本發明一實施例之製造包含一氮化氧化物穿隧層、一多層電荷捕獲層及一再氧化阻擋層之縮放氧化物-氮化物-氧化物結構之半導體-氧化物-氮化物-氧化物-半導體縮放方法之流程圖。 9 is a semiconductor-oxide-nitrogen of a scaled oxide-nitride-oxide structure comprising a nitride oxide tunneling layer, a multilayer charge trapping layer, and a reoxidation barrier layer, in accordance with an embodiment of the invention. Flowchart of a compound-oxide-semiconductor scaling method.
圖10係形成一氮化氧化物穿隧層之半導體-氧化物-氮化物-氧化物-半導體縮放方法之流程圖。 Figure 10 is a flow diagram of a semiconductor-oxide-nitride-oxide-semiconductor scaling method for forming a nitride oxide tunneling layer.
圖11A和11B根據本發明一實施例說明一縮放非揮發性電荷捕獲記憶體元件之一部分剖面圖,具有包含一氮化氧化物穿隧層、一多層電荷捕獲 層及一密集阻擋層之縮放氧化物-氮化物-氧化物結構。 11A and 11B are partial cross-sectional views showing a portion of a scaled non-volatile charge trapping memory device having a nitride oxide tunneling layer and a multilayer charge trap, in accordance with an embodiment of the invention. A scaled oxide-nitride-oxide structure of the layer and a dense barrier layer.
圖12係根據本發明一實施例說明形成一縮放非揮發性電荷捕獲記憶體元件之方法流程圖,該元件具有包含一氮化氧化物穿隧層、一多層電荷捕獲層及一密集阻擋層之縮放氧化物-氮化物-氧化物結構。 12 is a flow chart illustrating a method of forming a scaled non-volatile charge trapping memory device having a nitride oxide tunneling layer, a multilayer charge trapping layer, and a dense barrier layer, in accordance with an embodiment of the invention. Scale the oxide-nitride-oxide structure.
圖13A根據本發明一實施例說明包含一氮化氧化物穿隧層、一分離式多層電荷捕獲層及一密集阻擋層之非平面式多閘極元件。 FIG. 13A illustrates a non-planar multi-gate device including a nitride oxide tunneling layer, a separate multilayer charge trapping layer, and a dense barrier layer, in accordance with an embodiment of the invention.
圖13B說明圖13A之非平面式多閘極元件之剖面圖。 Figure 13B illustrates a cross-sectional view of the non-planar multi-gate element of Figure 13A.
圖14A和14B根據本發明一實施例說明包含一氮化氧化物穿隧層、一分離式多層電荷捕獲層、一密集阻擋層及一水平奈米線通道之非平面式多閘極元件。 14A and 14B illustrate a non-planar multi-gate element comprising a nitride oxide tunneling layer, a separate multilayer charge trapping layer, a dense barrier layer, and a horizontal nanowire channel, in accordance with an embodiment of the invention.
圖14C說明圖14A之非平面式多閘極元件垂直串之剖面圖。 Figure 14C illustrates a cross-sectional view of the vertical string of the non-planar multi-gate element of Figure 14A.
圖15A和15B說明包含一氮化氧化物穿隧層、一分離式多層電荷捕獲層、一密集阻擋層及一垂直奈米線通道之非平面式多閘極元件。 15A and 15B illustrate a non-planar multi-gate element comprising a nitride oxide tunneling layer, a separate multilayer charge trapping layer, a dense barrier layer, and a vertical nanowire channel.
圖16A至16F說明用於製造圖15A之非平面式多閘極元件之閘極優先方案。 16A through 16F illustrate a gate priority scheme for fabricating the non-planar multi-gate element of Fig. 15A.
圖17A至圖17F說明用於製造圖15A之非平面式多閘極元件之閘極後製方案。 17A through 17F illustrate a gate post-production scheme for fabricating the non-planar multi-gate element of Fig. 15A.
縮放一非揮發性電荷捕獲記憶體元件之實施例係參考圖式在此做描述。然而,特定實施例可在沒有這些特定細節之一或更多下或結合已知方法、材料及設備來實施。在下列說明中,例如特定材料、尺寸及製程參數等等眾多特定細節被提出,以提供本發明之徹底了解。在其它範 例中,熟知半導體設計及製造技術未以特別詳加說明以避免不必要地混淆本發明。整份說明書對“一實施例”之參考意謂著結合該實施例所述之特定特性、結構、材料或特徵係包含於本發明至少一實施例內。因此,在整份說明書之不同地方中之用語“一實施例中”之出現並不一定參考至本發明之相同實施例。更進一步,該些特定特性、結構、材料或特徵可以任何合適方式結合至一或更多實施例中。 Embodiments for scaling a non-volatile charge trapping memory component are described herein with reference to the drawings. However, specific embodiments may be practiced without one or more of these specific details or in combination with known methods, materials, and devices. Numerous specific details are set forth in the following description, such as the specific materials, dimensions, and process parameters, to provide a thorough understanding of the invention. In other models In the examples, well-known semiconductor design and fabrication techniques are not specifically described in order to avoid unnecessarily obscuring the invention. The reference to "an embodiment" in this specification means that the specific features, structures, materials or characteristics described in connection with the embodiments are included in at least one embodiment of the invention. Thus, appearances of the phrase "in an embodiment" Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner into one or more embodiments.
本發明一些實施例包含一縮放半導體-氧化物-氮化物-氧化物-半導體型元件。在本發明特定實施例中,改變該穿隧層、電荷捕獲層及阻擋層以縮放該半導體-氧化物-氮化物-氧化物-半導體型元件。在特定實施例中,該縮放半導體-氧化物-氮化物-氧化物-半導體元件係可操作於低於+/-10伏特程式化及抹除電壓。在某些這類實施例中,該縮放半導體-氧化物-氮化物-氧化物-半導體元件係操作於一抹除電壓介於-5伏特至-9伏特之間,且最好是介於-5伏特至-7伏特,以提供-1至-3伏特的初始抹除電壓臨界位準(VTE),且在溫度介於-40至95攝氏度(℃)之間操作時,經過1毫秒-10毫秒脈衝後,抹除電壓臨界位準最好是-2至-3伏特。在其它特定實施例中,該半導體-氧化物-氮化物-氧化物-半導體型元件操作於一程式化電壓介於5伏特至9伏特之間,且最好是介於5伏特至7伏特,以提供1伏特至3伏特的初始程式化電壓臨界位準(VTP),且在1毫秒-10毫秒程式化脈衝後,最好是5毫秒程式化脈衝後,程式化電壓臨界位準為2伏特至3伏特。這些示範性縮放半導體-氧化物-氮化物-氧化物-半導體元件在85℃及至少10,000寫入/抹除週期,最好是100,000週期下,於20年後提供介於1伏特至2伏特之間的壽命終止(EOL)記憶體視窗。 Some embodiments of the invention include a scaled semiconductor-oxide-nitride-oxide-semiconductor type component. In a particular embodiment of the invention, the tunneling layer, charge trapping layer, and barrier layer are altered to scale the semiconductor-oxide-nitride-oxide-semiconductor type element. In a particular embodiment, the scaled semiconductor-oxide-nitride-oxide-semiconductor component is operable to program and erase voltages below +/- 10 volts. In some such embodiments, the scaled semiconductor-oxide-nitride-oxide-semiconductor component operates at an erase voltage between -5 volts and -9 volts, and preferably between -5 Volt to -7 volts to provide an initial erase voltage critical level (VTE) of -1 to -3 volts, and between 1 and 10 milliseconds when operating between -40 and 95 degrees Celsius (°C) After the pulse, the erase voltage critical level is preferably -2 to -3 volts. In other particular embodiments, the semiconductor-oxide-nitride-oxide-semiconductor type device operates at a stylized voltage between 5 volts and 9 volts, and preferably between 5 volts and 7 volts. To provide an initial programmed voltage threshold (VTP) of 1 volt to 3 volts, and after 1 millisecond to 10 milliseconds of programmed pulse, preferably 5 milliseconds of programmed pulse, the programmed voltage threshold is 2 volts. Up to 3 volts. These exemplary scaled semiconductor-oxide-nitride-oxide-semiconductor elements provide between 1 volt and 2 volts after 20 years at 85 ° C and at least 10,000 write/erase cycles, preferably 100,000 cycles. End of Life (EOL) memory window.
在一些實施例中,一傳統純氧(氧化物)穿隧層係以具有一特定氮濃度變化曲線之氮化氧化物來取代,以降低該穿隧層對該純氧穿隧層之有效氧化物厚度,同時保留低界面陷阱密度。這個可降低(縮減)該程式化/抹除電壓,同時提供較一傳統未縮放元件一樣好或更佳之抹除電壓臨界位準(VTPNTE)。在特定其它實施例中,該傳統氮化物電荷捕獲層係以具有至少一頂部和底部不同化學計量層的多層氮氧化物薄膜來取代之。在一這類實施例中,該多層氮氧化物包含一富矽又貧氧頂部層以定位並限制該電荷質量中心遠離該穿隧氧化物層,藉此局部增加該電荷捕獲層內之陷阱密度。在特定其它實施例中,該傳統高溫氧化物阻擋層係以一再氧化阻擋層來取代之,以增加該阻擋氧化物密度並藉此降低隨著縮放所產生的記憶體衰退率。這類實施例提供足夠淨電荷給一適當記憶體視窗,同時也降低陷阱輔助性穿隧以在該半導體-氧化物-氮化物-氧化物-半導體元件係操作於一降低之程式化/抹除電壓時,改善或維持程式化及抹除臨界電壓(VTPNTE)。 In some embodiments, a conventional pure oxygen (oxide) tunneling layer is replaced by a nitrided oxide having a specific nitrogen concentration profile to reduce effective oxidation of the tunneling layer to the pure oxygen tunneling layer. Material thickness while retaining low interface trap density. This reduces (reduces) the stylized/erase voltage while providing a better or better erase voltage threshold level (VTPNTE) than a conventional unscaled component. In certain other embodiments, the conventional nitride charge trapping layer is replaced with a multilayer oxynitride film having at least one top and bottom different stoichiometric layers. In one such embodiment, the multilayered oxynitride comprises a cerium-rich and oxygen-depleted top layer to position and limit the charge mass center away from the tunneling oxide layer, thereby locally increasing trap density within the charge trapping layer . In certain other embodiments, the conventional high temperature oxide barrier layer is replaced with a reoxidation barrier layer to increase the barrier oxide density and thereby reduce the rate of memory degradation associated with scaling. Such embodiments provide sufficient net charge to a suitable memory window while also reducing trap assist tunneling to operate the semiconductor-oxide-nitride-oxide-semiconductor component in a reduced stylization/erasing Improve or maintain the stylized and erased threshold voltage (VTPNTE) at voltage.
在此所使用之用語“上方”、“下方”、“之間”及“上”參考至一層對其它層之相對位置。據此,例如,一層沉積或置於另一層上方或下方可以是直接接觸著該另一層或具有一或更多中介層。甚至,一層沉積或置於各層間可以是直接接觸著該些層或具有一或更多中介層。相對地,位於一第二層上之第一層係接觸著那個第二層。此外,所提供一層相對於其它層之相對位置係假設相對於起始基板之薄膜的沉積、修改及移除操作,並未考慮到該基板絕對方位。 The terms "above", "below", "between" and "upper" are used herein to refer to the relative position of one layer to the other. Accordingly, for example, a layer deposited or placed over or under another layer may be in direct contact with the other layer or have one or more interposers. Even a layer deposited or placed between layers may be in direct contact with the layers or have one or more interposers. In contrast, the first layer on a second layer is in contact with that second layer. Moreover, the relative position of one layer provided relative to the other layers assumes that the deposition, modification, and removal operations of the film relative to the starting substrate do not take into account the absolute orientation of the substrate.
根據本發明一實施例,該非揮發性電荷捕獲記憶體元件係一半導體-氧化物-氮化物-氧化物-半導體型元件,其中,一電荷捕獲層係一例 如氮化物之絕緣體層。在另一實施例中,該非揮發性電荷捕獲記憶體元件係一快閃記憶體型元件,其中,該電荷捕獲層係一導體層或一例如多晶矽之半導體層。運用該氮化氧化物穿隧層之非揮發性電荷捕獲記憶體元件可致能一較低程式化或抹除電壓並提供與一傳統元件一樣好或更佳之抹除電壓臨界位準(VTPNTE)。 According to an embodiment of the invention, the non-volatile charge trapping memory device is a semiconductor-oxide-nitride-oxide-semiconductor type device, wherein a charge trapping layer is an example. An insulator layer such as a nitride. In another embodiment, the non-volatile charge trapping memory component is a flash memory type component, wherein the charge trapping layer is a conductor layer or a semiconductor layer such as polysilicon. The non-volatile charge trapping memory component using the nitride oxide tunneling layer can enable a lower stylization or erase voltage and provide a good or better erase voltage critical level (VTPNTE) than a conventional component. .
圖5根據本發明一實施例說明一縮放非揮發性電荷捕獲記憶體元件之一部分剖面圖,具有包含一氮化氧化物穿隧層、一多層氮氧化物電荷捕獲層及一密集阻擋層之縮放氧化物-氮化物-氧化物結構。應理解到在此所揭示之各種其它半導體-氧化物-氮化物-氧化物-半導體實施例也可被運用以產生超出圖5所述特定實施例之縮放氧化物-氮化物-氧化物堆疊,然而,也可操作於一降低之程式化/抹除電壓下。因此,儘管可將圖5之特性參考至本說明書各處時,然而本發明未限於本特定實施例。 5 is a partial cross-sectional view showing a portion of a scaled non-volatile charge trapping memory device having a nitride oxide tunneling layer, a multilayered NOx charge trapping layer, and a dense barrier layer, in accordance with an embodiment of the invention. Scale the oxide-nitride-oxide structure. It should be understood that various other semiconductor-oxide-nitride-oxide-semiconductor embodiments disclosed herein can also be utilized to produce a scaled oxide-nitride-oxide stack that exceeds the particular embodiment illustrated in FIG. However, it is also possible to operate at a reduced stylized/erased voltage. Accordingly, while the features of FIG. 5 may be referenced throughout the specification, the invention is not limited to this particular embodiment.
在圖5所示特定實施例中,該半導體-氧化物-氮化物-氧化物-半導體型元件500包含一半導體-氧化物-氮化物-氧化物-半導體閘極堆疊502,內含形成於一基板508之表面506上方之氧化物-氮化物-氧化物堆疊504。半導體-氧化物-氮化物-氧化物-半導體型元件500進一步包含一或更多源極和汲極區域510,對準至該閘極堆疊502並由一通道區域512所分開。大體上,該縮放半導體-氧化物-氮化物-氧化物-半導體閘極堆疊502包含形成於其上並接觸著該縮放氧化物-氮化物-氧化物堆疊504及一部分基板508之閘極層514。該閘極層514與該基板508係由該縮放氧化物-氮化物-氧化物堆疊504所分開或電性隔離。 In the particular embodiment illustrated in FIG. 5, the semiconductor-oxide-nitride-oxide-semiconductor type device 500 includes a semiconductor-oxide-nitride-oxide-semiconductor gate stack 502, which is formed in a An oxide-nitride-oxide stack 504 over surface 506 of substrate 508. The semiconductor-oxide-nitride-oxide-semiconductor type component 500 further includes one or more source and drain regions 510 that are aligned to the gate stack 502 and separated by a channel region 512. In general, the scaled semiconductor-oxide-nitride-oxide-semiconductor gate stack 502 includes a gate layer 514 formed thereon that contacts the scaled oxide-nitride-oxide stack 504 and a portion of the substrate 508. . The gate layer 514 and the substrate 508 are separated or electrically isolated by the scaled oxide-nitride-oxide stack 504.
在一實施例中,基板508係一本體基板,由可包含矽、鍺、 矽-鍺或一III-V族化合物半導體材料之單一結晶材料,但不限於此。在另一實施例中,基板508係由具有一頂部磊晶層之本體層所構成。在一特定實施例中,該本體層係由可包含矽、鍺、矽/鍺、一III-V族化合物半導體材料及石英之單一結晶材料,但不限於此,而該頂部磊晶層係由可包含矽、鍺、矽/鍺及一III-V族化合物半導體材料之單一結晶層所構成,但不限於此。在另一實施例中,基板508係由位於一下方本體層上方之中間絕緣體層上的頂部磊晶層所構成。該頂部磊晶層係由可包含矽(也就是,用以形成絕緣體上矽(SOI)半導體基板)、鍺、矽儲及一III-V族化合物半導體材料之單一結晶層,但不限於此。該絕緣層係由可包含二氧化矽、氮化矽及氮氧化矽之材料所構成,但不限於此。該下方本體層係由可包含矽、鍺、矽/鍺、一III-V族化合物半導體材料及石英之單一結晶材料,但不限於此。基板508及因此所形成介於該源極和汲極區域510間之通道區域512可包括摻雜物雜質原子。在一特定實施例中,該通道區域係P型摻雜,且在一替代性實施例中,該通道區域係N型摻雜。 In an embodiment, the substrate 508 is a body substrate, which may include 矽, 锗, A single crystalline material of ruthenium-iridium or a III-V compound semiconductor material, but is not limited thereto. In another embodiment, substrate 508 is comprised of a body layer having a top epitaxial layer. In a specific embodiment, the body layer is composed of a single crystalline material which may include yttrium, lanthanum, cerium/lanthanum, a III-V compound semiconductor material, and quartz, but is not limited thereto, and the top epitaxial layer is composed of It may be composed of a single crystal layer of ruthenium, rhodium, iridium/ruthenium and a group III-V compound semiconductor material, but is not limited thereto. In another embodiment, substrate 508 is comprised of a top epitaxial layer on an intermediate insulator layer over a lower body layer. The top epitaxial layer is composed of a single crystal layer which may include germanium (that is, a germanium-on-insulator (SOI) semiconductor substrate), germanium, germanium, and a group III-V compound semiconductor material, but is not limited thereto. The insulating layer is composed of a material which may include cerium oxide, cerium nitride, and cerium oxynitride, but is not limited thereto. The lower body layer is composed of a single crystal material which may include yttrium, lanthanum, cerium/lanthanum, a group III-V compound semiconductor material, and quartz, but is not limited thereto. Substrate 508 and thus channel region 512 formed between the source and drain regions 510 can include dopant impurity atoms. In a particular embodiment, the channel region is P-type doped, and in an alternative embodiment, the channel region is N-doped.
基板508內之源極和汲極區域510可為具有與該通道區域512相反導電性之任何區域。例如,根據本發明一實施例,源極和汲極區域510係N型摻雜,而通道區域512係P型摻雜。在一實施例中,基板508係由具有1x1015-1x1019原子/立方公分範圍硼濃度之硼摻雜單結晶矽所構成。源極和汲極區域510係由具有5x1016-5x1019原子/立方公分範圍之N型摻雜物濃度之磷或砷摻雜區域所構成。在一特定實施例中,源極和汲極區域510在基板508內具有80-200奈米範圍之深度。根據本發明一替代性實施例,源極和汲極區域510係P型摻雜,而該基板508之通道區域係N型摻雜。該 半導體-氧化物-氮化物-氧化物-半導體型元件500進一步包含在通道區域512上方之閘極堆疊502,內含一氧化物-氮化物-氧化物堆疊504、一閘極層514及一閘極帽蓋層525。該氧化物-氮化物-氧化物堆疊504進一步包含穿隧層516、一電荷捕獲層518及一阻擋層520。 The source and drain regions 510 within the substrate 508 can be any region having opposite conductivity to the channel region 512. For example, in accordance with an embodiment of the invention, the source and drain regions 510 are N-doped while the channel region 512 is P-doped. In one embodiment, substrate 508 is comprised of a boron doped single crystal germanium having a boron concentration in the range of 1 x 10 15 - 1 x 10 19 atoms per cubic centimeter. The source and drain regions 510 are comprised of phosphorous or arsenic doped regions having an N-type dopant concentration in the range of 5 x 10 16 - 5 x 10 19 atoms per cubic centimeter. In a particular embodiment, the source and drain regions 510 have a depth in the range of 80-200 nm in the substrate 508. In accordance with an alternative embodiment of the present invention, the source and drain regions 510 are P-type doped while the channel region of the substrate 508 is N-type doped. The semiconductor-oxide-nitride-oxide-semiconductor type device 500 further includes a gate stack 502 over the channel region 512, including an oxide-nitride-oxide stack 504, a gate layer 514, and a Gate cap layer 525. The oxide-nitride-oxide stack 504 further includes a tunneling layer 516, a charge trap layer 518, and a barrier layer 520.
在一實施例中,該穿隧層516包含一氮化氧化物。因為程式化及抹除電壓產生橫跨一穿隧層之10百萬伏特/公分等級大電場,故該程式化/抹除穿隧電流係大於該穿隧層障礙高度比上該穿隧層厚度之函數。然而,在保留期間,沒有大電場出現,因此,該電荷損失係大於該穿隧層厚度比上障礙高度之函數。為了改善用於降低之操作電壓的穿隧電流而不犧牲電荷保留,在一特定實施例中,該穿隧層516係一氮化氧化物。氮化作用藉由引誘氮至一不同純二氧化矽薄膜來增加該穿隧層之相對電容率或介電常數(ε)。在某些實施例中,該氮化氧化物之穿隧層516具有相同於運用純氧穿隧氧化物之傳統半導體-氧化物-氮化物-氧化物-半導體型元件之物理厚度。在特定實施例中,氮化作用在標準溫度下提供具有一5.07有效介電常數之穿隧層。 In an embodiment, the tunneling layer 516 comprises a nitrided oxide. Since the stylized and erase voltages generate a large electric field of 10 million volts/cm across a tunneling layer, the stylized/erased tunneling current is greater than the tunneling barrier height ratio than the tunneling layer thickness The function. However, during the retention period, no large electric field occurs, and therefore, the charge loss is greater than the thickness of the tunneling layer as a function of the height of the barrier. In order to improve the tunneling current for reducing the operating voltage without sacrificing charge retention, in a particular embodiment, the tunneling layer 516 is a nitrided oxide. Nitriding increases the relative permittivity or dielectric constant (ε) of the tunneling layer by attracting nitrogen to a different pure hafnium oxide film. In some embodiments, the nitrided oxide tunneling layer 516 has the same physical thickness as a conventional semiconductor-oxide-nitride-oxide-semiconductor type component that utilizes a pure oxygen tunneling oxide. In a particular embodiment, the nitridation provides a tunneling layer having a effective dielectric constant of 5.07 at standard temperature.
在某些實施例中,該縮放半導體-氧化物-氮化物-氧化物-半導體元件之氮化穿隧層具有相同於運用純氧穿隧氧化物之傳統未縮放半導體-氧化物-氮化物-氧化物-半導體型元件之物理厚度。大體上,該氮化穿隧氧化物之較高介電常數使得該記憶體層充電較快。在這類實施例中,因為來自該控制閘極之大電場跨越該氮化穿隧氧化物(由於氮化穿隧氧化物相對較高的介電常數之故)時係降低的相當少,所以該電荷捕獲層518在程式化/抹除期間充電快於那個厚度之純氧穿隧氧化物。這些實施例讓該半導體-氧 化物-氮化物-氧化物-半導體型元件500可以一降低之程式化/抹除電壓來操作,而仍能取得相同於一傳統半導體-氧化物-氮化物-氧化物-半導體型元件之程式化/抹除電壓臨界位準(VTPNTE)。在一特定實施例中,該半導體-氧化物-氮化物-氧化物-半導體型元件500運用一穿隧層516,具有介於1.5奈米至3.0奈米間,且較佳地介於1.9奈米至2.2奈米間之物理厚度的氮化穿隧氧化物。 In some embodiments, the nitride tunneling layer of the scaled semiconductor-oxide-nitride-oxide-semiconductor component has the same conventional unscaled semiconductor-oxide-nitride as the pure oxygen tunneling oxide. The physical thickness of the oxide-semiconductor type element. In general, the higher dielectric constant of the nitride tunneling oxide allows the memory layer to charge faster. In such embodiments, since the large electric field from the control gate spans the nitride tunneling oxide (due to the relatively high dielectric constant of the nitride tunneling oxide), the reduction is relatively small, so The charge trapping layer 518 charges faster than that thickness of pure oxygen tunneling oxide during stylization/erasing. These examples allow the semiconductor-oxygen The compound-nitride-oxide-semiconductor type device 500 can be operated with a reduced stylized/erase voltage while still achieving the same stylization as a conventional semiconductor-oxide-nitride-oxide-semiconductor type device. / erase voltage critical level (VTPNTE). In a particular embodiment, the semiconductor-oxide-nitride-oxide-semiconductor type component 500 utilizes a tunneling layer 516 having a range of between 1.5 nm and 3.0 nm, and preferably between 1.9 nm. A nitrided tunneling oxide of physical thickness between meters and 2.2 nm.
在一進一步實施例中,該穿隧層516係以降低該基板界面處之陷阱密度的特定方式來進行氮化以改善電荷保留。對於該氮化氧化物穿隧層被縮放至與一純氧穿隧氧化物相同之物理厚度的特定實施例而言,電荷保留可大約相同於同一厚度之純氧穿隧氧化物。參考至圖6,其說明在該穿隧層616一實施例內之近似氮濃度變化曲線,往該基板界面613之氮濃度614快速地降低以限制一與該基板612接觸之氮化矽(Si2N4)層形成。若有陷阱出現於該基板界面613處,則包括極性分子之氮化矽層不利地增加該陷阱密度,藉此透過陷阱至陷阱穿隧來降低電荷保留。因此,藉由調整該氮化穿隧氧化物內之氮濃度,該程式化/抹除電壓Vcg可被降低而未顯著地降低該縮放半導體-氧化物-氮化物-氧化物-半導體元件之電荷保留。如圖6中進一步所示地,接近該界面613之穿隧層616厚度中的25%被氮化以具有小於約5x1021氮原子/立方公分的氮濃度614,而接近該電荷捕獲層618之穿隧層616厚度中的25%被氮化以具有至少5x1021氮原子/立方公分。 In a further embodiment, the tunneling layer 516 is nitrided in a particular manner to reduce the trap density at the substrate interface to improve charge retention. For a particular embodiment where the nitride oxide tunneling layer is scaled to the same physical thickness as a pure oxygen tunneling oxide, the charge retention can be about the same as the pure oxygen tunneling oxide of the same thickness. Referring to Figure 6, an approximate nitrogen concentration profile in an embodiment of the tunneling layer 616 is illustrated, the nitrogen concentration 614 to the substrate interface 613 is rapidly reduced to limit a tantalum nitride (Si) in contact with the substrate 612. 2 N 4 ) layer formation. If a trap occurs at the substrate interface 613, the tantalum nitride layer comprising polar molecules disadvantageously increases the trap density, thereby reducing charge retention through trap-to-trap tunneling. Therefore, by adjusting the nitrogen concentration in the nitride tunneling oxide, the stylized/erase voltage Vcg can be lowered without significantly reducing the charge of the scaled semiconductor-oxide-nitride-oxide-semiconductor component. Reserved. As further shown in FIG. 6, 25% of the thickness of the tunneling layer 616 near the interface 613 is nitrided to have a nitrogen concentration 614 of less than about 5 x 10 21 nitrogen atoms per cubic centimeter, near the charge trapping layer 618. 25% of the thickness of the tunneling layer 616 is nitrided to have at least 5 x 10 21 nitrogen atoms per cubic centimeter.
在一實施例中,該穿隧層內之氧化物氮化作用降低它的能障並增加相對於一純氧化物穿隧層之介電常數。如圖5所示地,穿隧層516係基於說明目的標註一中心線517。圖6說明具有該穿隧層616的一半厚度 接近該基板612且該穿隧層616的一半厚度接近該電荷捕獲層620之類似中心線。在一特定實施例中,遍及該穿隧層616厚度的第一個25%的氮濃度614係低於5x1021原子/立方公分,且在該穿隧層616厚度的50%處或在該中心線617處大約達到5x1021原子/立方公分。在一進一步實施例中,在接近該電荷捕獲層618之穿隧層616厚度的最後25%內的氮濃度614係超過5x1021原子/立方公分。在一示範性配置中,對於一2.2奈米穿隧層而言,在接近該基板612之穿隧層的第一個0.6奈米內的氮濃度614係低於5x1021原子/立方公分且在該穿隧層616厚度的1.1奈米處係至少5x1021原子/立方公分。在本方式中,可增加該穿隧層電容而不顯著地降低一縮放半導體-氧化物-氮化物-氧化物-半導體型元件之電荷保留。 In one embodiment, the oxide nitridation within the tunneling layer reduces its energy barrier and increases the dielectric constant relative to a pure oxide tunneling layer. As shown in FIG. 5, the tunneling layer 516 is labeled with a centerline 517 for illustrative purposes. 6 illustrates a similar centerline having a half thickness of the tunneling layer 616 proximate to the substrate 612 and a half thickness of the tunneling layer 616 proximate to the charge trapping layer 620. In a particular embodiment, the first 25% nitrogen concentration 614 across the thickness of the tunneling layer 616 is less than 5 x 10 21 atoms/cm 3 and is at or 50% of the thickness of the tunneling layer 616. Line 617 is approximately 5 x 10 21 atoms/cm 3 . In a further embodiment, the nitrogen concentration 614 in the last 25% of the thickness of the tunneling layer 616 near the charge trapping layer 618 exceeds 5 x 10 21 atoms per cubic centimeter. In an exemplary configuration, for a 2.2 nm tunneling layer, the nitrogen concentration 614 within the first 0.6 nm of the tunneling layer proximate to the substrate 612 is less than 5 x 10 21 atoms/cm 3 and is The 1.1 nm thickness of the tunneling layer 616 is at least 5 x 10 21 atoms/cm 3 . In this manner, the tunneling layer capacitance can be increased without significantly reducing the charge retention of a scaled semiconductor-oxide-nitride-oxide-semiconductor type component.
圖7A根據本發明一實施例說明顯示降低可貢獻至一氮化氧化物穿隧層之程式化電壓模擬示圖。如所示地,對於20埃純氧化物穿隧層及40埃氮化物電荷捕獲層之保留電壓上的漏電係等於20埃氮化氧化物穿隧層及40埃氮化物電荷捕獲層,而對於該氮化氧化物穿隧層之程式化電壓上的充電電流係大於該純氧化物穿隧層的那個。因此,在一程式化或抹除電壓為9.1伏特下,根據本發明一氮化氧化物穿隧層可提供與具有一10伏特程式化或抹除電壓之傳統純氧化物穿隧層所得相同之程式化/抹除位準。 FIG. 7A is a schematic diagram showing a stylized voltage display showing a reduction in contribution to a nitride nitride tunneling layer, in accordance with an embodiment of the invention. FIG. As shown, the leakage current on the retention voltage of the 20 angstrom pure oxide tunneling layer and the 40 Å nitride charge trapping layer is equal to 20 Å nitriding oxide tunneling layer and 40 Å nitride charge trapping layer, but The charging current on the stylized voltage of the nitride oxide tunneling layer is greater than the one of the pure oxide tunneling layers. Thus, a nitrided oxide tunneling layer in accordance with the present invention can provide the same uniform thickness as a conventional pure oxide tunneling layer having a 10 volt stylized or erased voltage at a stylized or erase voltage of 9.1 volts. Stylize/erase level.
參考回至圖5,該半導體-氧化物-氮化物-氧化物-半導體型元件500之電荷捕獲層518可進一步包含任何一般已知之電荷捕獲材料並具有任何合適厚度以儲存電荷及調整該元件之臨界電壓。在某些實施例中,電荷捕獲層518係氮化矽(SiN4)、富矽氮化矽或富矽氮氧化矽。該富矽薄膜包含界面矽游離鍵。在一特定實施例中,該電荷捕獲層518具有橫跨該電荷 捕獲層厚度之均勻化學計量。例如,該電荷捕獲層518可進一步包含具有不同矽、氧及氮組成成分之至少二氮氧化物層。該電荷捕獲層內之這類組成成分異質性具有超過具有一實際上同質組成成分之傳統半導體-氧化物-氮化物-氧化物-半導體電荷捕獲層的一些執行效率優勢。例如,降低該傳統半導體-氧化物-氮化物-氧化物-半導體電荷捕獲層厚度增加該陷阱至陷阱穿隧率,產生損失資料保留的結果。然而,當該電荷捕獲層之化學計量係根據本發明一實施例而做修改時,該電荷捕獲層厚度可被縮小而仍舊維持良好資料保留。 Referring back to FIG. 5, the charge trapping layer 518 of the semiconductor-oxide-nitride-oxide-semiconductor type component 500 can further comprise any generally known charge trapping material and have any suitable thickness to store charge and condition the element. Threshold voltage. In some embodiments, the charge trapping layer 518 is tantalum nitride (SiN 4 ), germanium-rich tantalum nitride or germanium-rich germanium oxide. The ruthenium rich film comprises an interfacial 矽 free bond. In a particular embodiment, the charge trap layer 518 has a uniform stoichiometry across the thickness of the charge trap layer. For example, the charge trap layer 518 can further comprise at least a oxynitride layer having different cerium, oxygen, and nitrogen constituents. Such compositional heterogeneity within the charge trapping layer has some performance efficiency advantages over conventional semiconductor-oxide-nitride-oxide-semiconductor charge trapping layers having a substantially homogeneous composition. For example, reducing the thickness of the conventional semiconductor-oxide-nitride-oxide-semiconductor charge trap layer increases the trap to trap tunneling, resulting in loss of data retention. However, when the stoichiometry of the charge trap layer is modified in accordance with an embodiment of the present invention, the thickness of the charge trap layer can be reduced while still maintaining good data retention.
在一特定實施例中,該底部氮氧化物層518A在具有一相對較低陷阱狀態密度的電荷捕獲層內提供一局部區域,藉此降低該穿隧氧化物界面處的陷阱密度以降低該縮放半導體-氧化物-氮化物-氧化物-半導體元件中的陷阱輔助性穿隧。這個導致一給予電荷捕獲層厚度的儲存電荷損失降低以致能用於該氧化物-氮化物-氧化物堆疊有效氧化物厚度縮放的電荷捕獲層縮放。在一這類實施例中,該底部氮氧化物518A具有含高矽濃度、高氧濃度及低氮濃度的第一組成成分以提供一富氧氮氧化物。這個第一氮氧化物對應至介於1.5奈米至5.0奈米之間的有效氧化物厚度可具有介於2.5奈米至4.0奈米之間的物理厚度。在一特定實施例中,該底部氮氧化物層518A具有一約為6的有效介電常數(ε)。 In a particular embodiment, the bottom oxynitride layer 518A provides a localized region within the charge trapping layer having a relatively low trap state density, thereby reducing trap density at the tunneling oxide interface to reduce the scaling Trap assisted tunneling in semiconductor-oxide-nitride-oxide-semiconductor elements. This results in a reduction in the stored charge loss imparted to the thickness of the charge trap layer to enable charge trap layer scaling for the oxide-nitride-oxide stack effective oxide thickness scaling. In one such embodiment, the bottom oxynitride 518A has a first composition comprising a high cerium concentration, a high oxygen concentration, and a low nitrogen concentration to provide an oxygen-rich nitrogen oxide. The effective oxide thickness of this first oxynitride corresponding to between 1.5 nm and 5.0 nm may have a physical thickness between 2.5 nm and 4.0 nm. In a particular embodiment, the bottom oxynitride layer 518A has an effective dielectric constant ([epsilon]) of about 6.
在一進一步實施例中,一頂部氮氧化物層518B在具有一相對較高陷阱狀態密度的電荷捕獲層內提供一局部區域。該相對較高陷阱狀態密度致能一降低厚度的電荷捕獲層以提供充足捕獲電荷使該該縮放氧化物-氮化物-氧化物堆疊內的記憶體視窗仍舊足夠。因此,該較高陷阱狀態密 度具有增加一特定電荷捕獲層厚度之記憶體元件的程式化及抹除電壓間差異,允許該電荷捕獲層厚度降低並藉此降低該縮放半導體-氧化物-氮化物-氧化物-半導體元件的氧化物-氮化物-氧化物之有效氧化物厚度的效應。在一特定實施例中,該頂部氮氧化物層組成成分具有一高矽濃度和一高氮濃度與一低氧濃度以產生一富矽又貧氧之氮氧化物。大體上,該頂部氮氧化物矽含量越高,該頂部氮氧化物所提供之陷阱狀態密度越高且可降低(藉此降低該電荷捕獲層厚度以致能較低電壓操作)的頂部氮氧化物層厚度越多。更進一步,該矽含量越高,該介電常數越大且該頂部氮氧化物層的有效氧化物厚度越小。相對於具有一實際上同質組成成分之傳統氮氧化物電荷捕獲層,本有效氧化物厚度降低可大於該富氧底部氮氧化物的有效氧化物厚度增加對於該電荷捕獲層在有效氧化物厚度上淨降低的位移。在一這類實施例中,該頂部氮氧化物具有一約為7的有效介電常數。 In a further embodiment, a top oxynitride layer 518B provides a localized region within the charge trapping layer having a relatively high trap state density. The relatively high trap state density enables a reduced thickness of the charge trapping layer to provide sufficient trapped charge to maintain a memory window within the scaled oxide-nitride-oxide stack. Therefore, the higher trap state is dense The stylization and erase voltage difference of a memory element having a specific charge trapping layer thickness, allowing the charge trap layer to be reduced in thickness and thereby reducing the scaled semiconductor-oxide-nitride-oxide-semiconductor component Effect of effective oxide thickness of oxide-nitride-oxide. In a particular embodiment, the top oxynitride layer composition has a high cerium concentration and a high nitrogen concentration and a low oxygen concentration to produce a cerium-rich and oxygen-depleted oxynitride. In general, the higher the top oxynitride content, the higher the trap state density provided by the top oxynitride and the lower the top NOx that can be reduced (thus reducing the thickness of the charge trap layer to enable lower voltage operation) The more layer thickness. Further, the higher the niobium content, the larger the dielectric constant and the smaller the effective oxide thickness of the top oxynitride layer. The effective oxide thickness reduction may be greater than the effective oxide thickness increase of the oxygen-rich bottom oxynitride relative to the conventional oxynitride charge trap layer having a substantially homogeneous composition for the charge trap layer on the effective oxide thickness Net reduced displacement. In one such embodiment, the top oxynitride has an effective dielectric constant of about 7.
圖7B說明指示穿隧層、電荷捕獲層及阻擋層沉積(沉積時)後之矽(Si)、氮(N)、氧(O)及氫(H)濃渡之示範性第二離子質譜(SIMS)變化曲線。一基礎線條件(“BL”)及像圖5(“Bilayer”)所述之雙層氮氧化物條件被重覆。該基礎線條件具有含一同質組成成分之傳統電荷捕獲層。該x軸代表在該阻擋層露出頂部表面處的0奈米深度透過由上往下堆疊開始進行並終止於該基板內。如所示地,對應至該電荷捕獲層一部分的雙層條件氧濃度在介於約5奈米至10奈米間之深度區域理所當然地係低於1.0x1022原子/立方公分。相對地,該基礎線條件在這個相同區域內顯示一實際上大於1.0x1022的較高氧濃度。如進一步所示地,該基礎線條件在該6奈米至10奈米標記間具有一實際上定值氧濃度,而該雙層條件在靠近該10奈米標記處 較該6奈米標記處實際上顯示更多氧。這個氧濃度不均勻性代表在該雙層條件中的貧氧頂部氮氧化物及富氧底部氮氧化物之間的轉移。 7B illustrates an exemplary second ion mass spectrum indicating the concentration of yttrium (Si), nitrogen (N), oxygen (O), and hydrogen (H) after tunneling, charge trapping, and barrier deposition (during deposition) ( SIMS) curve. A baseline condition ("BL") and a double layer NOx condition as described in Figure 5 ("Bilayer") are repeated. The baseline condition has a conventional charge trapping layer containing a homogeneous composition. The x-axis represents a depth of 0 nm at the exposed top surface of the barrier layer that begins with stacking from top to bottom and terminates within the substrate. As shown, the two-layer conditional oxygen concentration corresponding to a portion of the charge trap layer is, of course, less than 1.0 x 10 22 atoms/cm 3 in a depth region between about 5 nm and 10 nm. In contrast, the baseline condition exhibits a higher oxygen concentration that is substantially greater than 1.0 x 10 22 in this same region. As further shown, the baseline condition has a substantially constant oxygen concentration between the 6 nm to 10 nm mark, and the bilayer condition is near the 10 nm mark than the 6 nm mark It actually shows more oxygen. This oxygen concentration non-uniformity represents the transfer between the oxygen-depleted top nitrogen oxides and the oxygen-rich bottom nitrogen oxides in the two-layer condition.
在某些實施例中,該底部氮氧化物層厚度對該頂部氮氧化物層厚度的比值係介於1:6至6:1之間,且更佳地該底部氮氧化物厚度對該頂部氮氧化物厚度的比值至少為1:4。在該第一氮氧化物具有介於2.5奈米至4.0奈米間之物理厚度所在示範性配置中,對於具有淨物理厚度介於7.5奈米至10.0奈米之間的電荷捕獲層518而言,該第二氮氧化物518B具有介於5.0奈米至6.0奈米間之淨物理厚度。在一運用具有30埃物理厚度之底部氮氧化物特定實施例中,對於具有一90埃淨物理厚度的縮放電荷捕獲層而言,該頂部氮氧化物具有一60埃物理厚度。 In certain embodiments, the ratio of the thickness of the bottom oxynitride layer to the thickness of the top oxynitride layer is between 1:6 and 6:1, and more preferably the bottom NOx thickness is to the top. The ratio of the thickness of the oxynitride is at least 1:4. In an exemplary configuration in which the first oxynitride has a physical thickness between 2.5 nanometers and 4.0 nanometers, for a charge trapping layer 518 having a net physical thickness between 7.5 nanometers and 10.0 nanometers. The second oxynitride 518B has a net physical thickness of between 5.0 nm and 6.0 nm. In a particular embodiment utilizing a bottom oxynitride having a physical thickness of 30 angstroms, the top oxynitride has a physical thickness of 60 angstroms for a scaled charge trapping layer having a net physical thickness of 90 angstroms.
在這些特定實施例中,組成成分異質性被利用以既定位又限制陷阱至該電荷捕獲層(也就是集中該些陷阱)中,距該穿隧層界面一段距離的內嵌現場。圖8A根據本發明一實施例進一步說明一縮放半導體-氧化物-氮化物-氧化物-半導體元件保留期間能帶圖,該元件包含一氮化穿隧氧化物816、一多層電荷捕獲氮氧化物818及介於一基板812和控制閘極814之間之一密集阻擋層820。如所述地,該電荷捕獲層818之組成成分異質性影響該電荷捕獲層之富矽頂部氮氧化物818B及富氧底部氮氧化物818A之間的原子價和傳導帶。如圖8B所示地,根據本發明一實施例的電荷捕獲層提供該電荷捕獲層818內之富氧及富矽氮氧化物層的界面處的能帶調整。本帶隙調整用以定位一給予電荷捕獲層厚度之頂部氮氧化物層內的捕獲電荷質量中心進一步遠離該基板。在該些氮氧化物層間之傳導帶調整也可用以降低回流。 In these particular embodiments, compositional heterogeneity is utilized to both locate and trap traps into the charge trapping layer (i.e., to concentrate the traps) at an in-situ site at a distance from the tunneling layer interface. 8A further illustrates a band diagram of a scaled semiconductor-oxide-nitride-oxide-semiconductor device during retention, the device comprising a nitride tunneling oxide 816, a multilayer charge trapping nitrogen oxide, in accordance with an embodiment of the invention. The object 818 and a dense barrier layer 820 between a substrate 812 and a control gate 814. As described, the compositional heterogeneity of the charge trapping layer 818 affects the valence and conduction band between the yttrium-rich top oxynitride 818B and the oxygen-rich bottom oxynitride 818A of the charge trapping layer. As shown in FIG. 8B, a charge trapping layer in accordance with an embodiment of the present invention provides energy band adjustment at the interface of the oxygen-rich and yttria-rich oxide layer within the charge trapping layer 818. The bandgap adjustment is used to position a center of the trapped charge within the top oxynitride layer that is imparted to the thickness of the charge trap layer further away from the substrate. Conductive band adjustment between the oxynitride layers can also be used to reduce reflow.
如圖8A進一步所示地,在一特定實施例中,該富矽頂部氮氧化物818B被氧化或再氧化。相對於圖8A中用於說明目的之虛線所述之前氧化帶隙,這類富矽頂部區域氧化可在接近該阻擋層810產生分級帶隙。在一實施例中,大約該頂部氮氧化物層818B的一半被再氧化以在朝向該阻擋層820界面處具有一較高氧濃度。在另一實施例中,實際上全部該頂部氮氧化物層818B被再氧化以較沉積時具有一更高氧濃度。在一實施例中,該再氧化增加該頂部氮氧化物層818B的氧濃度大約0.25x1021-0.35x1021原子/公分。運用一再氧化電荷捕獲層之這類實施例可阻止陷阱漂移至該電荷捕獲層及該阻擋層間之界面,藉此允許該電荷捕獲層厚度降低而不引起與弄薄一實際上同質組成成分之荷捕獲層有關的電荷保留不利結果。阻止該電荷漂移至該阻擋氧化物層也降低抹除期間橫跨該阻擋氧化物的電場,其降低電子回流,或允許縮小該阻擋氧化物,同時維持相同位準的電子回流。在該電荷捕獲層內之不同化學計量區域所提供並如在特定實施例中進一步結合一部分電荷捕獲層再氧化的這類陷阱位置及限制可致能根據本發明之縮放半導體-氧化物-氮化物-氧化物-半導體元件以操作於一降低電壓或較快程式化和抹除時間,同時維持良好記憶體保留。 As further shown in FIG. 8A, in a particular embodiment, the cerium-rich top oxynitride 818B is oxidized or reoxidized. This yttrium-rich top region oxidation can produce a graded band gap near the barrier layer 810 relative to the previous oxidized band gap as illustrated by the dashed line for illustration purposes in FIG. 8A. In one embodiment, approximately one half of the top oxynitride layer 818B is reoxidized to have a higher oxygen concentration at the interface toward the barrier layer 820. In another embodiment, virtually all of the top oxynitride layer 818B is reoxidized to have a higher oxygen concentration than when deposited. In one embodiment, the reoxidation increases the oxygen concentration of the top oxynitride layer 818B by about 0.25 x 10 21 - 0.35 x 10 21 atoms / cm. Embodiments that employ a re-oxidation of the charge trapping layer can prevent traps from drifting to the interface between the charge trapping layer and the barrier layer, thereby allowing the charge trapping layer to be reduced in thickness without causing a thinning of a substantially homogeneous composition. The charge associated with the capture layer retains an unfavorable result. Preventing this charge from drifting to the barrier oxide layer also reduces the electric field across the barrier oxide during erasing, which reduces electron reflow, or allows the barrier oxide to be shrunk while maintaining the same level of electron reflow. Such trap locations and limitations provided by different stoichiometric regions within the charge trap layer and further recombined as part of the charge trap layer in a particular embodiment may enable scaling of the semiconductor-oxide-nitride in accordance with the present invention. - Oxide-semiconductor components operate at a reduced voltage or faster stylized and erased time while maintaining good memory retention.
雖只描述二氮氧化物層,也就是一頂部及一底部層於該些圖形且在此其它地方,然而本發明並未限於此,且該多層電荷儲存層可包含任意氮氧化物層數量n、其中任一者或全部具有不同氧、氮及/或矽組成成分。尤其,具有高達5不同組成成分氮氧化物層多層電荷儲存層之已被生產及測試。 Although only the oxynitride layer is described, that is, a top and a bottom layer are in the patterns and elsewhere, the invention is not limited thereto, and the multilayer charge storage layer may comprise any number of oxynitride layers n Any or all of them have different oxygen, nitrogen and/or bismuth compositions. In particular, multilayer charge storage layers having up to 5 different compositions of oxynitride layers have been produced and tested.
如圖5中進一步所述地,該氧化物-氮化物-氧化物堆疊之阻 擋層520包含一介於約30埃至約50埃間之二氧化矽層。縮放該半導體-氧化物-氮化物-氧化物-半導體型元件之氧化物-氮化物-氧化物堆疊中之阻擋層520係不普通的,因為若未正確執行則在某些偏壓條件下會不利地增加來自該控制閘極之載子回流之故。在一包含一部分再氧化電荷捕獲層實施例中,該阻檔層520係一較沉積時相對地更密集之高溫氧化物(HTO)。一密集氧化物具有一較低終端氫或氫氧鍵分數。例如,自一高溫氧化物中移除該氫或水具有增加該薄膜密度並改善該高溫氧化物品質的效應。該較高品質氧化物使該層在厚度上能被縮放。在一實施例中,沉積時之氫濃度係大於2.5x1020原子/立分公分並在該密集薄膜中降低至小於8.0x1019原子/立分公分。在一示範性實施例中,沉積時之高溫氧化物厚度係介於2.5奈米至10.0奈米之間,且因密集化作用而使各處更薄上10%至30%。 As further described in FIG. 5, the oxide-nitride-oxide stack barrier layer 520 comprises a ruthenium dioxide layer between about 30 angstroms and about 50 angstroms. Scaling the barrier layer 520 in the oxide-nitride-oxide stack of the semiconductor-oxide-nitride-oxide-semiconductor type device is not common because under certain bias conditions, if not performed correctly The carrier reflow from the control gate is disadvantageously increased. In an embodiment comprising a portion of the reoxidized charge trap layer, the barrier layer 520 is a relatively dense tungsten oxide (HTO) that is deposited more densely. A dense oxide has a lower terminal hydrogen or hydroxide bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x 10 20 atoms per centimeter and is reduced to less than 8.0 x 10 19 atoms per centimeter in the dense film. In an exemplary embodiment, the high temperature oxide thickness during deposition is between 2.5 nanometers and 10.0 nanometers, and is 10% to 30% thinner everywhere due to densification.
在一替代性實施例中,進一步改變該阻擋氧化物層以整合氮。在一這類實施例中,該氮係以橫跨該阻擋氧化物層厚度的氧化物-氮化物-氧化物堆疊形式進行整合。取代該傳統純氧阻檔層之這類三明治結構有利地降低該通道及控制閘極間之整個堆疊有效氧化物厚度並致能調整傳導帶位移以降低載子回流。該氧化物-氮化物-氧化物區塊層接著可與該氮化穿隧氧化物及包括一底部氮氧化物層和一頂部氮氧化物層之電荷捕獲層進行整合。 In an alternative embodiment, the barrier oxide layer is further altered to integrate nitrogen. In one such embodiment, the nitrogen is integrated in an oxide-nitride-oxide stack across the thickness of the barrier oxide layer. Such a sandwich structure that replaces the conventional pure oxygen barrier layer advantageously reduces the overall stack effective oxide thickness between the channel and the control gate and enables adjustment of the conduction band displacement to reduce carrier reflow. The oxide-nitride-oxide block layer can then be integrated with the nitride tunneling oxide and a charge trapping layer comprising a bottom oxynitride layer and a top oxynitride layer.
在該氧化物-氮化物-氧化物堆疊504上方係一閘極層514。該閘極層514可為任何導體或半導體材料。在一這類實施例中,該閘極層514係多晶矽(poly)。在另一實施例中,該閘極層514包含一金屬,例如,鉿、鍺、鈦、鉭、鋁、釕、鈀、鉑、鈷及鎳、它們的矽化物、它們的氮化物及 它們的碳化物,但不限於此。在一特定實施例中,該閘極層514係具有一物理厚度介於70奈米至250奈米之間的多晶矽。 A gate layer 514 is applied over the oxide-nitride-oxide stack 504. The gate layer 514 can be any conductor or semiconductor material. In one such embodiment, the gate layer 514 is polycrystalline. In another embodiment, the gate layer 514 comprises a metal such as tantalum, niobium, titanium, tantalum, aluminum, hafnium, palladium, platinum, cobalt, and nickel, their tellurides, their nitrides, and Their carbides are not limited to this. In a particular embodiment, the gate layer 514 has a polysilicon having a physical thickness between 70 nm and 250 nm.
如圖5中進一步所述地,該半導體-氧化物-氮化物-氧化物-半導體型元件500包含鄰接於該閘極層514上方之閘極帽蓋層525並具有大約相同於該閘極層514和氧化物-氮化物-氧化物堆疊504之關鍵尺寸。在某些實施例中,該閘極帽蓋層525形成該閘極堆疊502之頂部層並於該閘極層514和氧化物-氮化物-氧化物堆疊504圖案化期間提供一硬式遮罩。在一些實施例中,該閘極帽蓋層525有助於對該些半導體-氧化物-氮化物-氧化物-半導體元件之自我對準接觸件(SAC)之形成。該閘極帽蓋層525可由能夠提供後續蝕刻製程必選之任何材料所構成,例如,二氧化矽、氮化矽及氮氧化矽,但不限於此。 As further described in FIG. 5, the semiconductor-oxide-nitride-oxide-semiconductor type device 500 includes a gate cap layer 525 adjacent to the gate layer 514 and has approximately the same gate layer. The critical dimensions of 514 and oxide-nitride-oxide stack 504. In some embodiments, the gate cap layer 525 forms the top layer of the gate stack 502 and provides a hard mask during patterning of the gate layer 514 and the oxide-nitride-oxide stack 504. In some embodiments, the gate cap layer 525 facilitates the formation of self-aligned contacts (SAC) for the semiconductor-oxide-nitride-oxide-semiconductor elements. The gate cap layer 525 may be formed of any material that is capable of providing a subsequent etching process, such as, for example, hafnium oxide, hafnium nitride, and hafnium oxynitride, but is not limited thereto.
在一特定實施例中,一半導體-氧化物-氮化物-氧化物-半導體型元件運用一氧化物-氮化物-氧化物堆疊,包含對應至一大約18埃物理厚度之具有一14埃有效氧化物厚度的氮化穿隧氧化物、內含對應至一大約25埃物理厚度之具有一內含20埃有效氧化物厚度的底部氮氧化物層和對應至一大約60埃物理厚度之具有一30埃有效氧化物厚度的頂部氮氧化物層的電荷捕獲層、以及沉積至40埃並密集化至30埃的阻擋氧化物層。這類半導體-氧化物-氮化物-氧化物-半導體型元件可被操作於大約9伏特電壓範圍,以在1毫秒至10毫秒脈衝後提供一-2伏特初始抹除電壓臨界位準(VTE)。 In a particular embodiment, a semiconductor-oxide-nitride-oxide-semiconductor type device utilizes an oxide-nitride-oxide stack comprising a 14 angstrom effective oxidation corresponding to a physical thickness of about 18 angstroms. a nitride tunneling oxide having a thickness corresponding to a physical thickness of about 25 angstroms having a bottom oxynitride layer having an effective oxide thickness of 20 angstroms and a physical thickness corresponding to a thickness of about 60 angstroms. A charge trapping layer of the top oxynitride layer of effective oxide thickness, and a barrier oxide layer deposited to 40 angstroms and densed to 30 angstroms. Such a semiconductor-oxide-nitride-oxide-semiconductor type device can be operated in a voltage range of approximately 9 volts to provide a -2 volt initial erase voltage critical level (VTE) after 1 millisecond to 10 millisecond pulses. .
圖9說明例如圖5所述那個縮放半導體-氧化物-氮化物-氧化物-半導體之製造方法流程圖,該半導體-氧化物-氮化物-氧化物-半導體如上所述地包含一氮化氧化物穿隧層、一已部分再氧化之多層電荷捕獲氮氧化 物及一密集阻擋氧化物層。圖9之製造方法始於操作900,在基板一含矽表面上方形成一氮化氧化物穿隧層。圖10說明圖9中操作900之形成該氮化氧化物之特定方法流程圖。 Figure 9 illustrates a flow chart of a method of fabricating a scaled semiconductor-oxide-nitride-oxide-semiconductor such as that described in Figure 5, which includes a nitridation oxidation as described above. Multi-layer charge trapping nitrogen oxidation And a dense barrier oxide layer. The fabrication method of FIG. 9 begins at operation 900 by forming a nitride oxide tunneling layer over a substrate-containing surface. Figure 10 illustrates a flow chart of a particular method of forming the nitrided oxide of operation 900 of Figure 9.
在圖10所述實施例中,量身定製一半導體-氧化物-氮化物-氧化物-半導體型元件之氮化穿隧氧化物內的氮變化曲線係以多步驟氮化及氧化方法來完成之。在操作1001,一薄熱氧化物係由例如圖5基板508之基板表面上的含矽層所形成。因為與該基板具有一良好界面係需要的,故一化學氧化物形成可為該熱氧化作用前奏。因此,在一特定實施例中,一化學氧化物係出現於該熱氧化作用期間(相反於執行一傳統“氫氟酸最後處理”預先清潔)。在一這類實施例中,該化學氧化物係隨著臭氧水而生長以形成具有一大約1.0奈米厚度的化學氧化物層。 In the embodiment illustrated in FIG. 10, the nitrogen variation curve in the nitride tunneling oxide of a semiconductor-oxide-nitride-oxide-semiconductor type device is tailored to a multi-step nitridation and oxidation method. Finished. In operation 1001, a thin thermal oxide is formed from a germanium-containing layer on the surface of the substrate, such as substrate 508 of FIG. Since a good interface with the substrate is required, a chemical oxide formation can be a prelude to the thermal oxidation. Thus, in a particular embodiment, a chemical oxide is present during the thermal oxidation (as opposed to performing a conventional "hydrofluoric acid final treatment" pre-cleaning). In one such embodiment, the chemical oxide is grown with ozone water to form a chemical oxide layer having a thickness of about 1.0 nanometer.
該熱氧化物係形成至一約介於1.0奈米至1.8奈米間之厚度。在一特定實施例中,該熱氧化物係形成至一介於1.0奈米至1.2奈米間之厚度。因此,在操作501之熱氧化作用期間出現一1.0奈米化學氧化物所在實施例中,該表面氧化物厚度實際上未增加,然而,該氧化物品質被改善。在一進一步實施例中,該氧化物係相當低密度,有助於後續整合具有一顯著重量百比分的氮。然而,一薄膜密度太低會在該矽基板界面產生太多氮。在操作501下形成該二氧化矽層進一步充當下面進一步所述之後續熱處理期間阻擋額外基板氧化物形成之手段。在一實施例中,一大氣壓力垂直熱反應器(VTR)被運用以在介於680℃至800℃間之溫度下,存在有例如氧(O2)、氧化亞氮(N2O)、氧化氮(NO)、臭氧(O3)及蒸汽(H2O)之氧化氣體中,生長該熱氧化物。依據所選取氧化劑,該氧化操作1001可為3.5分鐘至20 分鐘持續時間。在一大氣壓實施例中,在介於700℃至750℃間之溫度,7分鐘至20分鐘製程時間下,運用氧氣來形成一約1.0奈米二氧化矽薄膜。 The thermal oxide is formed to a thickness of between about 1.0 nm and 1.8 nm. In a particular embodiment, the thermal oxide is formed to a thickness of between 1.0 nm and 1.2 nm. Thus, in the embodiment where a 1.0 nm chemical oxide occurs during the thermal oxidation of operation 501, the surface oxide thickness does not actually increase, however, the oxide quality is improved. In a further embodiment, the oxide is relatively low density, facilitating subsequent integration of nitrogen having a significant weight percentage. However, a film density that is too low will produce too much nitrogen at the interface of the germanium substrate. Forming the ruthenium dioxide layer under operation 501 further serves as a means of blocking the formation of additional substrate oxide during subsequent heat treatment as further described below. In one embodiment, an atmospheric pressure vertical thermal reactor (VTR) is employed to present, for example, oxygen (O 2 ), nitrous oxide (N 2 O), at temperatures between 680 ° C and 800 ° C. The thermal oxide is grown in an oxidizing gas of nitrogen oxide (NO), ozone (O 3 ), and steam (H 2 O). The oxidation operation 1001 can be from 3.5 minutes to 20 minutes duration depending on the selected oxidant. In the atmospheric pressure embodiment, oxygen is used to form a film of about 1.0 nm of cerium oxide at a temperature between 700 ° C and 750 ° C for a period of 7 minutes to 20 minutes.
在另一實施例中,該氧化操作1001係利用例如市場上可由美加州斯科特山谷市的AVIZA科技公司取得之先進垂直處理器(AVP)之次大氣壓處理器來執行之。該先進垂直處理器可被操作於上述垂直熱反應器之溫度範圍內及一介於1托耳(T)至大氣壓力間之壓力下。依據該操作壓力,用以形成介於約1.0奈米至1.8奈米厚度間之熱二氧化矽薄膜的氧化時間可如一熟知此項技術之人士所可能決定地延長多達近乎一小時。 In another embodiment, the oxidation operation 1001 is performed using, for example, a sub-atmospheric processor of an Advanced Vertical Processor (AVP) commercially available from AVIZA Technologies, Inc. of Scott Valley, California. The advanced vertical processor can be operated within the temperature range of the vertical thermal reactor and at a pressure between 1 Torr (T) and atmospheric pressure. Depending on the operating pressure, the oxidation time of the hot ruthenium dioxide film used to form a thickness between about 1.0 nm and 1.8 nm can be extended by up to nearly one hour as may be determined by those skilled in the art.
接著,在操作1002,在圖10所述之多個氧化及氮化方法實施例中,操作1001所形成之熱氧化物被氮化。大體上,在操作1002,一氮回火被執行以增加該介電係數(K)並降低該熱氧化物層之固定電荷。在一實施例中,該氮回火運用氮氣(N2)或例如氨(NH3)之氫化氮來源。在另一實施例中,該氮回火運用例如氘化氨(DH3)之氘化氮來源。在一特定實施例中,該氮回火係執行於700℃至850℃之間的溫度下,持續3.5分鐘至30分鐘的時間。在另一特定實施例中,該氮回火係執行於725℃至775℃間的溫度下,持續3.5分鐘至30分鐘間的時間。在一這類實施例中,氨係引進於溫度介於725℃至775℃之間的大氣壓力下,持續3.5分鐘至30分鐘。在一替代性實施例中,一次大氣壓的氨回火係執行於例如該先進垂直處理器之處理器中,以800℃至900℃進行5分鐘至30分鐘。在又一實施例中,一般稱之為氮電漿及熱回火結合者被執行。 Next, at operation 1002, in the plurality of oxidation and nitridation method embodiments illustrated in FIG. 10, the thermal oxide formed by operation 1001 is nitrided. Generally, at operation 1002, a nitrogen temper is performed to increase the dielectric constant (K) and reduce the fixed charge of the thermal oxide layer. In one embodiment, the nitrogen use tempering nitrogen (N 2) or ammonia, for example, (NH 3) hydrogenation of a nitrogen source. In another embodiment, the use of nitrogen tempering nitrogen sources such as deuterium, deuterated ammonia (DH 3) of. In a particular embodiment, the nitrogen tempering is performed at a temperature between 700 ° C and 850 ° C for a period of from 3.5 minutes to 30 minutes. In another particular embodiment, the nitrogen tempering is performed at a temperature between 725 ° C and 775 ° C for a period of between 3.5 minutes and 30 minutes. In one such embodiment, the ammonia is introduced at atmospheric pressure between 725 ° C and 775 ° C for between 3.5 minutes and 30 minutes. In an alternative embodiment, the primary atmospheric ammonia tempering is performed in a processor such as the advanced vertical processor, at 800 ° C to 900 ° C for 5 minutes to 30 minutes. In yet another embodiment, a combination of nitrogen plasma and thermal tempering is generally performed.
接在操作1002之後,一再氧化作用係執行於操作1004。在一實施例中,在該再氧化製程期間,一氧化氣體被熱裂解以在接近該薄膜 表面處提供氧基。該些氧基消除氮及氫捕獲電荷。該再氧化操作1002也在該基板界面處生長一額外氧化物以提供在該基板和該穿隧層內之氮濃度之間的物理位移。例如,參考回至圖5,該再氧化作用有助於分開該基板界面513與該穿隧層516內之氮濃度。如圖6所特定顯示地,對於一配置而言,該穿隧層616內之基板界面613處的氮濃度614顯著地係小於5x1021氮原子/立方公分且可以是5x1020氮原子/立方公分等級。來自該基板界面之氮位移改善一半導體-氧化物-氮化物-氧化物-半導體型元件之保留。在一實施例中,該基板界面613所生長之氧化物厚度係限定為1.2奈米至3.0奈米之間。在操作1004,該再氧化製程條件被選取以使得操作1001所形成之熱氧化物厚度阻止超過一大約3.0奈米厚度的氧化作用,其可提供缺乏任何有利氮濃度的穿隧層。一般稱之為氧化劑者可被運用於該再氧化製程,例如,氧化氮、氧化亞氮、氧、臭氧及蒸汽,但不限於此。任何這類氧化劑可利用操作於800℃至900℃間之溫度的已知熱處理器來引進。依據該些操作參數,再氧化時間可介於5分鐘至40分鐘之間的任一時間點。在一特定實施例中,氧化氮被運用於一大氣壓熔爐內,操作於一介於800℃至850℃間之溫度下,持續約15分鐘製程時間以在一矽基板上形成大約2.2奈米厚度的氮化氧化物薄膜。在一這類實施例中,該2.2奈米厚度的再氧化薄膜在接近該矽基板界面處形成一介於0.5奈米至0.8奈米之間的區域,該區域具有小於5x1021氮原子/立方公分的氮濃度。 Following operation 1002, a re-oxidation is performed at operation 1004. In one embodiment, during the reoxidation process, the oxidizing gas is thermally cracked to provide an oxy group near the surface of the film. These oxy groups eliminate nitrogen and hydrogen trap charges. The reoxidation operation 1002 also grows an additional oxide at the substrate interface to provide a physical displacement between the substrate and the nitrogen concentration within the tunneling layer. For example, referring back to FIG. 5, the reoxidation helps to separate the nitrogen concentration in the substrate interface 513 and the tunneling layer 516. As specifically shown in FIG. 6, for a configuration, the nitrogen concentration 614 at the substrate interface 613 in the tunneling layer 616 is significantly less than 5 x 10 21 nitrogen atoms per cubic centimeter and may be 5 x 10 20 nitrogen atoms per cubic centimeter. grade. The nitrogen displacement from the substrate interface improves the retention of a semiconductor-oxide-nitride-oxide-semiconductor type element. In one embodiment, the thickness of the oxide grown by the substrate interface 613 is defined to be between 1.2 nm and 3.0 nm. At operation 1004, the reoxidation process conditions are selected such that the thermal oxide thickness formed by operation 1001 prevents oxidation greater than about 3.0 nm thickness, which can provide a tunneling layer that lacks any favorable nitrogen concentration. Those generally referred to as oxidants can be used in the reoxidation process, for example, nitrogen oxide, nitrous oxide, oxygen, ozone, and steam, but are not limited thereto. Any such oxidant can be introduced using a known thermal processor operating at temperatures between 800 °C and 900 °C. Depending on the operating parameters, the reoxidation time can be anywhere between 5 minutes and 40 minutes. In a particular embodiment, the nitrogen oxide is used in a one-pressure furnace operating at a temperature between 800 ° C and 850 ° C for a period of about 15 minutes to form a thickness of about 2.2 nm on a substrate. A nitride oxide film. In one such embodiment, the 2.2 nm thick reoxidized film forms a region between 0.5 nm and 0.8 nm near the interface of the tantalum substrate, the region having less than 5 x 10 21 nitrogen atoms per cubic centimeter. Nitrogen concentration.
接在該再氧化操作1004之後,一第二氮回火係執行於操作1006,以再氮化該穿隧層。一第二氮回火被運用以進一步增加該穿隧層之介電係數而沒有在該基板界面處不利地引進大量氫或氮陷阱。在一實施例 中,該第二氮回火操作1006係利用與操作1002中所執行回火之一模一樣的條件來執行之。在另一實施例中,該第二氮回火操作1006係以較該第一氮回火操作1002高之溫度來執行以引進額外氮至該穿隧層中。在一實施例中,該氮回火運用例如氨之氫化氮來源。在另一實施例中,該氮回火運用例如氘化氨之氘化氮來源。在一特定實施例中,該氮回火操作1006於大氣壓力下,以一介於750℃至950℃間之溫度,執行一介於3.5分鐘至30分鐘間的製程時間來運用氨。在另一特定實施例中,該氮回火係執行於800°C至850℃間的大氣壓力下,持續5分鐘至10分鐘。 After the reoxidation operation 1004, a second nitrogen tempering is performed at operation 1006 to re-nitridate the tunneling layer. A second nitrogen tempering is employed to further increase the dielectric constant of the tunneling layer without introducing a significant amount of hydrogen or nitrogen traps at the substrate interface. In an embodiment The second nitrogen tempering operation 1006 is performed using the same conditions as the tempering performed in operation 1002. In another embodiment, the second nitrogen tempering operation 1006 is performed at a higher temperature than the first nitrogen tempering operation 1002 to introduce additional nitrogen into the tunneling layer. In one embodiment, the nitrogen tempering utilizes a source of hydrogenated nitrogen such as ammonia. In another embodiment, the nitrogen tempering utilizes a source of deuterated nitrogen such as deuterated ammonia. In a particular embodiment, the nitrogen tempering operation 1006 utilizes ammonia at atmospheric pressure for a process time between 3.5 minutes and 30 minutes at a temperature between 750 ° C and 950 ° C. In another particular embodiment, the nitrogen tempering is performed at atmospheric pressure between 800 ° C and 850 ° C for 5 minutes to 10 minutes.
如所述地,圖10所述之操作1001至操作1006提供二氧化操作及二氮化操作。所述之重複性氧化及氮化方案使該穿隧層內的氮濃度可專門量身定製以得到程式化電壓的降低或程式化速度的增加與一半導體-氧化物-氮化物-氧化物-半導體型元件記憶體保留的增加兩者。該氧化、氮化、再氧化、再氮化操作1001-1006的連續性質讓一小於3.0奈米厚度穿隧層內的氮濃度可估計,同時提供於該穿隧層及該基板間的界面具有非常少的氮和氫陷阱。該獨立的氧化、氮化、再氧化、再氮化操作1001-1006讓該第一和第二氧化作用及第一和第二氮化作用可依獨立設計條件來執行以提供更大自由度量身定製一穿隧層內的氮濃度變化曲線。在一有利的實施例中,操作1001、1002、1004和1006係連續地執行於單一熱處理器內,而沒有在各操作間將該基板自該處理器中移除。在一這類實施例中,製程壓力係維持在操作1001-1006所用大氣壓力下。首先,氧化操作1001係執行於一介於700℃至750℃間之溫度下。氣體流動接著如指定般地改變,以在一介於725℃至775℃間之溫度下執行該氮回火操作1002。該熔爐溫度接 著被陡升至800℃至850℃之間,且氣體流動再被改變以執行該再氧化操作1004。最後,在該熔爐保持於800℃至850℃之間時,氣體流動再被改變以執行該第二氮回火操作1006。 As described, operations 1001 through 1006 of FIG. 10 provide a dioxide operation and a diazotization operation. The repetitive oxidation and nitridation scheme allows the concentration of nitrogen in the tunneling layer to be tailored to achieve a reduction in stylized voltage or an increase in stylized speed with a semiconductor-oxide-nitride-oxide - Increase in memory retention of semiconductor type components. The continuous nature of the oxidation, nitridation, reoxidation, and re-nitridation operations 1001-1006 allows a nitrogen concentration in the tunneling layer of less than 3.0 nm thickness to be estimated while providing an interface between the tunneling layer and the substrate. Very few nitrogen and hydrogen traps. The separate oxidation, nitridation, reoxidation, and re-nitridation operations 1001-1006 allow the first and second oxidations and the first and second nitridation to be performed under independent design conditions to provide a greater measure of freedom Customize the curve of nitrogen concentration in a tunnel. In an advantageous embodiment, operations 1001, 1002, 1004, and 1006 are performed continuously within a single thermal processor without removing the substrate from the processor between operations. In one such embodiment, the process pressure is maintained at atmospheric pressure used in operations 1001-1006. First, the oxidation operation 1001 is performed at a temperature between 700 ° C and 750 ° C. The gas flow is then varied as specified to perform the nitrogen tempering operation 1002 at a temperature between 725 °C and 775 °C. The furnace temperature is connected The ramp is ramped up between 800 °C and 850 °C and the gas flow is changed to perform the reoxidation operation 1004. Finally, as the furnace is maintained between 800 ° C and 850 ° C, the gas flow is again altered to perform the second nitrogen tempering operation 1006.
隨著圖5氮化氧化物穿隧層516真正地完成,可藉由回到圖9所述之方法來繼續製造該氧化物-氮化物-氧化物堆疊。在一實施例中,多個氮化物或氮氧化物電荷捕獲層係於操作902和904下,以一低壓化學氣相沉積製程,使用包括例如矽烷(SiH4)、二氯矽烷(SiH2Cl2)、四氯矽烷(SiCl4)或雙三級丁氨基矽烷(BTBAS)類之矽來源,例如氮氣、氨、氧化亞氮或三氧化氮(NO3)類之氮來源及例如氧氣或氧化亞氮類之含氧氣體之製程氣體來形成之。替代性地,可使用已由氘取代氫的氣體,包含例如氘化氨(ND3)替代氨。以氘替代氫有利地鈍化在該基板界面處的矽懸空鍵,藉此增加半導體-氧化物-氮化物-氧化物-半導體型元件之NBTI(負偏壓溫度不穩定性)壽命。 As the nitride oxide tunneling layer 516 of FIG. 5 is truly completed, the oxide-nitride-oxide stack can be continued by returning to the method described in FIG. In one embodiment, a plurality of nitride or oxynitride-based layer on the charge trapping operation in 902 and 904 to a low pressure chemical vapor deposition process, including for example, using Silane (SiH 4), dichloro Silane (SiH 2 Cl 2 ) a source of ruthenium tetrachloride (SiCl 4 ) or a double tertiary butylamino decane (BTBAS) such as nitrogen, ammonia, nitrous oxide or nitrogen trioxide (NO 3 ) and such as oxygen or oxidation A process gas of a nitrogen-containing oxygen-containing gas is formed. Alternatively, use of hydrogen gas has been substituted by deuterium, deuterated ammonia, for example, comprise (ND 3) Alternative ammonia. Replacing hydrogen with hydrazine advantageously passivates the ruthenium dangling bonds at the interface of the substrate, thereby increasing the NBTI (negative bias temperature instability) lifetime of the semiconductor-oxide-nitride-oxide-semiconductor type element.
在一示範性配置中,在操作902,一氮氧化物電荷捕獲層可藉由將該基板放置於一沉積腔室內並引進包含氧化亞氮、氨及二氯矽烷之製程氣體,同時,維持該腔室在大約自5毫托耳(mT)至500毫托耳壓力下並維持該基板在大約700攝氏度至850攝氏度,且較佳地至少約為780攝氏度之溫度下,持續一段大約自2.5分鐘至20分鐘的時間,而被沉積於一穿隧層上方。在一進一步實施例中,該製程氣體可包含以約從8:1至1:8比值混合之氧化亞氮和氨的第一氣體混合物及約從1:7至7:1比值混合之二氯矽烷和氨的第二氣體混合物,且可以大約每分鐘5至200標準立方公分(sccm)之流速來引進。已發現到在這些條件下所產生或沉積之氮氧化物層產生一富矽又富氧之氮氧化物層,例如,圖5所述之電荷捕獲層518A。該電荷捕 獲層之形成可進一步涉及操作904之化學氣相沉積製程,運用約從8:1至1:8比值混合之氧化亞氮和氨的第一氣體混合物及約從1:7至7:1比值混合之二氯矽烷和氨的第二氣體混合物,以大約每分鐘5至20標準立方公分之流速來引進,產生一富矽、富氮又貧氧之氮氧化物層,例如,圖5所述之電荷捕獲層518B。 In an exemplary configuration, at operation 902, an oxynitride charge trap layer can be maintained by placing the substrate in a deposition chamber and introducing a process gas comprising nitrous oxide, ammonia, and methylene chloride. The chamber is maintained at a temperature of from about 5 millitorr (mT) to 500 millitorr and maintains the substrate at a temperature of from about 700 degrees Celsius to 850 degrees Celsius, and preferably at least about 780 degrees Celsius, for a period of about 2.5 minutes. It is deposited over a tunneling layer for up to 20 minutes. In a further embodiment, the process gas can comprise a first gas mixture of nitrous oxide and ammonia mixed in a ratio of from about 8:1 to 1:8 and a dichloride mixed from about 1:7 to 7:1 ratio. A second gas mixture of decane and ammonia, and may be introduced at a flow rate of from about 5 to 200 standard cubic centimeters per minute (sccm). It has been discovered that the oxynitride layer produced or deposited under these conditions produces a ruthenium-rich and oxygen-rich oxynitride layer, such as charge trapping layer 518A as described in FIG. The charge trap The formation of the layer may further involve a chemical vapor deposition process of operation 904, using a first gas mixture of nitrous oxide and ammonia mixed from about 8:1 to 1:8 ratio and a ratio of from about 1:7 to 7:1. A second gas mixture of mixed dichloromethane and ammonia is introduced at a flow rate of about 5 to 20 standard cubic centimeters per minute to produce a ruthenium-rich, nitrogen-rich, oxygen-depleted oxynitride layer, for example, as described in FIG. Charge trapping layer 518B.
在一實施例中,在操作902和904,一電荷捕獲層形成係接著以與使用於形成該穿隧層相同的製程工具來執行之,且未在操作901和904間將該基板自該沉積腔室中卸除。在一特定實施例中,不改變圖10之第二氮回火操作1006期間對基板加熱之溫度而沉積該電荷捕獲層。在一實施例中,接在操作901之氮化該穿隧層之後,該電荷捕獲層係藉由改變氨氣體流速並引進氧化亞氮和二氯矽烷來提供該些要求氣體比值而產生一富矽又富氧層和一富矽又富氮之氮氧化物層中任一者或是一雙層配置中的兩層來依序且立即地進行沉積。 In one embodiment, at operations 902 and 904, a charge trap layer formation is then performed in the same process tool used to form the tunneling layer, and the substrate is not deposited from between 901 and 904. Removed from the chamber. In a particular embodiment, the charge trapping layer is deposited without changing the temperature at which the substrate is heated during the second nitrogen tempering operation 1006 of FIG. In one embodiment, after nitriding the tunneling layer in operation 901, the charge trapping layer generates a rich by varying the ammonia gas flow rate and introducing nitrous oxide and dichlorosilane to provide the desired gas ratios. The ruthenium enriched layer and one of the ruthenium-rich and nitrogen-rich oxynitride layers or two of a two-layer configuration are deposited sequentially and immediately.
接在操作904之後,一阻擋層可在操作906,經由包含例如熱氧化作用或具有化學氣相沉積技術之沉積作用的任何合適手段來形成之。在一較佳實施例中,該阻擋層係以一高溫化學氣相沉積製程來形成之。大體上,該沉積製程涉及在大約從50毫托耳至1000毫托耳壓力下,提供例如矽烷、二氯矽烷或四氯矽烷類之矽來源及例如氧氣或氧化亞氮類之含氧氣體於一沉積腔室內,持續一段約自10分鐘至120分鐘的時間,同時,維持該基板在650℃至850℃溫度下。較佳地,該阻擋層係以相同於操作902和904形成該電荷捕獲層所運用之製程工具來依序沉積之。更佳地,該阻擋層係以相同於該電荷捕獲層(各層)和該穿隧層兩者之製程工具來形成,且 未在各操作間移除該基板。 Following operation 904, a barrier layer can be formed at operation 906 via any suitable means including, for example, thermal oxidation or deposition with chemical vapor deposition techniques. In a preferred embodiment, the barrier layer is formed by a high temperature chemical vapor deposition process. In general, the deposition process involves providing a source of ruthenium such as decane, dichlorodecane or tetrachloromethane and an oxygen-containing gas such as oxygen or nitrous oxide at a pressure of from about 50 mTorr to about 1000 mTorr. In a deposition chamber, the period of time is from about 10 minutes to 120 minutes while maintaining the substrate at a temperature of 650 ° C to 850 ° C. Preferably, the barrier layer is deposited sequentially in the same manner as the process tools used to form the charge trap layer in operations 902 and 904. More preferably, the barrier layer is formed by a process tool identical to both the charge trap layer (each layer) and the tunneling layer, and The substrate was not removed between operations.
在圖9所述實施例中,操作906所沉積之阻擋層係於操作908進行再氧化以增加該阻擋層氧化物密度。如在此其它處所述地,操作908可進一步氧化或再氧化該電荷捕獲層的一部分或全部,例如,圖5B所示電荷捕獲層518B的一部分或全部以得到例如圖8A所述之分級帶隙。大體上,該再氧化作用係執行於例如氧氣(O2)、氧化亞氮(N2O)、氧化氮(NO)、臭氧(O3)及蒸汽(H2O)之氧化氣體存在時。在一實施例中,該再氧化製程可以較該阻擋層沉積溫度高之溫度來執行之。在該阻擋氧化物沉積後之再氧化使氧化劑擴散更受到控制而可控制地氧化或再氧化該薄的電荷捕獲層。在一特別有利的實施例中,一稀釋濕式氧化作用被運用。該稀釋濕式氧化作用不同於一濕式氧化作用之處在於氫氧氣比值係介於1至1.3之間。在一特定實施例中,具有一約1.2氫氧氣比值的稀釋氧化作用係執行於一介於800℃至900℃之間的溫度下。在一進一步實施例中,該稀釋氧化作用持續時間可足以在一矽基板上生長出介於5.0奈米至12.5奈米之間的二氧化矽。在一這類實施例中,該持續時間係足以在一矽基板上生長出一大約10奈米至1.1奈米的二氧化矽層。這類稀釋氧化製程用以再氧化該沉積阻擋層氧化物且可進一步氧化或再氧化一部分電荷捕獲層以給予像圖8A或8B所述之傳導帶結構。在另一實施例中,該再氧化操作908可進一步用以在與該半導體-氧化物-氮化物-氧化物-半導體型元件相同基板上之非半導體-氧化物-氮化物-氧化物-半導體型元件區域中形成例如用於一互補式金屬氧化物半導體(CMOS)場效電晶體(FET)的閘極氧化物。在另一實施例中,該再氧化操作908可進一步用以擴散氘至該半導體-氧化物-氮化物-氧化物-半導體型元件之電荷捕 獲層或阻擋層各部分中。 In the embodiment illustrated in FIG. 9, the barrier layer deposited by operation 906 is reoxidized at operation 908 to increase the barrier oxide density. As described elsewhere herein, operation 908 may further oxidize or reoxidize a portion or all of the charge trapping layer, for example, a portion or all of charge trapping layer 518B of FIG. 5B to obtain a graded strip such as that depicted in FIG. 8A. Gap. In general, the reoxidation is carried out in the presence of an oxidizing gas such as oxygen (O 2 ), nitrous oxide (N 2 O), nitrogen oxide (NO), ozone (O 3 ), and steam (H 2 O). In one embodiment, the reoxidation process can be performed at a temperature that is higher than the barrier layer deposition temperature. Reoxidation after deposition of the barrier oxide causes the oxidant diffusion to be more controlled to controllably oxidize or reoxidize the thin charge trapping layer. In a particularly advantageous embodiment, a dilute wet oxidation is utilized. The dilution wet oxidation differs from a wet oxidation in that the hydrogen to oxygen ratio is between 1 and 1.3. In a particular embodiment, the dilute oxidation having a hydrogen to oxygen ratio of about 1.2 is carried out at a temperature between 800 ° C and 900 ° C. In a further embodiment, the dilution oxidation duration may be sufficient to grow cerium oxide between 5.0 nm and 12.5 nm on a substrate. In one such embodiment, the duration is sufficient to grow a layer of ceria having a thickness of from about 10 nm to about 1.1 nm on a substrate. Such a dilute oxidation process is used to reoxidize the deposition barrier oxide and may further oxidize or reoxidize a portion of the charge trap layer to impart a conduction band structure as described in FIG. 8A or 8B. In another embodiment, the reoxidation operation 908 can further be used to non-semiconductor-oxide-nitride-oxide-semiconductors on the same substrate as the semiconductor-oxide-nitride-oxide-semiconductor type device. A gate oxide, for example, for a complementary metal oxide semiconductor (CMOS) field effect transistor (FET) is formed in the type of device region. In another embodiment, the re-oxidation operation 908 can be further used to diffuse germanium into portions of the charge trapping layer or barrier layer of the semiconductor-oxide-nitride-oxide-semiconductor type element.
如圖9所述地,該方法接著可隨著例如圖5閘極層514之閘極層形成而完成於操作910。在某些實施例中,操作910可進一步包含例如圖5閘極帽蓋層525之閘極帽蓋層的形成。隨著該閘極堆疊製造的完成,進一步製程可如習知技術中所知般地發生以結束該半導體-氧化物-氮化物-氧化物-半導體型元件300的製造。 As illustrated in FIG. 9, the method can then be completed at operation 910 as, for example, the gate layer formation of gate layer 514 of FIG. In some embodiments, operation 910 can further include the formation of a gate cap layer, such as gate cap layer 525 of FIG. As the gate stack fabrication is completed, a further process can occur as is known in the art to terminate the fabrication of the semiconductor-oxide-nitride-oxide-semiconductor type component 300.
儘管本發明已以言語專述結構特性及/或方法動作,然要了解到在所附申請專利範圍中所定義之本發明不必受限於所述特定特性或動作。所揭示之該些特定特性及動作係欲了解本主張權利之發明努力說明的特別得體配置,而非用於限定本發明。 Although the present invention has been described in terms of structural features and/or methods, it is understood that the invention is not limited by the specific features or acts. The particular features and acts disclosed are intended to be illustrative of the particular embodiments of the invention.
配置方式及替代例Configuration method and alternatives
圖11A說明一半導體-氧化物-氮化物-氧化物-半導體型元件1100之中間結構的剖面圖,該元件具有包含一氮化氧化物穿隧層、一多層電荷捕獲層及一密集阻擋層的縮放氧化物-氮化物-氧化物結構。應理解到在此所揭示之各種其它半導體-氧化物-氮化物-氧化物-半導體實施例也可被運用以產生超出圖11A所述特定實施例之縮放氧化物-氮化物-氧化物堆疊,然而,也可操作於一降低之程式化/抹除電壓下。因此,儘管可將圖11A之特性參考至本說明書各處,然而本發明未限於本特定實施例。 Figure 11A illustrates a cross-sectional view of an intermediate structure of a semiconductor-oxide-nitride-oxide-semiconductor type device 1100 having a nitride oxide tunneling layer, a multilayer charge trapping layer, and a dense barrier layer. The scaled oxide-nitride-oxide structure. It should be understood that various other semiconductor-oxide-nitride-oxide-semiconductor embodiments disclosed herein can also be utilized to produce a scaled oxide-nitride-oxide stack that extends beyond the particular embodiment illustrated in Figure 11A. However, it is also possible to operate at a reduced stylized/erased voltage. Accordingly, although the features of FIG. 11A may be referenced throughout the specification, the invention is not limited to this particular embodiment.
在圖11A所示特定實施例中,該半導體-氧化物-氮化物-氧化物-半導體型元件1100包含一半導體-氧化物-氮化物-氧化物-半導體閘極堆疊1102,內含形成於一基板1108之表面1106上方之氧化物-氮化物-氧化物堆疊1104。半導體-氧化物-氮化物-氧化物-半導體型元件1100進一步包含 一或更多源極和汲極區域1110,對準至該閘極堆疊1102並由一通道區域1112進行電性連接。大體上,該縮放半導體-氧化物-氮化物-氧化物-半導體閘極堆疊1102進一步包含形成於其上並接觸該縮放氧化物-氮化物-氧化物堆疊1104之閘極層1114以及一在該閘極層1114上方之閘極帽蓋層1125。該閘極層1114與該基板1108係由該縮放氧化物-氮化物-氧化物堆疊1104所分開或電性隔離。 In the particular embodiment illustrated in FIG. 11A, the semiconductor-oxide-nitride-oxide-semiconductor type device 1100 includes a semiconductor-oxide-nitride-oxide-semiconductor gate stack 1102, which is formed in a An oxide-nitride-oxide stack 1104 over the surface 1106 of the substrate 1108. The semiconductor-oxide-nitride-oxide-semiconductor type element 1100 further includes One or more source and drain regions 1110 are aligned to the gate stack 1102 and electrically connected by a channel region 1112. In general, the scaled semiconductor-oxide-nitride-oxide-semiconductor gate stack 1102 further includes a gate layer 1114 formed thereon and contacting the scaled oxide-nitride-oxide stack 1104 and a A gate cap layer 1125 over the gate layer 1114. The gate layer 1114 and the substrate 1108 are separated or electrically isolated by the scaled oxide-nitride-oxide stack 1104.
在一實施例中,基板1108係一本體基板,由可包含矽、鍺、矽-鍺或一III-V族化合物半導體材料之單一結晶材料所構成,但不限於此。在另一實施例中,基板1108係由具有一頂部磊晶層之本體層所構成。在一特定實施例中,該本體層係由可包含矽、鍺、矽/鍺、一III-V族化合物半導體材料及石英之單一結晶材料所構成,但不限於此,而該頂部磊晶層係由可包含矽、鍺、矽/鍺及一III-V族化合物半導體材料之單一結晶層所構成,但不限於此。在另一實施例中,基板1108係由位於一下方本體層上方之中間絕緣體層上的頂部磊晶層所構成。該頂部磊晶層係由可包含矽(也就是,用以形成一絕緣體上矽(SOI)半導體基板)、鍺、矽/鍺及一III-V族化合物半導體材料之單一結晶層所構成,但不限於此。該絕緣層係由可包含二氧化矽、氮化矽及氮氧化矽之材料所構成,但不限於此。該下方本體層係由可包含矽、鍺、矽/鍺、一III-V族化合物半導體材料及石英之單一結晶材料所構成,但不限於此。基板1108及因此所形成介於該源極和汲極區域1110間之通道區域1112可包括摻雜物雜質原子。該通道區域1112可包括多晶矽或再結晶多晶矽以形成一單結晶通道區域。在一特定實施例中,在該通道區域1112包含一單結晶矽所在處,該通道區域可被形成以相對於該通道區 域一長軸具有<100>表面結晶方位。 In one embodiment, the substrate 1108 is a body substrate composed of a single crystalline material that may comprise yttrium, lanthanum, ytterbium, or a group III-V compound semiconductor material, but is not limited thereto. In another embodiment, substrate 1108 is comprised of a body layer having a top epitaxial layer. In a specific embodiment, the body layer is composed of a single crystalline material which may include yttrium, lanthanum, cerium/lanthanum, a III-V compound semiconductor material, and quartz, but is not limited thereto, and the top epitaxial layer It is composed of a single crystal layer which may include ytterbium, ytterbium, ytterbium/ytterbium and a group III-V compound semiconductor material, but is not limited thereto. In another embodiment, the substrate 1108 is comprised of a top epitaxial layer on an intermediate insulator layer over a lower body layer. The top epitaxial layer is composed of a single crystal layer which may comprise germanium (that is, to form a silicon-on-insulator (SOI) semiconductor substrate), germanium, germanium/tellurium, and a group III-V compound semiconductor material, but Not limited to this. The insulating layer is composed of a material which may include cerium oxide, cerium nitride, and cerium oxynitride, but is not limited thereto. The lower body layer is composed of a single crystal material which may include yttrium, lanthanum, cerium/lanthanum, a group III-V compound semiconductor material, and quartz, but is not limited thereto. The substrate 1108 and thus the channel region 1112 formed between the source and drain regions 1110 can include dopant impurity atoms. The channel region 1112 can comprise polycrystalline germanium or recrystallized polycrystalline germanium to form a single crystalline channel region. In a particular embodiment, the channel region 1112 includes a single crystalline germanium, the channel region can be formed relative to the channel region The long axis of the domain has a <100> surface crystal orientation.
基板1108內之源極和汲極區域1110可為具有相反於該通道區域1112導電性之任何區域。例如,根據本發明一實施例,源極和汲極區域1110係N型摻雜,而通道區域1112係P型摻雜。在一實施例中,基板1108係由具有1x1015-1x1019原子/立方公分範圍硼濃度之硼摻雜單結晶矽所構成。源極和汲極區域1110係由具有5x1016-5x1019原子/立方公分範圍之N型摻雜物濃度之磷或砷摻雜區域所構成。在一特定實施例中,源極和汲極區域1110在基板508內具有80-200奈米範圍之深度。根據本發明一替代性實施例,源極和汲極區域1110係P型摻雜,而該基板1108之通道區域係N型摻雜。 The source and drain regions 1110 within the substrate 1108 can be any region having conductivity opposite the channel region 1112. For example, in accordance with an embodiment of the invention, the source and drain regions 1110 are N-doped while the channel region 1112 is P-doped. In one embodiment, the substrate 1108 is comprised of a boron doped monocrystalline germanium having a boron concentration in the range of 1 x 10 15 - 1 x 10 19 atoms per cubic centimeter. The source and drain regions 1110 are comprised of phosphorous or arsenic doped regions having an N-type dopant concentration in the range of 5 x 10 16 - 5 x 10 19 atoms per cubic centimeter. In a particular embodiment, the source and drain regions 1110 have a depth in the range of 80-200 nm within the substrate 508. In accordance with an alternative embodiment of the present invention, the source and drain regions 1110 are P-doped while the channel region of the substrate 1108 is N-doped.
該氧化物-氮化物-氧化物堆疊1104包含一穿隧層1116、一多層電荷捕獲層1118及一阻擋層1120。 The oxide-nitride-oxide stack 1104 includes a tunneling layer 1116, a multilayer charge trap layer 1118, and a barrier layer 1120.
在一實施例中,該穿隧層1116係包含一氮化氧化物之氮化氧化物穿隧層。因為程式化及抹除電壓產生橫跨一穿隧層之10百萬伏特/公分等級大電場,故該程式化/抹除穿隧電流係大於該穿隧層障礙高度比上該穿隧層厚度之函數。然而,在保留期間,沒有大電場出現,因此,該電荷損失係大於該穿隧層厚度比上障礙高度之函數。氮化作用增加該穿隧層之相對電容率或介電常數(ε)以改善用於降低操作電壓之穿隧電流。在特定實施例中,氮化作用提供一穿隧層1116一介於4.75至5.25間之有效介電常數,且較佳地,介於4.90至5.1之間(在標準溫度下)。在一這類實施例中,在標準溫度下,氮化作用提供一具有5.07有效介電常數之穿隧層。 In one embodiment, the tunneling layer 1116 comprises a nitrided oxide tunneling layer of nitrided oxide. Since the stylized and erase voltages generate a large electric field of 10 million volts/cm across a tunneling layer, the stylized/erased tunneling current is greater than the tunneling barrier height ratio than the tunneling layer thickness The function. However, during the retention period, no large electric field occurs, and therefore, the charge loss is greater than the thickness of the tunneling layer as a function of the height of the barrier. Nitriding increases the relative permittivity or dielectric constant (ε) of the tunneling layer to improve the tunneling current used to reduce the operating voltage. In a particular embodiment, the nitridation provides a tunneling layer 1116 having an effective dielectric constant between 4.75 and 5.25, and preferably between 4.90 and 5.1 (at standard temperature). In one such embodiment, the nitridation provides a tunneling layer having an effective dielectric constant of 5.07 at standard temperature.
在這類實施例中,因為來自該控制閘極之大電場跨越該氮化 穿隧氧化物(由於氮化穿隧氧化物相對較高的介電常數之故)時係降低的相當少,所以該電荷捕獲層518在程式化/抹除期間進行充電會快於那個厚度之純氧化物穿隧層。這些實施例讓該半導體-氧化物-氮化物-氧化物-半導體型元件1100可以一降低之程式化/抹除電壓來操作,而仍能取得相同於一傳統半導體-氧化物-氮化物-氧化物-半導體型元件之程式化/抹除電壓臨界位準(VTPNTE)。 In such embodiments, because the large electric field from the control gate spans the nitridation The tunneling oxide (due to the relatively high dielectric constant of the nitride tunneling oxide) is relatively less reduced, so the charge trapping layer 518 will charge faster during that stylization/erasing than that thickness. Pure oxide tunneling layer. These embodiments allow the semiconductor-oxide-nitride-oxide-semiconductor type device 1100 to operate with a reduced stylized/erase voltage while still achieving the same conventional semiconductor-oxide-nitride-oxidation Stylized/erased voltage critical level (VTPNTE) for semiconductor-semiconductor components.
在一些實施例中,該氮化氧化物穿隧層具有相同於運用純氧化物穿隧層之傳統半導體-氧化物-氮化物-氧化物-半導體型元件的物理厚度,以改善用於降低之操作電壓的穿隧電流而不犧牲電荷保留。在某些實施例中,該半導體-氧化物-氮化物-氧化物-半導體型記憶體元件1100運用具有一介於1.5奈米至3.0奈米間厚度之氮化氧化物穿隧層1116,且更佳地介於1.9奈米至2.2奈米之間。在圖11B所示一特定實施例中,該氮化氧化物穿隧層1116包含接近該通道區域1112處之具有大約小於約5x1021氮原子/立方公分氮濃度的第一區域1116A及接近該多層電荷捕獲層1118處之具有至少5x1021氮原子/立方公分氮濃度的第二區域1116B。在圖11B所示一實施例中,該氮化氧化物穿隧層1116的第一和第二區域各包括大約不大於該穿隧層厚度的25%。 In some embodiments, the nitride oxide tunneling layer has the same physical thickness as a conventional semiconductor-oxide-nitride-oxide-semiconductor type component using a pure oxide tunneling layer to improve the reduction. The tunneling current of the operating voltage without sacrificing charge retention. In some embodiments, the semiconductor-oxide-nitride-oxide-semiconductor type memory device 1100 utilizes a nitride oxide tunneling layer 1116 having a thickness between 1.5 nm and 3.0 nm, and more The good land is between 1.9 nm and 2.2 nm. In a particular embodiment illustrated in FIG. 11B, the nitride oxide tunneling layer 1116 includes a first region 1116A near the channel region 1112 having a nitrogen concentration of less than about 5 x 10 21 nitrogen atoms per cubic centimeter and is adjacent to the multilayer A second region 1116B having a nitrogen concentration of at least 5 x 10 21 nitrogen atoms per cubic centimeter at the charge trap layer 1118. In an embodiment illustrated in FIG. 11B, the first and second regions of the nitride oxide tunneling layer 1116 each comprise no more than about 25% of the thickness of the tunneling layer.
在一進一步實施例中,該多層電荷捕獲層1118包含具有不同之矽、氧和氮組成成分之至少二氮化物層。在一實施例中,該多層電荷捕獲區域包含一實際上無陷阱之富矽又富氧氮化物的富氧第一層1118A,以及一含密集陷阱之富矽、富氮又貧氧氮化物的貧氧第二層1118B。已發現到該富氧第一層1118A降低程式化及抹除後之電荷損失率,其係在該保留模 式中顯現一小電壓偏移。該貧氧第二層1118B改善該速度並增加程式化和抹除電壓間之初始差異,卻未危及使用該矽-氧化物-氮氧化物-氧化物-矽結構實施例所製造之記憶體元件的電荷損失率,因而延伸該元件操作壽命。 In a further embodiment, the multilayer charge trap layer 1118 comprises at least a dinitride layer having a different composition of germanium, oxygen, and nitrogen. In one embodiment, the multilayer charge trapping region comprises an oxygen-free first layer 1118A which is substantially trap-free and rich in oxynitride, and a cerium-rich, nitrogen-rich and oxygen-depleted nitride containing dense traps. Oxygen-poor second layer 1118B. It has been found that the oxygen-rich first layer 1118A reduces the charge loss rate after stylization and erasing, which is in the retention mode. A small voltage shift appears in the equation. The oxygen-depleted second layer 1118B improves the speed and increases the initial difference between the stylized and erase voltages without jeopardizing the memory components fabricated using the bismuth-oxide-oxynitride-oxide-germanium structure embodiment. The rate of charge loss, thus extending the operational life of the component.
在另一實施例中,該多層電荷捕獲層1118係一分離式多層電荷捕獲層,進一步內含具有分開該富氧第一層1118A和該貧氧第二層1118B之氧化物的中間氧化物或抗穿隧層1118C。在該記憶體元件1100抹除期間,電洞往該阻擋層1120漂移,但是多數捕獲電洞電荷形成於該貧氧第二層1118B中。在程式化後,電子電荷累積於該貧氧第二層1118B界面處,因而在該富氧第一層1118A下方界面處有較少電荷累積。更進一步,因為該抗穿隧層1118C之故,該貧氧第二層1118B中捕獲之電子電荷穿隧可能性實際上係降低。這個可產生較該些傳統記憶體元件低的漏電結果。 In another embodiment, the multilayer charge trap layer 1118 is a separate multilayer charge trap layer further comprising an intermediate oxide having an oxide separating the oxygen-rich first layer 1118A and the oxygen-lean second layer 1118B or Anti-pass tunnel layer 1118C. During the erasing of the memory element 1100, the holes drift toward the barrier layer 1120, but most of the trap hole charges are formed in the oxygen-depleted second layer 1118B. After stylization, electron charge accumulates at the oxygen-depleted second layer 1118B interface, thereby accumulating less charge at the interface below the oxygen-rich first layer 1118A. Further, because of the anti-tunneling layer 1118C, the electron charge tunneling probability trapped in the oxygen-depleted second layer 1118B is actually reduced. This can result in lower leakage results than these conventional memory components.
儘管上面顯示及描述有二氮化物層,也就是一第一和一第二層,然本發明未限定於此,且該多層電荷捕獲層1118可包含一些氧化物、氮化物或氮氧化物層n,其中任一者或全部可具有不同氧、氮及/或矽化學計量組成成分。尤其,各具有不同化學計量組成成分的高達5,甚至更多氮化物層之多層電荷儲存結構被納入考量。這些層中的至少一些與其它層會由一或更多相當薄的氧化物層所分開。然而,如那些熟知此項技術之人士所理解地,大體上可期待儘可能運用最少層來完成一要求結果,以降低生產該元件所需製程步驟,並藉此提供一較簡單且更堅固製程。甚至,儘可能運用最少層又產生較高良率,因為它係較易於控制該較少層化學計量組成成分和尺寸之故。 Although a dinitride layer is shown and described above, that is, a first and a second layer, the invention is not limited thereto, and the multilayer charge trap layer 1118 may comprise some oxide, nitride or oxynitride layer. n, any or all of which may have different oxygen, nitrogen and/or bismuth stoichiometric compositions. In particular, multilayer charge storage structures of up to 5 or even more nitride layers each having a different stoichiometric composition are taken into account. At least some of these layers are separated from the other layers by one or more relatively thin oxide layers. However, as will be appreciated by those skilled in the art, it is generally contemplated that a minimum number of layers can be utilized to accomplish a desired result to reduce the number of process steps required to produce the component and thereby provide a simpler and more robust process. . Even using as few layers as possible produces higher yields because it is easier to control the lesser stoichiometric composition and size.
在另一實施例中,該阻擋層1120包括係一較沉積時相對地 更密集之高溫氧化物(HTO)。一密集高溫氧化物具有一較低終端氫或氫氧鍵分數。例如,自一高溫氧化物中移除該氫或水具有增加該薄膜密度並改善該高溫氧化物品質的效應。該較高品質氧化物使該層在厚度上能被縮放。在一實施例中,沉積時之氫濃度係大於2.5x1020原子/立分公分並在該密集薄膜中降低至小於8.0x1019原子/立分公分。在一示範性實施例中,沉積時含一密集高溫氧化物之阻擋層1120的厚度係介於2.5奈米至10.0奈米之間,且因密集化作用而使各處更薄上10%至30%。 In another embodiment, the barrier layer 1120 includes a relatively high temperature oxide (HTO) that is relatively denser when deposited. A dense high temperature oxide has a lower terminal hydrogen or hydroxide bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x 10 20 atoms per centimeter and is reduced to less than 8.0 x 10 19 atoms per centimeter in the dense film. In an exemplary embodiment, the thickness of the barrier layer 1120 containing a dense high temperature oxide during deposition is between 2.5 nm and 10.0 nm, and is 10% thinner to 10% due to densification. 30%.
在一替代性實施例中,進一步改變該阻擋層1120以整合氮。在一這類實施例中,該氮係以橫跨該阻擋層1120厚度的氧化物-氮化物-氧化物堆疊形式進行整合。取代該傳統純氧阻檔層之這類三明治結構有利地降低該通道區域1112及控制閘極1114間之整個堆疊的有效氧化物厚度並致能調整傳導帶位移以降低載子回流。該氧化物-氮化物-氧化物堆疊阻擋層1120接著可與該氮化氧化物穿隧層1116以及包括一富氧第一層1118A、一貧氧第二層1118B和一抗穿隧層1118C之分離式多層電荷捕獲層1118進行整合。 In an alternative embodiment, the barrier layer 1120 is further altered to incorporate nitrogen. In one such embodiment, the nitrogen is integrated in an oxide-nitride-oxide stack across the thickness of the barrier layer 1120. Such a sandwich structure that replaces the conventional pure oxygen barrier layer advantageously reduces the effective oxide thickness of the entire stack between the channel region 1112 and the control gate 1114 and enables adjustment of the conduction band displacement to reduce carrier reflow. The oxide-nitride-oxide stack barrier layer 1120 can then be coupled to the nitride oxide tunneling layer 1116 and include an oxygen-rich first layer 1118A, an oxygen-poor second layer 1118B, and an anti-tunneling layer 1118C. The split multilayer charge trap layer 1118 is integrated.
現在根據一實施例參考圖12流程圖來說明一記憶體元件之形成或製造方法,該元件包含一氮化氧化物穿隧層、一分離式多層電荷捕獲層及一密集阻擋層。 A method of forming or fabricating a memory device including a nitride oxide tunneling layer, a separate multilayer charge trapping layer, and a dense barrier layer will now be described with reference to the flow chart of FIG. 12 in accordance with an embodiment.
參考至圖12,該方法始於具有在一基板中或上形成一含多晶矽通道區域之操作1200,該通道區域電性連接該基板內之源極區域和汲極區域。如上所述地,該通道區域可包括P型或N型摻雜物雜質原子。在一特定實施例中,該通道區域係P型摻雜,且在一替代性實施例中,該通 道區域係N型摻雜。該源極和汲極區域可摻雜有與該通道區域相反類型之摻雜物雜質原子。例如,根據一特定實施例,該源極和汲極區域係N型摻雜,內含具有5x1016-5x1019原子/立方公分範圍濃度之磷或砷摻雜區域,而該通道區域係P型摻雜,內含具有1x1015-1x1019原子/立方公分範圍濃度之硼。 Referring to Figure 12, the method begins with an operation 1200 having a polysilicon-containing channel region formed in or on a substrate that is electrically coupled to a source region and a drain region within the substrate. As described above, the channel region may include P-type or N-type dopant impurity atoms. In a particular embodiment, the channel region is P-type doped, and in an alternative embodiment, the channel region is N-doped. The source and drain regions may be doped with dopant impurity atoms of the opposite type to the channel region. For example, in accordance with a particular embodiment, the source and drain regions are N-doped with a phosphorus or arsenic doped region having a concentration ranging from 5 x 10 16 to 5 x 10 19 atoms per cubic centimeter, and the channel region is P-type. The doping contains boron having a concentration ranging from 1 x 10 15 to 1 x 10 19 atoms/cm 3 .
在操作1202,包括一氮化氧化物之穿隧層係形成於該基板上之通道區域上方。大體上,包括一氮化氧化物之穿隧層該熱氧化物係藉由熱氧化該基板以形成一氧化物薄膜,再氮化該氧化物薄膜而成。因為與該基板的一良好界面係需要的,故該熱氧化物形成前可先形成一化學氧化物。在一特定實施例中,一化學氧化物係利用臭氧水來生長,以形成具有一大約介於1.0奈米厚度之化學氧化物層。該熱氧化物接著被形成達一介於1.0奈米至1.8奈米間之厚度。較佳地,該氧化物係為相當低的密度,有助於後續整合具有一顯著重量百比分的氮。然而,一薄膜密度太低會在該矽基板界面處產生太多氮。在一實施例中,一大氣壓力垂直熱反應器(VTR)被運用以在一介於680℃至800℃間之溫度下,例如氧氣(O2)、氧化亞氮(N2O)、氧化氮(NO)、臭氧(O3)及蒸汽(H2O)之氧化氣體存在時,生長該熱氧化物。依據所選取氧化劑,該氧化操作1001之持續時間可從3.5分鐘至20分鐘。在一大氣壓實施例中,在一介於700℃至750℃間之溫度,一介於7分鐘至20分鐘製程時間下,運用氧氣來形成一大約1.0奈米的二氧化矽薄膜。 At operation 1202, a tunneling layer comprising a nitrided oxide is formed over the channel region on the substrate. Generally, the tunneling layer including a nitride oxide is formed by thermally oxidizing the substrate to form an oxide film and then nitriding the oxide film. Because of a good interface with the substrate, a chemical oxide can be formed prior to the formation of the thermal oxide. In a particular embodiment, a chemical oxide is grown using ozone water to form a chemical oxide layer having a thickness of between about 1.0 nanometers. The thermal oxide is then formed to a thickness of between 1.0 nm and 1.8 nm. Preferably, the oxide is of a relatively low density to facilitate subsequent integration of nitrogen having a significant weight percentage. However, a film density that is too low will produce too much nitrogen at the interface of the germanium substrate. In one embodiment, an atmospheric pressure vertical thermal reactor (VTR) is employed at a temperature between 680 ° C and 800 ° C, such as oxygen (O 2 ), nitrous oxide (N 2 O), nitrogen oxides. When the oxidizing gas of (NO), ozone (O 3 ), and steam (H 2 O) is present, the thermal oxide is grown. The duration of the oxidation operation 1001 can range from 3.5 minutes to 20 minutes depending on the selected oxidant. In the atmospheric pressure embodiment, oxygen is used to form a film of about 1.0 nm of cerium oxide at a temperature between 700 ° C and 750 ° C for a period of from 7 minutes to 20 minutes.
在另一實施例中,該熱氧化物係利用例如市場上可由美加州斯科特山谷市的AVIZA科技公司取得之先進垂直處理器(AVP)之次大氣壓處理器來形成之。該先進垂直處理器可被操作於上述一垂直熱反應器實施例之溫度範圍內及一介於1托耳(T)至大氣壓力間之壓力下。依據該操作壓 力,用以形成介於大約1.0奈米至1.8奈米厚度間之熱二氧化矽薄膜的氧化時間可如一熟知此項技術之人士所可能決定地延長多達近乎一小時。 In another embodiment, the thermal oxide is formed using, for example, a sub-atmospheric processor of an Advanced Vertical Processor (AVP) commercially available from AVIZA Technologies, Inc. of Scott Valley, California. The advanced vertical processor can be operated within the temperature range of the above-described vertical thermal reactor embodiment and at a pressure between 1 Torr (T) and atmospheric pressure. According to the operation pressure The oxidization time of the hot cerium oxide film formed to form a thickness between about 1.0 nm and 1.8 nm can be extended by up to nearly one hour as may be determined by those skilled in the art.
接著,一氮回火被執行以氮化該熱氧化物層來增加該介電係數(K)並降低該熱氧化物層的固定電荷。在一實施例中,該氮回火運用氮氣(N2)或例如氨(NH3)之氫化氮來源。在另一實施例中,該氮回火運用例如氘化氨(DH3)之氘化氮來源。在一特定實施例中,該氮回火係執行於一介於700°C至850℃之間的溫度下,持續3.5分鐘至30分鐘的時間。在另一特定實施例中,該氮回火係執行於一介於725℃至775℃間的溫度下,持續3.5分鐘至30分鐘間的時間。在一這類實施例中,氨被引進於一介於725℃至775℃之間溫度的大氣壓力下,持續3.5分鐘至30分鐘。在一替代性實施例中,一次大氣壓的氨回火係執行於例如該先進垂直處理器之處理器中,以800℃至900℃進行5分鐘至30分鐘。在又一實施例中,一般稱之為氮電漿及熱回火結合者被執行。 Next, a nitrogen tempering is performed to nitride the thermal oxide layer to increase the dielectric constant (K) and reduce the fixed charge of the thermal oxide layer. In one embodiment, the nitrogen use tempering nitrogen (N 2) or ammonia, for example, (NH 3) hydrogenation of a nitrogen source. In another embodiment, the use of nitrogen tempering nitrogen sources such as deuterium, deuterated ammonia (DH 3) of. In a particular embodiment, the nitrogen tempering is performed at a temperature between 700 ° C and 850 ° C for a period of time ranging from 3.5 minutes to 30 minutes. In another particular embodiment, the nitrogen tempering is performed at a temperature between 725 ° C and 775 ° C for a period of between 3.5 minutes and 30 minutes. In one such embodiment, ammonia is introduced at an atmospheric pressure between 725 ° C and 775 ° C for between 3.5 minutes and 30 minutes. In an alternative embodiment, the primary atmospheric ammonia tempering is performed in a processor such as the advanced vertical processor, at 800 ° C to 900 ° C for 5 minutes to 30 minutes. In yet another embodiment, a combination of nitrogen plasma and thermal tempering is generally performed.
選擇性地,形成該氮化氧化物穿隧層進一步包含藉由將該基板曝露於氧氣中而再氧化該氧化物薄膜,且藉由將該基板曝露於氧化氮中而再氮化該再氧化之氮化氧化物薄膜。在一實施例中,在該再氧化製程期間,一氧化氣體被熱裂解以在接近該薄膜表面處提供氧基。該些氧基消除氮及氫捕獲電荷。該再氧化操作也在該基板和該穿隧層之間的界面處生長一額外氧化物以提供該基板和該穿隧層內之氮濃度間的物理位移。例如,參考回至圖11A和11B,在一實施例中,該穿隧層1116A內的氮濃度顯著地係小於該穿隧層1116B內的氮濃度。來自該基板界面之氮位移改善一半導體-氧化物-氮化物-氧化物-半導體型元件之保留。在一實施例中,該基板 界面所生長之氧化物厚度係限定為1.2奈米至3.0奈米之間。在該再氧化製程中,選取條件以使得操作1001所形成之熱氧化物厚度阻止超過一大約3.0奈米厚度的氧化作用,其可提供一缺乏任何有利氮濃度的穿隧層。一般稱之為氧化劑者可被運用於該再氧化製程,例如,氧化氮、氧化亞氮、氧氣、臭氧及蒸汽,但不限於此。任何這類氧化劑可利用操作於800℃至900℃間之溫度的已知熱處理器來引進。依據該些操作參數,再氧化時間可介於5分鐘至40分鐘之間的任一時間點。在一特定實施例中,氧化氮被運用於一大氣壓熔爐內,操作於一介於800℃至850℃間之溫度下,持續約15分鐘製程時間以在一矽基板上形成大約2.2奈米厚度的氮化氧化物薄膜。在一這類實施例中,該2.2奈米厚度的再氧化薄膜在接近該矽基板界面處形成一介於0.5奈米至0.8奈米間的區域,該區域具有小於5x1021氮原子/立方公分的氮濃度。 Optionally, forming the nitride oxide tunneling layer further comprises reoxidizing the oxide film by exposing the substrate to oxygen, and re-nitriding the reoxidation by exposing the substrate to nitrogen oxide A nitrided oxide film. In one embodiment, during the reoxidation process, the oxidizing gas is thermally cracked to provide an oxy group near the surface of the film. These oxy groups eliminate nitrogen and hydrogen trap charges. The reoxidation operation also grows an additional oxide at the interface between the substrate and the tunneling layer to provide a physical displacement between the substrate and the nitrogen concentration within the tunneling layer. For example, referring back to FIGS. 11A and 11B, in one embodiment, the concentration of nitrogen within the tunneling layer 1116A is significantly less than the concentration of nitrogen within the tunneling layer 1116B. The nitrogen displacement from the substrate interface improves the retention of a semiconductor-oxide-nitride-oxide-semiconductor type element. In one embodiment, the thickness of the oxide grown at the substrate interface is defined to be between 1.2 nm and 3.0 nm. In the reoxidation process, conditions are selected such that the thickness of the thermal oxide formed by operation 1001 prevents oxidation of more than about 3.0 nanometers thick, which provides a tunneling layer that lacks any favorable nitrogen concentration. Those generally referred to as oxidants can be used in the reoxidation process, for example, nitrogen oxides, nitrous oxide, oxygen, ozone, and steam, but are not limited thereto. Any such oxidant can be introduced using a known thermal processor operating at temperatures between 800 °C and 900 °C. Depending on the operating parameters, the reoxidation time can be anywhere between 5 minutes and 40 minutes. In a particular embodiment, the nitrogen oxide is used in a one-pressure furnace operating at a temperature between 800 ° C and 850 ° C for a period of about 15 minutes to form a thickness of about 2.2 nm on a substrate. A nitride oxide film. In one such embodiment, the 2.2 nm thick reoxidized film forms a region between 0.5 nm and 0.8 nm near the interface of the germanium substrate, the region having less than 5 x 10 21 nitrogen atoms per cubic centimeter. Nitrogen concentration.
接在該再氧化操作之後,一第二氮回火被執行以再氮化該穿隧層。一第二氮回火被運用以進一步增加該穿隧層之介電係數而沒有在該基板界面處不利地引進大量氫或氮陷阱。在一實施例中,該第二氮回火操作1006係利用與該初始或第一氮回火一模一樣的條件來執行之。在另一實施例中,該第二氮回火之再氮化操作係以較該第一氮回火高之溫度來執行以引進額外氮至該穿隧層中。在一實施例中,該氮回火運用例如氨之氫化氮來源。在另一實施例中,該氮回火運用例如氘化氨之氘化氮來源。在一特定實施例中,該氮回火操作1006於大氣壓力下,以一介於750℃至950°C間之溫度,執行一介於3.5分鐘至30分鐘間之製程時間來運用氨。在另一特定實施例中,該氮回火係執行於800℃至850℃間的大氣壓力下,持 續5分鐘至10分鐘。 After the reoxidation operation, a second nitrogen tempering is performed to re-nitridate the tunneling layer. A second nitrogen tempering is employed to further increase the dielectric constant of the tunneling layer without introducing a significant amount of hydrogen or nitrogen traps at the substrate interface. In one embodiment, the second nitrogen tempering operation 1006 is performed using the same conditions as the initial or first nitrogen tempering. In another embodiment, the second nitrogen tempering re-nitriding operation is performed at a higher temperature than the first nitrogen tempering to introduce additional nitrogen into the tunneling layer. In one embodiment, the nitrogen tempering utilizes a source of hydrogenated nitrogen such as ammonia. In another embodiment, the nitrogen tempering utilizes a source of deuterated nitrogen such as deuterated ammonia. In a particular embodiment, the nitrogen tempering operation 1006 utilizes ammonia at a temperature between 750 ° C and 950 ° C at a temperature between 750 ° C and 950 ° C for a process time between 3.5 minutes and 30 minutes. In another specific embodiment, the nitrogen tempering is performed at atmospheric pressure between 800 ° C and 850 ° C. Continue for 5 minutes to 10 minutes.
如所述地,操作1202與該再氧化作用和再氮化作用提供二氧化操作及二氮化操作。所述之重複性氧化及氮化方案使該穿隧層內的氮濃度可專門量身定製以得到程式化電壓的降低或程式化速度的增加與一半導體-氧化物-氮化物-氧化物-半導體型元件記憶體保留的增加兩者。該氧化、氮化、再氧化、再氮化操作的連續性質讓一小於3.0奈米厚度穿隧層內的氮濃度可估計,同時提供於該穿隧層及該基板間的界面具有非常少的氮和氫陷阱。該獨立的氧化、氮化、再氧化、再氮化操作讓該第一和第二氧化作用及第一和第二氮化作用可依獨立設計條件來執行以提供更大自由度來量身定製一穿隧層內的氮濃度變化曲線。在一有利的實施例中,操作係連續地執行於單一熱處理器內,而沒有在各操作間將該基板自該處理器中移除。在一這類實施例中,製程壓力係維持在大氣壓力下。該第一氧化操作係執行於一介於700℃至750℃間之溫度下。氣體流動接著如指定般地改變,以在一介於725℃至775℃間之溫度下執行該氮回火操作。該熔爐溫度接著被陡升至800℃至850℃之間,且氣體流動再被改變以執行該再氧化操作。最後,在該熔爐保持於800℃至850℃之間時,氣體流動再被改變以執行該第二氮回火操作。 As described, operation 1202 and the reoxidation and renitridation provide a dioxide operation and a diazotization operation. The repetitive oxidation and nitridation scheme allows the concentration of nitrogen in the tunneling layer to be tailored to achieve a reduction in stylized voltage or an increase in stylized speed with a semiconductor-oxide-nitride-oxide - Increase in memory retention of semiconductor type components. The continuous nature of the oxidation, nitridation, reoxidation, and re-nitridation operations allows for a nitrogen concentration in the tunneling layer of less than 3.0 nm thickness to be estimated, while providing very little interface between the tunneling layer and the substrate. Nitrogen and hydrogen traps. The separate oxidation, nitridation, reoxidation, and re-nitridation operations allow the first and second oxidations and the first and second nitridation to be performed in accordance with independent design conditions to provide greater freedom A curve of nitrogen concentration in a tunnel is formed. In an advantageous embodiment, the operation is continuously performed within a single thermal processor without removing the substrate from the processor between operations. In one such embodiment, the process pressure is maintained at atmospheric pressure. The first oxidation operation is performed at a temperature between 700 ° C and 750 ° C. The gas flow is then varied as specified to perform the nitrogen tempering operation at a temperature between 725 ° C and 775 ° C. The furnace temperature is then ramped up to between 800 ° C and 850 ° C and the gas flow is changed to perform the reoxidation operation. Finally, as the furnace is maintained between 800 ° C and 850 ° C, the gas flow is again changed to perform the second nitrogen tempering operation.
在操作1204中,一多層電荷捕獲層係形成於該氮化氧化物穿隧層上。大體上,該多層電荷捕獲層包含一實際上無陷阱之富氧第一層以及一陷阱密集之貧氧第二層。在某些實施例中,該多層電荷捕獲層係一分離式多層電荷捕獲層,進一步內含具有將該第一層和該第二層分開之氧化物的抗穿隧層。 In operation 1204, a multilayer charge trapping layer is formed over the nitride oxide tunneling layer. In general, the multilayer charge trap layer comprises a substantially trap free oxygen-rich first layer and a trap-dense oxygen-lean second layer. In certain embodiments, the multilayer charge trapping layer is a separate multilayer charge trapping layer further comprising an anti-tunneling layer having an oxide separating the first layer from the second layer.
在一特定實施例中,該富氧第一層係以一低壓化學氣相沉積製程,使用例如矽烷(SiH4)、氯矽烷(SiH3Cl)、二氯矽烷或DCS(SiH2Cl2)、四氯矽烷(SiCl4)或雙三級丁氨基矽烷(BTBAS)類之矽來源,例如氮氣(H2)、氨(NH3)、三氧化氮(NO3)或氧化亞氮(N2O)類之氮來源及例如氧氣(O2)或氧化亞氮(N2O)類之含氧氣體來形成或沉積之。例如,該富氧第一層可藉由將該基板放置於一沉積腔室中並引進包含氧化亞氮、氨及二氯矽烷之製程氣體,同時,維持該腔室在大約自5毫托耳(mT)至500毫托耳壓力下並維持該基板在一介於大約700℃至850℃之溫度,且在一些實施例中至少約為760攝氏度之溫度下,持續一段大約自2.5分鐘至20分鐘的時間而被沉積於該第一氘化層上方。尤其,該製程氣體可包含具有以約從8:1至1:8比值混合氧化亞氮和氨之第一氣體混合物,及具有以約從1:7至7:1比值混合二氯矽烷和氨之第二氣體混合物,且可以大約每分鐘5至200標準立方公分(sccm)範圍之流速來引進。已發現到在這些條件下所產生或沉積之氮氧化物層產生一富矽又富氧第一層。 In a particular embodiment, the oxygen-enriched first layer is subjected to a low pressure chemical vapor deposition process using, for example, decane (SiH 4 ), chlorodecane (SiH 3 Cl), dichloromethane or DCS (SiH 2 Cl 2 ). a source of ruthenium tetrachloromethane (SiCl 4 ) or a double tertiary butylamino decane (BTBAS) such as nitrogen (H 2 ), ammonia (NH 3 ), nitrogen trioxide (NO 3 ) or nitrous oxide (N 2 ) A nitrogen source of the class O) and an oxygen-containing gas such as oxygen (O 2 ) or nitrous oxide (N 2 O) are formed or deposited. For example, the oxygen-enriched first layer can be maintained by placing the substrate in a deposition chamber and introducing a process gas comprising nitrous oxide, ammonia, and methylene chloride, while maintaining the chamber at about 5 mTorr. (mT) to 500 mTorr and maintaining the substrate at a temperature between about 700 ° C and 850 ° C, and in some embodiments at least about 760 ° C for a period of about 2.5 minutes to 20 minutes. The time is deposited above the first deuterated layer. In particular, the process gas may comprise a first gas mixture having a mixture of nitrous oxide and ammonia in a ratio of from about 8:1 to 1:8, and having a mixture of dichloromethane and ammonia at a ratio of from about 1:7 to about 7:1. The second gas mixture can be introduced at a flow rate in the range of about 5 to 200 standard cubic centimeters (sccm) per minute. It has been discovered that the oxynitride layer produced or deposited under these conditions produces a ruthenium rich and oxygen rich first layer.
替代性地,可使用已由氘取代氫的氣體,包含例如由氘化氨(ND3)替代氨。由氘替代氫有利地鈍化在該矽-氧化物界面處的矽懸空鍵,藉此增加該些元件之NBTI(負偏壓溫度不穩定性)壽命。 Alternatively, a gas that has been replaced by deuterium may be used, including, for example, ammonia instead of ammonia (ND 3 ). The substitution of hydrogen facilitates the passivation of the ruthenium dangling bonds at the ruthenium-oxide interface, thereby increasing the NBTI (negative bias temperature instability) lifetime of the components.
一抗穿隧層接著被形成或沉積於該富氧第一層之表面上。該抗穿隧層可經由包含一電漿氧化製程、現場蒸汽產生技術(ISSG)或一基氧化製程之任何合適手段來形成或沉積之。在一實施例中,該基氧化製程涉及將氫氣(H2)及氧氣(O2)流入一批次處理工具或熔爐中,以經由氧化耗用一部分富氧第一層來造成該抗穿隧層之生長。 A primary tunneling layer is then formed or deposited on the surface of the oxygen-rich first layer. The anti-tunneling layer can be formed or deposited via any suitable means including a plasma oxidation process, an on-site steam generation technique (ISSG) or a base oxidation process. In one embodiment, the base oxidation process involves flowing hydrogen (H 2 ) and oxygen (O 2 ) into a batch of processing tool or furnace to consume a portion of the oxygen-rich first layer via oxidation to cause the tunneling resistance. The growth of the layer.
該多層電荷捕獲區域之貧氧第二層係接著形成於該抗穿隧層(1506)之表面上。該貧氧第二層可以一化學氣相沉積製程,使用包含氧化亞氮、氨及二氯矽烷之製程氣體,於大約自5毫托耳至500毫托耳腔室壓力下,並於大約700℃至850℃,且在某些實施例中至少約為760℃之基板溫度下,持續一段大約自2.5分鐘至20分鐘時間,而被沉積於該抗穿隧層上方。尤其,該製程氣體可包含以約從8:1至1:8比值混合氧化亞氮和氨之第一氣體混合物及以約從1:7至7:1比值混合二氯矽烷和氨之第二氣體混合物,且可以大約每分鐘5至20標準立方公分之流速來引進。已發現到在這些條件下所產生或沉積之氮氧化物層產生一富矽、富氮又貧氧第二層。 An oxygen-depleted second layer of the multilayer charge trapping region is then formed on the surface of the anti-tunneling layer (1506). The oxygen-depleted second layer can be subjected to a chemical vapor deposition process using a process gas comprising nitrous oxide, ammonia and dichloromethane at a pressure of from about 5 mTorr to 500 mTorr, and at about 700 From °C to 850 ° C, and in some embodiments at a substrate temperature of at least about 760 ° C, for a period of time from about 2.5 minutes to 20 minutes, is deposited over the anti-tunneling layer. In particular, the process gas may comprise a first gas mixture of nitrous oxide and ammonia mixed at a ratio of from about 8:1 to 1:8 and a second mixture of dichloromethane and ammonia at a ratio of from about 1:7 to 7:1. The gas mixture can be introduced at a flow rate of about 5 to 20 standard cubic centimeters per minute. It has been discovered that the oxynitride layer produced or deposited under these conditions produces a ruthenium-rich, nitrogen-rich, and oxygen-depleted second layer.
在一些實施例中,該貧氧第二層可以一化學氣相沉積製程,使用包含以約從1:7至7:1比值混合雙三級丁氨基矽烷和氨(NH3)之製程氣體,來沉積於該抗穿隧層上方,以進一步包含一所選碳濃度而增加其中之陷阱數量。在該第二氮氧化物層中之所選碳濃度可包含大約從5%至15%之碳濃度。 In some embodiments, the oxygen-depleted second layer can be subjected to a chemical vapor deposition process using a process gas comprising a mixture of two tertiary butyl amino decane and ammonia (NH 3 ) at a ratio of from about 1:7 to about 7:1. Deposited over the anti-tunneling layer to further include a selected carbon concentration to increase the number of traps therein. The selected carbon concentration in the second oxynitride layer can comprise a carbon concentration of from about 5% to 15%.
接著,在操作1206,一阻擋層係形成該多層電荷捕獲層或該分離式多層電荷捕獲層上。該阻擋層可經由包含例如熱氧化作用或具有化學氣相沉積技術之沉積作用的任何合適手段來形成之。在一較佳實施例中,該阻擋層係以一高溫化學氣相沉積製程來形成之。大體上,該沉積製程涉及在大約從50毫托耳至1000毫托耳壓力下,提供例如矽烷、二氯矽烷或四氯矽烷類之矽來源及例如氧氣或氧化亞氮類之含氧氣體於一沉積腔室內,持續一段約自10分鐘至120分鐘的時間,同時,維持該基板在650℃至850℃溫度下。較佳地,該阻擋層係以相同於形成該多層電荷捕獲層所運 用之製程工具來依序沉積之。更佳地,該阻擋層係以相同於該多層電荷捕獲層和該穿隧層兩者之製程工具來形成,且未在各操作間移除該基板。 Next, at operation 1206, a barrier layer is formed over the multilayer charge trap layer or the separate multilayer charge trap layer. The barrier layer can be formed via any suitable means including, for example, thermal oxidation or deposition with chemical vapor deposition techniques. In a preferred embodiment, the barrier layer is formed by a high temperature chemical vapor deposition process. In general, the deposition process involves providing a source of ruthenium such as decane, dichlorodecane or tetrachloromethane and an oxygen-containing gas such as oxygen or nitrous oxide at a pressure of from about 50 mTorr to about 1000 mTorr. In a deposition chamber, the period of time is from about 10 minutes to 120 minutes while maintaining the substrate at a temperature of 650 ° C to 850 ° C. Preferably, the barrier layer is transported in the same manner as the multilayer charge trapping layer. Use process tools to deposit them sequentially. More preferably, the barrier layer is formed by a process tool that is identical to both the multilayer charge trap layer and the tunneling layer, and the substrate is not removed between operations.
在圖12所述實施例中,操作1206所沉積之阻擋層係於操作1208進行再氧化以密集化該阻擋層氧化物。如在此之其它處所述地,操作1208可進一步氧化或再氧化該多層電荷捕獲層1116之第二區域1116B的一部分以得到例如圖8A所述之分級帶隙。大體上,該再氧化作用可執行於例如氧氣(O2)、氧化亞氮(N2O)、氧化氮(NO)、臭氧(O3)及蒸汽(H2O)之氧化氣體存在時。在一實施例中,該再氧化製程可以較該阻擋層沉積溫度高之溫度來執行之。在該阻擋氧化物沉積後之再氧化作用使氧化劑擴散更受到控制而可控制地氧化或再氧化一部分第二區域1116B。在一特別具有利的實施例中,一稀釋濕式氧化作用被運用。該稀釋濕式氧化作用不同於一濕式氧化作用之處在於氫氧氣比值係介於1至1.3之間。在一特定實施例中,具有一約1.2氫氧氣比值的稀釋氧化作用係執行於一介於800℃至900℃之間的溫度下。 In the embodiment illustrated in FIG. 12, the barrier layer deposited by operation 1206 is subjected to operation 1208 for reoxidation to densify the barrier oxide. Operation 1208 can further oxidize or reoxidize a portion of second region 1116B of the plurality of charge trapping layers 1116 to obtain a graded band gap such as that depicted in FIG. 8A, as described elsewhere herein. In general, the reoxidation can be performed in the presence of an oxidizing gas such as oxygen (O 2 ), nitrous oxide (N 2 O), nitrogen oxide (NO), ozone (O 3 ), and steam (H 2 O). In one embodiment, the reoxidation process can be performed at a temperature that is higher than the barrier layer deposition temperature. The reoxidation after deposition of the barrier oxide causes the oxidant diffusion to be more controlled to controllably oxidize or reoxidize a portion of the second region 1116B. In a particularly advantageous embodiment, a dilute wet oxidation is utilized. The dilution wet oxidation differs from a wet oxidation in that the hydrogen to oxygen ratio is between 1 and 1.3. In a particular embodiment, the dilute oxidation having a hydrogen to oxygen ratio of about 1.2 is carried out at a temperature between 800 ° C and 900 ° C.
在一進一步實施例中,該稀釋氧化作用持續時間足以在一矽基板上生長出介於5.0奈米至12.5奈米的二氧化矽。在一這類實施例中,該持續時間係足以在一矽基板上生長出一大約10奈米至1.1奈米的二氧化矽層。這類稀釋氧化製程用以再氧化該沉積阻擋層氧化物且可進一步氧化或再氧化一部分電荷捕獲層以給予如圖8A或8B所述之傳導帶結構。 In a further embodiment, the dilution oxidation is for a duration sufficient to grow cerium oxide between 5.0 nm and 12.5 nm on a substrate. In one such embodiment, the duration is sufficient to grow a layer of ceria having a thickness of from about 10 nm to about 1.1 nm on a substrate. Such a dilute oxidation process is used to reoxidize the deposition barrier oxide and may further oxidize or reoxidize a portion of the charge trap layer to impart a conduction band structure as described in Figure 8A or 8B.
在另一實施例中,該再氧化操作1208可進一步用以在與該半導體-氧化物-氮化物-氧化物-半導體型元件相同基板上之非半導體-氧化物-氮化物-氧化物-半導體型元件區域中形成例如用於一互補式金屬氧化物 半導體(CMOS)場效電晶體(FET)的閘極氧化物。在另一實施例中,該再氧化操作1208可進一步用以擴散氘至該半導體-氧化物-氮化物-氧化物-半導體型元件之多層電荷捕獲層或阻擋層各部分中。 In another embodiment, the reoxidation operation 1208 can be further utilized for non-semiconductor-oxide-nitride-oxide-semiconductors on the same substrate as the semiconductor-oxide-nitride-oxide-semiconductor type device. Formed in the region of the element, for example for a complementary metal oxide A gate oxide of a semiconductor (CMOS) field effect transistor (FET). In another embodiment, the re-oxidation operation 1208 can be further used to diffuse germanium into portions of the multi-layer charge trapping layer or barrier layer of the semiconductor-oxide-nitride-oxide-semiconductor type device.
該方法接著可隨著例如圖11A之閘極層1114的閘極層形成而完成,且在某些實施例中,隨著例如圖11A所述閘極帽蓋層1125之閘極帽蓋層的形成而完成。隨著該閘極堆疊製造的完成,進一步製程可如習知技術中所知般地發生以結束該半導體-氧化物-氮化物-氧化物-半導體型元件300的製造。 The method can then be completed with the formation of a gate layer such as gate layer 1114 of FIG. 11A, and in some embodiments, with the gate cap layer of gate cap layer 1125 as described, for example, in FIG. 11A. Formed and completed. As the gate stack fabrication is completed, a further process can occur as is known in the art to terminate the fabrication of the semiconductor-oxide-nitride-oxide-semiconductor type component 300.
在另一觀點中,本揭示也指向包含形成於一基板表面上或上方通道之二或更多側上方之多層電荷捕獲層的多閘極或多閘極表面記憶體元件,及其製造方法。多閘極元件包含平面式及非平面式元件兩者。一平面式多閘極元件(未顯示)大體上包含一雙閘極平面式元件,其中,一些第一層被沉積以在接著形成之通道區域下方形成一第一閘極,且一些第二層被沉積於其上方以形成一第二閘極。一非平面式多閘極元件大體上包含形成於一基板表面上或上方並由一閘極環繞於三側或更多側之水平或垂直通道區域。 In another aspect, the present disclosure also refers to a multi-gate or multi-gate surface memory element comprising a plurality of charge trapping layers formed on two or more sides of a channel on or above a substrate surface, and a method of fabricating the same. Multiple gate elements include both planar and non-planar components. A planar multi-gate element (not shown) generally includes a dual gate planar element, wherein some first layers are deposited to form a first gate below the subsequently formed channel region, and some second layers It is deposited over it to form a second gate. A non-planar multi-gate element generally comprises a horizontal or vertical channel region formed on or above a substrate surface and surrounded by a gate on three or more sides.
圖13A和13B說明包含一多層電荷捕獲層之非平面式多閘極記憶體元件實施例。參考至圖13A,該記憶體元件1300,通常稱之為鰭狀物場效電晶體,包含由連接該記憶體元件之源極區域1308和汲極區域1310之基板1306上的一表面1304上方的含矽材料薄膜或薄層所形成之通道區域1302。該通道區域1302之三側係由形成該元件之閘極1312的鰭狀物所封閉。如同上述實施例,該通道區域1302可包括多晶矽或再結晶多晶矽以 形成一單結晶通道區域。選擇性地,在該通道區域1302包含一單結晶所在處,該通道區域可被形成以相對於該通道區域一長軸具有<100>表面結晶方位。 13A and 13B illustrate an embodiment of a non-planar multi-gate memory device comprising a plurality of charge trapping layers. Referring to Figure 13A, the memory component 1300, commonly referred to as a fin field effect transistor, includes a surface 1304 over a substrate 1306 connected to a source region 1308 and a drain region 1310 of the memory device. A channel region 1302 formed by a thin film or thin layer of germanium material. The three sides of the channel region 1302 are enclosed by fins that form the gate 1312 of the component. As with the above embodiments, the channel region 1302 may comprise polysilicon or recrystallized polysilicon to A single crystalline channel region is formed. Optionally, the channel region 1302 includes a single crystal where the channel region can be formed to have a <100> surface crystal orientation relative to a long axis of the channel region.
該閘極1312(自源極至汲極方向進行估測)之厚度決定該記憶體元件之有效通道長度。 The thickness of the gate 1312 (estimated from the source to the drain) determines the effective channel length of the memory element.
根據本揭示,圖13A之非平面式多閘極記憶體元件1300可包含一分離式電荷捕獲層、一氮化氧化物穿隧層及一密集阻擋層。圖13B係圖13A之非平面式記憶體元件之一部分剖面圖,包含一部分基板1306、通道區域1302及說明一多層電荷捕獲層1314、一氮化氧化物穿隧層1316和一密集阻擋層1318之閘極1312。該閘極1312進一步包含位在該阻擋層上方以形成該記憶體元件1300之控制閘極的金屬閘極層1320。在一些實施例中,一摻雜多晶矽代替金屬可被沉積,以取代金屬來提供一多晶矽閘極層。該通道區域1302及閘極1312可直接形成於基板1306上或該基板上或上方所形成之例如一埋入式氧化物層的絕緣或介電層1322上。 According to the present disclosure, the non-planar multi-gate memory device 1300 of FIG. 13A can include a separate charge trapping layer, a nitride oxide tunneling layer, and a dense barrier layer. 13B is a partial cross-sectional view of a non-planar memory device of FIG. 13A, including a portion of substrate 1306, channel region 1302, and illustrating a multilayer charge trap layer 1314, a nitride oxide tunneling layer 1316, and a dense barrier layer 1318. The gate 1312. The gate 1312 further includes a metal gate layer 1320 positioned over the barrier layer to form a control gate of the memory device 1300. In some embodiments, a doped polysilicon instead of a metal can be deposited to replace the metal to provide a polysilicon gate layer. The channel region 1302 and the gate 1312 can be formed directly on the substrate 1306 or on an insulating or dielectric layer 1322 such as a buried oxide layer formed on or over the substrate.
參考至圖13B,在例如所示那個的某些實施例中的穿隧層1316係一氮化氧化物穿隧層1316,且包含接近該通道區域1302處之具有一大約小於5x1021氮原子/立方公分氮濃度的第一區域1316A和接近該多層電荷捕獲層1314處之具有至少5x1021氮原子/立方公分氮濃度的第二區域1316B。在一實施例中,類似於圖11B所揭示那個,該氮化氧化物穿隧層1316的第一和第二區域各包括大約不大於該穿隧層厚度的25%。 Referring to Figure 13B, the tunneling layer 1316 in some embodiments, such as the one shown, is a nitrided oxide tunneling layer 1316 and includes a nitrogen atom of less than about 5 x 10 21 at the channel region 1302. A first region 1316A of cubic centimeter nitrogen concentration and a second region 1316B near the multilayer charge trapping layer 1314 having a nitrogen concentration of at least 5 x 10 21 nitrogen atoms per cubic centimeter. In one embodiment, similar to that disclosed in FIG. 11B, the first and second regions of the nitride oxide tunneling layer 1316 each comprise no more than about 25% of the thickness of the tunneling layer.
該多層電荷捕獲層1314包含接近該穿隧層1316之含氮化物的至少一富氧第一層1314A及位在該富氧第一層上方的貧氧第二層 1314B。大體上,該貧氧第二層1314B包含一富矽又貧氧氮化物層且包含分佈於該多層電荷捕獲層1314內的多數電荷陷阱,而該富氧第一層1314A包含一富氧氮化物或氮氧化矽且相對於該貧氧第二層係富氧的,以降低其中的電荷陷阱數量。富氧係意謂著在該含氧第一層1314A內的氧濃度係從大約15至40%,而在該貧氧第二層1314B內的氧濃度係小於5%。 The multilayer charge trap layer 1314 includes at least one oxygen-rich first layer 1314A adjacent to the tunneling layer 1316 and an oxygen-lean second layer positioned above the oxygen-rich first layer. 1314B. In general, the oxygen-depleted second layer 1314B includes a germanium-rich and oxygen-depleted nitride layer and includes a plurality of charge traps distributed within the multilayer charge trap layer 1314, and the oxygen-rich first layer 1314A comprises an oxygen-rich nitride. Or ruthenium oxynitride and oxygen-rich relative to the oxygen-depleted second layer to reduce the number of charge traps therein. Oxygen-enriched means that the oxygen concentration in the oxygen-containing first layer 1314A is from about 15 to 40%, and the oxygen concentration in the oxygen-depleted second layer 1314B is less than 5%.
在一些實施例中,例如圖13B所示那個,該多層電荷儲存層1314進一步包含至少一薄的中間或抗穿隧層1314C,內含例如一氧化物之介電層以將該貧氧第二層1314B與該富氧第一層1314A分開。如上所述地,該抗穿隧層1314C實際上降低在程式化期間所累積於該貧氧第二層1314B界面處之電子電荷穿隧至該富氧第一層1314A的可能性。 In some embodiments, such as the one shown in FIG. 13B, the multi-layer charge storage layer 1314 further includes at least one thin intermediate or anti-tunneling layer 1314C containing a dielectric layer such as an oxide to deplete the oxygen-depleted second Layer 1314B is separated from the oxygen-rich first layer 1314A. As described above, the anti-tunneling layer 1314C actually reduces the likelihood that electron charges accumulated at the interface of the oxygen-depleted second layer 1314B during tunneling will tunnel to the oxygen-rich first layer 1314A.
如同上述實施例,該富氧第一層1314A及該貧氧第二層1314B中任一者或兩者可包含氮化矽或氮氧化矽,並可例如經由包含氧化亞氮/氨及二氯矽烷/氨氣體混合物之化學氣相沉積製程,以量身定製之比值和流速來提供一富矽又富氧之氮氧化物層而形成之。該多層電荷儲存結構之貧氧第二層係接著形成於該中間氧化物層上。該貧氧第二層1314B具有不同於該底部富氧第一層1314A那個之氧、氮及/或矽化學計量組成成分,也可經由一化學氣相沉積製程,使用包含二氯矽烷/氨及氧化亞氮/氨氣體混合物之製程氣體,以量身定製之比值和流速來提供一富矽又貧氧之頂部氮化物層而形成或沉積之。 As with the above embodiments, either or both of the oxygen-enriched first layer 1314A and the oxygen-lean second layer 1314B may comprise tantalum nitride or hafnium oxynitride and may, for example, comprise nitrous oxide/ammonia and dichloride. A chemical vapor deposition process of a decane/ammonia gas mixture is formed by providing a rich and oxygen-rich oxynitride layer at a tailored ratio and flow rate. An oxygen-lean second layer of the multilayer charge storage structure is then formed on the intermediate oxide layer. The oxygen-depleted second layer 1314B has a stoichiometric composition of oxygen, nitrogen and/or helium different from the bottom oxygen-enriched first layer 1314A, and may also be subjected to a chemical vapor deposition process using dichloromethane/ammonia and The process gas of the nitrous oxide/ammonia gas mixture is formed or deposited at a tailored ratio and flow rate to provide a rich and oxygen-depleted top nitride layer.
在包含一含氧化物之中間或抗穿隧層1314C之那些實施例中,該抗穿隧層可使用基氧化作用來氧化該富氧第一層1314A至一所選深度而形成之。基氧化作用可在例如1000-1100℃溫度下使用一單晶圓工具 或在800-900℃溫度下使用一批次反應器工具來執行之。一氫氣和氧氣混合物可在300-500托耳壓力下運用於一批次製程或在10-15托耳壓力下使用一單一氣相工具,使用一單晶圓工具則持續1-2分鐘時間,或者,使用一批次製程則持續30分鐘-1小時時間。 In those embodiments comprising an intermediate or anti-tunneling layer 1314C, the anti-tunneling layer can be formed by oxidizing the oxygen-rich first layer 1314A to a selected depth using a base oxidation. Base oxidation can be used at a temperature of, for example, 1000-1100 ° C using a single wafer tool Or use a batch of reactor tools to perform at 800-900 °C. A hydrogen and oxygen mixture can be used in a batch process at 300-500 Torr or a single gas phase tool at 10-15 Torr, using a single wafer tool for 1-2 minutes. Alternatively, use a batch process for a period of 30 minutes to 1 hour.
該富氧第一層1314A之合適厚度可從大約30埃至大約130埃(有一些變異值,例如,±10埃),其中,大約5-20埃厚度可經由基氧化作用來消耗以形成該抗穿隧層1314C。在一些實施例中,該貧氧第二層1314B可形成高達130埃厚,其中,30-70埃厚度可經由基氧化作用來消耗以形成該阻擋層1318。在一些實施例中,該富氧第一層1314A和該貧氧第二層1314B之厚度比值係大約1:1,然而其它比值也是可行的。 A suitable thickness of the oxygen-enriched first layer 1314A can range from about 30 angstroms to about 130 angstroms (with some variation, for example, ± 10 angstroms), wherein a thickness of about 5-20 angstroms can be consumed via basal oxidation to form the Anti-pass tunnel layer 1314C. In some embodiments, the oxygen-depleted second layer 1314B can form up to 130 angstroms thick, wherein a thickness of 30-70 angstroms can be consumed via basal oxidation to form the barrier layer 1318. In some embodiments, the thickness ratio of the oxygen-enriched first layer 1314A to the oxygen-lean second layer 1314B is about 1:1, although other ratios are also possible.
該阻擋層1318包括一較沉積時相對地更密集之高溫氧化物(HTO)。一密集高溫氧化物具有一較低終端氫或氫氧鍵分數。例如,自一高溫氧化物中移除該氫或水具有增加該薄膜密度並改善該高溫氧化物品質的效應。該較高品質氧化物使該層在厚度上可被縮放。在一實施例中,沉積時之氫濃度係大於2.5x1020原子/立分公分且在該密集薄膜中降低至小於8.0x1019原子/立分公分。在一示範性實施例中,包括一密集高溫氧化物之阻擋層1318的厚度在沉積時係介於2.5奈米至10.0奈米之間,且因密集化作用而使各處更薄上10%至30%。 The barrier layer 1318 includes a relatively high temperature oxide (HTO) that is relatively denser when deposited. A dense high temperature oxide has a lower terminal hydrogen or hydroxide bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x 10 20 atoms per centimeter and is reduced to less than 8.0 x 10 19 atoms per centimeter in the dense film. In an exemplary embodiment, the thickness of the barrier layer 1318 including a dense high temperature oxide is between 2.5 nm and 10.0 nm at the time of deposition, and is 10% thinner everywhere due to the densification. Up to 30%.
在一替代性實施例中,進一步改變該阻擋層1318以整合氮。在一這類實施例中,該氮係以橫跨該阻擋層1318厚度的氧化物-氮化物-氧化物堆疊形式進行整合。取代該傳統純氧阻檔層之這類三明治結構有利地降低該通道區域1302及控制閘極1320間之整個堆疊的有效氧化物厚度並 致能調整傳導帶位移以降低載子回流。該氧化物-氮化物-氧化物堆疊阻擋層1318接著可與該氮化氧化物穿隧層1316及包括一富氧第一層1314A、一貧氧第二層1314B和一抗穿隧層1314C之分離式多層電荷捕獲層1314進行整合。 In an alternative embodiment, the barrier layer 1318 is further altered to integrate nitrogen. In one such embodiment, the nitrogen is integrated in an oxide-nitride-oxide stack across the thickness of the barrier layer 1318. Such a sandwich structure replacing the conventional pure oxygen barrier layer advantageously reduces the effective oxide thickness of the entire stack between the channel region 1302 and the control gate 1320 and Enable adjustment of the conduction band displacement to reduce carrier reflow. The oxide-nitride-oxide stack barrier layer 1318 can then be combined with the nitride oxide tunneling layer 1316 and include an oxygen-rich first layer 1314A, an oxygen-poor second layer 1314B, and an anti-tunneling layer 1314C. The separate multilayer charge trap layer 1314 is integrated.
在圖14A及14B所示之另一實施例中,該記憶體元件可包含由位在連接該記憶體元件之源極區域和汲極區域之基板上之一表面上方的半導體材料薄膜所形成之奈米線通道區域。奈米線通道區域係意謂著在一結晶矽材料薄條帶內所形成之傳導通道區域,具有最大剖面尺寸約為10奈米(nm)或更小,且較佳地,大約小於6奈米。選擇性地,該通道區域可被形成以相對於該通道一長軸具有<100>表面結晶方位。 In another embodiment shown in FIGS. 14A and 14B, the memory device can comprise a thin film of semiconductor material disposed over a surface of a substrate connected to a source region and a drain region of the memory device. Nano line channel area. The nanowire channel region means a conductive channel region formed in a thin strip of crystalline germanium material having a maximum cross-sectional dimension of about 10 nanometers (nm) or less, and preferably, less than about 6 nanometers. Meter. Optionally, the channel region can be formed to have a <100> surface crystal orientation relative to a long axis of the channel.
參考至圖14A,該記憶體元件1400包含形成自一基板1406上之一表面上或上方的半導體材料薄膜或薄層並連接該記憶體元件之源極區域1408和汲極區域1410之水平奈米線通道區域1402。在所示實施例中,該元件具有一繞式閘極(GAA)結構,其中,該奈米通道區域1402之所有側被該元件之閘極1412所封閉。該閘極1412(自源極至汲極方向進行估測)之厚度決定該元件之有效通道長度。如同上述實施例,該奈米線通道區域1402可包括多晶矽或再結晶多晶矽以形成一單結晶通道區域。選擇性地,在該通道區域1402包含一單結晶矽所在處,該通道區域可被形成以相對於該通道區域一長軸具有<100>表面結晶方位。 Referring to FIG. 14A, the memory device 1400 includes a thin film of semiconductor material or a thin layer formed on or above one surface of a substrate 1406 and connected to the source region 1408 and the drain region 1410 of the memory device. Line channel area 1402. In the illustrated embodiment, the component has a wound gate (GAA) structure in which all sides of the nanochannel region 1402 are enclosed by the gate 1412 of the component. The thickness of the gate 1412 (estimated from the source to the drain) determines the effective channel length of the component. As with the above embodiments, the nanowire channel region 1402 can comprise polycrystalline germanium or recrystallized polycrystalline germanium to form a single crystalline channel region. Optionally, the channel region 1402 includes a single crystalline germanium region that can be formed to have a <100> surface crystalline orientation relative to a long axis of the channel region.
根據本揭示,圖14A之非平面式多閘極記憶體元件1400可包含一分離式電荷捕獲層、一氮化氧化物穿隧層和一密集阻擋層。圖14B係圖14A之非平面式多閘極元件之一部分剖面圖,包含一部分基板1406、 奈米線通道區域1402及該閘極1412。參考至圖14B,該閘極1412包含一氮化氧化物穿隧層1414、一多層電荷捕獲層1416、一密集阻擋層1418。該閘極1412進一步包含位在該阻擋層上方以形成該記憶體元件1400之控制閘極之閘極層1420。該閘極層1420可包括一沉積金屬或一摻雜多晶矽。 In accordance with the present disclosure, the non-planar multi-gate memory device 1400 of FIG. 14A can include a separate charge trap layer, a nitride oxide tunneling layer, and a dense barrier layer. 14B is a partial cross-sectional view of a non-planar multi-gate element of FIG. 14A, including a portion of the substrate 1406, The nanowire channel region 1402 and the gate 1412. Referring to FIG. 14B, the gate 1412 includes a nitride oxide tunneling layer 1414, a multilayer charge trapping layer 1416, and a dense barrier layer 1418. The gate 1412 further includes a gate layer 1420 positioned over the barrier layer to form a control gate of the memory device 1400. The gate layer 1420 can include a deposition metal or a doped polysilicon.
在例如所示那個之某些實施例中,該穿隧層1414係一氮化氧化物穿隧層1414,包含接近該通道區域1402處之具有一大約小於5x1021氮原子/立方公分氮濃度的第一區域1414A及接近該多層電荷捕獲層1416處之具有至少5x1021氮原子/立方公分氮濃度的第二區域1414B。在一實施例中,類似於圖11B所揭示那個,該氮化氧化物穿隧層1414的第一和第二區域各包括大約不大於該穿隧層厚度的25%。 In some embodiments, such as the one shown, the tunneling layer 1414 is a nitride oxide tunneling layer 1414 comprising a nitrogen concentration near the channel region 1402 of less than about 5 x 10 21 nitrogen atoms per cubic centimeter. The first region 1414A and the second region 1414B having a nitrogen concentration of at least 5 x 10 21 nitrogen atoms per cubic centimeter at the multilayer charge trap layer 1416. In one embodiment, similar to the one disclosed in FIG. 11B, the first and second regions of the nitride oxide tunneling layer 1414 each comprise no more than about 25% of the thickness of the tunneling layer.
該多層電荷捕獲層1416包含較接近該穿隧層1414之含氮化物的至少一薄的富氧第一層1416A和位在該富氧第一層上方之外部貧氧第二層1416B。大體上,該貧氧第二層1416B包括一富矽又貧氧氮化物層並包含散佈於該多層電荷捕獲層1416內之多數電荷陷阱,而該富氧第一層1416A包括一富氧氮化物或氮氧化矽層且相對於該貧氧第二層係富氧的,以減少其中之電荷陷阱數量。富氧係意謂著在該富氧第一層1416A內的氧濃度係從大約15至40%,而在該貧氧第二層1416B內的氧濃度係小於5%。 The multilayer charge trap layer 1416 includes at least one thin oxygen-rich first layer 1416A adjacent to the nitride-containing layer 1414 and an outer oxygen-lean second layer 1416B positioned above the oxygen-rich first layer. In general, the oxygen-depleted second layer 1416B includes a germanium-rich and oxygen-depleted nitride layer and includes a plurality of charge traps dispersed within the plurality of charge trap layers 1416, and the oxygen-rich first layer 1416A includes an oxygen-rich nitride. Or a layer of oxynitride and oxygen-rich relative to the oxygen-depleted second layer to reduce the number of charge traps therein. Oxygen-enriched means that the oxygen concentration in the oxygen-enriched first layer 1416A is from about 15 to 40%, and the oxygen concentration in the oxygen-lean second layer 1416B is less than 5%.
在一些實施例中,如同圖14B所示那個,該多層電荷捕獲層1416進一步包含至少一薄的中間或抗穿隧層1416C,內含例如一氧化物之介電層以將該貧氧第二層1416B與該富氧第一層1416A分開。如上所述地,該抗穿隧層1416C實際上降低程式化期間所累積於該貧氧第二層1416B界面處之電子電荷穿隧至該富氧第一層1416A之可能性。 In some embodiments, as shown in FIG. 14B, the multilayer charge trap layer 1416 further includes at least one thin intermediate or anti-tunneling layer 1416C containing a dielectric layer such as an oxide to deplete the oxygen-depleted second Layer 1416B is separated from the oxygen-rich first layer 1416A. As described above, the anti-tunneling layer 1416C actually reduces the likelihood that electron charges accumulated at the interface of the oxygen-depleted second layer 1416B during tunneling will tunnel to the oxygen-rich first layer 1416A.
如同上述實施例,該富氧第一層1416A和該貧氧第二層1416B中任一者或兩者可包括氮化矽或氮氧化矽,並可例如經由包含氧化亞氮/氨及二氯矽烷/氨氣體混合物之化學氣相沉積製程,以量身定製之比值和流速來提供一富矽又富氧之氮氧化物層而形成之。該多層電荷儲存結構之貧氧第二層接著係形成於該中間氧化物層上。該貧氧第二層1416B具有不同於該富氧第一層1416A那個之氧、氮及/或矽化學計量組成成分,也可經由一化學氣相沉積製程,使用包含二氯矽烷/氨及氧化亞氮/氨氣體混合物之製程氣體,以量身定製之比值和流速來提供一富矽又貧氧之頂部氮化物層而形成或沉積之。 As with the above embodiments, either or both of the oxygen-enriched first layer 1416A and the oxygen-lean second layer 1416B may comprise tantalum nitride or hafnium oxynitride, and may comprise, for example, via nitrous oxide/ammonia and dichloride. A chemical vapor deposition process of a decane/ammonia gas mixture is formed by providing a rich and oxygen-rich oxynitride layer at a tailored ratio and flow rate. An oxygen-lean second layer of the multilayer charge storage structure is then formed on the intermediate oxide layer. The oxygen-depleted second layer 1416B has a stoichiometric composition of oxygen, nitrogen and/or helium different from the oxygen-rich first layer 1416A, and may also be subjected to a chemical vapor deposition process using dichloromethane/ammonia and oxidation. The process gas of the nitrous/ammonia gas mixture is formed or deposited at a tailored ratio and flow rate to provide a rich and oxygen-depleted top nitride layer.
在包含一含氧化物之中間或抗穿隧層1416C之那些實施例中,該抗穿隧層可使用基氧化作用來氧化該富氧第一層1416A至一所選深度而形成之。基氧化作用可在例如1000-1100℃溫度下使用一單晶圓工具或在800-900攝氏度溫度下使用一批次反應器工具來執行之。一氫氣和氧氣混合物可在300-500托耳壓力下運用於一批次製程或在10-15托耳壓力下使用一單一氣相工具,使用一單晶圓工具則持續1-2分鐘時間,或者,使用一批次製程則持續30分鐘-1小時時間。 In those embodiments comprising an intermediate or anti-tunneling layer 1416C, the anti-tunneling layer can be formed by oxidizing the oxygen-rich first layer 1416A to a selected depth using radical oxidation. The base oxidation can be carried out using, for example, a single wafer tool at a temperature of 1000-1100 ° C or using a batch of reactor tools at a temperature of 800-900 ° C. A hydrogen and oxygen mixture can be used in a batch process at 300-500 Torr or a single gas phase tool at 10-15 Torr, using a single wafer tool for 1-2 minutes. Alternatively, use a batch process for a period of 30 minutes to 1 hour.
該富氧第一層1416A之合適厚度可從大約30埃至大約130埃(具有一些變異值,例如,±10埃),其中,大約5-20埃厚度可經由基氧化作用來消耗以形成該抗穿隧層1416C。該貧氧第二層1416B之合適厚度至少為30埃。在某些實施例中,該貧氧第二層1416B可形成高達130埃厚,其中,30-70埃厚度可經由基氧化作用來消耗以形成該阻擋層1418。在一些實施例中,富氧第一層1416A和該貧氧第二層1416B之厚度比值係大約1:1, 然而其它比值也是可行的。 A suitable thickness of the oxygen-enriched first layer 1416A can range from about 30 angstroms to about 130 angstroms (with some variation, for example, ± 10 angstroms), wherein a thickness of about 5-20 angstroms can be consumed via basal oxidation to form the Anti-through tunnel layer 1416C. The oxygen-depleted second layer 1416B has a suitable thickness of at least 30 angstroms. In certain embodiments, the oxygen-depleted second layer 1416B can be formed up to 130 angstroms thick, wherein a thickness of 30-70 angstroms can be consumed via base oxidation to form the barrier layer 1418. In some embodiments, the thickness ratio of the oxygen-enriched first layer 1416A to the oxygen-lean second layer 1416B is about 1:1. However, other ratios are also possible.
該阻擋層1418包括一較沉積時相對地更密集之高溫氧化物(HTO)。一密集高溫氧化物具有一較低終端氫或氫氧鍵分數。例如,自一高溫氧化物中移除該氫或水具有增加該薄膜密度並改善該高溫氧化物品質的效應。該較高品質氧化物使該層在厚度上可被縮放。在一實施例中,沉積時之氫濃度係大於2.5x1020原子/立分公分且在該密集薄膜中降低至小於8.0x1019原子/立分公分。在一示範性實施例中,包括一密集高溫氧化物之阻擋層1418的厚度在沉積時係介於2.5奈米至10.0奈米之間,且因密集化作用而使各處更薄上10%至30%。 The barrier layer 1418 includes a relatively high temperature oxide (HTO) that is relatively denser when deposited. A dense high temperature oxide has a lower terminal hydrogen or hydroxide bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x 10 20 atoms per centimeter and is reduced to less than 8.0 x 10 19 atoms per centimeter in the dense film. In an exemplary embodiment, the thickness of the barrier layer 1418 including a dense high temperature oxide is between 2.5 nanometers and 10.0 nanometers at the time of deposition, and is 10% thinner everywhere due to densification. Up to 30%.
在一替代性實施例中,進一步改變該阻擋層1418以整合氮。在一這類實施例中,該氮係以橫跨該阻擋層1418厚度的氧化物-氮化物-氧化物堆疊形式進行整合。取代該傳統純氧阻檔層之這類三明治結構有利地降低該通道區域1402及閘極層1420間之整個堆疊的有效氧化物厚度並致能調整傳導帶位移以降低載子回流。該氧化物-氮化物-氧化物堆疊阻擋層1418接著可與該氮化氧化物穿隧層1414及包括一富氧第一層1416A、一貧氧第二層1416B和一抗穿隧層1416C之分離式多層電荷捕獲層1416進行整合。 In an alternative embodiment, the barrier layer 1418 is further altered to incorporate nitrogen. In one such embodiment, the nitrogen is integrated in an oxide-nitride-oxide stack across the thickness of the barrier layer 1418. Such a sandwich structure that replaces the conventional pure oxygen barrier layer advantageously reduces the effective oxide thickness of the entire stack between the channel region 1402 and the gate layer 1420 and enables adjustment of the conduction band displacement to reduce carrier reflow. The oxide-nitride-oxide stack barrier layer 1418 can then be coupled to the nitride oxide tunneling layer 1414 and include an oxygen-rich first layer 1416A, an oxygen-depleted second layer 1416B, and an anti-tunneling layer 1416C. The split multilayer charge trap layer 1416 is integrated.
圖14C說明圖14A中安排成位元成本可調或BiCS架構1422之非平面式多閘極元件1400垂直串之剖面圖。該架構1422由一非平面式多閘極元件1400垂直串或堆疊所構成,其中,每一個元件或單元包含位在該基板1406上方並連接該記憶體元件之源極區域和汲極區域(未顯示於圖形中)之通道區域1402,具有一繞式閘極(GAA)結構,其中,該奈米線通道區 域1402所有側係由一閘極區域1412所封閉。相較於一簡單層堆疊,該BiCS架構減少關鍵性微影成像步驟數,使得每一記憶體位元成本下降。 14C illustrates a cross-sectional view of a vertical string of non-planar multi-gate elements 1400 arranged in a bit cost adjustable or BiCS architecture 1422 of FIG. 14A. The structure 1422 is formed by a vertical string or stack of non-planar multi-gate elements 1400, wherein each element or cell includes a source region and a drain region above the substrate 1406 and connected to the memory device (not The channel region 1402 shown in the figure has a winding gate (GAA) structure, wherein the nanowire channel region All of the sideways of domain 1402 are enclosed by a gate region 1412. Compared to a simple layer stack, the BiCS architecture reduces the number of critical lithography imaging steps, resulting in a reduction in cost per memory bit.
在另一實施例中,該記憶體元件係或包含一非平面式元件,內含由一基板上之一些傳導半導體層上方或之處凸出的半導體材料內或之中所形成之一垂直奈米線通道。在圖15A切面所示之本實施例一版本中,該記憶體元件1500包括由連接該元件之源極區域1504和汲極區域1506之半導體材料圓柱體中所形成之垂直奈米線通道區域1502。該通道區域1502係由一穿隧層1508、一多層電荷捕獲層1510、一阻擋層1512及位於該阻擋層上方以形成該記憶體元件1500之控制閘極的閘極層1514所環繞。該通道區域1502可包含在一實際上實心半導體材料圓柱體外層內之環狀區域,或可包含形成於一介電填充材料圓柱體上方之環狀層。如同上述水平奈米線,該通道區域1502可包括用以形成一單結晶通道區域之多晶矽或再結晶多晶矽。選擇性地,在該通道區域1502包含一結晶矽所在處,該通道可被形成以相對於該通道一長軸具有<100>表面結晶方位。 In another embodiment, the memory component is or comprises a non-planar component containing one of the semiconductor materials formed in or on a semiconductor material overlying or partially on a substrate. Rice noodle channel. In the first embodiment of the embodiment shown in Fig. 15A, the memory device 1500 includes a vertical nanowire channel region 1502 formed by a semiconductor material cylinder connecting the source region 1504 and the drain region 1506 of the device. . The channel region 1502 is surrounded by a tunneling layer 1508, a multilayer charge trapping layer 1510, a barrier layer 1512, and a gate layer 1514 over the barrier layer to form a control gate of the memory device 1500. The channel region 1502 can comprise an annular region within an outer layer of a substantially solid cylindrical body of semiconductor material, or can comprise an annular layer formed over a cylinder of dielectric filler material. Like the horizontal nanowires described above, the channel region 1502 can include polysilicon or recrystallized polysilicon to form a single crystalline channel region. Optionally, the channel region 1502 includes a crystalline germanium that can be formed to have a <100> surface crystalline orientation relative to a long axis of the channel.
在一些實施例中,例如圖15B所示那個,該穿隧層1508係一氮化氧化物穿隧層,包含接近該通道區域1502處之具有一大約小於5x1021氮原子/立方公分氮濃度的第一區域1508A及接近該多層電荷捕獲層1510處之具有至少5x1021氮原子/立方公分氮濃度的第二區域1508B。在一實施例中,類似於圖11B所揭示那個,該氮化氧化物穿隧層1508的第一和第二區域各包括大約不大於該穿隧層厚度的25%。 In some embodiments, such as that shown in FIG. 15B, the tunneling layer 1508 is a nitrided oxide tunneling layer comprising a nitrogen concentration near the channel region 1502 having a nitrogen concentration of less than about 5 x 10 21 nitrogen atoms per cubic centimeter. The first region 1508A and the second region 1508B having a nitrogen concentration of at least 5 x 10 21 nitrogen atoms per cubic centimeter at the multilayer charge trap layer 1510. In one embodiment, similar to the one disclosed in FIG. 11B, the first and second regions of the nitride oxide tunneling layer 1508 each comprise no more than about 25% of the thickness of the tunneling layer.
該多層電荷捕獲層1510係一分離式多層電荷捕獲層,進一步包含較接近該穿隧層1508之含氮化物的至少一薄的富氧第一層1510A和 位在該富氧第一層上方之外部貧氧第二層1510B。大體上,該貧氧第二層1510B包括一富矽又貧氧氮化物層並包含散佈於該多層電荷捕獲層1510內之多數電荷陷阱,而該富氧第一層1510A包括一富氧氮化物或氮氧化矽層且相對於該貧氧第二層係富氧的,以減少其中之電荷陷阱數量。富氧係意謂著在該富氧第一層1510A內的氧濃度係從大約15至40%,而在該貧氧第二層1510B內的氧濃度係小於5%。 The multilayer charge trap layer 1510 is a separate multilayer charge trap layer further comprising at least one thin oxygen-rich first layer 1510A and a nitride-containing layer closer to the tunneling layer 1508. An outer oxygen depleted second layer 1510B is positioned above the oxygen-rich first layer. In general, the oxygen-depleted second layer 1510B includes a germanium-rich and oxygen-depleted nitride layer and includes a plurality of charge traps dispersed within the plurality of charge trap layers 1510, and the oxygen-rich first layer 1510A includes an oxygen-rich nitride. Or a layer of oxynitride and oxygen-rich relative to the oxygen-depleted second layer to reduce the number of charge traps therein. Oxygen-enriched means that the oxygen concentration in the oxygen-enriched first layer 1510A is from about 15 to 40%, and the oxygen concentration in the oxygen-poor second layer 1510B is less than 5%.
在一些實施例中,如圖15B所示那個,該分離式多層電荷捕獲層1510進一步包含至少一薄的中間或抗穿隧層1510C,內含例如一氧化物之介電層以將該貧氧第二層1510B與該富氧第一層1510A分開。如上所述地,該抗穿隧層1510C實際上降低程式化期間所累積於該貧氧第二層1510B界面處之電子電荷穿隧至該富氧第一層1510A之可能性。 In some embodiments, as shown in FIG. 15B, the split multilayer charge trap layer 1510 further includes at least one thin intermediate or anti-tunneling layer 1510C containing a dielectric layer such as an oxide to deplete the oxygen. The second layer 1510B is separated from the oxygen-rich first layer 1510A. As described above, the anti-tunneling layer 1510C actually reduces the likelihood that electron charges accumulated at the interface of the oxygen-depleted second layer 1510B during tunneling will tunnel to the oxygen-rich first layer 1510A.
如同上述實施例,該富氧第一層1510A和該貧氧第二層1510B中任一者或兩者可包括氮化矽或氮氧化矽,並可例如經由包含氧化亞氮/氨及二氯矽烷/氨氣體混合物之化學氣相沉積製程,以量身定製之比值和流速來提供一富矽又富氧之氮氧化物層而形成之。該多層電荷儲存結構之貧氧第二層接著係形成於該中間氧化物層上。該貧氧第二層1510B具有不同於該富氧第一層1510A那個之氧、氮及/或矽化學計量組成成分,也可經由一化學氣相沉積製程,使用包含二氯矽烷/氨及氧化亞氮/氨氣體混合物之製程氣體,以量身定製之比值和流速來提供一富矽又貧氧之頂部氮化物層而形成或沉積之。 As with the above embodiments, either or both of the oxygen-enriched first layer 1510A and the oxygen-lean second layer 1510B may include tantalum nitride or hafnium oxynitride, and may include, for example, nitrous oxide/ammonia and dichloride. A chemical vapor deposition process of a decane/ammonia gas mixture is formed by providing a rich and oxygen-rich oxynitride layer at a tailored ratio and flow rate. An oxygen-lean second layer of the multilayer charge storage structure is then formed on the intermediate oxide layer. The oxygen-depleted second layer 1510B has a stoichiometric composition of oxygen, nitrogen and/or helium different from the oxygen-rich first layer 1510A, and may also be subjected to a chemical vapor deposition process using dichloromethane/ammonia and oxidation. The process gas of the nitrous/ammonia gas mixture is formed or deposited at a tailored ratio and flow rate to provide a rich and oxygen-depleted top nitride layer.
在包含一含氧化物之中間或抗穿隧層1510C之那些實施例中,該抗穿隧層可使用基氧化作用來氧化該富氧第一層1510A至一所選深 度而形成之。基氧化作用可在例如1000-1100℃溫度下使用一單晶圓工具或在800-900攝氏度溫度下使用一批次反應器工具來執行之。一氫氣和氧氣混合物可在300-500托耳壓力下運用於一批次製程或在10-15托耳壓力下使用單一氣相工具,使用一單晶圓工具則持續1-2分鐘時間,或者,使用一批次製程則持續30分鐘-1小時時間。 In those embodiments comprising an intermediate or anti-tunneling layer 1510C, the anti-tunneling layer may oxidize the oxygen-rich first layer 1510A to a selected depth using base oxidation. Formed by degrees. The base oxidation can be carried out using, for example, a single wafer tool at a temperature of 1000-1100 ° C or using a batch of reactor tools at a temperature of 800-900 ° C. A hydrogen and oxygen mixture can be used in a batch process at 300-500 Torr or a single gas phase tool at 10-15 Torr, using a single wafer tool for 1-2 minutes, or , using a batch process for 30 minutes - 1 hour.
該富氧第一層1510A之合適厚度可從大約30埃至大約130埃(具有一些變異值,例如,±10埃),其中,大約5-20埃厚度可經由基氧化作用來消耗以形成該抗穿隧層1510C。該貧氧第二層1510B之合適厚度至少為30埃。在某些實施例中,該貧氧第二層1510B可形成高達130埃厚,其中,30-70埃厚度可經由基氧化作用來消耗以形成該阻擋層1512。在一些實施例中,富氧第一層1510A和該貧氧第二層1510B之厚度比值係大約1:1,然而其它比值也是可行的。 A suitable thickness of the oxygen-enriched first layer 1510A can range from about 30 angstroms to about 130 angstroms (with some variation, for example, ±10 angstroms), wherein a thickness of about 5-20 angstroms can be consumed via basal oxidation to form the Anti-through tunnel layer 1510C. The oxygen-depleted second layer 1510B has a suitable thickness of at least 30 angstroms. In certain embodiments, the oxygen-depleted second layer 1510B can be formed up to 130 angstroms thick, wherein a thickness of 30-70 angstroms can be consumed via base oxidation to form the barrier layer 1512. In some embodiments, the thickness ratio of the oxygen-enriched first layer 1510A to the oxygen-lean second layer 1510B is about 1:1, although other ratios are also possible.
該阻擋層1512包括一較沉積時相對地更密集之高溫氧化物(HTO)。一密集高溫氧化物具有一較低終端氫或氫氣鍵分數。例如,自一高溫氧化物中移除該氫或水具有增加該薄膜密度並改善該高溫氧化物品質的效應。該較高品質氧化物使該層在厚度上可被縮放。在一實施例中,沉積時之氫濃度係大於2.5x1020原子/立分公分且在該密集薄膜中降低至小於8.0x1019原子/立分公分。在一示範性實施例中,包括一密集高溫氧化物之阻擋層1512的厚度在沉積時係介於2.5奈米至10.0奈米之間,且因密集化作用而使各處更薄上10%至30%。 The barrier layer 1512 includes a relatively high temperature oxide (HTO) that is relatively denser when deposited. A dense high temperature oxide has a lower terminal hydrogen or hydrogen bond fraction. For example, removing the hydrogen or water from a high temperature oxide has the effect of increasing the density of the film and improving the quality of the high temperature oxide. The higher quality oxide allows the layer to be scaled in thickness. In one embodiment, the concentration of hydrogen during deposition is greater than 2.5 x 10 20 atoms per centimeter and is reduced to less than 8.0 x 10 19 atoms per centimeter in the dense film. In an exemplary embodiment, the thickness of the barrier layer 1512 including a dense high temperature oxide is between 2.5 nm and 10.0 nm at the time of deposition, and is 10% thinner everywhere due to the densification. Up to 30%.
在一替代性實施例中,進一步改變該阻擋層1512以整合氮。在一這類實施例中,該氮係以橫跨該阻擋層1512厚度的氧化物-氮化物 -氧化物堆疊形式進行整合。取代該傳統純氧阻檔層之這類三明治結構有利地降低該通道區域1502及閘極層1514間之整個堆疊的有效氧化物厚度並致能調整傳導帶位移以降低載子回流。該氧化物-氮化物-氧化物堆疊阻擋層1512接著可與該氮化氧化物穿隧層1508及包括一富氧第一層1510A、一貧氧第二層1510B和一抗穿隧層1510C之分離式多層電荷捕獲層1510進行整合。 In an alternative embodiment, the barrier layer 1512 is further altered to integrate nitrogen. In one such embodiment, the nitrogen is oxide-nitride across the thickness of the barrier layer 1512. - Integration of oxide stacks. Such a sandwich structure that replaces the conventional pure oxygen barrier layer advantageously reduces the effective oxide thickness of the entire stack between the channel region 1502 and the gate layer 1514 and enables adjustment of the conduction band displacement to reduce carrier reflow. The oxide-nitride-oxide stack barrier layer 1512 can then be coupled to the nitride oxide tunneling layer 1508 and include an oxygen-rich first layer 1510A, an oxygen-depleted second layer 1510B, and an anti-tunneling layer 1510C. The separate multilayer charge trap layer 1510 is integrated.
圖15A之記憶體元件1500不是使用一閘極優先就是使用閘極後製方案來製造之。圖16A-F說明用於製造圖15A之非平面式多閘極元件的閘極優先方案。圖17A-F說明用於製造圖15A之非平面式多閘極元件的閘極後製方案。 The memory component 1500 of Figure 15A is fabricated using either a gate priority or a gate post scheme. 16A-F illustrate a gate priority scheme for fabricating the non-planar multi-gate element of FIG. 15A. 17A-F illustrate a gate post-production scheme for fabricating the non-planar multi-gate element of FIG. 15A.
參考至圖16A,在一閘極優先方案中,一第一或下方介電層1602係形成於一基板1606內,例如一源極區域或一汲極區域的第一摻雜擴散區域1604上方。一閘極層1608係沉積於該第一介電層1602上方以形成該元件之控制閘極,且一第二或上方介電層1610形成於其上方。如同上述實施例,該第一和第二介電層1602、1610可經由化學氣相沉積製程、基氧化製程來沉積,或經由氧化一部分下層或下方基板而形成之。該閘極層1608可包括經由化學氣相沉積製程所沉積之金屬或摻雜多晶矽。大體上,該閘極層1608之厚度約為40-110埃,且該第一和第二介電層1602、1610約為20-80埃。 Referring to FIG. 16A, in a gate priority scheme, a first or lower dielectric layer 1602 is formed in a substrate 1606, such as a source region or a first doped diffusion region 1604 of a drain region. A gate layer 1608 is deposited over the first dielectric layer 1602 to form a control gate of the component, and a second or upper dielectric layer 1610 is formed thereover. As with the above embodiments, the first and second dielectric layers 1602, 1610 can be deposited via a chemical vapor deposition process, a base oxidation process, or via oxidation of a portion of the lower or lower substrate. The gate layer 1608 can include a metal or doped polysilicon deposited via a chemical vapor deposition process. Generally, the gate layer 1608 has a thickness of about 40-110 angstroms, and the first and second dielectric layers 1602, 1610 are about 20-80 angstroms.
參考至圖16B,一第一開口1612係蝕刻穿透該第二介電層1610、該閘極層1608和該第一介電層1602,到達該基板1606內之擴散區域1604。接著,阻擋層1614、多層電荷捕獲層1616和穿隧層1618各層係接著 沉積於該開口中,並將該上方介電層1610之表面平坦化以產生圖16C所示之中間結構。 Referring to FIG. 16B, a first opening 1612 is etched through the second dielectric layer 1610, the gate layer 1608, and the first dielectric layer 1602 to reach a diffusion region 1604 within the substrate 1606. Next, the barrier layer 1614, the multilayer charge trap layer 1616, and the tunneling layer 1618 are layered. Deposited in the opening and planarizing the surface of the upper dielectric layer 1610 to create the intermediate structure shown in FIG. 16C.
如同上述實施例,該阻擋層1614可為一密集阻擋層,包括較沉積時相對地更密集且具有一較低終端氫或氫氧鍵分數之密集高溫氧化物。 As with the above embodiments, the barrier layer 1614 can be a dense barrier layer comprising dense high temperature oxides that are relatively denser when deposited and have a lower terminal hydrogen or hydroxide bond fraction.
雖未顯示,但會了解到如同上述實施例,該多層電荷捕獲層1616可包含一分離式多層電荷捕獲層,包括較接近或沉積於該密集阻擋層1614上之一外部貧氧第二層及沉積或形成於該貧氧第二層上之一內部富氧第一層。大體上,該貧氧第二層包括一富矽又貧氧之氮化物層,並包括散佈於多個電荷捕獲層之多數電荷陷阱,而該富氧第一層包括一富氧氮化物或氮氧化矽,且相對於該頂部電荷捕獲層係富氧的,以減少其中之電荷陷阱數量。在一些實施例中,該多層電荷捕獲層1616係一分離式多層電荷捕獲層,進一步內含至少一薄的中間或抗穿隧層,該薄層包括例如一氧化物之介電質以將該外部貧氧第二層與該內部富氧第一層分開。 Although not shown, it will be appreciated that as with the above embodiments, the multilayer charge trapping layer 1616 can comprise a separate multilayer charge trapping layer, including an outer oxygen depleted second layer that is closer to or deposited on the dense barrier layer 1614 and Depositing or forming an inner first oxygen-rich layer on the oxygen-depleted second layer. In general, the oxygen-depleted second layer includes a germ