TW202109528A - Memory device and manufacturing method thereof - Google Patents

Abstract

A memory device and a manufacturing method are provided. The memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between an extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction.

Description

Memory element and manufacturing method thereof

The present invention relates to a memory device and a manufacturing method thereof, and more particularly to a dynamic random access memory (DRAM) device and a manufacturing method thereof.

With the development of the DRAM manufacturing process, the bit line contact structure provided between the substrate and the bit line has been changed from a stripe structure to a plurality of columnar structures. Due to the limitation of the lithography process, a part of the active area is likely to remain around the columnar bit line contact structure. The remaining part of the active area and the bit line may form a parasitic capacitance, and may be in electrical contact with an adjacent capacitance contact structure, which may cause a short circuit. Therefore, the reliability of the DRAM is affected.

The invention provides a memory element and a manufacturing method thereof. The memory device can be a DRAM device, and can have high reliability.

The memory device of the embodiment of the present invention includes a word line, a bit line, an active area, and a bit line contact structure. The character line is arranged in the substrate and extends along the first direction. The bit line is arranged on the substrate and extends along the second direction. The first direction is staggered with the second direction. The active area is arranged in the substrate, extends along the third direction, and is interleaved with the word line and the bit line. The third direction is different from the first direction and the second direction. The bit line contact structure is arranged between the active area and the bit line. The top view of the bit line contact structure has a long axis. The angle between the extension direction of the long axis and the third direction is smaller than the angle between the extension direction of the long axis and the first direction, and less than the angle between the extension direction of the long axis and the second direction.

The manufacturing method of the memory device of some embodiments of the present invention includes forming an active area, a word line, and an initial bit line contact structure in a substrate; and forming a bit line on the substrate and removing the initial bit line contact structure. The part that does not overlap the bit line forms a bit line contact structure. The character line extends in the first direction. The bit line extends along a second direction staggered with the first direction. The active area is interleaved with the word line and the bit line, and extends along a third direction different from the first direction and the second direction, and the bit line structure is arranged between the active area and the bit line. The lithography process used to form the initial bit line contact structure includes the use of a free-form lens array so that light passes through the free-form lens array before being incident on the photomask. The special-shaped lens array includes a plurality of lenses. The multiple lenses are arranged along a parallelogram-like contour. The parallelogram-like profile has a major axis. The angle between the extending direction of the long axis and the third direction is smaller than the angle between the extending direction of the long axis and the first direction and the angle between the extending direction of the long axis and the second direction.

Based on the above, the angle between the extension direction of the long axis of the initial bit line contact structure and the third direction is smaller than the angle between the extension direction of the long axis and the first direction, and is smaller than the extension direction of the long axis and the third direction. The angle between the second directions allows the long axis of the initial bit line contact structure disposed on the active area to be close to the extending direction of the active area (that is, the third direction). In this way, the outline of the initial bit line contact structure can be as close as possible to the edge of a part of the active area on the side of the character line, and completely cover the part of the active area. In other words, when the initial bit line contact structure is formed, the top of the active area can be completely removed, which can avoid some parts of the active area remaining around the subsequently formed bit line contact structure. Parasitic capacitance may be formed between these residual parts of the active region and the bit line, and may cause a short circuit problem with the adjacent capacitance contact structure. Therefore, the bit line contact structure formed by the manufacturing method of the present invention can avoid the above-mentioned parasitic capacitance and short circuit problems, and can improve the reliability of the memory device.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

In the structure shown in FIG. 1, the bit line BL has not yet been formed, and only the position of the bit line BL is indicated by a dashed outline. In addition, for the sake of brevity, the active area AA is also drawn with a dotted line.

Please refer to FIG. 1, the memory device 10 of some embodiments of the present invention includes a plurality of active areas AA. The active area AA may be a doped area disposed in the substrate W. The multiple active areas AA can be separated from each other, and the positions of one or more transistors T can be defined respectively. For example, as shown in FIG. 1, two transistors T are formed in the same active area AA. In addition, the memory device 10 further includes a plurality of word lines WL, a plurality of initial bit line contact structures BC, and a plurality of capacitive contact structures CC. Each active area AA intersects at least one word line WL, and overlaps at least one initial bit line contact structure BC and at least one capacitor contact structure CC. For example, as shown in FIG. 1, each active area AA is interleaved with two word lines WL, and overlaps an initial bit line contact structure BC and two capacitor contact structures CC. The gate (not shown) of the transistor T located in the active area AA is electrically connected to the word line WL, and the source and drain (neither shown) of the transistor T are electrically connected to the initial bit line The contact structure BC and the capacitive contact structure CC. It can be seen that each word line WL can be located between an initial bit line contact structure BC and a capacitor contact structure CC. In some embodiments, referring to FIG. 1, two transistors T located in the same active area AA can share the same source/drain and the initial bit line contact structure BC electrically connected to the source/drain. Each initial bit line contact structure BC is configured to electrically connect one of the source and drain of the corresponding transistor T to a bit line BL (not yet formed at this time, only the bit line is shown in dashed lines) BL position), and each capacitive contact structure CC is configured to electrically connect the other of the source and drain of the corresponding transistor T to a storage capacitor (not shown). In some embodiments, the word line WL may be a buried word line and disposed in the substrate W, and the bit line BL and a storage capacitor (not shown) are disposed on the substrate W. Each transistor T and its corresponding storage capacitor (not shown) can be used as a memory cell of the DRAM integrated circuit, and the bit line BL and the word line WL can be configured to receive voltage to drive the DRAM integrated circuit. Memory unit.

In some embodiments, the plurality of word lines WL extend along the first direction D1 and are arranged along the second direction D2, and the plurality of bit lines BL extend along the second direction D2 and are arranged along the first direction D1. The first direction D1 and the second direction D2 are staggered. For example, the first direction D1 may be substantially orthogonal to the second direction D2. On the other hand, the multiple active areas AA extend along the third direction D3. The third direction D3 is staggered with the first direction D1 and the second direction D2. In some embodiments, the angle between the third direction D3 and the first direction D1 is 30° to 45°. In addition, a plurality of initial bit line contact structures BC may be arranged in an array along the first direction D1 and the second direction D2. Similarly, a plurality of capacitive contact structures CC can also be arranged in an array along the first direction D1 and the second direction D2. Each column of initial bit line contact structures BC arranged along the second direction D2 can overlap the bit line BL, and each initial bit line contact structure BC can be located in two adjacent capacitor contact structures in the first direction D1 Between CC. In some embodiments, as shown in FIG. 1, each capacitive contact structure CC only partially overlaps the active area AA below. In these embodiments, each capacitive contact structure CC can be regarded as being displaced toward the adjacent initial bit line contact structure BC, and the distance between the adjacent capacitive contact structure CC and the initial bit line contact structure BC can be shortened. In this way, the area of the memory cell of the DRAM integrated circuit can be reduced, and the storage density of the DRAM memory circuit can be improved.

Please refer to FIG. 2, in some embodiments, the top-view pattern of the initial bit line contact structure BC may be a parallelogram-like shape. Such a parallelogram can be regarded as a shape convex from the edge of a parallelogram, and has an arc-shaped contour. Viewed from another angle, this type of parallelogram can be similar to an ellipse. In these embodiments, the initial bit line contact structure BC may have a long axis AX. The extension direction AD of the long axis AX is different from the extension direction of the word line WL (that is, the first direction D1), the extension direction of the bit line BL (that is, the second direction D2), and the extension direction of the active area AA (that is, That is, the third party to D3). In addition, the extension direction AD of the long axis AX of the initial bit line contact structure BC is close to the extension direction of the active area AA (that is, the third direction D3), and it and the extension direction of the active area AA (that is, the third direction D3) The included angle A3 is smaller than the included angle A1 between it and the extending direction of the character line WL (that is, the first direction D1) or the included angle between it and the extending direction of the bit line BL (that is, the second direction D2) A2. For example, the included angle A3 may be 10° to 30°, and the included angle A1 and the included angle A2 may be 40° to 60° and 30° to 50°, respectively.

As shown in FIG. 2, the portion of the active area AA located between two adjacent word lines WL may be substantially a parallelogram area. The parallelogram area has a long diagonal line DG1 substantially overlapping the long axis AX of the initial bit line contact structure BC and a short diagonal line DG2 staggered with the long diagonal line DG1. Since the long axis AX of the initial bit line contact structure BC substantially overlaps the long axis DG1 of the parallelogram area, the initial bit line contact structure BC can cover the long diagonal DG1 of the parallelogram area of the active area AA. Two diagonal areas connected. In addition, in some embodiments, on the vertical projection plane perpendicular to the normal direction of the substrate W, the area of the initial bit line contact structure BC is larger than the area of the parallelogram area of the active area AA. In other words, the initial bit line contact structure BC can also cover the other two diagonal areas connected by the short diagonal DG of the parallelogram area of the active area AA. In this way, the part of the active area AA located between two adjacent word lines WL can be completely covered by the initial bit line contact structure BC. In addition, based on the extension direction AD of the long axis AX of the initial bit line contact structure BC close to the extension direction of the active area AA (that is, the third direction D3), the edge of the initial bit line contact structure BC can be as close as possible to the active area AA the edge of. In this way, it can be avoided that the initial bit line contact structure BC is electrically connected to the adjacent capacitive contact structure CC.

1 and 3, in the process of forming the bit line BL, some parts of the initial bit line contact structure BC shown in FIG. 1 can be removed to form the bit line contact structure BC' shown in FIG. 3 . In some embodiments, some parts of the initial bit line contact structure BC (as shown in FIG. 1) that do not overlap the bit line BL are removed, so that the formed bit line contact structure BC' (as shown in FIG. The opposite sides shown in 3) are substantially in line with the contour of the bit line BL. As shown in FIG. 3, the top view shape of the bit line contact structure BC' can be regarded as another parallelogram, and has a long axis AX'. The long axis AX' can be regarded as the longer one of a set of diagonal lines of the bit line contact structure BC'. The extension direction AD' of the long axis AX' is different from the extension direction of the word line WL (that is, the first direction D1), the extension direction of the bit line BL (that is, the second direction D2), and the extension direction of the active area AA ( That is, the third party to D3). In addition, the extension direction AD' of the long axis AX' of the bit line contact structure BC' is close to the extension direction of the active area AA (that is, the third direction D3), and it and the extension direction of the active area AA (that is, the third direction) The included angle A3' between D3) is smaller than the included angle A1' between it and the extension direction of the character line WL (ie the first direction D1) or the extension direction of the bit line BL (ie the second direction D2) The angle between A2'. For example, the included angle A3' may be 10° to 30°, and the included angle A1' and the included angle A2' may be 40° to 60° and 30° to 50°, respectively.

3 and 4, in some embodiments, a plurality of trench isolation structures TI are disposed in the substrate W. The trench isolation structure TI may be configured to separate a plurality of active areas AA formed in the substrate W. For example, the trench isolation structure TI may be a shallow trench isolation (STI) structure or a deep trench isolation (DTI) structure. In some embodiments, the bit line contact structure BC' is disposed in the substrate W, and is electrically connected to the lower active area AA and the upper bit line BL. In these embodiments, the bit line contact structure BC' is located on the top of the active area AA. In some embodiments, the sidewalls on opposite sides of the bit line contact structure BC' are substantially coplanar with the sidewalls of the upper bit line BL and the lower active area AA. In addition, the bit line contact structure BC' is located between adjacent capacitive contact structures CC. In some embodiments, the capacitive contact structure CC is disposed on the substrate W, and a plurality of contact plugs CP are respectively disposed between the plurality of capacitive contact structures CC and the plurality of active regions AA in the substrate W. As shown in FIG. 4, two adjacent contact plugs CP can be located on opposite sides of the bit line contact structure BC', and overlap the two active areas located on the opposite sides of the bit line contact structure BC' AA. In some embodiments, the contact plug CP extends from the top of the substrate W to the corresponding active area AA. In addition, in some embodiments, the contact plug CP can further extend into the trench isolation structure TI between it and the adjacent bit line contact structure BC'. In this way, the distance between the adjacent contact plug CP and the bit line contact structure BC' can be shortened, and the area of the memory cell of the DRAM can be reduced.

In some embodiments, a plurality of capacitive contact structures CC may be respectively disposed between two adjacent isolation structures WA. It should be noted that, for the sake of brevity, FIG. 1 to FIG. 3 do not show the isolation structure WA. Please refer to FIG. 4, the isolation structure WA covers the sidewall of the capacitive contact structure CC. In some embodiments, the isolation structure WA extends further down and is located between the adjacent bit line BL and the contact plug CP. Furthermore, in some embodiments, the isolation structure WA may further extend into the trench isolation structure TI, so that the extended portions of the isolation structure WA are located between the adjacent bit line contact structure BC' and the contact plug CP . In these embodiments, the bottom surface of the isolation structure WA may be lower than the bottom surface of the bit line contact structure BC' and the bottom surface of the contact plug CP, but higher than the bottom surface of the trench isolation structure TI.

The bit line BL is located between two adjacent capacitive contact structures CC (or between two adjacent contact plugs CP), and can be respectively connected to the adjacent capacitive contact structures CC (or in phase with each other through an isolation structure WA). The adjacent contact plugs CP) are isolated from each other. In some embodiments, the top surface of the bit line BL is lower than the top surface of the isolation structure WA and the top surface of the capacitive contact structure CC. In these embodiments, a dielectric structure DS may be disposed above the bit line BL. The dielectric structure DS is located between adjacent isolation structures WA and covers the top surface of the bit line BL. In some embodiments, the top surface of the dielectric structure DS is substantially coplanar with the top surface of the isolation structure WA and the top surface of the capacitive contact structure CC.

In some embodiments, the substrate W may be a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or the SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiC, SiGeC, and the like. The compound semiconductor may include a group III-V semiconductor material or a group II-VI semiconductor material. In some embodiments, the substrate W may be doped into a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type. In some embodiments, the material of the trench isolation structure TI in the substrate W is an insulating material. For example, the material of the trench isolation structure TI may respectively include silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof. In addition, the material of the word line (please refer to FIG. 1), the bit line contact structure BC' and the contact plug CP at least partially disposed in the substrate W may be conductive materials. In some embodiments, the materials of the word line WL, the bit line contact structure BC', and the contact plug CP respectively include doped or undoped polysilicon, metal materials (for example, tungsten), and the like. On the other hand, the material of the bit line BL and the capacitive contact structure CC on the substrate W is also a conductive material, for example, it includes doped or undoped polysilicon, titanium nitride, tungsten, the like or the like, respectively. Its combination. In addition, the dielectric structure DS on the substrate W is made of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof. In some embodiments, the isolation structure WA may be a single-layer structure, and the material of the single-layer structure may include silicon oxide or other low-k dielectric materials (for example, a dielectric material with a dielectric constant lower than 4). In an alternative embodiment, the isolation structure WA may be a multilayer structure, such as a silicon oxide-silicon nitride-silicon oxide (ONO) multilayer structure. In addition, in other embodiments, the isolation structure WA has an air gap.

In some embodiments, although not shown, a metal silicide layer may be provided between the contact plug CP and the capacitive contact structure CC and/or between the bit line contact structure BC' and the bit line BL. For example, the material of the metal silicide layer can include cobalt silicide (Co-silicide), titanium silicide (Ti-silicide), tungsten silicide (W-silicide), tantalum silicide (Ta-silicide), molybdenum silicide (Mo- silicide), its analogues or a combination thereof. By providing these metal silicide layers, the contact resistance between the contact plug CP and the capacitive contact structure CC and/or between the bit line contact structure BC' and the bit line BL can be reduced.

In some embodiments, the manufacturing method of the initial bit line contact structure BC shown in FIG. 1 includes a lithography process, an etching process, and a deposition process. By performing the lithography process and the etching process, a recess RS for accommodating the initial bit line contact structure BC can be defined on the surface of the substrate W (the dotted line shown in FIG. 4). The recess RS is located at the top of the active area AA, and can extend laterally into the adjacent trench isolation structure TI (filled by the isolation structure WA in the subsequent process, as shown in FIG. 4). Subsequently, a deposition process (such as a chemical vapor deposition process) may be performed to fill the recess RS with a conductive material to form the initial bit line contact structure BC. In some embodiments, the conductive material can initially extend to the portion outside the recess RS of the substrate W, and then the conductive material can be removed by a planarization process (for example, a chemical mechanical polishing process and/or an etching process). On the part of the substrate W other than the recess RS, the initial bit line contact structure BC is finally formed.

Please refer to Figure 1, Figure 4, Figure 5, in the lithography process for forming the initial bit line contact structure BC, the light emitted by the light source can first pass through the free-form lens array LN, and then The photomask PM is used to expose the photoresist pattern (not shown) formed on the substrate W. After the photoresist pattern is developed, an opening defining the contour of the recess RS can be formed in the photoresist pattern. Then, an etching process is performed on the substrate W (or the substrate W and the trench isolation structure TI) using the patterned photoresist pattern as a mask to form a recess RS (marked in FIG. 4). Subsequently, an initial bit line contact structure BC can be formed in the recess RS by a deposition process. In some embodiments, the aforementioned photoresist pattern is a negative photoresist. In these embodiments, the physical portion BP of the photomask PM overlaps the initial bit line contact structure BC, and the opening portion WP of the photomask PM surrounds the physical portion BP. Alternatively, a positive photoresist can also be used, and the opening portion WP of the photomask PM exposes the initial bit line contact structure BC, that is, the physical portion BP of the photomask PM surrounds the opening portion WP. In some embodiments, the special-shaped lens array LN includes a plurality of lenses LS. For example, as shown in FIG. 5, the special-shaped lens array LN includes 4 lenses LS. In an embodiment using a negative photoresist, a plurality of lenses LS may be arranged at a plurality of corners of the physical part BP of the photomask PM. For example, the physical part BP of the mask PM is rectangular, and four lenses LS are arranged at the four corners of the physical part BP. In this way, the four lenses LS are arranged along an outline similar to a parallelogram, and the diagonal of such a parallelogram substantially overlaps the long axis AX of the initial bit line contact structure BC. A pair of lenses LS of the plurality of lenses LS may be arranged in the extending direction AD of the long axis AX of the initial bit line contact structure BC. In addition, in an alternative embodiment using a positive photoresist, a plurality of lenses LS may be arranged at a plurality of corners of the opening part WP of the mask PM. In these alternative embodiments, the plurality of lenses LS can still be configured in the manner shown in FIG. 5, but the positions of the physical part BP and the opening part WP of the mask PM are reversed. Furthermore, in some embodiments, at least two of the plurality of lenses LS may have different shapes and/or areas. For example, as shown in FIG. 5, the area of the two lenses LS arranged along the extension direction AD of the long axis AX may be smaller than the area of the other two lenses LS, and the shapes may also be slightly different. Those with ordinary knowledge in the art can adjust the shape and size of the LS of each lens according to the shape of the initial bit line contact structure BC to be defined, and the embodiments of the present invention are not limited thereto.

It can be seen from the above that by adjusting the configuration of the special-shaped lens array LN, the path of the incident light passing through the photomask PM can be changed, and the shape of the formed recess RS or the initial bit line contact structure BC can be different from that of the photomask. The shape of the physical part BP of PM. In other words, the shape of the physical part BP of the mask PM does not need to be the same as the shape of the recess RS/initial bit line contact structure BC. In other words, the profile of the initial bit line structure BC can be fine-tuned by the configuration of the special-shaped lens array LN, without the need to change the pattern of the photomask PN.

Referring to FIG. 6, in other embodiments, a pair of lenses LS in the plurality of lenses LS each includes a plurality of sub-lenses LS'. For example, a pair of lenses LS arranged along the extension direction AD of the long axis AX includes two sub-lens LS', respectively. The two sub-lens LS' can be mirrored with respect to the long axis AX of the initial bit line contact structure BC. Those with ordinary knowledge in the field can also set other lenses LS to have multiple sub-lenses separated from each other according to design requirements. The embodiment of the present invention is not limited to the configuration of multiple lenses LS.

In summary, the memory device 10 of the embodiment of the present invention includes a word line WL, a bit line BL, an active area AA, a bit line contact structure BC' and a capacitor contact structure CC, and can be used as a DRAM device. The active area AA defines the position of one or more transistors T. The gate of the transistor T is electrically connected to the word line WL, and the drain and source of the transistor T are electrically connected to the bit line contact structure BC' and the capacitor contact structure CC. The bit line contact structure BC' is configured to electrically connect the active area AA to the bit line BL, and the capacitive contact structure CC is configured to electrically connect the active area AA to a storage capacitor (not shown). The word line WL extends along the first direction D1, and the bit line BL extends along the second direction D2 staggered with the first direction D1. On the other hand, the active area AA extends along a third direction D3 different from the first direction D1 and the second direction D2.

The part of the active area AA between two adjacent word lines WL may be a parallelogram. In addition, the initial structure of the bit line contact structure BC' (that is, the initial bit line contact structure BC as shown in FIGS. 1 and 2) covering some parallelogram portions of the active area AA has a parallelogram-like or elliptical-like shape The long axis AX of the initial structure (ie, the initial bit line contact structure BC) can substantially overlap the long diagonal DG1 of the parallelogram portions of the active area AA. In other words, the initial structure of the bit line contact structure BC' (that is, the initial bit line contact structure BC) can completely cover the active area AA when its contour is as close as possible to the edge of the parallelogram portion of the active area AA. The parallelogram part. In other words, when forming the initial structure of the bit line contact structure BC' (that is, the initial bit line contact structure BC), the top of the active area AA can be completely removed, and the subsequent formation of the bit line contact structure BC can be avoided 'There are still some parts of the active area AA around. Parasitic capacitance may be formed between these remaining parts of the active area AA and the bit line BL, and may cause a short circuit with the adjacent capacitance contact structure CC. Therefore, the bit line contact structure BC' formed by the manufacturing method of the present invention can avoid the above-mentioned parasitic capacitance and short circuit problems, and can improve the reliability of the memory device 10.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Memory components A1, A1’, A2’, A3’, A2, A3, A4, A5, A6: included angle AA: active area AD, AD’: Extension direction AX, AX’: long axis BC: Initial bit line contact structure BC’: Bit line contact structure BL: bit line BP: main part CC: Capacitive contact structure CP: contact plug D1: First direction D2: second direction D3: Third party DG1: Long diagonal DG2: short diagonal DS: Fill structure LN: lens array PM: photomask RS: recessed T: Transistor TI: trench isolation structure W: base WA: isolation structure WL: Character line WP: opening part

FIG. 1 illustrates a schematic top view of an intermediate structure of a manufacturing process of a memory device according to some embodiments of the present invention. FIG. 2 is an enlarged schematic diagram of the initial bit line contact structure and surrounding components of FIG. 1. FIG. 3 is a schematic top view of a memory device according to some embodiments of the present invention. Fig. 4 is a schematic cross-sectional view taken along the line X-X' of Fig. 3. 5 is a schematic top view of a free-form lens array and a mask pattern used to form the initial bit line contact structure shown in FIGS. 1 and 2. FIG. 6 is a schematic top view of a special-shaped lens array and a mask pattern in other embodiments.

10: Memory components

A1’, A2’, A3’: included angle

AA: active area

AD’: Extension direction

AX’: Long axis

BC’: Bit line contact structure

BL: bit line

CC: Capacitive contact structure

D1: First direction

D2: second direction

D3: Third party

T: Transistor

W: base

WL: Character line

Claims (13)

A memory device including: The character line is arranged in the substrate and extends along the first direction; Bit lines are arranged on the substrate and extend along a second direction, wherein the first direction is staggered with the second direction; The active area is disposed in the substrate and extends along a third direction, and is interleaved with the word line and the bit line, wherein the third direction is different from the first direction and the second direction ;as well as The bit line contact structure is disposed between the active area and the bit line, wherein the top view of the bit line contact structure has a long axis, and the extending direction of the long axis is the same as the first The angle between the three directions is smaller than the angle between the extension direction of the long axis and the first direction, and is smaller than the angle between the extension direction of the long axis and the second direction. The memory device according to claim 1, wherein the sidewalls on opposite sides of the bit line contact structure are substantially coplanar with the sidewalls on opposite sides of the bit line. The memory device according to the first item of the scope of patent application, wherein the top view shape of the bit line contact structure is a parallelogram-like shape. The memory device according to the third item of the scope of patent application, wherein the parallelogram-like shape has a partially arc-shaped outline. The memory device described in claim 1 further includes a capacitive contact structure electrically connected to the active area, wherein the word line is located between the capacitive contact structure and the bit line contact structure between. A method for manufacturing a memory element includes: Forming active regions, word lines, and initial bit line contact structures in the substrate; and Forming a bit line on the substrate, and removing a portion of the initial bit line contact structure that does not overlap the bit line to form a bit line contact structure, The word line extends in a first direction, the bit line extends in a second direction staggered in the first direction, and the active area is staggered along the word line and the bit line. Extending in a third direction different from the first direction and the second direction, and the bit line contact structure is disposed between the active area and the bit line, and The lithography process used to form the initial bit line contact structure includes the use of a special-shaped lens array so that light passes through the special-shaped lens array before being incident on the mask. The special-shaped lens array includes a plurality of lenses. A plurality of lenses are arranged along a parallelogram-like contour, the parallelogram-like contour has a long axis, and the angle between the extending direction of the long axis and the third direction is smaller than the extending direction of the long axis and the The included angle between the first direction and the included angle between the extending direction of the long axis and the second direction. According to the method of manufacturing a memory device described in item 6 of the scope of the patent application, the shape of the physical part or the opening part of the photomask used to define the initial bit line contact structure is different from that of the plurality of The arrangement shape of the lens. The method for manufacturing a memory device as described in claim 7, wherein the physical portion or the opening portion of the photomask is substantially rectangular and has a length substantially parallel to the first direction Direction and a width direction substantially parallel to the second direction. The method for manufacturing a memory device as described in claim 6, wherein the initial bit line contact structure is disposed on a part of the active area located on one side of the word line, and the active area The top view shape of the part is substantially a parallelogram and has long diagonals and short diagonals staggered with each other, and wherein the long axis of the initial bit line contact structure substantially overlaps the active area The long diagonal of the part. According to the method for manufacturing a memory device described in claim 9, wherein the initial bit line contact structure substantially completely covers the part of the active area. According to the method for manufacturing a memory device described in the scope of the patent application, the top view shape of the initial bit line contact structure is a parallelogram-like shape and has an arc-shaped outline. According to the manufacturing method of the memory device described in claim 6, wherein the initial bit line contact structure extends to two opposite sides of the active area along the first direction. According to the manufacturing method of the memory device described in the scope of patent application, before forming the bit line and the bit line contact structure, it further includes forming a trench isolation structure in the substrate, wherein the trench An isolation structure surrounds the active area, and an edge portion of the initial bit line contact structure extends into the trench isolation structure.

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