TWI830781B - Planarization method for semiconductor structure having memory modules - Google Patents

Abstract

A planarization method for semiconductor structure having memory modules is provided. A dielectric layer is formed on a substrate structure having memory modules, and a contour surface of the dielectric layer has a plurality of protrusions respectively corresponding to the memory modules. A mask layer is conformally formed on the contour surface and the mask layer includes top portions that respectively cover the top surfaces of the protrusions, wherein the mask layer and the dielectric layer have a polishing selectivity. Then, the top portions of the mask layer are removed, so that a plurality of openings is formed on the mask layer to respectively expose the top surfaces of the protrusions. Then, the mask layer is used as a mask, to at least remove the protrusions exposed through the opening. Finally, the mask layer is removed and portion of the dielectric layer is polished, to make the dielectric layer has a substantially planar second surface, wherein a spacing is between the second surface and the memory modules. This planarization method has the advantage of reducing material costs.

Description

Planarization method of semiconductor structure with memory module

The present invention relates to a semiconductor manufacturing process, and in particular to a planarization method of a semiconductor structure with a memory module.

Many modern electronic devices have electronic memories, among which non-volatile memory can retain its stored data even if the power supply is interrupted. Currently, a magnetoresistive random-access memory (MRAM) is A non-volatile random access memory that has gained popularity in recent years. For example, MRAM includes magnetic tunnel junctions (MTJ) devices that use magnetic polarization to store information. For example, MRAM devices include MTJ stacks with multiple magnetic layers. These MTJ stack layers are generally connected to interconnects in the interlayer dielectric layer (ILD).

However, in some processes of semiconductor devices including MRAM, the MRAM protrudes from the semiconductor device. Therefore, when the dielectric layer covering the MRAM is subsequently planarized and polished, too much of the dielectric layer must be polished off to meet the planarization requirements. , causing an increase in material costs.

The present invention provides a method for planarizing a semiconductor structure with a memory module, which can meet the planarization requirements without grinding off excessive dielectric layers, and has the advantage of reducing material costs.

The planarization method of a semiconductor structure with a memory module provided by the present invention includes: providing a semiconductor device, the semiconductor device includes a substrate structure and a plurality of memory modules, the substrate structure has a first surface, and the memory modules each have at least It includes a multi-layer material cylinder protruding from the first surface; a dielectric layer is formed on the substrate structure and covers the multi-layer material cylinder, wherein the dielectric layer has a contour surface, and the contour surface has a plurality of protrusions corresponding to the plurality of multi-layers. The material cylinder has a top surface and a side wall respectively; a masking layer is formed, and the masking layer conformally covers the contour surface with the convex part, wherein the masking layer includes a plurality of high tops respectively covering the convexities. On the top surface of the part, there is a grinding selectivity ratio between the mask layer and the dielectric layer; remove the high top of the mask layer to form multiple openings in the mask layer to respectively expose the top surface of the convex part; use the mask layer As a mask, at least the protrusions exposed through the openings are removed; the mask layer is removed; and a portion of the dielectric layer is ground so that the dielectric layer has a substantially flat second surface, wherein the second surface is in contact with the multi-layer material cylinder Keep spacing between them.

In an embodiment of the present invention, the above-mentioned grinding selectivity ratio is greater than 20. In an embodiment of the present invention, the material of the above-mentioned dielectric layer is ultra-low-k material (ULK).

In an embodiment of the invention, the mask layer includes a metal layer. In one embodiment, the metal layer is made of tungsten, copper or aluminum.

In one embodiment of the invention, the memory module is a magnetoresistive random access memory (MRAM).

In one embodiment of the present invention, a first chemical mechanical polishing process is used to remove the high top portion of the mask layer, and a second chemical mechanical polishing process is used to remove the mask layer.

In one embodiment of the present invention, the protrusions are removed through an etching back process until the protrusions are removed and a plurality of shallow recesses are formed on the contour surface, and the bottoms of the shallow recesses are lower than the mask layer.

In one embodiment of the present invention, the above-mentioned step of grinding a portion of the dielectric layer continues until the shallow depressions are eliminated and the dielectric layer has a substantially flat second surface.

In an embodiment of the present invention, the thickness of the mask layer is between 10 nanometers and 20 nanometers.

In the present invention, a mask layer is conformally covered on the contour surface of the dielectric layer with the convex portion, and there is a grinding selectivity ratio between the mask layer and the dielectric layer, and openings are formed in the mask layer to correspond to the The raised portion is removed through an etching back process through the opening, and then the mask layer is removed and the dielectric layer is subjected to a planarization process of chemical mechanical polishing. Since the protrusions of the dielectric layer have been removed first, planarization requirements can be achieved without grinding off too much of the dielectric layer, which has the advantage of reducing material costs.

In order to make the above and other objects, features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

1A to 1G are schematic cross-sectional structural diagrams of the process of a planarization method of a semiconductor structure with a memory module according to an embodiment of the present invention. As shown in FIG. 1A , a semiconductor device 10 is provided. The semiconductor device 10 includes a substrate structure 12 and a plurality of memory modules 14 . The substrate structure 12 has a first surface 121, and a plurality of memory modules 14 are protrudingly disposed on the first surface 121. In one embodiment, the memory modules 14 are, for example, magnetoresistive random access memories (MRAM). The memory module 14 at least includes a multi-layer material cylinder 16. The multi-layer material cylinder 16 includes, for example, an upper electrode layer 18, a magnetic tunnel junction stack layer 20 and a lower electrode layer 22. In one embodiment, the multi-layer material cylinder 16 The height H1 of the protruding first surface 121 is, for example, 175 nanometers, and the distance D1 between two adjacent multi-layer material pillars 16 is, for example, 110 nanometers. In one implementation, the semiconductor device 10 further includes a logic circuit module (not shown) disposed on the substrate structure 12 .

As shown in FIG. 1B , a dielectric layer 24 is formed on the substrate structure 12 . The dielectric layer 24 covers the first surface 121 and the multi-layer material cylinder 16 . The material of the dielectric layer 24 is, for example, an ultra-low dielectric material. The constant is, for example, less than about 2.5. The side of the dielectric layer 24 away from the first surface 121 has a profile surface 241. The profile surface 241 has a plurality of protrusions 26, and the plurality of protrusions 26 respectively correspond to a plurality of multi-layer material cylinders 16. , in one embodiment, the raised portion 26 has a top surface 261 and a side wall 262, and the side wall 262 connects the top surface 261 and the contour surface 241. The distance D2 (ie, the general thickness of the dielectric layer) between the partial contour surface 241 without the protruding portion 26 and the first surface 121 is, for example, 215 nanometers.

Next, as shown in 1C, the mask layer 28 is formed, and the mask layer 28 conformally covers the contour surface 241 with the protruding portion 26. Since the mask layer 28 conformally covers the contour surface 241, the mask layer 28 conformally covers the contour surface 241. The mask layer 28 includes a plurality of high tops 281 covering the top surface 261 of the protruding portion 26. In one embodiment, the thickness of the mask layer 28 is between 10 nanometers and 20 nanometers. There is a polishing selectivity ratio between the mask layer 28 and the dielectric layer 24. In one embodiment, the mask layer 28 includes silicon nitride, silicon nitride carbide, silicon oxynitride, metal, metal nitride, metal oxide, Or a combination thereof. The metal material can be tungsten, copper, titanium, tantalum, hafnium, zinc, zirconium or aluminum. In one embodiment, the grinding selectivity ratio between the mask layer 28 and the dielectric layer 24 is greater than 20. The polishing rate of the dielectric layer 24 is greater than the polishing rate of the mask layer 28 . In one embodiment, the mask layer 28 is a double-layer structure of titanium nitride and tungsten.

Thereafter, as shown in FIG. 1D , the high top portion 281 of the mask layer 28 is removed to form a plurality of openings 282 in the mask layer 28 , and the top surfaces 261 of the protruding portions 26 are respectively exposed through the openings 282 . In one embodiment, the high top portion 281 (shown in FIG. 1C ) is removed by a chemical mechanical polishing process, for example. Next, using the mask layer 28 with the opening 282 as a mask, as shown in FIG. 1E , at least the protruding portion 26 exposed through the opening 282 of the mask layer 28 is removed. In one embodiment, the protrusions 26 are removed through an etching back process until the protrusions 26 are removed and a plurality of shallow recesses 30 are formed on the contour surface 241 , wherein the bottoms 301 of the shallow recesses 30 are lower than the mask. Layer 28.

Next, the mask layer 28 is removed. In one embodiment, the mask layer 28 is removed by a chemical mechanical polishing process or an etching process. As shown in FIG. 1F , with the removal of the mask layer 28 , the dielectric layer 24 There are still a plurality of shallow concave portions 30 on the contour surface 241, but there are no longer convex portions 26 with large height differences. Finally, the chemical mechanical polishing process is used to polish part of the dielectric layer 24 again, as shown in FIG. 1G , so that the dielectric layer 24 has a substantially flat second surface 242 , where the step of polishing the part of the dielectric layer 24 continues until the shallow recess 30 is eliminated. And there is a distance D3 between the substantially flat second surface 242 of the dielectric layer 24 and the multi-layer material pillar 16 .

According to the above, in the planarization method of the semiconductor structure with the memory module according to the embodiment of the present invention, a mask layer is first used to conformally cover the contour surface of the dielectric layer with the convex portion, wherein the mask layer and the dielectric layer There is a grinding selectivity ratio between the electrical layers, and openings are formed in the mask layer to correspond to the protrusions. After the protrusions are removed by etching back through the openings, the mask layer is removed, and finally the dielectric layer is Chemical mechanical polishing planarization process. This design of first removing the protrusions of the dielectric layer through the openings of the mask layer with a grinding selectivity helps to achieve the final planarization without grinding off too much of the dielectric layer. Planarization requirements have the advantage of reducing material costs.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

10:Semiconductor devices 12:Substrate structure 121: First surface 14:Memory module 16:Multilayer material cylinder 18: Upper electrode layer 20: Magnetic tunnel junction stack layer 22: Lower electrode layer H1: height D1, D2, D3: spacing 24: Dielectric layer 241:Contour surface 242: Second surface 26:Protruding part 261:Top surface 262:Side wall 28:Mask layer 281:High top 282:Open your mouth 30:Shallow concave part 301: Bottom

1A to 1G are schematic cross-sectional structural diagrams of the process of a planarization method of a semiconductor structure with a memory module according to an embodiment of the present invention.

24: Dielectric layer

241:Contour surface

28:Mask layer

30:Shallow concave part

301: Bottom

Claims (8)

A method for planarizing a semiconductor structure with a memory module includes: providing a semiconductor device, the semiconductor device includes a substrate structure and a plurality of memory modules, the substrate structure has a first surface, and the memory modules The group respectively includes at least one multi-layer material cylinder protruding from the first surface; forming a dielectric layer on the substrate structure and covering the multi-layer material cylinder, wherein the dielectric layer has a contour surface, and the contour surface The surface has a plurality of raised parts respectively corresponding to the multi-layer material cylinders, and the raised parts respectively have a top surface and a side wall; forming a masking layer, the masking layer conformally covers the surfaces with the raised parts. On the contour surface of the raised portion, the mask layer includes a plurality of high tops respectively covering the top surfaces of the raised portions, and there is a grinding selectivity ratio between the mask layer and the dielectric layer; remove The high tops of the mask layer are used to form a plurality of openings in the mask layer to expose the top surfaces of the protrusions respectively; using the mask layer as a mask, at least remove the top surfaces exposed through the openings. The protrusions, wherein the protrusions are removed by an etching back process until the protrusions are removed and the contour surface forms a plurality of shallow recesses, and the bottoms of the shallow recesses are lower than the mask layer; Remove the mask layer; and grind a portion of the dielectric layer until the shallow depressions are eliminated, so that the dielectric layer has a substantially flat second surface, wherein the second surface is in contact with the multi-layer material cylinders Leave some space between them. The method for planarizing a semiconductor structure with a memory module as claimed in claim 1, wherein the grinding selectivity ratio is greater than 20. The planarization method of a semiconductor structure with a memory module as claimed in claim 1, wherein the mask layer includes a metal layer, metal nitride, metal oxide, silicon nitride, silicon nitride carbide, silicon oxynitride or combination thereof. The method for planarizing a semiconductor structure with a memory module as claimed in claim 3, wherein the metal layer is made of tungsten, copper, titanium, tantalum, hafnium, zinc, zirconium or aluminum. The planarization method of a semiconductor structure with a memory module as claimed in claim 1, wherein the material of the dielectric layer is an ultra-low dielectric material (ULK). The planarization method of a semiconductor structure with memory modules as claimed in claim 1, wherein the memory modules are magnetoresistive random access memories (MRAM). The planarization method of a semiconductor structure with a memory module as claimed in claim 1, wherein a first chemical mechanical polishing process is used to remove the high tops of the mask layer, and a second chemical mechanical polishing process is used to remove the high tops of the mask layer. Remove this mask layer. The planarization method of a semiconductor structure with a memory module as claimed in claim 1, wherein the thickness of the mask layer is between 10 nanometers and 20 nanometers.

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