TWI813789B - Method for planarizing semiconductor structure - Google Patents

Abstract

A method for planarizing semiconductor structure is provided. A dielectric layer is formed on a substrate structure having a pluraliry of memory modules, and the contour surface of the dielectric layer has a plurality of first protruding platforms and second protruding platforms, wherein the distribution of the first protruding platforms corresponds to the distribution of the memory modules having higher patent density and the distribution of the second protruding platforms corresponds to the distribution of the memory modules having lower patent density. An etch back process is performed to form the first recess on the top surface of each first protruding platform and form the second recess on the top surface of each second protruding platform, wherein the remaining wall between the inner side wall of each first recess and the outer side wall of each first protruding platform has a first thickness, the remaining wall between the inner side wall of each second recess and the outer side wall of each second protruding platform has a second thickness, and the first thickness is greater than the second thickness. Then, the portion of the dielectric layer is polished, the walls are removed and the dielectric layer has a substantially flat surface.

Description

Planarization Methods for Semiconductor Structures

The present invention relates to a semiconductor manufacturing process, and in particular to a planarization method of a semiconductor structure.

During the fabrication of semiconductor devices, it is often necessary to planarize the surface of the semiconductor device in one or more fabrication steps, wherein chemical mechanical polishing is a process for planarizing the surface of the semiconductor device. However, due to different layouts on semiconductor devices, uneven thickness is easily caused by the interaction between the layout and the grinding process. Therefore, it is difficult to ensure the uniformity of planarization.

On the other hand, many modern electronic devices have electronic memories, in which non-volatile memory can retain its stored data even if the power supply is interrupted. Currently, a magnetoresistive random-access memory (Magnetoresistive random-access memory, MRAM) Compared with volatile memories such as dynamic random access memory (DRAM) and static random access memory (SRAM), MRAM not only has similar performance and density, but also has a lower power consumption and has become one of the next generation of promising non-volatile electronic memories.

However, in some processes of semiconductor devices including MRAM, the MRAM protrudes from the semiconductor device, and the aggregation density of MRAM on the semiconductor device is not the same, so that when the dielectric layer covering the MRAM is polished using a chemical mechanical polishing process, it may This will cause over-grinding in some areas and under-grinding in some areas, resulting in within-die inconsistencies.

The present invention provides a method for planarizing a semiconductor structure, which is helpful for producing semiconductor components with better component characteristics.

The planarization method of a semiconductor structure provided by the present invention includes: providing a semiconductor device, the semiconductor device includes a substrate structure and a plurality of memory modules, the substrate structure has a first surface, and the memory modules are protrudingly disposed on the first surface, The configuration of the memory module is at least divided into a first area and a second area. The distribution of the memory module in the first area and the second area has a first pattern density and a second pattern density respectively, and the first pattern density is greater than the second area. Two pattern densities; forming a dielectric layer on the substrate structure and covering the first surface and the memory module, wherein the dielectric layer has a contour surface, and the contour surface has a plurality of first raised platforms and a plurality of second raised platforms. , the first raised platform corresponds to part of the memory module in the first area, and the second raised platform corresponds to part of the memory module in the second area, wherein each first raised platform has a first top surface and a first outer side wall, each second raised platform has a second top surface and a second outer side wall; an etching back process is performed to form first recesses on the first top surface of the first raised platform, respectively. A second recess is formed on the second top surface of the second raised platform, wherein each first recess has a first inner wall, a first wall is formed between the first inner wall and the first outer wall, and the first wall has a first thickness, each second recess has a second inner wall, a second wall is formed between the second inner wall and the second outer wall, the second wall has a second thickness, wherein the first thickness is greater than the second thickness; and grinding part of the dielectric layer to remove the first wall portion and the second wall portion, so that the dielectric layer has a substantially flat second surface.

In an embodiment of the invention, the first recess and the second recess have the same depth.

In an embodiment of the present invention, the first raised platform and the second raised platform have a first height and a second height respectively, and the depths of the first recessed portion and the second recessed portion are smaller than the first height and the second height.

In an embodiment of the present invention, the above-mentioned second thickness is greater than or equal to 0.2 microns.

In an embodiment of the present invention, the first raised platform and the second raised platform are trapezoid-shaped.

In an embodiment of the present invention, the first thickness is the shortest distance between the first inner wall and the first outer wall, and the second thickness is the shortest distance between the second inner wall and the second outer wall.

In one embodiment of the present invention, before performing the above-mentioned etchback process, a reverse mask layer is formed to cover the dielectric layer. The reverse mask layer has a plurality of first opening patterns and a plurality of second opening patterns. The distribution of the first opening pattern and the second opening pattern respectively correspond to the distribution of the first raised platform and the second raised platform.

In an embodiment of the present invention, the material of the above-mentioned dielectric layer is ultra-low-k material (ULK).

In one embodiment of the invention, the memory module is a magnetoresistive random access memory (MRAM).

In the present invention, a first recess is formed on the first raised platform with a higher distribution pattern density and the first wall portion is retained, and a second recessed portion is formed on the second raised platform with a lower distribution pattern density and the second wall portion is retained, wherein, Since the thickness of the first wall portion is greater than the thickness of the second wall portion, it will be helpful to avoid causing certain problems when the dielectric layer having the first wall portion and the second wall portion is subsequently polished by a chemical mechanical polishing process. Some areas are over-polished and some areas are under-polished, resulting in within-die inconsistencies. The planarization method of the semiconductor structure will help to produce semiconductor devices with better device characteristics.

In order to make the above and other objects, features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

1A to 1D are schematic cross-sectional structural diagrams of the process of a planarization method of a semiconductor structure according to an embodiment of the present invention. As shown in FIG. 1A , a semiconductor device 10 is provided. The semiconductor device 10 includes a substrate structure 12 and a plurality of memory modules 14 . The substrate structure 12 has a first surface 121, and a plurality of memory modules 14 are protrudingly disposed on the first surface 121. In one embodiment, the memory modules 14 are, for example, magnetoresistive random access memories (MRAM). The memory module 14 has different distribution densities on the substrate structure 12. The substrate structure 12 has, for example, a first area Z1 and a second area Z2. The distribution of the memory module 14 in the first area Z1 has a first pattern density. The distribution of the body mold group 14 in the second zone Z2 has a second pattern density. In one embodiment, the first pattern density is greater than the second pattern density. In order to facilitate understanding and description of the embodiment of the present invention, in FIG. 1A , there are four sets of memory modules 14 in the first zone Z1 and two sets of memory modules 14 in the second zone Z2 as an example, but it is not limited to this. .

As shown in FIG. 1B , a dielectric layer 16 is formed on the substrate structure 12 . The dielectric layer 16 covers the first surface 121 and the memory module 14 . The material of the dielectric layer 16 is, for example, an ultra-low dielectric material. The side of the dielectric layer 16 away from the first surface 121 has a profile surface 161. The profile surface 161 has a plurality of first raised platforms 18 and a plurality of second raised platforms 20. The first raised platforms 18 correspond to the first raised platform 18 and the second raised platform 20. For some or all of the memory modules 14 in the first zone Z1, the second raised platform 20 corresponds to some or all of the memory modules 14 in the second zone Z2. In one embodiment, the first raised platform 18 and the second raised platform 20 are, for example, trapezoid-shaped. Each first raised platform 18 has a first top surface 181 and a first outer wall 182 . The first outer wall 182 Connecting the first top surface 181 and the contour surface 161 , each second raised platform 20 has a second top surface 201 and a second outer side wall 202 . The second outer side wall 202 connects the second top surface 201 and the contour surface 161 . In one embodiment, the first raised platform 18 has a first height H1, and the second raised platform 20 has a second height H2, where the first height H1 is the longitudinal distance from the first top surface 181 to the contour surface 161, and The second height H2 is the longitudinal distance from the second top surface 201 to the contour surface 161. In one embodiment, the first height H1 may be greater than or equal to the second height H2.

Next, as shown in FIG. 1C , an etching back process is performed to form the first recess 22 on the first top surface 181 of the first raised platform 18 and the second top surface 201 of the second raised platform 20 respectively. The second recessed portion 24 , wherein each first recessed portion 22 has a first inner wall 221 , a first wall portion 26 is formed between the first inner wall 221 and the first outer wall 182 , and the first wall portion 26 has a first thickness d1 , in one embodiment, the first thickness d1 is the shortest distance between the first inner wall 221 and the first outer wall 182; each second recess 24 has a second inner wall 241, a second inner wall 241 and a second inner wall 241. A second wall portion 28 is formed between the outer side walls 202. The second wall portion 28 has a second thickness d2. In one embodiment, the second thickness d2 is the shortest distance between the second inner side wall 241 and the second outer side wall 202. . Please also refer to FIG. 2 . FIG. 2 is a schematic diagram of the first recess, the second recess, the first wall part and the second wall part according to an embodiment of the present invention. FIG. 2 mainly illustrates the first thickness of the first wall part 26 The relationship between d1 and the second thickness d2 of the second wall portion 28, wherein the first thickness d1 of the first wall portion 26 located in the first zone Z1 is greater than the second thickness d1 of the second wall portion 28 located in the second zone Z2 Thickness d2.

Continuing with the above description, in one embodiment, as shown in FIG. 1C , the first recess 22 and the second recess 24 have the same depth D, and the depth D of the first recess 22 and the second recess 24 is smaller than the first raised platform. 18 and the second height H2 of the second raised platform 20 . The second thickness d2 of the thinner second wall portion 28 is greater than or equal to 0.2 microns. In one embodiment, when the first pattern density is, for example, about 4.41%, the first thickness d1 is 0.5 microns. When the pattern density is, for example, about 1.71%, the second thickness d2 is 0.2 microns.

In a figure not shown, before performing the etching back process, a reverse mask layer is formed to cover the dielectric layer 16. The reverse mask layer has a plurality of first opening patterns and a plurality of second opening patterns. The distribution of the first opening pattern and the second opening pattern respectively correspond to the distribution of the first raised platform 18 and the second raised platform 20, so that the reverse mask layer can be used as a mask to perform an etching back process on the dielectric layer 16. . In one embodiment, under the premise that the first raised platform 18 and the second raised platform 20 have the same size, the size of the first opening pattern is smaller than the size of the second opening pattern, so that the first opening pattern is smaller during the etching back process. The raised platform 18 may retain the thicker first wall portion 26 .

As shown in FIG. 1D , after performing the etch back process, a chemical mechanical polishing process is used to polish part of the dielectric layer 16 to remove the first wall portion 26 (shown in FIG. 1C ) and the second wall portion 28 (shown in FIG. 1C ), in one embodiment, the chemical mechanical polishing process further removes part of the contour surface 161, so that the dielectric layer 16 has a substantially flat second surface 162.

According to the above, in the planarization method of the semiconductor structure according to the embodiment of the present invention, the first recess is formed on the first bump platform with a higher distribution pattern density and the first wall portion is retained, and the first recess is formed on the second bump with a lower distribution pattern density. The platform forms a second recess and retains the second wall. The thickness of the first wall is greater than the thickness of the second wall, which will facilitate the subsequent chemical mechanical polishing process of the first wall and the second wall. When the dielectric layer is polished, it will not cause over-polishing in some areas and insufficient polishing in some areas, resulting in within-die inconsistencies. The planarization method of the semiconductor structure will help to produce semiconductor devices with better device characteristics.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

10:Semiconductor devices 12:Substrate structure 121: First surface Z1: Zone 1 Z2: The second zone 14:Memory module 16: Dielectric layer 161:Contour surface 162: Second surface 18:The first raised platform 181:First top surface 182:First outer wall 20: The second raised platform 201:Second top surface 202:Second outer wall H1: first height H2: second height 22: First concave part 221:First inner wall 24:Second recess 241:Second inner wall 26:The first wall d1: first thickness 28:Second Wall d2: second thickness D: Depth

1A to 1D are schematic cross-sectional structural diagrams of the process of a planarization method of a semiconductor structure according to an embodiment of the present invention. FIG. 2 is a schematic diagram of the first recessed part, the second recessed part, the first wall part and the second wall part according to an embodiment of the present invention.

Z1: Zone 1

Z2: The second zone

16: Dielectric layer

161:Contour surface

18:The first raised platform

181:First top surface

182:First outer wall

20: The second raised platform

201:Second top surface

202:Second outer wall

H1: first height

H2: second height

22: First concave part

221:First inner wall

24:Second recess

241:Second inner wall

26:The first wall

d1: first thickness

28:Second Wall

d2: second thickness

D: Depth

Claims (9)

A method for planarizing semiconductor structures, including: A semiconductor device is provided. The semiconductor device includes a substrate structure and a plurality of memory modules. The substrate structure has a first surface. The memory modules are protrudingly disposed on the first surface. The memory modules The configuration is at least divided into a first area and a second area, the distribution of the memory modules in the first area and the second area has a first pattern density and a second pattern density respectively, and the A pattern density is greater than the second pattern density; A dielectric layer is formed on the substrate structure and covers the first surface and the memory modules, wherein the dielectric layer has a profile surface with a plurality of first raised platforms and a plurality of third Two raised platforms, the first raised platforms correspond to some of the memory modules in the first area, and the second raised platforms correspond to some of the memory modules in the second area. , wherein each first raised platform has a first top surface and a first outer wall, and each second raised platform has a second top surface and a second outer wall; An etching back process is performed to form a first recessed portion on the first top surfaces of the first raised platforms respectively, and a first recessed portion is formed on the second top surfaces of the second raised platforms respectively. Two recessed parts, each of the first recessed parts has a first inner wall, a first wall part is formed between the first inner wall and the first outer wall, the first wall part has a first thickness, each The second recess has a second inner wall. A second wall is formed between the second inner wall and the second outer wall. The second wall has a second thickness, wherein the first thickness is greater than the second wall. 2 thickness; and Grinding part of the dielectric layer to remove the first wall portions and the second wall portions so that the dielectric layer has a substantially flat second surface. The planarization method of a semiconductor structure as claimed in claim 1, wherein the first recesses and the second recesses have the same depth. The planarization method of a semiconductor structure as claimed in claim 2, wherein the first raised platforms and the second raised platforms respectively have a first height and a second height, and the first recesses and the The depths of the second recesses are smaller than the first height and the second height. The planarization method of a semiconductor structure as claimed in claim 1, wherein the second thickness is greater than or equal to 0.2 microns. The planarization method of a semiconductor structure as claimed in claim 1, wherein the first raised platforms and the second raised platforms are in a trapezoidal shape. The planarization method of a semiconductor structure as claimed in claim 5, wherein the first thickness is the shortest distance between the first inner wall and the first outer wall, and the second thickness is the shortest distance between the second inner wall and the first outer wall. The shortest distance between the second outer side walls. The planarization method of a semiconductor structure as claimed in claim 1, wherein before performing the etching back process, a reverse mask layer is formed to cover the dielectric layer, and the reverse mask layer has a plurality of first opening patterns. And a plurality of second opening patterns, the distribution of the first opening patterns and the second opening patterns respectively correspond to the distribution of the first raised platforms and the second raised platforms. The planarization method of a semiconductor structure as claimed in claim 1, wherein the material of the dielectric layer is ultra-low dielectric material (ULK). The planarization method of a semiconductor structure as claimed in claim 1, wherein the memory modules are magnetoresistive random access memories (MRAM).

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