TW202113973A - Planarization method for semiconductor structure having memory modules - Google Patents

Abstract

A planarization method for semiconductor structure having memory modules is provided. A dielectric layer is formed on a substrate structure having memory modules, and a contour surface of the dielectric layer has a plurality of protrusions respectively corresponding to the memory modules. A mask layer is conformally formed on the contour surface and the mask layer includes top portions that respectively cover the top surfaces of the protrusions, wherein the mask layer and the dielectric layer have a polishing selectivity. Then, the top portions of the mask layer are removed, so that a plurality of openings is formed on the mask layer to respectively expose the top surfaces of the protrusions. Then, the mask layer is used as a mask, to at least remove the protrusions exposed through the opening. Finally, the mask layer is removed and portion of the dielectric layer is polished, to make the dielectric layer has a substantially planar second surface, wherein a spacing is between the second surface and the memory modules. This planarization method has the advantage of reducing material costs.

Description

Method for planarizing semiconductor structure with memory module

The present invention relates to a semiconductor manufacturing process, in particular to a method for planarizing a semiconductor structure with a memory module

Many modern electronic devices have electronic memory. Among them, non-volatile memory can retain its stored data in the event of power interruption. At present, a magnetoresistive random-access memory (MRAM) is A non-volatile random access memory that has become popular in recent years. For example, MRAM includes magnetic tunnel junctions (MTJ) devices that use magnetic polarization to store information. For example, MRAM devices include MTJ stacked layers with a plurality of magnetic layers. These MTJ stack layers are generally connected to interconnects in the interlayer dielectric layer (ILD).

However, in part of the manufacturing process of semiconductor devices containing MRAM, MRAM protrudes from the semiconductor device. Therefore, when the subsequent dielectric layer covering MRAM is planarized and polished, too much dielectric layer must be polished to meet the requirements of planarization. , Resulting in an increase in material costs.

The present invention provides a method for planarizing a semiconductor structure with a memory module, which can achieve the requirements of planarization without grinding off excessive dielectric layers, and has the advantage of reducing material costs.

The planarization method of a semiconductor structure with a memory module provided by the present invention includes: providing a semiconductor device. The semiconductor device includes a substrate structure and a plurality of memory modules, the substrate structure has a first surface, and the memory modules are at least Containing multilayer material pillars protruding from the first surface; forming a dielectric layer on the substrate structure and covering the multilayer material pillars, wherein the dielectric layer has a contour surface, and the contour surface has a plurality of protrusions corresponding to the plurality of multilayers, respectively Material column, the protrusions respectively have a top surface and side walls; a mask layer is formed, and the mask layer conformally covers the contour surface with the protrusions, wherein the mask layer includes a plurality of high tops respectively covering the protrusions The top surface of the mask layer has a polishing selection ratio between the mask layer and the dielectric layer; the high top part of the mask layer is removed to form a plurality of openings in the mask layer to respectively expose the top surface of the protrusion; with the mask layer As a mask, at least the protrusions exposed through the opening are removed; the mask layer is removed; and a part of the dielectric layer is polished so that the dielectric layer has a substantially flat second surface, wherein the second surface and the multilayer material column Leave space between them.

In an embodiment of the present invention, the aforementioned polishing selection ratio is greater than 20. In an embodiment of the present invention, the material of the above-mentioned dielectric layer is an ultra-low dielectric material (ULK).

In an embodiment of the present invention, the above-mentioned mask layer includes a metal layer. In one embodiment, the material of the metal layer is tungsten, copper or aluminum.

In an embodiment of the present invention, the above-mentioned memory module is a magnetoresistive random access memory (MRAM).

In an embodiment of the present invention, the high top of the mask layer is removed by the first chemical mechanical polishing process, and the mask layer is removed by the second chemical mechanical polishing process.

In an embodiment of the present invention, the protrusions are removed by an etch-back process until the protrusions are removed and a plurality of shallow recesses are formed on the contour surface, and the bottom of the shallow recesses is lower than the mask layer.

In an embodiment of the present invention, the above-mentioned step of grinding a part of the dielectric layer continues until the shallow recesses are eliminated and the dielectric layer has a substantially flat second surface.

In an embodiment of the present invention, the thickness of the aforementioned mask layer is between 10 nanometers and 20 nanometers.

In the present invention, a mask layer is conformally covered on the contour surface of the dielectric layer with protrusions, and there is a polishing selection ratio between the mask layer and the dielectric layer, and an opening is formed in the mask layer to correspond to For the protrusions, the protrusions are removed by an etch-back process through the opening, and then the mask layer is removed and the dielectric layer is subjected to a planarization process of chemical mechanical polishing. Since the protrusions of the dielectric layer have been removed first, there is no need to grind off too much dielectric layer to meet the requirements of planarization, which has the advantage of reducing material costs.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific examples are given in conjunction with the accompanying drawings, which are described in detail as follows.

1A to 1G are schematic cross-sectional structure diagrams of the process of a planarization method of a semiconductor structure with a memory module according to an embodiment of the present invention. As shown in FIG. 1A, a semiconductor device 10 is provided. The semiconductor device 10 includes a substrate structure 12 and a plurality of memory modules 14. The substrate structure 12 has a first surface 121, and a plurality of memory modules 14 are protrudingly disposed on the first surface 121. In one embodiment, the memory modules 14 are, for example, magnetoresistive random access memory (MRAM). The memory module 14 at least includes a multi-layer material column 16 which includes, for example, an upper electrode layer 18, a magnetic tunnel junction stack layer 20, and a lower electrode layer 22. In one embodiment, the multi-layer material column 16 The height H1 of the protruding first surface 121 is, for example, 175 nm, and the distance D1 between two adjacent multilayer material pillars 16 is, for example, 110 nm. In one implementation, the semiconductor device 10 further includes a logic circuit module (not shown in the figure) disposed on the substrate structure 12.

As shown in FIG. 1B, a dielectric layer 24 is formed on the substrate structure 12. The dielectric layer 24 covers the first surface 121 and the multi-layer material column 16. The material of the dielectric layer 24 is, for example, an ultra-low dielectric material. For example, the constant is less than about 2.5. The side of the dielectric layer 24 away from the first surface 121 has a contour surface 241, and the contour surface 241 has a plurality of protrusions 26 corresponding to the plurality of multilayer material pillars 16 respectively. In one embodiment, the protrusion 26 has a top surface 261 and a side wall 262, and the side wall 262 connects the top surface 261 and the contour surface 241. Wherein, the distance D2 (that is, the general thickness of the dielectric layer) between the partial contour surface 241 without the protrusion 26 and the first surface 121 is, for example, 215 nm.

Next, as shown in 1C, a mask layer 28 is formed, and the mask layer 28 conformally covers the contour surface 241 with the protrusions 26, wherein, since the mask layer 28 conformally covers the contour surface 241, the mask layer 28 covers the contour surface 241 conformally. The cover layer 28 includes a plurality of high tops 281 covering the top surface 261 of the protrusion 26. In one embodiment, the thickness of the cover layer 28 is between 10 nanometers and 20 nanometers. There is a polishing selection ratio between the mask layer 28 and the dielectric layer 24. In one embodiment, the mask layer 28 includes silicon nitride, silicon carbide nitride, silicon oxynitride, metal, metal nitride, metal oxide, Or a combination thereof, the metal material can be tungsten, copper, titanium, tantalum, hafnium, zinc, zirconium or aluminum. In one embodiment, the polishing selection ratio between the mask layer 28 and the dielectric layer 24 is greater than 20. The polishing rate of the dielectric layer 24 is greater than the polishing rate of the mask layer 28. In one embodiment, the mask layer 28 is a double-layer structure of titanium nitride and tungsten.

After that, as shown in FIG. 1D, the high top 281 of the mask layer 28 is removed to form a plurality of openings 282 in the mask layer 28, and the top surfaces 261 of the protrusions 26 are respectively exposed through the openings 282. In one embodiment, the removal method of the high top 281 (marked in FIG. 1C) is, for example, a chemical mechanical polishing process. Next, using the mask layer 28 with the opening 282 as a mask, as shown in FIG. 1E, at least the protrusions 26 exposed through the opening 282 of the mask layer 28 are removed. In one embodiment, the protrusion 26 is removed through an etch-back process until the protrusion 26 is removed and a plurality of shallow recesses 30 are formed on the contour surface 241, wherein the bottom 301 of the shallow recess 30 is lower than the mask Layer 28.

Next, the mask layer 28 is removed. In one embodiment, the mask layer 28 is removed by a chemical mechanical polishing process or an etching process. As shown in FIG. 1F, as the mask layer 28 is removed, the dielectric layer 24 There are a number of shallow recesses 30 remaining on the contour surface 241, but there is no protrusion 26 with a large height difference anymore. Finally, a chemical mechanical polishing process is used to polish part of the dielectric layer 24 again, as shown in FIG. 1G, so that the dielectric layer 24 has a substantially flat second surface 242, wherein the step of polishing part of the dielectric layer 24 continues until the shallow recesses 30 are eliminated In addition, a distance D3 is reserved between the substantially flat second surface 242 of the dielectric layer 24 and the multilayer material pillar 16.

According to the above, in the planarization method of the semiconductor structure with the memory module of the embodiment of the present invention, a mask layer is used to conformally cover the contour surface of the dielectric layer with the protrusions, wherein the mask layer and the dielectric layer There is a polishing selection ratio between the electrical layers, and openings are formed in the mask layer to correspond to the protrusions. After the protrusions are removed by an etch-back process through the openings, the mask layer is removed, and finally the dielectric layer is processed The planarization process of chemical mechanical polishing. This design of removing the protrusions of the dielectric layer first through the openings of the mask layer with the polishing selection ratio helps to achieve the final planarization polishing without the need to grind off the excessive dielectric layer. The requirement of planarization has the advantage of reducing material costs.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

10: Semiconductor devices 12: Substrate structure 121: first surface 14: Memory module 16: Multi-layer material cylinder 18: Upper electrode layer 20: Magnetic tunnel junction stacking layer 22: Lower electrode layer H1: height D1, D2, D3: spacing 24: Dielectric layer 241: Contour surface 242: second surface 26: raised part 261: top surface 262: Sidewall 28: Mask layer 281: high top 282: open 30: shallow recess 301: bottom

1A to 1G are schematic cross-sectional structure diagrams of the process of a planarization method of a semiconductor structure with a memory module according to an embodiment of the present invention.

24: Dielectric layer

241: Contour surface

28: Mask layer

30: shallow recess

301: bottom

Claims (10)

A method for planarizing a semiconductor structure with a memory module includes: A semiconductor device is provided. The semiconductor device includes a substrate structure and a plurality of memory modules, the substrate structure has a first surface, and the memory modules respectively include at least a multilayer material pillar protruding from the first surface; A dielectric layer is formed on the substrate structure and covers the multilayer material pillars, wherein the dielectric layer has a contour surface, the contour surface has a plurality of protrusions corresponding to the multilayer material pillars, the The protrusions respectively have a top surface and a side wall; Forming a mask layer that conformally covers the contour surface with the protrusions, wherein the mask layer includes a plurality of high tops covering the top surfaces of the protrusions, respectively, There is a polishing selection ratio between the mask layer and the dielectric layer; Removing the high tops of the mask layer to form a plurality of openings in the mask layer to respectively expose the top surfaces of the protrusions; Using the mask layer as a mask to remove at least the protrusions exposed through the openings; Remove the mask layer; and Part of the dielectric layer is polished so that the dielectric layer has a second surface that is substantially flat, wherein a distance is maintained between the second surface and the multi-layer material pillars. The method for planarizing a semiconductor structure with a memory module according to claim 1, wherein the polishing selection ratio is greater than 20. The method for planarizing a semiconductor structure with a memory module according to claim 1, wherein the mask layer includes a metal layer, metal nitride, metal oxide, silicon nitride, silicon carbide nitride, silicon oxynitride Or a combination. The method for planarizing a semiconductor structure with a memory module according to claim 3, wherein the material of the metal layer is tungsten, copper, titanium, tantalum, hafnium, zinc, zirconium or aluminum. The method for planarizing a semiconductor structure with a memory module according to claim 1, wherein the material of the dielectric layer is an ultra-low dielectric material (ULK). The method for planarizing a semiconductor structure with a memory module according to claim 1, wherein the memory modules are magnetoresistive random access memory (MRAM). The planarization method of a semiconductor structure with a memory module according to claim 1, wherein the high tops of the mask layer are removed by a first chemical mechanical polishing process, and a second chemical mechanical polishing process is used Remove the mask layer. The planarization method of a semiconductor structure with a memory module according to claim 1, wherein the protrusions are removed by an etch-back process until the protrusions are removed and the contour surface forms a plurality of shallow recesses, The bottom of the shallow recesses is lower than the mask layer. The method for planarizing a semiconductor structure with a memory module according to claim 8, wherein the step of grinding a portion of the dielectric layer is continued until the shallow recesses are eliminated and the dielectric layer has the substantially flat second surface . The method for planarizing a semiconductor structure with a memory module according to claim 1, wherein the thickness of the mask layer is between 10 nanometers and 20 nanometers.

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