TWI690988B - Method for forming semiconductor structure - Google Patents

Abstract

The present invention provides a semiconductor process, the process including: firstly, a substrate comprising a plurality of gate structures is provided, followed by forming a first dielectric layer on the substrate, and each of the gate structures being located on the substrate in a first dielectric layer, and then sequentially forming a second dielectric layer and a third dielectric layer on the first dielectric layer, and the third dielectric layer having a non-planar top surface. A planarization process is then performed, to remove a portion of the third dielectric layer, a portion of the second dielectric layer, a portion of the first dielectric layer, and part of the gate structure.

Description

Semiconductor manufacturing method

The present invention relates to the field of semiconductor manufacturing processes, and in particular to a method for reducing the occurrence of dishing during semiconductor planarization processes.

In semiconductor manufacturing processes, planarization steps, such as chemical mechanical polishing (CMP), are quite common steps. When the density of semiconductor devices in different regions (such as device regions and peripheral regions) on a substrate is different, it is easy to affect the rate of the planarization step. Especially in a region with a low element density, because the rate of the planarization step is relatively fast, a phenomenon of dishing is likely to occur. This situation also often occurs when a substrate contains components of different heights. In some cases, the same dielectric layer on the substrate contains elements with different heights, and a stop layer is provided on the top of each element, but the planarized surface will stay on top of the highest element. Because the rate of planarizing the removal of the dielectric layer is much faster than the rate of removing the stop layer, it may still remove some of the surrounding dielectric layer and other materials and affect the yield of the semiconductor device.

The present invention provides a semiconductor manufacturing process including the following steps: First, a substrate is provided, which includes a plurality of gate structures, and then a first dielectric layer is formed on the substrate, and each of the gate structures is located on the substrate In the first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially formed on the first dielectric layer, and the third dielectric layer has an uneven top surface, and then a flat Step, remove part of the third dielectric layer and the second dielectric layer, and perform an etching step to remove part of the third dielectric layer, part of the second dielectric layer, part of the first dielectric The gate structure of each layer and part.

One of the features of the present invention is that the second dielectric layer is formed by high-density plasma chemical vapor deposition (HDP CVD), and the steepness of the original uneven surface is amplified to form a clear highest point first, followed by The highest point is covered with a third dielectric layer (such as silicon nitride) that is less likely to be removed, and a new highest point is generated. Next, the planarization step first contacts and removes the highest point of the third dielectric layer. In this process, the third dielectric layer at the highest point will be removed first, but at the same time, the possibility of depressions in other parts is reduced, resulting in a relatively flat top surface, which helps the subsequent etch back steps to be uniform Remove the remaining part of the semiconductor device to improve the process yield.

10: base

12: Gate structure

12A: Gate dielectric layer

12B: Gate conductive layer

12C: Mask layer

112: Gate structure

212: Gate structure

14: Side wall

16: Contact etching stop layer

20: the first dielectric layer

20a: top surface

22: Second dielectric layer

22a: top surface

22b: highest point

22c: top surface

24: third dielectric layer

24b: highest point

30: Grinding disc

P1: Flattening step

P2: Back etching step

W1: width

1 to 7 are schematic structural diagrams of the semiconductor manufacturing process of the present invention.

In order to enable those of ordinary skill in the art of the present invention to further understand the present invention, the preferred embodiments of the present invention are specifically enumerated below, and in conjunction with the accompanying drawings, the composition of the present invention and the desired effects are described in detail .

For the convenience of description, the drawings of the present invention are only schematic diagrams to make it easier to understand the present invention, and the detailed proportions thereof can be adjusted according to design requirements. As described in the text, the relative relationship between the relative elements in the figure should be understood by those skilled in the art in terms of the relative position of the objects, so they can be Turning over and presenting the same components, all of which should belong to the scope disclosed in this manual, and will be described here first.

Please refer to FIG. 1. First, the present invention provides a substrate 10. The substrate 10 may include a fin structure (not shown). The substrate 10 has a plurality of gate structures 12, wherein at least the gate structures 12 It includes two gate structures with different heights (for example, the gate structure 112 with a lower height and the gate structure 212 with a higher height in FIG. 1), and each gate structure 12 includes a gate dielectric layer 12A and a gate The polar conductive layer 12B and a mask layer 12C. The material of the gate dielectric layer 12A may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a dielectric material containing a dielectric constant greater than 4, for example, selected from hafnium oxide ( hafnium oxide, HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), alumina (aluminum oxide, Al ₂ O ₃ ), lanthanum oxide ( lanthanum oxide, La ₂ O ₃ ), tantalum oxide (tantalum oxide, Ta ₂ O ₅ ), yttrium oxide (Yttrium oxide, Y ₂ O ₃ ), zirconium oxide (zirconium oxide, ZrO ₂ ), strontium titanate oxide , SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrconium oxide, HfZrO ₄ ), strontium bismuth tantalate (Strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT) , Lead zirconate titanate (lead zirconate titanate, PbZrxTi ₁ -xO ₃ , PZT), barium strontium titanate (barium strontium titanate, BaxSr ₁ -xTiO ₃ , BST), or a combination thereof. The material of the gate conductive layer 12B may include undoped polysilicon, heavily doped polysilicon, or a single layer or multiple layers of metal layers, such as work function metal layers, barrier layers, and low resistance metal layers. The mask layer 12C may include a single-layer structure or multiple layers of dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxynitride (SiON) Or a combination.

In addition, the semiconductor structure may further include side walls 14 located on both sides of each gate structure 12, and a contact etch stop layer 16 covering the gate structure 12 and the side walls 14. The characteristics of the above-mentioned gate structure 12, the side wall 14 and the contact etch stop layer 16, etc., belong to the conventional technology in the art, This will not go into details.

Next, a first dielectric layer 20 is formed on the substrate 10. In this embodiment, the material of the first dielectric layer 20 is, for example, a silicon oxide layer, which is formed by flowable chemical vapor deposition (FCVD). Is formed on the substrate 10 and completely covers each gate structure 12 (including the gate structure 112 and the gate structure 212), the sidewall 14 and the contact etch stop layer 16. It is worth noting that the first dielectric layer 20 formed by the method of flow chemical vapor deposition has the characteristics of softer material, certain viscosity and flowability. Therefore, when it is formed on an uneven surface, the top surface 20a of the first dielectric layer 20 will also exhibit an uneven surface. Especially above the higher gate structure 212, the surface 20a of the first dielectric layer 20 will be more protruding than other surfaces around it.

Next, as shown in FIG. 2, a second dielectric layer 22 is formed over the first dielectric layer 20 by means of high density plasma chemical vapor deposition (HDP CVD) On it. The material of the second dielectric layer 22 is, for example, a silicon oxide layer. It is worth noting that although the materials of the first dielectric layer 20 and the second dielectric layer 22 may include, for example, a silicon oxide layer, due to their different formation methods, the characteristics of the material will also be changed to a certain extent. For example, the applicant found that the second dielectric layer 22 is formed by high-density plasma chemical vapor deposition. The material of the second dielectric layer 22 has a harder characteristic, and if it is formed on an uneven surface, it will not only follow the unevenness Uneven surfaces are generated and will increase the roughness of the uneven surface. In other words, if the original uneven surface has a more protruding part, the protruding part will be more obvious after the second dielectric layer 22 is formed by high density plasma chemical vapor deposition. As seen from FIG. 2, the second dielectric layer 22 has a top surface 22a, and the top surface 22a and the top surface 20a have different shapes. The top surface 22a includes a highest point 22b above the gate structure 212. That is, the vertical distance from the highest point 22b to the top surface 20a of the lower first dielectric layer 20 will be greater than the vertical distance from other areas of the top surface 22a to the top surface 20a of the lower first dielectric layer 20. In addition, the highest point 22b to the base below The vertical distance of the surface of the bottom 10 will also be greater than the vertical distance from other areas of the top surface 22a to the surface of the base 10 below.

Next, as shown in FIG. 3, a third dielectric layer 24 is further formed on the second dielectric layer 22, wherein the third dielectric layer 24 is, for example, a silicon nitride layer, and the thickness is preferably between 30 and 60 angstroms. But it is not limited to this. Compared with the second dielectric layer 22, the thickness of the third dielectric layer 24 is thinner (the thickness of the second dielectric layer 22 is about 500 angstroms or more), so the third dielectric layer 24 will cover conformally On the top surface 22a of the second dielectric layer 22, the uppermost point 22b is also covered, and a new highest point 24b is formed.

Next, as shown in FIG. 4, a planarization step P1 is performed on the semiconductor structure, for example, a chemical mechanical polishing (CMP) process. It is worth noting that the grinding disc (or polishing pad) 30 used in the chemical mechanical polishing process is a flat surface, so when the grinding disc 30 gradually approaches the semiconductor structure from above, it first contacts the highest point 24b. Since the material of the third dielectric layer 24 is, for example, silicon nitride, the rate of the planarization step P1 will slow down. Specifically, the rate of removing the third dielectric layer 24 in the planarization step P1 will be much smaller than the rate of removing the second dielectric layer 22 (for example, the rate of removing the second dielectric layer 22 will be It is more than 20 times the rate of removing the third dielectric layer 24). At this time, the planarization step P1 only removes the highest point 24b and a small part of the surrounding area, and temporarily does not remove the other areas of the third dielectric layer 24 having lower surfaces. In addition, the grinding disc 30 used in the chemical mechanical grinding process can select a grinding disc with higher hardness, which can further ensure that the flattening step P1 will only remove the highest point 24b and a small part of the surrounding area, and will not temporarily remove the first The other areas of the lower surface of the third dielectric layer 24 are.

As shown in FIG. 5, as the planarization step P1 proceeds, the third dielectric layer 24 at the highest point 24b will be removed to expose a portion of the second dielectric layer 22 underneath. However, since the highest point 24b originally exhibits a peak shape, even if a part of the second dielectric layer 22 is exposed, the exposed second dielectric layer 22 The range (eg width, etc.) is also relatively small. As shown in FIG. 5, assuming that the width of the exposed second dielectric layer 22 is W1, the width W1 only occupies less than one-tenth of the area of the entire semiconductor structure. As mentioned above, the sag phenomenon generated during the planarization step usually occurs during an open, large-area planarization step with a fast removal rate. Since the second dielectric layer 22 is exposed to a small amount, therefore Failure to meet the conditions of open and large areas can effectively avoid the occurrence of depressions.

In addition, the rate of the flattening step P1 is also affected by the pressure. More specifically, at the beginning, only the highest point 24b contacts the grinding disc 30, so the downward pressure provided by the grinding disc 30 will be concentrated on the highest point 24b. As the planarization step P1 continues, the exposed portion of the second dielectric layer 22 will be more and more. However, at this time, the top surface of the third dielectric layer 24 also tends to be flat, that is, more surface of the third dielectric layer 24 will contact the grinding disc 30, and only the highest point 24b contacts the grinding disc 30 at the beginning. The pressure on each position of the third dielectric layer 24 will be dispersed and reduced. Therefore, the rate of the overall flattening step P1 will also slow down. Therefore, although a larger area of the second dielectric layer is exposed at this time, the rate of the planarization step P1 is slowed, and the rate of removing the dielectric layer is too fast, which reduces the possibility of causing a sag phenomenon.

As shown in FIG. 6, after removing part of the third dielectric layer 24, the second dielectric layer 22 is exposed, that is, the planarization step P1 is stopped. At this time, the second dielectric layer 22 has a relatively flat top surface 22c. In addition, the planarization step P1 of the present invention does not remove the first dielectric layer 20 or the gate structure 12. As shown in FIG. 7, an etching step P2 is performed next. The etching back step P2 may include one or more etching steps to remove the remaining third dielectric layer 24 and the remaining second dielectric layer 22 , Part of the first dielectric layer 20, part of the contact etch stop layer 16, part of the side wall 14 and part of the gate structure 12. Preferably, after the etching back step P2 is performed, each gate structure 12 has a top surface with the same height.

One of the features of the present invention is that high density plasma chemical vapor deposition (HDP CVD) Form the second dielectric layer 22, and enhance or magnify the steepness of the original uneven surface, first form a clear highest point 22b, and then cover the highest point 22b with a third dielectric layer 24 that is less likely to be removed (Silicon nitride, for example), and create a new highest point 24b. Next, the planarization step P1 first contacts and removes the highest point 24b of the third dielectric layer 24. During this process, the third dielectric layer 24 at the highest point 24b will be removed first, but at the same time it reduces the possibility of depressions in other parts, resulting in a relatively flat top surface, which helps the subsequent etch-back step The remaining semiconductor elements can be removed uniformly, improving the process yield.

The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: base

12: Gate structure

12A: Gate dielectric layer

12B: Gate conductive layer

12C: Mask layer

112: Gate structure

212: Gate structure

14: Side wall

16: Contact etching stop layer

20: the first dielectric layer

20a: top surface

22: Second dielectric layer

22c: top surface

24: third dielectric layer

30: Grinding disc

W1: width

Claims (10)

A semiconductor manufacturing process includes the following steps: providing a substrate with a plurality of gate structures on the substrate; forming a first dielectric layer on the substrate, and each of the gate structures in the first dielectric layer Forming a second dielectric layer and a third dielectric layer on the first dielectric layer in sequence, and the third dielectric layer has an uneven top surface; performing a planarization step to remove part of the A third dielectric layer and the second dielectric layer, wherein during the planarization step, the rate of removing the second dielectric layer is more than 20 times the rate of removing the third dielectric layer; and proceeding In an etching step, part of the third dielectric layer, part of the second dielectric layer, part of the first dielectric layer and part of each gate structure are removed. The semiconductor manufacturing process as described in item 1 of the patent application scope, wherein the plurality of gate structures include at least two gate structures with different heights. The semiconductor process as described in item 1 of the patent application range, wherein the first dielectric layer is an oxide layer formed by a flow chemical vapor deposition (FCVD) step. The semiconductor process described in item 1 of the patent application scope, wherein the second dielectric layer is an oxide layer formed by a high density plasma chemical vapor deposition (HDP CVD) step. The semiconductor manufacturing process as described in item 1 of the patent application scope, wherein the third dielectric layer is a silicon nitride layer. The semiconductor process as described in item 5 of the patent application range, wherein the thickness of the third dielectric layer is between 30 Angstroms and 60 Angstroms. The semiconductor manufacturing process as described in item 1 of the patent scope, wherein the non-flat top mask has a highest point, and the planarization step first removes the third dielectric layer on the highest point. The semiconductor process as described in item 1 of the patent application scope, in which the planarization step is performed Before, the top surfaces of the first dielectric layer and the second dielectric layer are both uneven surfaces, and the uneven surfaces of the first dielectric layer and the second dielectric layer have different surface shapes. The semiconductor manufacturing process as described in item 1 of the patent application scope, wherein after the etching step is performed, each gate structure has the same height. The semiconductor manufacturing process as described in item 1 of the patent application scope, wherein the planarization step does not remove the first dielectric layer.

Images