TWI830318B - 在介電表面中用於增加表面積、接合強度、及對準之接合的齒型、陰影線、及其他表面圖案 - Google Patents

在介電表面中用於增加表面積、接合強度、及對準之接合的齒型、陰影線、及其他表面圖案 Download PDF

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TWI830318B
TWI830318B TW111128862A TW111128862A TWI830318B TW I830318 B TWI830318 B TW I830318B TW 111128862 A TW111128862 A TW 111128862A TW 111128862 A TW111128862 A TW 111128862A TW I830318 B TWI830318 B TW I830318B
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recesses
protrusions
dielectric material
material layer
semiconductor device
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TW111128862A
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TW202327020A (zh
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凱爾 K 克比
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美商美光科技公司
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment

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Abstract

本發明係關於一種半導體裝置，其包括具有一第一主表面及與該第一主表面相對之一第二主表面的一半導體基板、在該第一主表面上方之一第一介電材料層及在該第二主表面上方之一第二介電材料層。該第一層包括複數個凹部，且該第二層包括複數個突起。該複數個凹部中之每一者由一形狀界定，且該複數個突起中之每一者與該複數個凹部中之一對應一者豎直對準且由該複數個凹部中之該對應一者的形狀界定。

Description

在介電表面中用於增加表面積、接合強度、及對準之接合的齒型、陰影線、及其他表面圖案
本技術大體上係關於在介電表面中具有表面圖案之半導體裝置，且更特別地，具有用於增加半導體晶粒堆疊之混合及熔融接合之表面積、接合強度及對準的表面圖案。
半導體裝置製造商經常尋求為電腦、手機、尋呼機、個人數位助理及許多其他產品製造更小、更快及/或更強大的具有更高組件密度之裝置。晶粒製造商面臨越來越大的壓力，以減少晶粒佔用之體積，且亦提高所得囊封總成之容量。為了滿足此等需求，晶粒製造商通常將多個晶粒彼此上下堆疊，以安裝晶粒之電路板或其他元件上的有限表面積內增加裝置之容量或效能。與習知配置相比，堆疊之半導體裝置，例如三維積體電路(3DIC)，通常享有縮減之佔用面積。
熔融及混合接合為用於形成3DIC之接合程序。在熔融接合中，在兩個相對的半導體晶粒之介電層之間形成介電接合。混合接合進一步包括在晶粒之導電結構之間形成的金屬-金屬接合。混合接合在形成具 有縮減高度及更佳熱效能之總成方面展示巨大的希望；因此，非常期望改良之混合接合方法。
100:半導體裝置
102:半導體晶粒
104:半導體晶粒
106:基板
108:第一主表面
110:基板
112:第二主表面
114:第一介電層
116:第二介電層
118:凹部
120:突起
122:底面
124:頂面
126:側壁
128:側壁
200:半導體裝置
222:第一導電觸點
224:第二導電觸點
226:第一雙鑲嵌焊墊
228:第二雙鑲嵌焊墊
230:第一通孔
232:第二通孔
300:半導體晶粒
302:第一導電觸點
304:第二導電觸點
306:基板
308:第一主表面
312:第二主表面
314:第一介電層
316:第二介電層
318:凹部
320:突起
400:半導體裝置
402:半導體晶粒
404:半導體晶粒
418:凹部
420:突起
422:第一導電觸點
424:第二導電觸點
430:外圍部分
432:中心部分
500:半導體晶粒
506:基板
508:第一主表面
512:第二主表面
514:第一介電層
514a:介電層
514b:介電層
516:第二介電層
516a:介電層
516b:介電層
518:凹部
520:突起
522:第一導電觸點
524:第二導電觸點
530:外圍部分
532:中心部分
600:半導體裝置
602:半導體晶粒
604:半導體晶粒
606:半導體晶粒
618:凹部
620:突起
622a:第一導電觸點
622b:第一導電觸點
624a:第二導電觸點
624b:第二導電觸點
700:步驟
702:步驟
704:步驟
706:步驟
708:步驟
710:步驟
712:步驟
714:步驟
716:步驟
718:步驟
720:步驟
800:系統
802:處理器
804:記憶體
806:輸入/輸出裝置
808:其他子系統或組件
A:角度
d:距離
h1:高度
h2:高度
w:寬度
參考以下圖式可更好地理解本技術之許多態樣。圖式中之組件未必按比例縮放。相反，重點在於清楚地繪示本技術之原理。
圖1A為根據本技術之實施例的具有突起及凹部之半導體裝置的截面圖，圖1B為圖1A之半導體裝置的放大截面圖，且圖1C為圖1A之半導體裝置的仰視平面圖。
圖2A及圖2B為根據本技術之實施例的包括複數個突起及凹部之另一半導體裝置的截面圖。
圖2C及圖2D為根據本技術之實施例的具有突起及凹部之半導體裝置的放大截面圖。
圖3為根據本技術之實施例的具有複數個凹部及突起之半導體晶粒的截面圖。
圖4A為根據本技術之實施例的具有複數個凹部及突起之半導體裝置的截面圖，且圖4B為圖4A之半導體裝置的仰視平面圖。
圖5為根據本技術之實施例的具有複數個凹部及突起之半導體晶粒的截面圖。
圖6A為根據本技術之實施例的半導體裝置在組裝之前的截面圖，且圖6B為圖6A之半導體裝置在組裝之後的截面圖。
圖7為根據本技術之實施例的形成半導體裝置之方法的流程圖。
圖8為包括根據本技術之實施例組態之半導體總成之系統的示意圖。
相關申請案之交互參考
本申請案主張於2021年8月27日提出申請之美國臨時專利申請案第63/238,071號之優先權，該美國臨時專利申請案之揭示內容以全文引用之方式併入本文中。
揭示了在介電表面中具有表面圖案以改良熔融及混合接合之半導體裝置的若干實施例之具體細節。在一些實施例中，例如，半導體裝置包括具有第一主表面及與第一主表面相對之第二主表面的半導體基板。半導體裝置亦可包括在第一主表面上方之第一介電材料層。第一層可包括複數個凹部，且複數個凹部中之每一者可由形狀界定。半導體裝置可進一步包括在第二主表面上方之第二介電材料層。第二層可包括複數個突起。複數個突起中之每一者可與複數個凹部中之對應一者豎直對準並由複數個凹部中之對應一者之形狀界定。本技術可在半導體裝置之熔融及混合接合期間增加表面積、接合強度及對準。
熟習相關技術者將認識到，除非上下文另有說明，否則本文中所揭示之結構可使用習知半導體製造技術形成。可例如使用化學氣相沈積、物理氣相沈積、原子層沈積、電鍍、化學鍍、旋塗及/或其他合適的技術來沈積材料。類似地，可例如使用電漿蝕刻、濕法蝕刻、化學機械平面化或其他合適的技術來移除材料。
本文中揭示眾多具體細節，以便對本技術之實施例進行全面且有利的描述。然而，熟習此項技術者將理解，該技術可具有額外實施 例，且該技術可在沒有下文參考圖1A至圖7所描述之實施例之數個細節的情況下實踐。例如，已省略此項技術眾所周知的半導體裝置及/或封裝之一些細節，以便不模糊本技術。一般而言，應理解，除本文中所揭示之彼等具體實施例外，各種其他裝置及系統可在本技術之範圍內。
如本文中所使用，術語「垂直」、「側向」、「上部」、「下部」、「上面」及「下面」可指代半導體裝置中之特徵鑒於圖中所展示之定向的相對方向或位置。例如，「上部」或「最上部」可指代特徵經定位比另一特徵更靠近頁之頂部。然而，此等術語應被廣義地解釋為包括具有其他定向之半導體裝置，例如倒置或傾斜定向，其中頂部/底部、上方/下方、上面/下面，上/下及左/右可取決於定向互換。
圖1A為根據本技術之實施例的包括複數個凹部及突起之半導體裝置(「裝置100」)的截面圖。裝置100包括兩個半導體晶粒102及104(「晶粒102及104」)。晶粒102包括具有第一主表面108之基板106，且晶粒104包括具有與第一主表面108相對之第二主表面112之基板110。晶粒102包括在第一主表面108上方之第一介電層114，且晶粒104包括在第二主表面112上方之第二介電層116。第一介電層114可包含與第二介電層116相同之介電材料。第一介電層114及第二介電層116之材料可包括原矽酸四乙酯、碳氮化矽、二氧化矽或其組合。
一起參考圖1A及圖1B，第一介電層114包括複數個凹部118，且第二介電層116包括複數個突起120。複數個突起120中之每一者可與複數個凹部118中之對應一者豎直對準。複數個凹部118及突起120中之每一者由縱向截面形狀界定。縱向截面形狀可為梯形、矩形、正方形、直線或任何其他合適的形狀。複數個凹部118中之每一者包括平坦的底面 122，且複數個突起120中之每一者包括平坦的頂面124。可藉由自第一介電層114蝕刻掉材料來形成複數個凹部118。可藉由自第二介電層116蝕刻掉材料來形成複數個突起120。
參考圖1B，複數個凹部118及突起120中之每一者分別具有側壁126及128，其具有相同的角度A、高度h1及寬度w。角度A可在0度至幾乎90度之範圍內。在一些實施例中，角度A在0至45度之範圍內。高度h1可不超過2、4或6微米。寬度w可不超過2、4或6微米。在一些實施例中，高度h1及寬度w為相同的。在其他實施例中，高度h1小於寬度w。在其他實施例中，高度h1大於寬度w。第一介電層114及第二介電層116包括高度h2。高度h2為至少高度h1。例如，高度h2可為2、4、6、8、10微米，或大於高度h1之任何合適的高度。在所繪示實施例中，第一介電層114及第二介電層116之高度h2大於複數個凹部118及突起120之高度h1。在其他實施例中，高度h2大約等於高度h1。儘管圖1B繪示具有相同高度h2之第一介電層114及第二介電層116，但第一介電層114可具有與第二介電層116不同的高度。
複數個凹部118及突起120中之每一者可具有任何合適數目之側壁及尺寸。在一些實施例中，複數個凹部118及突起120中之每一者可具有三個或多於三個側壁。例如，複數個凹部118及突起120中之每一者可具有三個側壁、四個側壁(如在圖1C中所繪示)、五個側壁、六個側壁或任何合適數目之側壁。每一側壁可具有相同或不同的尺寸。例如，每一側壁可具有相同或不同的高度及/或角度。
參考圖1C，在一些實施例中，晶粒104之複數個突起120包含垂直配置行及列的突起。在此實施例中，晶粒102之複數個凹部118 包含垂直配置列及行之凹部。複數個突起120中之每一者間隔開距離d。距離d可為任何合適的距離。在一些實施例中，距離d可至少為複數個凹部118及突起120中之每一者之寬度w。在其他實施例中，距離d可不大於寬度w。在另外其他實施例中，距離d可大約為寬度w。例如，距離d可為2、4、6、8、10、15或20微米，或任何合適的距離。複數個凹部118及突起120中之每一者由一橫向截面形狀界定。該橫向截面形狀可為矩形、正方形、直線或任何其他合適的形狀。儘管圖1C繪示複數個突起120中之每一者均等地間隔開距離d，但複數個突起120中之每一者或部分可間隔開不同的距離。此外，儘管圖1C繪示具有40個突起及相應之40個凹部的裝置100，但裝置100可包括較少或較多之突起及凹部。例如，裝置100可包括在1至40或多於40之範圍內之任何數目之突起及凹部。
複數個凹部118及突起120可分別在晶粒102及104上具有任何合適的配置圖案。在圖1C之所繪示實施例中，複數個凹部118及突起120配置成對準的垂直之凹部及突起列及行。在其他實施例中，複數個凹部118及突起120可具有交錯的垂直之突起及凹部列及行。此外，在其他實施例中，複數個凹部118及突起120不需要配置成垂直之列及行，但可配置成熟習此項技術者容易瞭解之其他圖案(例如，六邊形陣列，沿著輻射對稱線、呈非對稱配置等)。在又一些實施例中，複數個凹部118及突起120可均具有相似的尺寸，或可經組態有不同的尺寸(例如，以在晶粒上容納其他特徵)。例如，一些對應對之凹部118及突起120可經組態有一個比另一個大得多的尺寸，以提供一對細長的實質上延伸之晶粒102及104之尺寸。
與沒有複數個凹部及突起之情況相比，複數個凹部118及 突起120可分別提供晶粒102及104之增加之表面積。如熟習此項技術者將容易瞭解，晶粒102及104之表面積取決於高度h1、側壁角A、距離d及凹部及突起之數目。在一些實施例中，複數個凹部118及突起120可分別使晶粒102及104中之每一者之表面積增加10%至300%。例如，晶粒102及104中之每一者之表面積的增加可為10%、30%、60%、120%、240%、300%或任何合適的百分比。
圖2A及圖2B為根據本技術之實施例的包括複數個凹部及突起之半導體裝置200(「裝置200」)的截面圖。裝置200通常類似於裝置100，只不過裝置200進一步包括分別具有第一導電觸點222及第二導電觸點224之晶粒102及104。複數個凹部118中之至少一者包括安置在其中之第一導電觸點222，且複數個突起120中之至少對應一者包括安置在其上之第二導電觸點224。參考圖2A，在一些實施例中，複數個凹部118及突起120中之一或多者分別包括第一導電觸點222及第二導電觸點224。參考圖2B，在一些實施例中，複數個凹部118及突起120中之每一者分別包括第一導電觸點222及第二導電觸點224。第一導電觸點222及第二導電觸點224可包括導電材料，例如但不限於銅、銀、金、氧化鋅、鋁及錫。如熟習此項技術者將瞭解，第一導電觸點222及第二導電觸點224分別連接至晶粒102及104上之主動或被動電路系統(未繪示)。例如，第一導電觸點222及第二導電觸點224可藉由跡線、通孔及其他導電組件(未繪示)分別連接至晶粒102及104。在一些實施例中，第一導電觸點222及第二導電觸點224為大約相同的大小或具有大約相同的尺寸。在一些實施例中，第一導電觸點222及第二導電觸點224具有不同的尺寸。例如，第一導電觸點222可具有比第二導電觸點224更大的截面寬度，或反之亦然。
圖2C為圖2A之半導體裝置200的放大截面圖，除了晶粒102及104分別包括第一雙鑲嵌焊墊226及第二雙鑲嵌焊墊228。第一雙鑲嵌焊墊226及第二雙鑲嵌焊墊228可藉由圖案化介電層114及116，後續接著沈積導電材料及平坦化來形成。
圖2D為圖2A之半導體裝置200的另一放大截面圖，除了晶粒102及104分別包括第一通孔230及第二通孔232。除了圖2C之雙鑲嵌焊墊226及228以及圖2D之通孔230及232之外，其他結構可嵌入在凹部118及突起120中以電耦接晶粒102及104或晶粒102及104之連接組件，例如圖2A至圖2B中所展示之導電觸點222及224。
圖3為根據本技術之實施例的具有複數個凹部及突起之半導體晶粒300(「晶粒300」)的截面圖。晶粒300包括具有第一主表面308及與第一主表面308相對之第二主表面312的基板306。晶粒300包括在第一主表面308上方之第一介電層314及在第二主表面312上方之第二介電層316。第一介電層314包括複數個凹部318，且第二介電層316包括複數個突起320。複數個突起320中之每一者可與複數個凹部318中之對應一者豎直對準。
參考圖3，第一介電層314及第二介電層316通常可分別與裝置100之第一介電層114及第二介電層116相似或相同。複數個凹部318及突起320通常可分別與裝置100之複數個凹部118及突起120(如參考圖1A至圖1C所描述)，或分別與裝置200之複數個凹部218及突起220(如參考圖2A及圖2B所描述)相同或共用相似的特徵。在所繪示實施例中，例如，複數個凹部318中之至少一者包括安置在其中之第一導電觸點302，且複數個突起320中之至少對應一者包括安置在其上之第二導電觸點 304。儘管圖3繪示複數個凹部318及突起320中之一者分別具有第一導電觸點302及第二導電觸點304，但在其他實施例中，複數個凹部318及突起320中之每一者或無一者可包括導電觸點。如熟習此項技術者將瞭解，第一導電觸點302及第二導電觸點304連接至晶粒300中之主動或被動電路系統且藉由基板穿孔(未繪示)彼此連接。
圖4A為根據本技術之實施例的具有複數個凹部及突起之半導體裝置400(「裝置400」)的截面圖。裝置400大體上類似於如參考圖1A至圖1C所描述之裝置100，除了裝置400包括半導體晶粒402及404(「晶粒402及404」)，該等半導體晶粒具有位於環繞裝置400之中心部分432之外圍部分430處的複數個凹部418及突起420。裝置400進一步包括位於中心部分432處之第一導電觸點422及第二導電觸點424。參考圖4B，在一些實施例中，複數個突起420包含垂直之突起列及行，且第二導電觸點424位於中心部分432處。在此實施例中，晶粒402之複數個凹部418包含垂直之凹部列及行。儘管圖4A繪示僅位於中心部分432處之第一導電觸點422及第二導電觸點424，但第一導電觸點422及第二導電觸點424可僅位於複數個凹部418及突起420處、中心部分432及複數個凹部418及突起420兩者處，或在中心部分432及複數個凹部418及突起420之部分處。儘管圖4B繪示具有84個突起及相應之84個凹部的裝置400，但裝置100可包括更少或更多之突起及凹部。例如，裝置100可包括在1至84個或多於84個之範圍內之任何數目之突起及凹部。
圖5為根據本技術之實施例的具有複數個凹部及突起之半導體晶粒500(「晶粒500」)的截面圖。晶粒500包括具有第一主表面508及與第一主表面508相對之第二主表面512的基板506。晶粒500包括在第 一主表面508上方之第一介電層514及在第二主表面512上方之第二介電層516。第一介電層514包括複數個凹部518，且第二介電層516包括複數個突起520。晶粒500通常類似於參考圖3所描述之晶粒300，除了複數個凹部518及突起520位於環繞晶粒500之中心部分532之外圍部分530處。在所繪示實施例中，晶粒500進一步包括分別安置在中心部分532處之第一介電層514及第二介電層516上的第一導電觸點522及第二導電觸點524。在一些實施例中，複數個凹部518中之一或多者可包括安置在其中之第一導電觸點522，且複數個突起520中之至少對應一者可包括安置在其上之第二導電觸點524。在其他實施例中，第一導電觸點522及第二導電觸點524可僅安置在複數個凹部518及突起520中之一或多者上。
圖6A為組裝之前的半導體裝置600(「裝置600」)的截面圖，且圖6B為組裝之後的裝置600的截面圖。裝置600包括半導體晶粒602、604及606(「晶粒602、604及606」)。晶粒602及604可分別與如參考圖1A至圖2B所描述之晶粒102及104或分別與如參考圖4A至圖4B所描述之晶粒402及404大體上相似或相同。晶粒606可與如參考圖3所描述之晶粒300或如參考圖5所描述之晶粒500大體上相似或相同。晶粒602堆疊在晶粒606上方，該晶粒606堆疊在晶粒604上方。複數個突起620中之每一者與複數個凹部618中之對應一者豎直對準。晶粒602之介電層514a與晶粒606之介電層516a接合，且晶粒606之介電層514b與晶粒604之介電層516b接合(在圖6B中以虛線展示之接合)。在一些實施例中，在組裝時，第一導電觸點622a及622b分別電耦接至第二導電觸點624a及624b。儘管圖6A及圖6B繪示具有三個半導體晶粒602、604及606之裝置600，但裝置600可包括較少或較多之半導體晶粒。
圖7為根據本技術之實施例的形成半導體裝置之方法的流程圖。步驟700及702形成第一半導體晶粒。在方法之步驟700，提供具有第一主表面之第一半導體基板。在步驟702，將第一介電材料層安置在第一半導體基板之第一主表面上。在步驟704，對第一介電材料層進行蝕刻以在第一層中形成複數個凹部。複數個凹部中之每一者由一形狀界定。在步驟706，將第一導電觸點安置在第一介電材料層中。在一些實施例中，在對第一層進行蝕刻的同時，在步驟704期間安置第一導電觸點。在其他實施例中，在步驟704之後(例如，在對第一層進行蝕刻之後)安置第一導電觸點。
步驟708及710形成第二半導體晶粒。在方法之步驟708，提供具有第二主表面之第二半導體基板。在步驟710，將第二介電材料層安置在第二半導體基板之第二主表面上。在步驟712，對第二介電材料層進行蝕刻以在第二層中形成複數個突起。複數個突起中之每一者由複數個凹部中之對應一者之形狀界定。在步驟714，將第二導電觸點安置在第二介電材料層中。在一些實施例中，在步驟712期間安置第二導電觸點，同時對第二層進行蝕刻。在其他實施例中，在步驟712之後(例如，在對第二層進行蝕刻之後)安置第二導電觸點。
在步驟716，對第一及第二半導體晶粒進行表面活化(例如，經由電漿活化)。在步驟718，將第一半導體晶粒之複數個突起中之每一者與複數個凹部中之對應一者對準。在步驟720，將第一半導體晶粒與第二半導體晶粒接合，包括將第一導電觸點與第二導電觸點電耦接。
儘管圖1A至圖6B繪示半導體裝置及/或晶粒之每一介電層具有複數個凹部或複數個突起，但在一些實施例中，每一介電層可包括凹 部及突起兩者。例如，半導體裝置可包括具有複數個凹部及突起之第一半導體晶粒的第一介電層及具有複數個對應之突起及凹部之第二半導體晶粒的第二介電層。
具有上文參考圖1A至圖7所描述特徵之半導體裝置及/或晶粒中之任一者可併入至大量更大及/或更複雜之系統中之任何者中，其代表性實例為圖8中示意性展示之系統800。系統800可包括處理器802、記憶體804(例如，SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置806及/或其他子系統或組件808。上文參考圖1A至圖7所描述之半導體晶粒及/或封裝可包括在圖8中所展示之元件中之任何者中。所得系統800可經組態以執行廣泛各種合適的計算、處理、儲存、感測、成像及/或其他功能中之任何者。因此，系統800之代表性實例包括但不限於電腦及/或其他資料處理器，例如台式電腦、膝上型電腦、網際網路器具、手持裝置(例如，掌上電腦、可穿戴電腦、蜂巢或移動電話、個人數位助理、音樂播放器等)、平板、多處理器系統、基於處理器或可程式化之消費電子產品、網路電腦及小型電腦。系統800之其他代表性實例包括燈、攝影機、車輛等。關於此等及其他實例，系統800可容納在單個單元中或分佈在多個互連單元上(例如，藉由通信網路)。因此，系統800之組件可包括本端及/或遠端記憶體儲存裝置以及廣泛各種合適之電腦可讀媒體中之任何者。
自前述內容，將瞭解，出於繪示之目的，本文中已描述本技術之特定實施例，但在不脫離本發明之情況下可進行各種修改。因此，本發明不受除所附申請專利範圍以外之任何限制。此外，在特定實施例之上下文中描述的新技術之某些態樣亦可在其他實施例中組合或消除。此 外，儘管已在彼等實施例之上下文中描述與新技術之某些實施例相關聯的優點，但其他實施例亦可展現出此等優點，且並非所有實施例都必須展現落入本技術範圍內之此等優點。因此，本發明及相關聯技術可囊括本文中未明確展示或描述之其他實施例。
100:半導體裝置
102:半導體晶粒
104:半導體晶粒
106:基板
108:第一主表面
110:基板
112:第二主表面
114:第一介電層
116:第二介電層
118:凹部
120:突起
122:底面
124:頂面
126:側壁
128:側壁

Claims (18)

  1. 一種半導體裝置，其包含：一半導體基板，其具有一第一主表面及與該第一主表面相對之一第二主表面；一第一介電材料層，其在該第一主表面上，該第一介電材料層包括複數個凹部，該複數個凹部中之每一者由一形狀界定；及一第二介電材料層，其在該第二主表面上，該第二介電材料層包括複數個突起，該複數個突起中之每一者與該複數個凹部中之一對應一者豎直對準且由該複數個凹部中之該對應一者的形狀界定，其中該複數個凹部中之至少一者包括安置在其中之一第一導電觸點，且該複數個突起中之至少對應一者包括安置在其上之一第二導電觸點。
  2. 如請求項1之半導體裝置，其中該複數個凹部中之該至少一者包括一第一雙鑲嵌焊墊，且該複數個突起中之該至少對應一者包括一第二雙鑲嵌焊墊。
  3. 如請求項1之半導體裝置，其中該複數個凹部中之該至少一者包括一第一導電通孔，且該複數個突起中之該至少對應一者包括一第二導電通孔。
  4. 如請求項1之半導體裝置，其中該複數個凹部中之每一者包括一平坦 的底面。
  5. 如請求項1之半導體裝置，其中該複數個突起中之每一者包括一平坦的頂面。
  6. 如請求項1之半導體裝置，其中該複數個突起包含垂直配置列及行之突起。
  7. 如請求項1之半導體裝置，其中該第一介電材料層及該第二介電材料層包括原矽酸四乙酯、碳氮化矽、二氧化矽或其組合。
  8. 一種半導體裝置，其包含：一第一半導體晶粒，其包括：一第一半導體基板，其具有一第一主表面，及一第一介電材料層，其在該第一主表面上，該第一介電材料層包括複數個凹部，該複數個凹部中之每一者由一形狀界定；及一第二半導體晶粒，其包括：一第二半導體基板，其具有與該第一主表面相對之一第二主表面，及一第二介電材料層，其在該第二主表面上，該第二介電材料層包括複數個突起，該複數個突起中之每一者與該複數個凹部中之一對應一者豎直對準且由該複數個凹部中之該對應一者的形狀界定，其中該複數個凹部中之至少一者包括安置在其中之一第一導電觸 點，且該複數個突起中之至少對應一者包括安置在其上之一第二導電觸點。
  9. 如請求項8之半導體裝置，其中該複數個凹部中之該至少一者包括一第一雙鑲嵌焊墊，且該複數個突起中之該至少對應一者包括一第二雙鑲嵌焊墊。
  10. 如請求項8之半導體裝置，其中該複數個凹部中之每一者包括一第一表面及第一側壁，且該複數個突起中之每一者包括一第二表面及第二側壁，該第二表面及該等第二側壁分別具有與該第一表面及該等第一側壁相同的尺寸。
  11. 如請求項10之半導體裝置，其中該等第一側壁以一角度組態，且該等第二側壁以與該等第一側壁相同的一角度組態。
  12. 如請求項11之半導體裝置，其中該角度大於0度且小於90度。
  13. 如請求項8之半導體裝置，其中該第一介電材料層包含與該第二介電材料層相同的一材料。
  14. 一種形成一半導體裝置之方法，該方法包含：形成一第一半導體晶粒，其包括：提供具有一第一主表面之一第一半導體基板，及 在該第一主表面上提供一第一介電材料層；在該第一介電材料層中形成複數個凹部，該複數個凹部中之每一者由一形狀界定；形成一第二半導體晶粒，其包括：提供具有一第二主表面之一第二半導體基板，及在該第二主表面上提供一第二介電材料層；在該第二介電材料層中形成複數個突起，該複數個突起中之每一者由該複數個凹部中之一對應一者的形狀界定；將該複數個突起中之每一者與該複數個凹部中之對應一者對準；及提供與該複數個凹部中之至少一者接觸之一第一導電觸點，及提供與該複數個突起中之至少對應一者接觸之一第二導電觸點。
  15. 如請求項14之方法，其進一步包含：在該第一介電材料層中提供一第一導電觸點並在該第二介電材料層中提供一第二導電觸點。
  16. 如請求項15之方法，其進一步包含：將該第一導電觸點與該第二導電觸點電耦接。
  17. 如請求項14之方法，其中形成該等凹部包含自該第一介電材料層蝕刻掉材料。
  18. 如請求項14之方法，其中形成該等突起包含自該第二介電材料層蝕刻掉材料。
TW111128862A 2021-08-27 2022-08-02 在介電表面中用於增加表面積、接合強度、及對準之接合的齒型、陰影線、及其他表面圖案 TWI830318B (zh)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090166782A1 (en) * 2007-12-28 2009-07-02 Micron Technology, Inc. Wafer processing
CN107768258A (zh) * 2016-08-19 2018-03-06 台湾积体电路制造股份有限公司 半导体封装件及其形成方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090166782A1 (en) * 2007-12-28 2009-07-02 Micron Technology, Inc. Wafer processing
CN107768258A (zh) * 2016-08-19 2018-03-06 台湾积体电路制造股份有限公司 半导体封装件及其形成方法

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