TWI825091B - Wafer processing methods - Google Patents

Abstract

[Project] Provide a wafer processing method that can appropriately divide a wafer on which a plurality of flash memory chips are formed. [Solution] The wafer processing method consists of at least the following process: a cutting groove forming process, which uses a cutting blade (28) to cut the planned dividing line (14) to form a cutting groove ( 30); Modified layer formation process, which is to position the focusing point of the laser light (LB) with a penetrating wavelength with respect to the semiconductor substrate (4) on the semiconductor substrate (14) corresponding to the planned division line (14) 4), the semiconductor substrate (4) is irradiated with laser light (LB) to form a modified layer (42); the segmentation process is to grind the back surface of the semiconductor substrate (4) to remove the cracks (60) from the modified layer (42). 42) growing and dividing the wafer (2) into individual flash memory wafers (12); and a DAF dividing process on the back side of the wafer (2) that is divided into individual flash memory wafers (12) (2b) Configure the DAF62 and expand the support tape (66) supporting the DAF62 to separate the DAF62 into each flash memory chip (12).

Description

Wafer processing methods

The present invention relates to a wafer processing method, which involves alternately stacking a first memory layer of a plurality of metal films and an insulating film on the surface of a semiconductor substrate, and alternately using the insulating layer as a bonding layer on the first memory layer. A wafer in which a plurality of flash memory wafers composed of a plurality of laminated second memory layers of metal films and insulating films is divided by dividing predetermined lines is divided into individual flash memory wafers.

Devices such as IC, LSI, and flash memory are laminated on the surface of a semiconductor substrate such as silicon, and are divided along planned division lines to be produced in the form of a wafer. Furthermore, the wafer is divided into individual devices by processing devices such as laser processing equipment and dicing equipment, and each divided device is used in electrical appliances such as mobile phones and personal computers.

Furthermore, there is a proposal to position a focusing point of a laser light of a wavelength that is penetrating to the semiconductor substrate inside the semiconductor substrate and irradiate the semiconductor substrate with the laser light along the planned division line inside the semiconductor substrate. A technique in which a modified layer is formed, and then the back surface of a semiconductor substrate is ground and thinned, and cracks are grown from the modified layer to divide the wafer into individual devices (see, for example, Patent Document 1). [Prior technical literature] [Patent Document]

[Patent Document 1] Japanese Patent Application Publication No. 2014-7330

[Problem to be solved by the invention]

The above-mentioned technology has the advantage of disposing an adhesive sheet called DAF (Die Attach Film) on the back side of a wafer that is divided into individual devices for expansion, and dividing the DAF into sizes corresponding to the devices.

However, a plurality of metal films and insulating films are alternately laminated on the first memory layer to be connected to the surface of the semiconductor substrate, and a plurality of metal films and insulating films are alternately laminated on the first memory layer using the insulating layer as a bonding layer. When a plurality of flash memory wafers composed of the second memory layer are divided into individual flash memory wafers by dividing predetermined lines, when the above technology is used, there is a growth from the modified layer. The crack zigzags in the bonding layer and reaches the second memory layer, damaging the second memory layer and preventing the wafer from being properly divided into individual flash memory chips.

The object of the present invention, which was created in view of the above-mentioned facts, is to provide a wafer processing method that can appropriately divide a wafer on which a plurality of flash memory chips are formed. [Means used to solve problems]

In order to solve the above problems, the present invention provides the following wafer processing method. It is a wafer processing method in which a first memory layer in which a plurality of metal films and insulating films are alternately stacked is connected to the surface of a semiconductor substrate, and an insulating layer is alternately used as a bonding layer on top of the first memory layer. A method for processing a wafer in which a plurality of flash memory wafers composed of a plurality of laminated second memory layers of metal films and insulating films are divided into separate flash memory wafers by dividing predetermined lines. It is characterized in that it consists of at least the following process: a cutting groove forming process, which uses a cutting blade to cut the planned division line to form a cutting groove in the second memory layer; The modification layer forming process is to position the focusing point of laser light with a wavelength that is penetrating to the semiconductor substrate inside the semiconductor substrate corresponding to the planned division line and irradiate the semiconductor substrate with the laser light to form a modified layer. quality layer; a dividing process, which is to grind the back side of the semiconductor substrate to cause cracks to grow from the modified layer to divide the wafer into individual flash memory wafers; and a DAF dividing process, which is to divide the wafer into individual flash memory wafers The backside of the wafer is equipped with DAF and the support tape supporting DAF is expanded to separate the DAF into each flash memory chip.

In the cutting groove forming process, it is preferable that the cutting groove reaches the bonding layer. [Effects of the invention]

Because the wafer processing method provided by the present invention at least consists of the following processes: a cutting groove forming process, which is to use a cutting knife to cut the planned division line to form a cutting groove in the second memory layer; a modified layer forming process, which is Positioning the condensing point of the laser light having a penetrating wavelength with respect to the semiconductor substrate inside the semiconductor substrate corresponding to the planned dividing line and irradiating the semiconductor substrate with the laser light to form a modified layer; and the dividing process, which The backside of the semiconductor substrate is ground to cause cracks to grow from the modified layer to divide the wafer into individual flash memory wafers; and the DAF division process is provided on the backside of the wafer that is divided into individual flash memory wafers. The DAF is divided into individual flash memory wafers by expanding the support tape supporting the DAF. Therefore, cracks growing from the modified layer are not guided to the cutting grooves in a zigzag manner, and the wafer can be appropriately divided into individual flash memory wafers. Memory chip.

Hereinafter, embodiments of the wafer processing method of the present invention will be described with reference to the drawings.

In FIG. 1 , a wafer 2 that can be processed by the wafer processing method of the present invention is shown. The disc-shaped wafer 2 has a plurality of flash memory chips 12, which are connected to the first memory layer 6 of a plurality of metal films and insulating films alternately laminated on the surface of the semiconductor substrate 4. The insulation is provided on the first memory layer 6. As a bonding layer 8, the second memory layer 10 of a plurality of metal films and insulating films is alternately stacked. The plurality of flash memory chips 12 are partitioned by grid-like dividing lines 14 .

As the semiconductor substrate 4 of the wafer 2, for example, a silicon substrate having a thickness of about 400 μm can be used. As the first memory layer 6 and the second memory layer 10, it is preferable that a total of 48 layers of metal films and insulating films are alternately laminated to a thickness of about 10 μm, or a total of 32 layers of metal films and insulating films are alternately laminated to a thickness of about 8 μm. . Furthermore, as the bonding layer 8, a nitride film or a SiO ₂ film with a thickness of about 1 μm can be used.

In the embodiment shown in the figure, a cutting groove forming process is first performed in which the planned division line 14 is cut with a cutting blade to form a cutting groove in the second memory layer 10 . The cutting groove forming process can be implemented using, for example, the cutting device 16 partially shown in FIGS. 1 and 2 . The dicing device 16 includes a nip holding table 18 that suctions and holds the wafer 2, and a cutting means 20 that cuts the wafer 2 that is suctioned and held by the nip holding table 18 (see FIG. 2 ).

As shown in FIG. 1 , a porous circular suction nip plate 22 connected to a suction means (not shown) is arranged at the upper end portion of the nip tray mounting base 18 . The suction means is attached to the nip tray mounting base 18 . An attractive force is generated on the upper surface of the suction chuck 22 to attract and hold the wafer 2 placed thereon. Furthermore, the clamping plate mounting table 18 is rotated by a clamping plate mounting table motor (not shown) around an axis extending in the up-down direction, and is rotated by an X-axis feeding means (not shown). The X-axis direction indicated by arrow X in Figure 1 is forward and backward.

As shown in FIG. 2 , the cutting means 20 includes a rotating sleeve 24 extending in the Y-axis direction orthogonal to the X-axis direction (the direction indicated by arrow Y in FIG. 2 ), and rotates with the Y-axis direction as the axis. The rotating shaft 26 is freely supported on the rotating shaft sleeve 24, a rotating shaft motor (not shown) that rotates the rotating shaft 26, and an annular cutting blade 28 installed on the front end of the rotating shaft 26. The rotating shaft sleeve 24 moves forward and backward in the Y-axis direction by a Y-axis feeding means (not shown), and moves up and down in the up and down direction by a lifting means (not shown). In addition, the planes defined in the X-axis direction and the Y-axis direction are substantially horizontal.

As shown in FIG. 1(a) , in the cutting groove forming process, the surface 2 a of the wafer 2 is first directed upward, and the wafer 2 is attracted and held on the chuck mounting table 18 . Next, the imaging means (not shown) of the cutting device 16 is used to image the wafer 2 from above. Based on the image of the wafer 2 captured by the imaging means, the planned division line 14 is aligned in the X-axis direction, and the cutting blade is 28 is positioned above the planned division line 14 aligned in the X-axis direction. Next, the cutting blade 28 is rotated in the direction indicated by arrow A in FIG. 2 . Next, the rotating sleeve 24 is lowered, so that the cutting edge of the cutting blade 28 is cut into the planned division line 14 aligned in the X-axis direction, and the clamping plate mounting table 18 is relatively moved in X with respect to the cutting means 20 at a specific feed speed. The machining feed is performed in the axial direction, thereby performing cutting processing to form the cutting groove 30 in the second memory layer 10 along the planned division line 14 . The width of the cutting groove 30 is about 20 μm, for example. Furthermore, the depth of the cutting groove 30 is set to be at least the same depth as the thickness of the second memory layer 10 (for example, about 8 μm or about 10 μm), so as to reach the depth of the bonding layer 8 (for example, about 9 μm or about 11 μm). Better. Or as shown in FIG. 3 , the cutting groove 30 may go beyond the bonding layer 8 and reach the first memory layer 6 .

Next, only the parts spaced between the planned division lines 14 in the Y-axis direction are relatively indexed in the Y-axis direction with respect to the nip plate mounting table 18 . Furthermore, by alternately repeating the cutting process and the indexing feed, the cutting grooves 30 are formed along all the aligned dividing lines 14 in the X-axis direction. Furthermore, after rotating the puck mounting table 18 90 degrees, by alternately repeating the cutting process and indexing feed, the cutting groove 30 is formed along all the planned dividing lines 14 that are orthogonal to the planned dividing lines 14 where the cutting grooves 30 were previously formed. Cutting groove 30. In this way, the cutting groove forming process is performed, and the cutting grooves 30 are formed in a grid shape along the grid-shaped planned division lines 14 .

After the cutting groove formation process is carried out, a modified layer forming process is carried out. This modified layer forming process is performed by positioning the focusing point of the laser light with a wavelength penetrating to the semiconductor substrate 4 corresponding to the planned division line 14. The inside of the semiconductor substrate 4 is irradiated with laser light to form a modified layer. The modified layer formation process can be implemented using, for example, the laser processing device 32 partially shown in FIGS. 4 and 5 . The laser processing apparatus 32 includes a nip table 34 that attracts and holds the wafer 2, and a light collector 36 that irradiates the wafer 2 sucked and held by the nip table 34 with laser pulse light LB (see FIG. 5 ). As shown in FIG. 4 , a porous circular suction nip plate 38 connected to a suction means (not shown) is disposed at the upper end portion of the nip tray mounting base 34 . Furthermore, the puck mounting base 34 is configured to be rotatable and to be capable of moving forward and backward in the X-axis direction and the Y-axis direction.

When the description continues with reference to FIG. 4 , in the modified layer formation process, first, a circular protective tape 40 for protecting the flash memory chip 12 is affixed to the surface 2 a of the wafer 2 where the cutting grooves 30 are formed in a grid shape. . Next, with the back surface 2 b of the wafer 2 facing upward, the wafer 2 is sucked and held on the chuck mounting table 34 . Next, the imaging means (not shown) of the laser processing device 32 is used to image the wafer 2 from above. Based on the image of the wafer 2 captured by the imaging means, the planned division line 14 is aligned in the X-axis direction, and the The condenser 36 is positioned above the planned division line 14 aligned in the X-axis direction. At this time, although the back surface 2 b of the wafer 2 faces upward and the surface 2 a on which the planned division line 14 is formed faces downward, the imaging means of the laser processing device 32 includes an infrared ray irradiation means of irradiating the wafer 2 with infrared rays, and a capture means. An optical system that irradiates infrared rays by infrared irradiation means, and an imaging element (infrared CCD) that outputs an electrical signal corresponding to the infrared rays captured by the optical system, can transmit the planned division lines on the surface 2a through the back surface 2b of the wafer 2 14.

Next, the focusing point position adjustment means (not shown) of the laser processing device 32 is used to raise and lower the focusing point of the pulse laser light LB on the semiconductor substrate 4 corresponding to the planned division line 14 interior. Next, as shown in FIG. 5 , while the nip plate 34 is relatively processed in the X-axis direction at a specific feed speed relative to the condenser 36 , the semiconductor substrate 4 is irradiated from the condenser 36 . The pulse laser light LB having a penetrating wavelength is used to form a modified layer forming process along the planned division line 14 to form the modified layer 42 inside the semiconductor substrate 4 . In addition, although the modified layer 42 is formed inside the semiconductor substrate 4 and does not appear substantially on the back surface, the image is expressed as a chain line. The modified layer 42 has a smaller strength than its surroundings, and, as shown in FIG. 6 , extends in the thickness direction of the semiconductor substrate 4 . Next, only the portions of the planned division lines 14 spaced apart in the Y-axis direction are indexed and fed relative to the condenser 36 by the nip tray 34 in the Y-axis direction. Furthermore, by alternately repeating the cutting process and the indexing feed, the modified layer 42 is formed inside the semiconductor substrate 4 along all the planned dividing lines 14 aligned in the X-axis direction. Furthermore, after rotating the nip plate mounting table 34 90 degrees, by alternately repeating the modified layer forming process and the indexing feed, all division plans orthogonal to the division plan lines 14 on which the modified layer 42 was previously formed are formed. The wires 14 form the modified layer 42 inside the semiconductor substrate 4 . In this way, the modified layer forming process is performed, and the modified layer 42 is formed in a lattice shape inside the semiconductor substrate 4 along the lattice-shaped planned division lines 14 . Such a modified layer forming process can be carried out under the following processing conditions, for example.

Wavelength of pulsed laser light: 1064nm

Repeat frequency: 80kHz

Average output: 1.0W

Feed speed: 400mm/s

After the modified layer formation process is performed, a dividing process is performed. This dividing process is to grind the back surface of the semiconductor substrate 4 (the back surface 2b of the wafer 2) to grow cracks from the modified layer 42 to divide the wafer 2 into individual flash memories. Bulk wafer 12. The dividing process can be carried out using, for example, the grinding device 44 partially shown in FIG. 7 . The grinding device 44 includes a chuck mounting base 46 that attracts and holds the wafer 2, and a grinding means 48 that grinds the wafer 2 that is attracted and held by the chuck mounting base 46.

The nip stage 46 is rotatably configured to attract and hold the wafer 2 thereon. The grinding means 48 includes a rotating shaft 50 connected to a rotating shaft motor (not shown) and extending in the up-down direction, and a disc-shaped roller bracket 52 fixed to the lower end of the rotating shaft 50 . Under the roller bracket 52, the annular grinding wheel 56 is fixed by bolts 54. A plurality of grinding grindstones 58 are fixed to the outer peripheral portion of the lower surface of the grinding wheel 56 and are arranged annularly at intervals in the circumferential direction.

Continuing the description with reference to FIG. 7 , in the dividing process, first, the back surface 2 a of the wafer 2 is directed upward, and the wafer 2 is attracted and held on the upper surface of the nip mounting table 46 . Next, the clamping tray mounting base 46 is rotated in the counterclockwise direction at a specific rotation speed (for example, 300 rpm) when viewed from above. Furthermore, when viewed from above, the rotating shaft 50 is rotated in the counterclockwise direction at a specific rotation speed (for example, 6000 rpm). Next, the rotating shaft 50 is lowered using the lifting means (not shown) of the grinding device 44 so that the grinding grindstone 58 contacts the back surface 2 b of the wafer 2 . After that, the rotating shaft 50 is lowered at a specific grinding feed speed (for example, 1.0 μm/s). Accordingly, the backside 2b of the wafer 2 can be ground to modify the wafer 2 to a specific thickness (for example, about 100 μm).

Furthermore, during grinding of the wafer 2 , a specific pressing force due to the grinding feed acts on the wafer 2 , so the cracks 60 move from the modified layer 42 formed inside the semiconductor substrate 4 toward the thickness direction of the wafer 2 grow. In the embodiment shown in the figure, as shown in FIG. 8(b) , in the cutting groove forming process, the cutting groove 30 is formed beyond the bonding layer 8 and reaches the first memory layer 6 , so that the modification is performed. The layer 42 grows up to the point where the cracks 60 of the first memory layer 6 are led into cutting grooves 30 without tortuosity. Therefore, as shown in FIG. 8( a ), the wafer 2 can be appropriately divided into individual parts along the planned division line 14 by using the grid-shaped cracks 60 grown from the grid-shaped modified layer 42 as a starting point for division. Flash memory chip 12. Furthermore, since the crack 60 grown from the modified layer 42 is used as the starting point for division, the time interval between adjacent flash memory chips 12 is essentially zero. In addition, if the depth of the cutting groove 30 is at least the same as the thickness of the second memory layer 10 , the cracks 60 growing from the modified layer 42 will not bend in the bonding layer 8 . Furthermore, in the illustrated embodiment, the modified layer 42 is removed by grinding. However, the modified layer 42 may not be removed and the dividing starting point may include the modified layer 42 .

After the division process is carried out, a DAF division process is carried out, in which a DAF is arranged on the back 2b of the wafer 2 divided into each flash memory chip 12, and the supporting tape supporting the DAF is expanded to divide the DAF into each flash. Memory chip 12. In the DAF dividing process, first, a circular DAF 62 having the same diameter as the wafer 2 is prepared. In the illustrated embodiment, as shown in FIG. 9 , the DAF 62 is supported at the central portion of a circular support tape 66 fixed to a frame 64 with an annular periphery. Furthermore, DAF 62 is attached and arranged on the back surface 2 b of the wafer 2 divided into individual flash memory chips 12 . At this time, although the wafer 2 is divided into individual flash memory chips 12 , the disc-shaped wafer 2 is maintained in the shape of the protective tape 40 . Next, as shown in FIG. 10 , the protective tape 40 is removed from the surface 2 a of the wafer 2 divided into individual flash memory chips 12 . In addition, in FIG. 10 , reference numeral 68 indicates a dividing line formed from the cutting groove 30 or the crack 60 or the like.

Then, the supporting tape 66 supporting the DAF62 is expanded to separate the DAF62 into each flash memory chip 12 . The segmentation of the DAF 62 can be performed using, for example, the expansion device 70, a portion of which is shown in FIG. 11 . The expansion device 70 includes a cylindrical expansion drum 72, an annular holding member 74 that is arranged radially outward of the expansion drum 72 in an elevating and lowering manner, and is attached to the holding member 74 at intervals in the circumferential direction. A plurality of holding tools 76 on the outer periphery of the upper end. The diameter of the expansion drum 72 is larger than the diameter of the wafer 2 and smaller than the inner diameter of the frame 64 . Furthermore, the inner diameter and outer diameter of the holding member 74 are formed to correspond to the inner diameter and outer diameter of the frame 64 , so that the frame 64 can be placed on the upper surface of the holding member 74 .

Continuing the description with reference to FIG. 11 , first, the wafer 2 divided into individual flash memory chips 12 is placed upward, and the frame 64 is placed on the upper surface of the holding member 74 . At this time, the upper surface of the holding member 74 is positioned at almost the same height as the upper end of the expansion drum 72 shown by the solid line in FIG. 11 . Next, the frame 64 is fixed with a plurality of clamps 76 . Next, the holding member 74 is lowered by a lifting means (not shown) such as a cylinder. In this way, since the frame 64 and the holding member 74 are lowered together, the support tape 66 fixed to the frame 64 is expanded by the expansion drum 72 that rises relatively, so that radial tension acts on the support tape 66 . Accordingly, as shown by the two-dot chain line in FIG. 11 , the distance between adjacent flash memory chips 12 becomes wider, and the DAF 62 arranged on the back surface 2 b of the divided wafer 2 follows each flash. The memory wafer 12 is divided appropriately (neatly) along the periphery of each flash memory wafer 12 . Furthermore, each flash memory chip 12 on which DAF62 is mounted on the back side is mounted on a printed circuit board (not shown) or the like via an adhesive sheet (DAF62).

As described above, in the illustrated embodiment, during the dividing process, the cracks 60 grown from the modified layer 42 are not guided to the cutting grooves 30 in a zigzag manner, so the wafer 2 can be divided along the planned dividing line 14 Appropriately divided into individual flash memory wafers 12. Furthermore, in the illustrated embodiment, since the cracks 60 grown from the modified layer 42 are used as the starting point for division, the spacing between adjacent flash memory chips 12 can be substantially zero and, In the illustrated embodiment, in the DAF dividing process, the DAF 62 can be divided appropriately (neatly) along the periphery of each flash memory chip 12 .

In addition, before the cutting groove forming process is carried out, the DAF 62 is disposed on the back surface 2 b of the wafer 2 , and it is considered that not only the second memory layer 10 but also the DAF 62 also interacts with the first memory layer 6 and the semiconductor substrate 4 during the cutting trench forming process. When cutting together, with DAF62 installed on the backside 2b of wafer 2, during cutting, wafer 2 shakes due to the elasticity of the adhesive layer of DAF62, so on the backside 2b side of wafer 2, Cracks occurring inside the wafer 2 may have a negative impact on the quality of the flash memory chip 12 . However, in the illustrated embodiment, since the DAF 62 is not disposed on the back surface 2b of the wafer 2 during the cutting groove formation process, and the cutting groove 30 is formed on the second memory layer 10, on the back surface 2b side of the wafer 2, No cracks are generated inside the wafer 2 .

2‧‧‧wafer 4‧‧‧Semiconductor substrate 6‧‧‧The first memory layer 8‧‧‧Combining layer 10‧‧‧Second memory layer 12‧‧‧Flash memory chip 30‧‧‧Cutting groove 42‧‧‧Modification layer 60‧‧‧Crack 62‧‧‧DAF

FIG. 1 (a) is a perspective view showing a state where a wafer is placed on a chuck stage of a dicing device, and (b) is a cross-sectional view of the wafer. FIG. 2 is a perspective view showing a state in which a cutting groove forming process is carried out. Figure 3 is a cross-sectional view of a wafer with cutting grooves formed. FIG. 4 is a perspective view of a state in which a protective tape is disposed on the surface of a wafer and the wafer is placed on a chuck mounting table of the laser processing apparatus. FIG. 5 is a perspective view showing a state in which a modified layer formation process is carried out. Figure 6 is a cross-sectional view of a wafer with cutting grooves and modified layers formed. Fig. 7 is a perspective view showing a state in which division work is carried out. 8(a) is a perspective view of a wafer divided into individual flash memory chips, and (b) is a cross-sectional view of the wafer divided into individual flash memory chips. FIG. 9 is a perspective view of a state where a DAF is disposed on the back side of a wafer divided into individual flash memory chips. FIG. 10 is a perspective view showing a state in which the protective tape is removed from the surface of the wafer divided into individual flash memory chips. FIG. 11 is a perspective view showing a state in which the DAF is divided into individual flash memory wafers.

2‧‧‧wafer

2a‧‧‧Surface

2b‧‧‧Back

6‧‧‧The first memory layer

8‧‧‧Combining layer

10‧‧‧Second memory layer

12‧‧‧Flash memory chip

30‧‧‧Cutting groove

40‧‧‧Protective tape

46‧‧‧Plate holding table

60‧‧‧Crack

Claims (2)

A method for processing a wafer, which consists of alternately stacking a first memory layer of a plurality of metal films and an insulating film on the surface of a semiconductor substrate, and alternately stacking an insulating layer as a bonding layer on top of the first memory layer. A wafer processing method in which a plurality of flash memory wafers composed of a plurality of metal films and a second memory layer of an insulating film is divided into individual flash memory wafers by dividing predetermined lines is characterized in that , consisting of at least the following projects: The cutting groove forming process is to use a cutting blade to cut the planned division line to form a cutting groove in the second memory layer; The modification layer forming process is to position the focusing point of laser light with a wavelength that is penetrating to the semiconductor substrate inside the semiconductor substrate corresponding to the planned division line and irradiate the semiconductor substrate with the laser light to form a modified layer. qualitative layer; and The dividing process is to grind the back side of the semiconductor substrate to cause cracks to grow from the modified layer to divide the wafer into individual flash memory wafers; and In the DAF dividing process, a DAF is placed on the back side of a wafer divided into individual flash memory wafers, and a support tape supporting the DAF is expanded to divide the DAF into individual flash memory wafers. The wafer processing method as described in claim 1, wherein In the cutting groove forming process, the cutting groove reaches the bonding layer.