TWI824623B - 晶片結構及其製法、半導體封裝結構及其製法 - Google Patents
晶片結構及其製法、半導體封裝結構及其製法 Download PDFInfo
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- TWI824623B TWI824623B TW111126748A TW111126748A TWI824623B TW I824623 B TWI824623 B TW I824623B TW 111126748 A TW111126748 A TW 111126748A TW 111126748 A TW111126748 A TW 111126748A TW I824623 B TWI824623 B TW I824623B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 220
- 229910052751 metal Inorganic materials 0.000 claims abstract description 220
- 239000010410 layer Substances 0.000 claims description 256
- 235000012431 wafers Nutrition 0.000 claims description 57
- 238000004806 packaging method and process Methods 0.000 claims description 50
- 238000004519 manufacturing process Methods 0.000 claims description 35
- 239000007787 solid Substances 0.000 claims description 32
- 239000008393 encapsulating agent Substances 0.000 claims description 24
- 238000002161 passivation Methods 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 239000012790 adhesive layer Substances 0.000 claims description 10
- 239000000565 sealant Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 210000000746 body region Anatomy 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000010292 electrical insulation Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 6
- 238000007789 sealing Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 125000000843 phenylene group Chemical group C1(=C(C=CC=C1)*)* 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
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Abstract
本發明係一種晶片結構及其製法、半導體封裝結構及其製法,其中該晶片結構包含一晶片本體、多個分別形成於該晶片本體之晶片接墊上的金屬凸塊,與直接形成於該晶片本體上的圖樣凸塊;其中該圖樣凸塊包含有至少二個不同上、下平面圖樣,而該些金屬凸塊的頂面均高於該上平面圖樣所在的一高度位置;當研磨該晶片結構至該高度位置,該圖樣凸塊的上平面圖樣會與該些金屬凸塊經研磨後的該頂面齊平;故於封裝時,可藉由檢測該圖樣凸塊的上平面圖樣是否外露,來判斷該些金屬凸塊是否全部外露且齊平,避免發生研磨深度不足或過研磨的情況。
Description
本發明係一種晶片結構及其製法、半導體封裝結構及其製法,特別指一種可避免過研磨的晶片結構及其製法、晶片優先的半導體封裝結構及其製法。
晶圓級封裝的晶片優先半導體封裝結構的製程中,會對如圖10A所示之一晶片90進行封膠製程,以一封膠體94一併包覆該晶片90的一主動面91、形成於該主動面91上的多個晶片接墊92以及多個金屬凸塊93,最後研磨該封膠體94,使該些金屬凸塊93外露,以利後續的重佈線層製程的進行。
然而於研磨製程中,研磨的深度不易控制,如圖10A所示,該封膠體94的研磨深度不足,部分金屬凸塊93外露於該封膠體94,而部分金屬凸塊93a並未外露於該封膠體94,或是如圖10B所示該封膠體94的研磨深度過深,使部分金屬凸塊93b被研磨過多,甚至是將該些金屬凸塊93研磨至消失,或是損傷該些晶片接墊92。
因此,有必要進一步改良現有的晶片結構及半導體封裝結構。
有鑑於上述既有晶片結構及半導體封裝結構的缺陷,本發明的主要目的係提供一種新的晶片結構及其製法、半導體封裝結構及其製法,以解決先前技術的缺陷。
為達上述目的,本發明所使用的主要技術手段係令上述晶片結構包括:一晶片本體,係包含一主動面,該主動面係包含一晶片接墊區以及一無晶片接墊區,其中該晶片接墊區係形成多個晶片接墊;多個金屬凸塊,係分別形成於該晶片接墊區的對應晶片接墊上,且該些金屬凸塊的頂面均高於一第一高度;以及至少一圖樣凸塊,係形成於該無晶片接墊區;其中該至少一圖樣凸塊係包含二不同的第一平面圖樣及第二平面圖樣,且該第一平面圖樣係位在該第一高度,該第二平面圖樣係位在一第二高度處,且該第二高度係低於該第一高度。
由上述說明可知,本發明主要於該晶片本體的主動面上形成至少一圖樣凸塊,其中該至少一圖樣凸塊在不同高度處包含二不同平面圖樣,而其中較高的第一平面圖樣係位於該第一高度;如此,當研磨此一晶片結構至第一高度處,該至少一圖樣凸塊的較高平面圖樣會與該些金屬凸塊經研磨後的該頂面齊平;是以,當此一晶片結構進行封裝時,可藉由該平面圖樣是否外露,而判斷該些金屬凸塊的頂面均已外露,即代表研磨深度已足夠,以避免過度研磨的情況發生,提升該封裝的良率。
為達上述目的,本發明所使用的主要技術手段係令上述晶片結構的製法包括:(a)提供一晶圓,該晶圓包含有多個晶片本體區域,各該晶片本體區域包含有一主動面,該主動面包含有一晶片接墊區以及一無晶片接墊區,並於該些晶片接墊區形成多個晶片接墊;(b)於該些晶片接墊區內的各該晶片接墊形成一金屬凸塊,並於該些無晶片接墊區形成多個圖樣凸塊,該些圖樣凸塊在不同高度處包含二不同的第一平面圖樣及第二平面圖樣;其中該些金屬凸塊的頂面均高於一第一高度,且各該圖樣凸塊的該第一平面圖樣係位於該第一高度,該第二平面圖樣則位於一第二高度;其中該第二高度低於該第一高度;以及(c)切割該些晶片本體區域的相鄰邊界,形成多個晶片結構。
由上述說明可知,本發明的晶片結構的製法主要於各該晶片本體區域之無晶片接墊區形成多個圖樣凸塊,且由於各該圖樣凸塊的第一平面圖樣係位於該第一高度,當此一晶片結構經研磨至第一高度處,各該圖樣凸塊的第一平面圖樣會與位在相同晶片本體區域中該些金屬凸塊的經研磨後的頂面齊平;因此,當各該晶片結構進行封裝並於研磨製程步驟中,可藉由檢測其圖樣凸塊所外露的該平面圖樣,以判斷各該晶片本體區域中的該些金屬凸塊的頂面是否一併外露,可確保各該晶片結構不會發生研磨深度不足或過度研磨的狀況。
為達上述目的,本發明的主要技術手段係令上述半導體封裝結構包括:一第一線路層;
至少一晶片結構,係設置於該第一線路層上,其包含:一主動面,係形成有多個金屬凸塊及至少一圖樣凸塊,且該主動面朝上;其中該至少一圖樣凸塊在不同高度係包含二不同平面圖樣,且其中一平面圖樣與該些金屬凸塊的頂面齊平;多個金屬柱,係形成於該第一線路層上,並與該第一線路層電連接;一封膠體,係形成於該第一線路層上,並包覆該至少一晶片及該些金屬柱於其中;其中該封膠體的一上表面與該至少一晶片的各該金屬凸塊的該頂面、該至少一圖樣凸塊的其中一平面圖樣及各該金屬柱的一頂面齊平,以構成一平面;以及一第二線路層,係形成於該平面上,以與該些金屬凸塊及該些金屬柱電連接,並與該些圖樣凸塊電絕緣。
由上述說明可知,本發明的半導體封裝結構係主要封裝一具有圖樣凸塊的晶片結構,由於該圖樣凸塊的其中一平面圖樣與係該些金屬凸塊的頂面齊平,故於半導體封裝製程的研磨步驟期間,藉由檢測該平面圖樣外露,可得知該些金屬凸塊的該頂面均外露並齊平,同時亦與該些金屬柱的頂面齊平,而構成一平面,一併確保後續形成於該平面上的該第二線路層的良率。
為達上述目的,本發明所使用的主要技術手段係令上述半導體封裝結構的製法包括:(a)提供一載板,於該載板上形成一第一線路層;(b)於該第一線路層上形成多個金屬柱,該些金屬柱係分別與該第一線路層電連接;
(c)將多個晶片結構設置於該第一線路層上,其中各該晶片結構包含一主動面,該主動面係形成有多個金屬凸塊及至少一圖樣凸塊,且該主動面朝上;其中該些圖樣凸塊的其中一平面圖樣與該些金屬凸塊的頂面齊平;(d)於該第一線路層上形成一封膠體,以包覆該些金屬柱及該些晶片;(e)研磨該封膠體的一上表面,直到該上表面與該些晶片的各該金屬凸塊的該頂面、該至少一圖樣凸塊的其中一平面圖樣及該些金屬柱的頂面齊平,以構成一平面;(f)於該平面上形成一第二線路層,令該第二線路層與該些金屬柱及該些晶片的該些金屬凸塊電連接,並與該些圖樣凸塊電絕緣;(g)移除該載板;以及(h)進行一切割步驟,以分離各該半導體封裝結構。
由上述說明可知,本發明的半導體封裝結構的製法係主要由該封膠體包覆該第一線路層上的該些金屬柱及具有至少一圖樣凸塊的該些晶片,由於該圖樣凸塊的其中一平面圖樣係與該同一晶片上的該些金屬凸塊的頂面齊平,故於封膠體研磨步驟中,可判斷該平面圖樣外露,得知該些金屬凸塊的該頂面均已外露且齊平,同時亦與該些金屬柱的頂面齊平,而構成一平面,一併確保後續形成於該平面上的該第二線路層的良率。
10、10’:晶片結構
100:晶圓
11:晶片本體
110:晶片本體區域
111:主動面
112:鈍化層
113:晶片接墊區
114:無晶片接墊區
115:晶片接墊
12:金屬凸塊
121:頂面
122:第一底面
13:圖樣凸塊
131:第一平面圖樣
132:第二平面圖樣
133:外中空金屬柱
1331:第二底面
134:內實心金屬柱
1341:第三底面
14:第一介電層
140:頂面
141:第一開孔
142:第二開孔
15:第二介電層
151:頂面
20、20’、20”:半導體封裝結構
21:封裝體
211:錫球
30、30’:第一線路層
31:開口
32:金屬線路
33:翹曲控制層
34:底面
40:晶片
41:黏著層
42:背面
50:金屬柱
51:頂面
60、60’、600:封膠體
61、610:上表面
62:平面
70、70’:第二線路層
71:金屬墊
72:被動元件
73:焊球
80:載板
81:黏膠層
90:晶片
91:主動面
92:晶片接墊
93、93a、93b:金屬凸塊
94:封膠體
圖1A:本發明晶片結構的第一實施例的一剖面圖。
圖1B:圖1A晶片結構於第一高度的一剖面圖。
圖2A:圖1A晶片結構的一局部放大圖。
圖2B:圖2A的A-A割面線的一剖面圖。
圖2C:圖2A的B-B割面線的一剖面圖。
圖3A:本發明晶片結構的第二實施例的一局部放大剖面圖。
圖3B:本發明晶片結構的第三實施例的一局部放大剖面圖。
圖4A至圖4E:本發明晶片結構的製程中不同步驟的剖面圖。
圖5A:圖4D的F1區域的一局部放大圖。
圖5B:圖4D的F2區域的一局部放大圖。
圖6:本發明半導體封裝結構的第一實施例的一剖面圖。
圖7:本發明半導體封裝結構的第二實施例的一剖面圖。
圖8:本發明半導體封裝結構的第三實施例的一剖面圖。
圖9A至圖9E:本發明半導體封裝結構的製法之封裝製程中不同步驟的剖面圖。
圖10A、圖10B:現有技術之半導體封裝結構的剖面圖。
本發明係針對晶片結構及其製法、半導體封裝結構及其製法進行改良,以下謹以多個實施例配合圖式詳加說明本發明的技術內容。
首先說明本發明之晶片結構的技術內容,請參閱圖1A,係本發明晶片結構10的第一實施例,其包含一晶片本體11、多個金屬凸塊12以及至少一圖樣凸塊13。
請參閱圖1A及圖1B,如圖1A所示,上述晶片本體11的一主動面111係包含一晶片接墊區113以及一無晶片接墊區114,其中該晶片接墊區113係形成多個晶片接墊115,以供該些金屬凸塊12分別形成於其上,而該無晶片接墊區114則供該至少一圖樣凸塊13形成於其中,即該至少一圖樣凸塊13直接形成於該主動面111上,各該圖樣凸塊13係在不同高度處包含二個平面圖樣,如圖2B及圖2C所示的第一平面圖樣131及第二平面圖樣132;其中該些金屬凸塊12的頂面121均高於一第一高度L1,且各該圖樣凸塊13的第一平面圖樣131係位於該第一高度L1,該第二平面圖樣132則位於一第二高度L2;其中該第二高度L2小於該第一高度L1(以晶片本體11的其中一平面為共同基準高度L0);於本實施例,如圖1B所示,該無晶片接墊區114係可圍繞該晶片接墊區113,但不以此為限。
請參閱圖1A及圖2A,於本實施例,該晶片本體11的主動面111係進一步形成一第一介電層14,其對應該些晶片接墊115形成多個第一開孔141,且對應該至少一圖樣凸塊13形成至少一第二開孔142;於本實施例,該第一介電層14的頂面140係位在該第二高度L2,該第二開孔142係呈一環形開孔,但不以此為限,而該第一介電層14的材料係選自聚醯亞胺(polyimide,PI)、聚對伸苯基並二噁唑(PBO)或其他相似材料;又於本實施例,該第一介電層14係呈透明或半透明,且如圖2A所示,該第一介電層14的高度範圍H1為3μm至7μm。於一實施例,該晶片本體11的該主動面111與該第一介電層14之間係可進一步形成一鈍化層112。
請繼續參閱圖1A,於本實施例,該晶片本體11的該第一介電層14的頂面140係形成一第二介電層15,以包覆各該金屬凸塊12及該至少一圖樣
凸塊13,如圖1A所示,該第二介電層15的頂面151係高於該第一高度L1;於本實施例,該第二介電層15的材料係可與該第一介電層14同樣選自PI、PBO或其他相似材料;又於本實施例,該第二介電層15係可與該第一介電層14同樣呈透明或半透明,且該第二介電層15的高度範圍H2為10μm至20μm。於本實施例,該第一介電層14的楊氏模量較該第二介電層15的楊氏模量為高,即該第一介電層14較該第二介電層15硬,因此,該第一介電層14可於後續晶片封裝製程中保護形成於該主動面111上之較脆的該鈍化層112,或進一步保護由該鈍化層112覆蓋,且形成於該主動面111上的一內層鈍化層(圖上未示出)。
請繼續參閱圖1A,上述多個金屬凸塊12係分別形成於該晶片接墊區113的對應晶片接墊115上,其中於本實施例,如圖2A所示,各該金屬凸塊12的一第一底面122係匹配穿入對應的第一開孔141並形成於其對應的晶片接墊115上;於本實施例,各該金屬凸塊12位在該第一開孔141的部分的直徑小於其在該第二介電層15的部分的直徑,即如圖2A所示,各該金屬凸塊12位在該第一開孔141的部分之上端的一第一直徑D1小於其在該第二介電層15中的部分的一第二直徑D2;又於本實施例,各該金屬凸塊12係一實心金屬柱。
請參閱圖1A,上述至少一圖樣凸塊13係形成於該無晶片接墊區114,由於該些金屬凸塊12的頂面121、各該圖樣凸塊13的第一平面圖樣131及第二介電層15的頂面151均高於該第一高度L1,故經研磨後至該第一高度L1或研磨至低於該第一高度L1但高於第二高度L2後,即如圖2A及2B所示,該圖樣凸塊13的該第一平面圖樣131即與該些金屬凸塊12的頂面121及該第二介電層15的頂面151齊平。於一實施例,可將四組圖樣凸塊13分別設置於該晶片本體11的該無晶片接墊區114的四個角落;於本實施例,係將二組圖樣凸塊13設置於
該無晶片接墊區114的二相鄰角落或相對角落,但該圖樣凸塊13的數量、相對位置及設置排列方式均不以此為限。
以下進一步說明該至少一圖樣凸塊13的結構,請參閱圖2A,上述各圖樣凸塊13係包含一外中空金屬柱133以及一內實心金屬柱134,其中該外中空金屬柱133的一第二底面1331係匹配穿入該第一介電層14之對應的第二開孔142,並形成於該主動面111上;又於本實施例,該第二底面1331係形成於該鈍化層112上;該內實心金屬柱134的一第三底面1341係穿入對應的外中空金屬柱133內,並形成於該第一介電層14上,並與該外中空金屬柱133相隔一間隙G,其中該間隙G係填滿該第二介電層15;如此,在該第一介電層14的高度範圍H1內,並不存在該內實心金屬柱134,藉以令該圖樣凸塊13在經研磨後之該第二介電層15的高度範圍H2內呈現該第一平面圖樣131。於本實施例,各該外中空金屬柱133位在該第二開孔142的部分的直徑小於其在該第二介電層15的部分的直徑,即各該外中空金屬柱133位在該第二開孔142的部分之上端的一第三直徑D3小於其在該第二介電層15中的部分的一第四直徑D4;又於本實施例,如圖2B所示,該外中空金屬柱133係為一中空圓柱體,因此於圖2A中,其對應之第二開孔142係呈一”O”字形;故於本實施例,如圖2B所示,該第一平面圖樣131呈同心圓圖樣;而在該第一介電層14的高度範圍H1內(即不高圖1A所示之第二高度L2)呈現該第二平面圖樣132,即如圖2C所示,呈單一空心圓圖樣;於另一實施例,該內實心金屬柱134可為一實心角柱體,即如圖3A所示,該第一平面圖樣131呈外圓內方圖樣,而該第二平面圖樣呈單一空心圓形圖樣;或於另一實施例,該外中空金屬柱133可為一中空角柱體,即如圖3B所示,該第一平面圖樣131呈外方內圓圖樣,而該第二平面圖樣呈單一空心方形圖樣,自然也
可令該第一平面圖樣131呈同心四角形圖樣;如此,該至少一圖樣凸塊13的外中空金屬柱133及該內實心金屬柱134的形狀組合可任意搭配,該至少一圖樣凸塊13的形狀並不限於同心圓柱體或同心四角柱體。
以上為本發明晶片結構的結構說明,以下進一步說明本發明晶片結構之製法,請參閱圖4A至圖4E,係本發明晶片結構的第一實施例的製法,其包含下述之步驟(a)至(c)。
於步驟(a)中,如圖4A所示,提供一晶圓100,該晶圓100包含有多個晶片本體區域110,各該晶片本體區域110包含有一主動面111,該主動面111包含有一晶片接墊區113以及一無晶片接墊區114,並於該些晶片接墊區113形成多個晶片接墊115。
於步驟(b)中,如圖4B及4C所示,於該些晶片接墊區113內的各該晶片接墊115形成一金屬凸塊12,並於該些無晶片接墊區114形成多個圖樣凸塊13,該些圖樣凸塊13在不同高度處包含二不同的第一平面圖樣131及第二平面圖樣132;配合參閱圖1A及圖2B所示,其中該些金屬凸塊12的頂面121均高於一第一高度L1,且各該圖樣凸塊13的第一平面圖樣131係位於該第一高度L1,再如圖1A及圖2C所示,該第二平面圖樣132則位於一第二高度L2;其中該第二高度L2低於該第一高度L1。該步驟(b)中係進一步包含下述之步驟(b1)至(b3),也可進一步包含步驟(b4),且該些步驟(b1)至(b4)係對應圖4B至圖4E。
於步驟(b1)中,如圖4B所示,於該主動面111上形成一第一介電層14,其中該第一介電層14係對應該些晶片接墊115形成多個第一開孔141,各該第一開孔141係匹配對應的金屬凸塊12並貫穿該第一介電層14,並於該無晶片接墊區114形成多個第二開孔142;於本實施例,如圖1A所示,其中該第一介
電層14的一頂面係位在該第二高度L2,且該第一介電層14係呈透明或半透明。於一實施例,各該晶片本體區域110的該主動面111與該第一介電層14之間係可進一步形成一鈍化層112。
於步驟(b2)中,如圖4C所示,於外露於各該第一開孔141的對應晶片接墊115上形成該些金屬凸塊12,並於該些無晶片接墊區114形成該些圖樣凸塊13;其中各該圖樣凸塊13的一外中空金屬柱133係形成於該主動面111上;於本實施例,各該外中空金屬柱133係形成於該主動面111上之對應的第二開孔142;於本實施例,各該外中空金屬柱133係形成於該鈍化層112上;各該圖樣凸塊13的一內實心金屬柱134係形成於對應的外中空金屬柱133內的該第一介電層14的該頂面上,並與其對應外中空金屬柱133相隔一間隙G;再配合圖1A所示,其中該些金屬凸塊12的頂面121及各該圖樣凸塊13的該外中空金屬柱133的頂面及該內實心金屬柱134的頂面均高於該第一高度L1,各該圖樣凸塊13位在該第一高度L1的該外中空金屬柱133及該內實心金屬柱134係構成該第一平面圖樣131,即如圖2B所示;而位在第二高度L2的該外中空金屬柱133係構成該第二平面圖樣132,即如圖2C所示。於本實施例,該外中空金屬柱133係為一中空圓柱體或一中空角柱體,且該內實心金屬柱134係為一實心圓柱體或一實心角柱體。
於步驟(b3)中,如圖4D所示,於該第一介電層14上形成一第二介電層15,如圖4D之F1區域及圖5A所示,該第二介電層15係包覆該些金屬凸塊12及該些圖樣凸塊13於其中;或如圖4D之F2區域及圖5B所示,該第二介電層15係覆蓋該些金屬凸塊12的側面、各該圖樣凸塊13的該外中空金屬柱133及該內實心金屬柱134的側面,惟如圖1A所示,該第二介電層15的頂面151係高於該
第一高度L1;又該第二介電層15係一併填充該些外中空金屬柱133及該些內實心金屬柱134之間的間隙G;於本實施例,該第二介電層15係呈透明或半透明,且該第一介電層14的楊氏模量較該第二介電層15的楊氏模量為高。
於步驟(b4)中,研磨至如圖4D所示的第一高度L1處,即如圖4E所示,該第二介電層15的該頂面151、該些圖樣凸塊13的該第一平面圖樣131及該些金屬凸塊12的該頂面121齊平;於本實施例,如圖4D所示,各該金屬凸塊12位在該第一開孔141的部分的直徑係小於其在該第二介電層15的部分的直徑;又於本實施例,各該外中空金屬柱133位在該第二開孔142的部分的直徑係小於其在該第二介電層15中的部分的直徑。
於步驟(c)中,如圖4E所示,切割該些晶片本體區域110的相鄰邊界,形成多個晶片結構10’。
由上述說明可知,上述晶片結構10於進行後續封裝製程中的研磨製程時可防止研磨深度不足或過研磨之現象發生,首先請參閱圖2B,當該晶片結構10被研磨達一預設的目標深度時,即向下研磨至第一高度L1,該圖樣凸塊13的該第一平面圖樣131與該些金屬凸塊12的該頂面121齊平,此時,可判斷該晶片結構10的研磨深度足夠並可不必再進行研磨;再請參閱圖1A,當該晶片結構被研磨至第二高度L2時,此時該圖樣凸塊13的該內實心金屬柱134消失,如圖2C所示,該圖樣凸塊13的該第二平面圖樣132外露於該第一介電層14,故藉由檢測該第二平面圖樣132是否出現,可輕易地確認圖1A的晶片結構10於後續的封裝製程中是否被過研磨,進一步提升良率。
以上為本發明晶片結構及其製法的說明,以下進一步說明本發明以上述晶片結構10進行半導體封裝的半導體封裝結構及其製法;首先說明本發明之半導體封裝結構的技術內容。
請參閱圖6,係本發明半導體封裝結構20的第一實施例,其包含一第一線路層30、至少一晶片40、多個金屬柱50、一封膠體60、一第二線路層70;其中該至少一晶片40係上述之晶片結構10,且該至少一晶片40、該些金屬柱50及該封膠體60係形成於該第一線路層30上,該第二線路層70係形成於該封膠體60上。
上述第一線路層30係包含多個開口31,且該第一線路層30中的金屬線路32之部分係自該些開口31外露;於本實施例,該第一線路層30係一重佈線層,於另一實施例,該第一線路層30也可為一基板,但均不以此為限。
上述至少一晶片40係設置於該第一線路層30上,且該至少一晶片40的該主動面111朝上;於本實施例,該至少一晶片40係進一步包含一黏著層41,其係設置於該至少一晶片40的一背面42與該第一線路層30之間;又於本實施例,該半導體封裝結構20係包含一晶片40,但該至少一晶片40的設置數量並不以此為限。
上述多個金屬柱50係形成於該第一線路層30上,並與該第一線路層30電連接,其中該些金屬柱50係圍繞該至少一晶片40。
上述封膠體60係形成於該第一線路層30上,並包覆該至少一晶片40及該些金屬柱50於其中;其中該封膠體60的一上表面61係與該至少一晶片40的各該金屬凸塊12的該頂面121、該至少一圖樣凸塊13的該第一平面圖樣131、該第二介電層15的該頂面151以及各該金屬柱50的一頂面51齊平,以共同
構成一平面62。由於該至少一晶片40的該些金屬凸塊12與該至少一圖樣凸塊13間係由第二介電層15包覆,故該封膠體60不會填充於該些金屬凸塊12與該至少一圖樣凸塊13間;因此,相較以封膠體60材料包覆,本發明以第二介電層15包覆該至少一晶片40的該些金屬凸塊12與該至少一圖樣凸塊13,可避免以該封膠體60包覆而在研磨時可能產生的剝落或空洞,以確保該平面62的構成與平整度,可提高後續於該平面62上製作重佈線層,尤其是製作重佈線層中的細線路的良率。
上述第二線路層70係形成於該平面62上,以與該至少一晶片40的該些金屬凸塊12及該些金屬柱50電連接,且由於該些圖樣凸塊13僅為輔助研磨之用而不與該晶片40電連接,該第二線路層70係與該些圖樣凸塊13電絕緣;於本實施例,該第二線路層70係進一步包含多個金屬墊71,其係分別形成於該第二線路層70上,並與該第二線路層70電連接;又於本實施例,該第二線路層70係一重佈線層,於另一實施例,該第二線路層70也可為一基板,但均不以此為限。
於本實施例,係進一步包含至少一被動元件72及多個焊球73,該至少一被動元件72係電連接該第二線路層70的對應金屬墊71,並靠近對應的該晶片40;該些焊球73係形成於該第二線路層70的對應金屬墊71上,且該些焊球73係圍繞對應的被動元件72。於本實施例,該半導體封裝結構20係對應該晶片40包含一被動元件72,且該被動元件72係盡可能靠近其對應晶片40,以縮短電性及訊號傳輸路徑;又於本實施例,該被動元件72可為一積體被動元件(Integrated passive device,IPD)或一積層陶瓷電容器(Multi-layer ceramic capacitor,MLCC),但並不以此為限。
再請參閱圖7,係本發明半導體封裝結構20的第二實施例,於本實施例,係將另一封裝體21疊設於本發明第一實施例之該半導體封裝結構20的該第一線路層30上,其中該封裝體21的多個錫球211係分別穿過該第一線路層30的對應開口31與該金屬線路32電連接而達成層疊式封裝(package on package,PoP)。
再請參閱圖8,係本發明的第三實施例,本實施例的半導體封裝結構20’與圖6所示之該半導體封裝結構20大致相同,惟不同之處在於該第一線路層30係進一步包含一翹曲控制層33,其係形成於該第一線路層30上;其中該第一線路層30的該些開口31係向上貫穿該翹曲控制層33,且各該開口31周壁於該第一線路層30的斜率係與其在該翹曲控制層33的斜率相同;於本實施例,由於該第一線路層30之重佈線層的層數較該第二線路層70之重佈線層的層數少,該第二線路層70的收縮力較該第一線路層30的收縮力大,所以該半導體封裝結構20’會向下翹曲;因此,在該第一線路層30上設置該翹曲控制層33可消除該第一線路層30與該第二線路層70之間的應力差異,使其收縮力相同,消除該半導體封裝結構20’的翹曲。
由上述本發明第一實施例的說明可知,該半導體封裝結構20係以該封膠體60包覆該晶片40及該些金屬柱50,可藉由檢測該至少一圖樣凸塊13的該第一平面圖樣131是否外露於該封膠體60的上表面61,確保各該金屬凸塊12的該頂面121及各該金屬柱50的該頂面51均完整外露,並與該第二介電層15的該頂面151齊平,以與該第二線路層70電連接,可避免研磨深度不足或過研磨的情況;此外,該第一及第二介電層14、15已全面覆蓋該晶片40的該主動面111,該封膠體60不會包覆該些金屬凸塊12及該至少一圖樣凸塊13,於後續之
研磨製程時,可減少該封膠體60及該第二介電層15所受到的應力,填充於該些金屬凸塊12及該至少一圖樣凸塊13之間的第二介電層15不會脫落,於形成該第二線路層70時,該平面62不會有坑洞而可避免因該第二線路層70中的金屬線路凹陷所造成的元件失效;又由本發明的第三實施例可知,可進一步在該第一線路層30上設置該翹曲控制層33以消除該第一及第二線路層30、70之間層數不同而產生的翹曲,進一步提升該半導體封裝結構20’的良率及可靠度。
以上為本發明半導體封裝結構20的結構說明,以下進一步說明本發明半導體封裝結構20的封裝方法,請參閱圖9A至圖9E,係本發明半導體封裝結構的第一實施例的製法,其包含下述之步驟(a)至(h)。
於該步驟(a),如圖9A所示,提供一載板80,於該載板80上形成一第一線路層30’;於本實施例,一黏膠層81係預先形成於該載板80上,該些第一線路層30’再形成於該黏膠層81上,其中該黏膠層81可為一膠黏層或一剝離層。
於該步驟(b),如圖9A所示,於該第一線路層30’上形成多個金屬柱50,該些金屬柱50係分別與該第一線路層30’電連接,並將多個為上述之晶片結構10的晶片40設置於該第一線路層30’上,且各該晶片40的該主動面111朝上;於本實施例,係進一步於各該晶片40的一背面42及該第一線路層30’之間設置一黏著層41。
於該步驟(c),如圖9B所示,於該第一線路層30’上形成一封膠體600,以包覆該些金屬柱50及該些晶片40;於本實施例,該封膠體600的一上表面610係高於該些金屬柱50的該頂面51及該些晶片40的該第二介電層15的該頂面151
於該步驟(d),研磨如圖9B所示之該封膠體600的一上表面610,直到如圖9C所示,該封膠體60’的該上表面61與該些晶片40的該些金屬凸塊12的該頂面121、該至少一圖樣凸塊13的該第一平面圖樣131、該第二介電層15的該頂面151以及各該金屬柱50的該頂面51齊平,以共同構成一平面62。
於該步驟(e),如圖9C所示,於該平面62上形成一第二線路層70’,令該第二線路層70’與該些金屬柱50及該些晶片40的該金屬凸塊12電連接,並與該些圖樣凸塊13電絕緣;於本實施例,係進一步於該第二線路層70’上形成多個金屬墊71,該些金屬墊71係與該第二線路層70’中的金屬線路電連接。
於該步驟(f),如圖9D所示,移除該載板80,使該第一線路層30’的底面34外露;於本實施例,如圖9E所示,係進一步於該第一線路層30’的該底面34形成多個開口31,以令該第一線路層30’中的金屬線路32之部分自該些開口31外露;又於本實施例,如圖9E所示,係進一步將多個焊球73形成於該第二線路層70’上的對應金屬墊71,並將多個被動元件72電連接該第二線路層70’上的對應金屬墊71,其中各該被動元件72係靠近對應的該晶片40並由該些焊球73圍繞。
於該步驟(g),如圖9E所示,進行一切割步驟,以分離各該半導體封裝結構20”。
由上述說明可知,本發明的半導體封裝結構20的製法係由該封膠體600包覆該第一線路層30’上的該些晶片40及該些金屬柱50,由於該些圖樣凸塊13的該第一平面圖樣131與同一晶片40上的該些金屬凸塊12的該頂面121齊平,於該封膠體600的研磨步驟中,可藉由判斷該第一平面圖樣131外露,確
保該些金屬凸塊12的該頂面121完整外露,並與該些金屬柱50的該頂面51齊平以構成一平面62,不會發生研磨深度不足或過研磨的情況,一併確保後續形成於該平面62上的該第二線路層70’的良率。
以上所述僅是本發明的實施例而已,並非對本發明做任何形式上的限制,雖然本發明已以實施例揭露如上,然而並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明技術方案的範圍內,當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例,但凡是未脫離本發明技術方案的內容,依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾,均仍屬於本發明技術方案的範圍內。
10:晶片結構
11:晶片本體
111:主動面
112:鈍化層
113:晶片接墊區
114:無晶片接墊區
115:晶片接墊
12:金屬凸塊
121:頂面
13:圖樣凸塊
14:第一介電層
140:頂面
15:第二介電層
151:頂面
Claims (25)
- 一種晶片結構,包括:一晶片本體,係包含一主動面,該主動面係包含一晶片接墊區以及一無晶片接墊區,其中該晶片接墊區係形成多個晶片接墊;多個金屬凸塊,係分別形成於該晶片接墊區的對應晶片接墊上,且該些金屬凸塊的頂面均高於一第一高度;以及至少一圖樣凸塊,係形成於該無晶片接墊區;其中該至少一圖樣凸塊係包含二不同形狀的第一平面圖樣及第二平面圖樣,且該第一平面圖樣係位在該第一高度,該第二平面圖樣係位在一第二高度處,且該第二高度係低於該第一高度。
- 如請求項1所述之晶片結構,係進一步包含:一第一介電層,係形成於該主動面上,並對應該些晶片接墊形成多個第一開孔,各該第一開孔係匹配對應的金屬凸塊並貫穿該第一介電層,並於該無晶片接墊區對應該至少一圖樣凸塊形成至少一第二開孔;其中該第一介電層的頂面係位於該第二高度;以及一第二介電層,係形成於該第一介電層上;其中該第二介電層係包覆各該金屬凸塊及該至少一圖樣凸塊,且該第二介電層的一頂面係高於該第一高度。
- 如請求項2所述之晶片結構,其中該晶片本體的該主動面與該第一介電層之間係進一步形成一鈍化層。
- 如請求項3所述之晶片結構,其中:各該金屬凸塊遠離其頂面的一底面係匹配穿入對應的第一開孔,並形成於其對應的晶片接墊上,且各該金屬凸塊係一實心金屬柱;以及 各該至少一圖樣凸塊係包含:一外中空金屬柱,其遠離該第二介電層的該頂面的一底面係匹配穿入對應的第二開孔,並形成於該鈍化層上;其中位在該第二高度的該外中空金屬柱係構成該第二平面圖樣;以及一內實心金屬柱,其遠離該第二介電層的該頂面的一底面係穿入對應的外中空金屬柱內,並形成於該第一介電層上,並與該外中空金屬柱相隔一間隙,其中該間隙係由該第二介電層填滿;其中位在該第一高度的該外中空金屬柱及該內實心金屬樣係構成該第一平面圖樣。
- 如請求項4所述之晶片結構,其中:該第一介電層係呈透明或半透明;該第二介電層係呈透明或半透明;以及該第一介電層的楊氏模量較該第二介電層的楊氏模量為高。
- 如請求項4或5所述之晶片結構,其中:各該金屬凸塊位在該第一開孔的部分的直徑係小於其在該第二介電層中的部分的直徑;或各該外中空金屬柱位在該第二開孔的部分的直徑係小於其在該第二介電層中的部分的直徑。
- 如請求項6所述之晶片結構,其中:該外中空金屬柱係為一中空圓柱體或一中空角柱體;以及該內實心金屬柱係為一實心圓柱體或一實心角柱體。
- 一種晶片結構的製法,包括: (a)提供一晶圓,該晶圓包含有多個晶片本體區域,各該晶片本體區域包含有一主動面,該主動面包含有一晶片接墊區以及一無晶片接墊區,並於該些晶片接墊區形成多個晶片接墊;(b)於該些晶片接墊區內的各該晶片接墊形成一金屬凸塊,並於該些無晶片接墊區形成多個圖樣凸塊,該些圖樣凸塊在不同高度處包含二不同形狀的第一平面圖樣及第二平面圖樣;其中該些金屬凸塊的頂面均高於一第一高度,且各該圖樣凸塊的該第一平面圖樣係位於該第一高度,該第二平面圖樣則位於一第二高度;其中該第二高度低於該第一高度;以及(c)切割該些晶片本體區域的相鄰邊界,形成多個晶片結構。
- 如請求項8所述之晶片結構的製法,其中該步驟(b)係進一步包含:(b1)於該主動面上形成一第一介電層,其中該第一介電層係對應該些晶片接墊形成多個第一開孔,各該第一開孔係匹配對應的金屬凸塊並貫穿該第一介電層,並於該無晶片接墊區形成多個第二開孔;其中該第一介電層的一頂面係位在該第二高度;(b2)於外露於各該第一開孔的晶片接墊上形成該些金屬凸塊,並於該些無晶片接墊區形成該些圖樣凸塊;其中各該圖樣凸塊的一外中空金屬柱係形成於該主動面上之對應的第二開孔,且各該圖樣凸塊的一內實心金屬柱係形成於對應的外中空金屬柱內的該第一介電層的該頂面上,並與其對應外中空金屬柱相隔一間隙;其中該些金屬凸塊的頂面及各該圖樣凸塊的該外中空金屬柱的頂面及該內實心金屬柱的頂面均高於該第一高度,各該圖樣凸塊位在該第一高度的 的該外中空金屬柱及該內實心金屬柱係構成該第一平面圖樣,而位在第二高度的該外中空金屬柱係構成該第二平面圖樣;以及(b3)於該第一介電層上形成一第二介電層,其中該第二介電層係覆蓋該些金屬凸塊的側面、各該圖樣凸塊的該外中空金屬柱及該內實心金屬柱的側面或包覆該些金屬凸塊及該些圖樣凸塊於其中;其中該第二介電層係一併填充該些外中空金屬柱及該些內實心金屬柱之間的間隙。
- 如請求項9所述之晶片結構的製法,其中該步驟(c)於切割該些晶片本體區域的相鄰邊界前,進一步研磨該些金屬凸塊的該頂面及該些圖樣凸塊或該第二介電層的一頂面至該第一高度,使該第二介電層經研磨後的頂面、該些圖樣凸塊的該些第一平面圖樣及該些金屬凸塊經研磨後的該頂面齊平。
- 如請求項9所述之晶片結構的製法,其中該步驟(b1)係進一步於各該晶片本體區域的該主動面與該第一介電層之間形成一鈍化層。
- 如請求項9所述之晶片結構的製法,其中:該第一介電層係呈透明或半透明;該第二介電層係呈透明或半透明;以及該第一介電層的楊氏模量較該第二介電層的楊氏模量為高。
- 如請求項9至12中任一項所述之晶片結構的製法,其中:各該金屬凸塊位在該第一開孔的部分的直徑係小於其在該第二介電層中的部分的直徑;或各該外中空金屬柱位在該第二開孔的部分的直徑係小於其在該第二介電層中的部分的直徑。
- 如請求項13所述之晶片結構的製法,其中:該外中空金屬柱係為一中空圓柱體或一中空角柱體;以及該內實心金屬柱係為一實心圓柱體或一實心角柱體。
- 一種半導體封裝結構,包括:一第一線路層;至少一如請求項1至7中任一項所述之晶片結構,係設置於該第一線路層上,且其晶片本體的該主動面朝上;多個金屬柱,係形成於該第一線路層上,並與該第一線路層電連接;一封膠體,係形成於該第一線路層上,並包覆該至少一晶片及該些金屬柱於其中;其中該封膠體的一上表面與該至少一晶片的各該金屬凸塊的該頂面、該至少一圖樣凸塊的第一平面圖樣及各該金屬柱的一頂面齊平,以共同構成一平面;以及一第二線路層,係形成於該平面上,以與該至少一晶片的該些金屬凸塊及該些金屬柱電連接,並與該些圖樣凸塊電絕緣。
- 如請求項15所述之半導體封裝結構,其中:該第一線路層係包含多個開口,該第一線路層中的金屬線路之部分係自該些開口外露;以及該第二線路層係進一步包含多個金屬墊,其係分別形成於該第二線路層上,並與該第二線路層電連接。
- 如請求項16所述之半導體封裝結構,係進一步包含:至少一被動元件,其係電連接該第二線路層的對應金屬墊,並靠近對應的晶片;以及 多個焊球,其係形成於該第二線路層的對應金屬墊上,且該些焊球係圍繞對應的被動元件。
- 如請求項16或17所述之半導體封裝結構,其中該第一線路層上進一步形成一翹曲控制層;其中該些開口係向上貫穿該翹曲控制層,且各該開口周壁於該第一線路層的斜率係與其在該翹曲控制層的斜率相同。
- 如請求項18所述之半導體封裝結構,其中各該至少一晶片本體的一背面及該第一線路層之間係進一步設置有一黏著層。
- 如請求項19所述之半導體封裝結構,其中該第一線路層係為一基板或一重佈線層,該第二線路層係為一基板或一重佈線層。
- 一種半導體封裝結構的製法,包括:(a)提供一載板,於該載板上形成一第一線路層;(b)將多個如請求項1至7中任一項所述之晶片結構設置於該第一線路層上,且各該晶片本體的該主動面朝上,並於該第一線路層上形成多個金屬柱,該些金屬柱係分別與該第一線路層電連接;(c)於該第一線路層上形成一封膠體,以包覆該些金屬柱及該些晶片;(d)研磨該封膠體的一上表面,直到該上表面與該些晶片的各該金屬凸塊的該頂面、該至少一圖樣凸塊的第一平面圖樣及各該金屬柱的一頂面齊平,以共同構成一平面;(e)於該平面上形成一第二線路層,令該第二線路層與該些金屬柱及該些晶片的該些金屬凸塊電連接,並與該些圖樣凸塊電絕緣;(f)移除該載板,使該第一線路層的底面外露;以及(g)進行一切割步驟,以分離各該半導體封裝結構。
- 如請求項21所述之半導體封裝結構的製法,其中:於該步驟(e),係進一步於該第二線路層上形成多個金屬墊,該些金屬墊係與該第二線路層中的金屬線路電連接;以及於該步驟(f),係進一步於該第一線路層的底面形成多個開口,以令該第一線路層中的金屬線路之部分自該些開口外露。
- 如請求項22所述之半導體封裝結構的製法,其中於該步驟(f)中,係進一步將多個焊球形成於該第二線路層上的對應金屬墊,並將多個被動元件電連接該第二線路層上的對應金屬墊,其中各該被動元件係靠近對應的該晶片並由對應的該些焊球圍繞。
- 如請求項21至23中任一項所述之半導體封裝結構的製法,其中於該步驟(b)中,係進一步於各該晶片的一背面及該第一線路層之間設置一黏著層。
- 如請求項24所述之半導體封裝結構的製法,其中該第一線路層係為一基板或一重佈線層,該第二線路層係為一基板或一重佈線層。
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