TWI824556B - Power factor correction converter, controller and digital peak-hold circuit thereof - Google Patents

Abstract

A power factor correction converter includes a rectifier, a power factor correction controller, a power stage circuit, and a feedback circuit, wherein the power factor correction converter is configured to convert an AC voltage into an output voltage. The power factor correction controller includes an analog-to-digital converter, a digital peak-hold circuit, a reference voltage generator, an error amplifier, and a pulse-width modulation circuit, wherein the power factor correction controller is configured to generate a driving signal according to a rectification signal and a feedback signal. The digital peak-hold circuit includes a delay circuit, a digital rising detector, a tracking register, a digital falling detector, and a holding register, wherein the digital peak-hold circuit is configured to generate a peak signal according to a digital input signal.

Description

Power factor correction converter, controller and its digital peak hold circuit

The present invention relates to a converter, in particular to a power factor correction converter. The present invention also relates to a power factor correction controller and a digital peak hold circuit suitable for a power factor correction converter.

Power Factor Correction converter (PFC converter) is a common circuit in the power supply field. It is often used in power supplies to solve the problem of power loss. Among them, power loss The problem is related to Power Factor (PF). Power factor is defined as the ratio between real power and apparent power, where real power is the power actually consumed by a load coupled to a power supply (such as a power supply), and apparent power is the power consumed by the power supply. The total power required to be supplied. Generally speaking, the power factor is between 0 and 1. When the value of the power factor is less than 1, it means that the voltage and current provided by the power supply are out of phase, thereby causing the power loss. problem; and when the value of the power factor is closer to 0, it means that the power loss problem is more serious.

Please refer to FIG. 1A , which is a module block diagram of a power factor correction converter 10 in the prior art. As shown in FIG. 1A , the power factor correction converter 10 of the prior art includes a rectifier Converter 101, a power factor correction controller 102 and a power stage circuit 103, wherein the power factor correction converter 10 is used to convert an AC voltage Vac into an output voltage Vo in the same phase as it, so that the value of the power factor is close to 1, thereby avoiding the problem of power loss.

Although the power factor correction converter 10 of the prior art can improve the power loss problem, it still has problems of circuit size, cost and overall power consumption during operation. Please refer to FIG. 1B , which is a waveform comparison diagram between the rectified voltage Vi and the output voltage Vo in the power factor correction converter 10 of the prior art. As shown in FIG. 1B , the waveform W1 is the waveform of the output voltage Vo, and the waveform W2 is the waveform of the rectified voltage Vi. The value of the output voltage Vo is a fixed value (for example, 400 volts). The rectified voltage Vi is converted by the rectifier 101 The AC voltage Vac is generated after rectification. As shown in the dotted box Sq1 of FIG. 1B , when the peak value of the rectified voltage Vi is low (for example, 85 volts), the power factor correction converter 10 of the prior art will still convert it to a larger fixed value. (400 volts) output voltage Vo. Since the voltage difference between the peak value of the rectified voltage Vi and the output voltage Vo is large (for example, 315 volts), the power factor correction converter 10 of the prior art must use larger energy storage components (for example, capacitors or inductors). ) and switches (eg, diodes or transistors) to avoid circuit burnout, thereby increasing the cost and overall power consumption during operation of the power factor correction converter 10 of the prior art.

In view of this, the present invention proposes a power factor correction controller and a digital peak hold circuit suitable for a power factor correction converter, so that the value of the output voltage Vo follows the peak change of the rectified voltage Vi to reduce the voltage between the two. difference, thereby reducing the circuit size, cost and overall power consumption of the power factor correction converter during operation.

The invention provides a digital peak hold circuit, including: a delay circuit for delaying a digital input signal to generate a delayed input signal, wherein the delayed input signal is delayed by at least one clock cycle of the digital input signal; a digital rising signal A sensor is used to compare the digital input signal and the delayed input signal to generate a rising signal. When the digital input signal is greater than the delayed input signal, the digital rising sensor controls the rising signal to be converted into a consistent function. state; a tracking register for latching the value of the digital input signal to generate a tracking signal when the rising signal is in the enabled state; a digital falling sensor for comparing the digital input signal and The delayed input signal generates a falling signal, wherein when the digital input signal is smaller than the delayed input signal, the digital falling sensor controls the falling signal to transition to the enabled state; and a holding register for At the point when the falling signal transitions to the enabled state, the value of the tracking signal is latched to generate a peak signal.

In some embodiments, when the tracking register receives a reset signal, the tracking register sets the tracking signal to a reset value, wherein the initial value of the tracking signal is the reset value; and /Or when the holding register receives another reset signal, the holding register sets the peak signal to another reset value, wherein the initial value of the peak signal is the other reset value.

In some embodiments, the above-mentioned digital peak hold circuit further includes a hold signal generator for generating a hold signal. The hold signal generator is used for triggering one of the hold signals when the falling signal transitions to the enabled state. Pulse, wherein the holding register latches the value of the tracking signal at the trigger point of the pulse to generate the peak signal.

In some embodiments, the above-mentioned digital peak hold circuit further includes a digital filter, which is used to shield or filter the noise of the digital input signal, so that the value of the digital input signal is 1/2 of the digital input signal. Monotonically increasing or decreasing within a period or 1/4 period.

In some embodiments, the above-mentioned digital peak hold circuit is suitable for a power factor correction converter, wherein the power factor correction converter includes: a rectifier for rectifying an AC voltage to generate a rectified voltage; a power stage circuit, It includes at least one switch and an inductor for converting the rectified voltage into an output voltage through a switched inductor conversion method; a feedback circuit for generating a feedback signal according to the output voltage ; An analog-to-digital converter for converting a rectified signal into a digital input signal, wherein the rectified signal is related to the rectified voltage; a reference voltage generator for generating a reference voltage based on the peak signal; an error An amplifier for generating an error amplification signal based on the difference between the feedback signal and the reference voltage; and a pulse width modulation circuit for pulse width modulation of the error amplification signal to generate a driver A signal, wherein the driving signal is used to control the switching of the at least one switch.

In some embodiments, the rectified signal has a full-wave rectification form or a half-wave rectification form.

In some embodiments, there is a linear or piecewise linear mapping relationship between the reference voltage and the peak signal, so that the output voltage and the value of the rectified voltage corresponding to the peak signal have a corresponding linear or piecewise linear mapping relationship. Another mapping relationship, in which the output voltage is always greater than the value of the rectified voltage corresponding to the peak signal.

In some embodiments, the reference voltage generator includes: a lookup table for mapping the peak signal according to the mapping relationship to generate a mapping output signal; and a digital-to-analog converter for converting the mapping output signal is the reference voltage, wherein the mapping output signal is a digital signal, and the reference voltage is an analog signal.

In some embodiments, the lookup table includes a read only memory (ROM), a random access memory (RAM), a flash memory (Flash), and combinations thereof.

The present invention also provides a power factor correction controller suitable for a power factor correction converter, including: an analog-to-digital converter for converting a rectified signal into a digital input signal; a digital peak hold circuit for A peak signal is generated according to the digital input signal. The digital peak hold circuit includes: a delay circuit for delaying the digital input signal to generate a delayed input signal, wherein the delayed input signal is delayed by at least one time from the digital input signal. pulse cycle; a digital rising sensor for comparing the digital input signal and the delayed input signal to generate a rising signal, wherein when the digital input signal is greater than the delayed input signal, the digital rising sensor controls the The rising signal is converted to the enabled state; a tracking register is used to latch the value of the digital input signal to generate a tracking signal at the time when the rising signal is converted to the enabled state; a digital falling sensor, For comparing the digital input signal and the delayed input signal to generate a falling signal, wherein when the digital input signal is smaller than the delayed input signal, the digital falling sensor controls the falling signal to transition to the enabled state; and a holding register for latching the value of the tracking signal to generate the peak signal when the falling signal transitions to the enabled state; a reference voltage generator for generating a reference based on the peak signal voltage; an error amplifier for generating an error amplification signal based on the difference between a feedback signal and the reference voltage; and a pulse width modulation circuit for pulse width modulation of the error amplification signal A driving signal is generated, wherein the driving signal is used to control the switching of at least one switch.

The present invention also provides a power factor correction converter, which includes: a rectifier for rectifying an AC voltage to generate a rectified voltage; a power factor correction controller for generating a rectified voltage based on a rectified signal and a feedback signal. The driving signal, wherein the rectified signal is related to the rectified voltage, the power factor correction controller includes: an analog-to-digital converter for converting the rectified signal into a digital input signal; a digital peak hold circuit for The digital input signal generates a peak signal. The digital peak hold circuit includes: a delay circuit for delaying the a digital input signal to generate a delayed input signal, wherein the delayed input signal is delayed by at least one clock cycle of the digital input signal; a digital rising sensor for comparing the digital input signal and the delayed input signal to generate a rising signal, wherein when the digital input signal is greater than the delayed input signal, the digital rising sensor controls the rising signal to transition to an enabled state; a tracking register is used to when the rising signal is in the enabled state , latches the value of the digital input signal to generate a tracking signal; a digital drop sensor is used to compare the digital input signal and the delay input signal to generate a drop signal, wherein when the digital input signal is less than the delay input When the signal is generated, the digital falling sensor controls the falling signal to transition to the enabled state; and a holding register is used to latch the value of the tracking signal at the time when the falling signal transitions to the enabled state. to generate the peak signal; a reference voltage generator to generate a reference voltage based on the peak signal; an error amplifier to generate an error amplification signal based on the difference between the feedback signal and the reference voltage ; and a pulse width modulation circuit for performing pulse width modulation on the error amplification signal to generate a drive signal, wherein the drive signal is used to control the switching of the switch; a power stage circuit including at least one switch and an inductor for converting the rectified voltage into an output voltage through a switched inductive conversion method; and a feedback circuit for generating the feedback signal according to the output voltage.

The following will be described in detail through specific embodiments to make it easier to understand the purpose, technical content, characteristics and achieved effects of the present invention.

10:Power factor correction converter

20:Power factor correction converter

100: Rectifier

101: Rectifier

102:Power factor correction controller

103: Power stage circuit

200:Power factor correction controller

210:Analog-to-digital converter

220: Digital peak hold circuit

221: Delay circuit

222:Digital rise sensor

223: Trace register

224:Digital drop sensor

225: Hold register

226:Hold signal generator

230: Reference voltage generator

231:Lookup table

232:Digital to analog converter

240: Error amplifier

250: Pulse width modulation circuit

300: Power stage circuit

400:Feedback circuit

AND: AND gate

clk: clock

C1: Capacitor

COM: comparator

D:Input terminal

D1: Diode

D-FF:D type flip-flop

DRV: drive signal

D _Vo : Map output signal

D _VAC : digital input signal

D _VAC [k]: The value of the digital input signal at the kth clock cycle

D _VAC [k-1]: The value of the digital input signal at the k-1th clock cycle

D _VAC _falling: falling signal

D _VAC _holding:holding signal

D _VAC _peak:peak signal

D _VAC _rising: rising signal

D _VAC _tracking: tracking signal

DD _VAC : Delay input signal

DD _VAC [k]: The value of delayed input signal in the kth clock cycle

k, k-1: clock cycle count value

L1:Inductor

Q: Positive phase output terminal

Q_bar: inverting output terminal

Q1: Transistor

R1-R2: Resistor

Reg: temporary register

S1-S3: Segmentation

S100-S400: Steps

S210-S250: Steps

S221-S225: Steps

Sq1: dashed box

t1-t5: time point

T1-T3: time period

Vac: AC voltage

Vref: reference voltage

VAC: rectified signal

VEOA: error amplification signal

VFB: feedback signal

Vi: rectified voltage

Vo: output voltage

W1-W8: waveform

FIG. 1A is a module block diagram of a prior art power factor correction converter.

FIG. 1B is a waveform comparison diagram between the rectified voltage and the output voltage in the power factor correction converter of the prior art.

FIG. 2 is a module block diagram of a power factor correction converter according to an embodiment of the present invention.

FIG. 3 is a module block diagram of a power factor correction controller according to an embodiment of the present invention.

FIG. 4 is a waveform diagram of the input/output voltage of each component in the power factor correction controller as a function of time in one embodiment of the present invention.

FIG. 5A is a module block diagram of a digital peak hold circuit according to an embodiment of the present invention.

FIG. 5B is a module block diagram of a digital peak hold circuit in another embodiment of the present invention.

FIG. 6A is a circuit schematic diagram of a digital peak hold circuit in one embodiment of the present invention.

FIG. 6B is a circuit schematic diagram of a digital peak hold circuit in another embodiment of the present invention.

7A and 7B are module block diagrams of a digital peak hold circuit in another embodiment of the present invention.

FIG. 8A is a schematic diagram of the mapping relationship between the reference voltage and the peak signal in one embodiment of the present invention.

FIG. 8B is a schematic diagram of a reference voltage generator in an embodiment of the present invention.

FIG. 9 is a circuit schematic diagram of a power stage circuit in an embodiment of the present invention.

FIG. 10 is a schematic circuit diagram of a feedback circuit in an embodiment of the present invention.

FIG. 11A is a flowchart (1) of the control method of the power factor correction converter in one embodiment of the present invention.

FIG. 11B is a flowchart (2) of the control method of the power factor correction converter in one embodiment of the present invention.

FIG. 11C is a flowchart (3) of the control method of the power factor correction converter in one embodiment of the present invention.

FIG. 12 is a waveform comparison diagram between the AC voltage and the output voltage in the power factor correction converter in one embodiment of the present invention.

The diagrams in the present invention are schematic and are mainly intended to represent the coupling relationship between circuits and the relationship between signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale. For the sake of clear explanation, many practical details will be explained in the following description, but this is not intended to limit the patentable scope of the present invention.

Please refer to FIG. 2 , which is a module block diagram of the power factor correction converter 20 in one embodiment of the present invention. As shown in FIG. 2 , the power factor correction converter 20 includes a rectifier 100 , a power factor correction controller 200 , a power stage circuit 300 and a feedback circuit 400 . The power factor correction controller 200 is coupled to the rectifier 100 , the power factor correction controller 200 and the feedback circuit 400 . The power stage circuit 300 and the feedback circuit 400 are coupled to the rectifier 100 and the feedback circuit 400 . The structure and function of each of the rectifier 100, the power factor correction controller 200, the power stage circuit 300 and the feedback circuit 400 will be explained in detail below, and the operation of each other will be described.

In some embodiments, the rectifier 100 is used to rectify an AC voltage Vac into a rectified voltage Vi, where the rectified voltage Vi is a half-wave signal or a full-wave signal. When the rectified voltage Vi is the half-wave signal, it means that the rectifier 100 eliminates the negative voltage in the AC voltage Vac, and then rectifies it into the rectified voltage Vi in the form of half-wave rectification; when the rectified voltage Vi is the full-wave signal wave signal, it represents that the rectifier 100 converts the AC voltage Vac The negative voltage in is converted into a positive voltage, which is then rectified into a rectified voltage Vi in the form of full-wave rectification. The structure and function of the rectifier are well known to those with ordinary knowledge in the technical field to which the present invention belongs, and therefore will not be described in detail.

In some embodiments, the power factor correction controller 200 is used to generate a driving signal DRV according to the rectified signal VAC and a feedback signal VFB, where the rectified signal VAC is related to the rectified voltage Vi. In some embodiments, the rectified signal VAC is a half-wave signal or a full-wave signal, where the rectified signal VAC may be equal to or not equal to the rectified voltage Vi. In other words, when the rectified voltage Vi is a half-wave signal, the rectified signal VAC is the half-wave signal or a full-wave signal; when the rectified voltage Vi is a full-wave signal, the rectified signal VAC is a half-wave signal or The full wave signal.

Please refer to FIG. 3 , which is a schematic circuit diagram of the power factor correction controller 200 in one embodiment of the present invention. As shown in FIG. 3 , in some embodiments, the power factor correction controller 200 includes an analog-to-digital converter 210 , a digital peak hold circuit 220 , a reference voltage generator 230 , an error amplifier 240 and a pulse width modulation Circuit 250, in which the analog-to-digital converter 210 is coupled to the digital peak hold circuit 220, the digital peak hold circuit 220 is coupled to the reference voltage generator 230, the reference voltage generator 230 is coupled to the error amplifier 240, and the error amplifier 240 is coupled to the pulse width modulation Transform circuit 250. The structures and functions of the decimal peak holding circuit 220, the reference voltage generator 230, the error amplifier 240 and the pulse width modulation circuit 250 of the analog-to-digital converter 21 will be explained in detail below, and the operation of each other will be described.

Please refer to FIG. 4 . FIG. 4 is a waveform diagram of the input/output voltage of each component in the power factor correction controller 200 changing with time in one embodiment of the present invention. As shown in Figure 4, in some embodiments, the analog-to-digital converter 210 is used to convert the rectified signal VAC (corresponding to the waveform W3) into a digital input signal D _VAC (corresponding to the waveform W4), wherein the digital input signal D _VAC is a continuous staircase waveform, and the digital input signal D _VAC is based on a clock frequency to continuously update its value. As shown in the clock clk and waveform W4 in Figure 4, the value of the digital input signal D _VAC is updated every time a clock cycle passes. The structure and function of the analog-to-digital converter are well known to those with ordinary knowledge in the technical field to which the present invention belongs, and therefore will not be described in detail.

In some embodiments, the digital peak hold circuit 220 is used to generate a peak signal D _{VAC_peak} according to the digital input signal D _VAC . Please refer to FIG. 5A , which is a module block diagram of the digital peak hold circuit 220 in one embodiment of the present invention. As shown in FIG. 5A, the digital peak hold circuit 220 includes a delay circuit 221, a digital rising sensor 222, a tracking register 223, a digital falling sensor 224 and a holding register 225. The delay circuit 221 is coupled to a digital rising sensor 222, a tracking register 223, and a digital falling sensor 224. The digital rising sensor 222 is coupled to the tracking register 223, and the tracking register 223 is coupled to the holding register 225. The digital drop sensor 224 is coupled to the holding register 225 . The structure and function of the delay circuit 221, the digital rising sensor 222, the tracking register 223, the digital falling sensor 224 and the holding register 225 will be explained in detail below, and the operation of each other will be described.

In some embodiments, the delay circuit 221 is used to delay the digital input signal D _VAC to generate a delayed input signal DD _VAC , wherein the delayed input signal DD _VAC is delayed by at least one clock cycle from the digital input signal D _VAC . As shown in Figure 4, in this embodiment, the delayed input signal DD _VAC is delayed by one clock cycle of the digital input signal D _VAC , so the delayed input signal DD _VAC has a value of DD _VAC [k] in a k-th clock cycle. It is equal to the value D _VAC [k-1] of the digital input signal D _VAC in the previous clock cycle, that is, the k-1th clock cycle. Among them, k is the clock cycle count value, and k-1 represents the previous clock cycle of the k-th clock cycle. Taking the first clock cycle (time point t1) and waveform W4 in Figure 4 as an example, the value D _VAC [1] of the digital input signal D _VAC in the first clock cycle (time point t1) is 1, and the digital The value D _VAC [0] of the input signal D VAC in the previous clock cycle, that is, the 0th clock cycle (time point t0) is 0, so the delayed input signal DD _VAC has a value of D _VAC in the first clock cycle (time point t1 ) value DD _VAC [1] is equal to 0. It should be noted that the delay of the delayed input signal DD _VAC from the digital input signal D _VAC is not limited to one clock cycle, but can also be two clock cycles, three clock cycles, or a plurality of other clock cycles.

In some embodiments, the digital rising sensor 222 is used to compare the digital input signal D _VAC and the delayed input signal DD _VAC to generate a rising signal D _VAC _rising, wherein when the digital input signal D _VAC rises in the k-th clock cycle When the value D _VAC [k] is greater than the value DD _VAC [k] of the delayed input signal DD _VAC in the k-th clock cycle, the rising signal D _VAC _rising is converted to the consistent enable state (enable). Taking time point t1 in Figure 4 as an example, the value D _VAC [1] of the digital input signal in the first clock cycle (time point t1) is 1 and the delayed input signal DD _VAC in the first clock cycle (time point The value DD _VAC [1] of t1) is 0. At this time, the value D _VAC [1] of the digital input signal in the k-th clock cycle is greater than the value DD _VAC [1] of the delayed input signal DD _VAC in the k-th clock cycle. ], so that the rising signal D _VAC _rising is converted to the enable state, where the enable state is a high potential.

In some embodiments, the tracking register 223 is used to latch the value of the digital input signal D _VAC to generate _a tracking signal D _VAC _tracking (corresponding to in waveform W5). As shown in the waveforms W4 and W5 of Figure 4, when the rising signal D _{VAC_rising} is in the enabled state, the tracking register 223 latches the value of the digital input signal D _VAC to generate the tracking signal D _{VAC_tracking} . Therefore, In period T1, waveform W4 coincides with waveform W5. In some embodiments, when the tracking register 223 receives a reset signal, the tracking register 223 sets the tracking signal D _{VAC_tracking} to a reset value, where the initial value of the tracking signal D _{VAC_tracking} is the reset value. In other words, the tracking register 223 has a reset function, so that the tracking register 223 can set the tracking signal D _{VAC_tracking} to the reset value. In some embodiments, the reset value is the disabled state (ie, low potential).

In some embodiments, the digital falling sensor 224 is used to compare the digital input signal D _VAC and the delayed input signal DD _VAC to generate a falling signal D _VAC _falling, where when the digital input signal D _VAC falls at the kth clock cycle (For example, the value D _VAC [k] at time point t3) is less than the value DD _VAC [k] of the delayed input signal DD _VAC at the k-th clock cycle (time point t3), the falling signal D _VAC _falling is converted to Enabled state. Take time point t3 in Figure 4 as an example. Time point t3 is the time point when the digital input signal D _VAC falls for the first time after rising. At this time, the value D _VAC [k] of the digital input signal D _VAC at time point t3 is 5 and delayed. The value DD _VAC [k] of the input signal DD _VAC at time point t3 is 6. Since the value D _VAC [k] of the digital input signal at time _point t3 is smaller than the value DD VAC [k] of the delayed input signal DD _VAC at time point t3, the falling signal D _{VAC_falling} is converted to the enabled state.

In some embodiments, the holding register 225 is used to latch the value of the tracking signal D _VAC _tracking to generate the peak signal D _{VAC _peak (corresponding to the waveform) at the time when the falling signal D VAC _falling} transitions to the enabled state. W6). As shown in waveforms W5 and W6 in Figure 4, when the falling signal D _{VAC_falling} transitions to the enabled state (for example, time point t3, time point t4, and time point t5), the holding register 225 will be latched. Lock the value of the tracking signal D _VAC _tracking to generate the peak signal D _VAC _peak. Taking time point t3 as an example, when the falling signal D _VAC _falling transitions to the enabled state at time point t3, the holding register 225 will generate a peak signal D _VAC _peak, where the value of the peak signal D _VAC _peak is equal to the tracking signal. D _VAC _tracking is the value at time point t3. Therefore, during the period T2, the value of the peak signal D _VAC _peak is latched and maintained at the value of the tracking signal D _VAC _tracking at time point t3. Taking time point t4 as an example, when When the falling signal D _VAC _falling transitions to the enabled state at time point t4, the holding register 225 will generate a peak signal D _VAC _peak, where the value of the peak signal D _VAC _peak is equal to the value of the tracking signal D _VAC _tracking at time point t4. value, therefore in the period T3, the value of the peak signal D _VAC _peak is latched and maintained at the value of the tracking signal D _VAC _tracking at time point t4.

In some embodiments, when the holding register 225 receives another reset signal, the holding register 225 sets the peak signal D _VAC _peak to another reset value, where the initial value of the peak signal D _VAC _peak is is the other reset value. In other words, the holding register 225 has a reset function, so that the holding register 225 can set the peak signal D _{VAC_peak} to the other reset value. In some embodiments, the other reset value is the disabled state (ie, low potential).

Please refer to FIG. 5B , which is a module block diagram of the digital peak hold circuit 220 in another embodiment of the present invention. As shown in FIG. 5B , in some embodiments, the digital peak hold circuit 220 further includes a hold signal generator 226 , wherein the hold signal generator 226 is coupled between the digital drop sensor 224 and the hold register 225 . The holding signal generator 226 is used to generate a holding signal D _VAC _holding, and is used to trigger a pulse of the holding signal D _VAC _holding when the falling signal D _VAC _falling transitions to the enabled state, wherein the holding signal is temporarily held. The register 225 latches the value of the tracking signal D _VAC _tracking at the triggering point of the pulse to generate the value of the peak signal D _VAC _peak.

Please refer to FIGS. 6A and 6B simultaneously. FIG. 6A is a circuit schematic diagram of the digital peak hold circuit 220 in one embodiment of the present invention. FIG. 6B is a circuit schematic diagram of the digital peak hold circuit 220 in another embodiment of the present invention. As shown in FIG. 6A, in some embodiments, the delay circuit 221 is a register Reg, and the digital rise sensor 222 is composed of a comparator COM and a D-type flip-flop D-FF. The register 223 is a register Reg, the digital drop sensor 224 is composed of a comparator COM and a D-type flip-flop D-FF, and the holding register 225 is a register Reg. As shown in FIG. 6B , in some embodiments, the hold signal generator 226 is composed of a D-type flip-flop D-FF and an AND gate AND.

Please refer to FIG. 7A and FIG. 7B simultaneously. FIG. 7A and FIG. 7B are module block diagrams of the digital peak hold circuit 220 in another second embodiment of the present invention. As shown in FIG. 7A and FIG. 7B , in some embodiments, the digital peak hold circuit 220 further includes a digital filter 227 , wherein the digital filter 227 is coupled to the delay circuit 221 , the digital rise sensor 222 , and the tracking register. 223 and digital drop sensor 224. The digital filter 227 is used to mask or filter the noise in the digital input signal D _VAC , so that the value of the digital input signal D _VAC is within 1/2 cycle or 1/4 cycle of the digital input signal D _VAC . Monotonically increase (monotonically increase) or monotonically decrease (monotonically decrease), thereby preventing the digital input signal D _VAC from producing a large error value.

In some embodiments, the reference voltage generator 230 is used to generate a reference voltage Vref according to the peak signal D _VAC _peak, where the reference voltage Vref is a certain value. Generally speaking, the reference voltage Vref has excellent stability, making it less susceptible to changes in value caused by noise. Under ideal circumstances, after the reference voltage Vref is generated, it is maintained at a fixed value, and the value of the reference voltage Vref will not be changed by any noise or load.

In some embodiments, there is a linear or piecewise linear mapping relationship between the reference voltage Vref and the peak signal D _{VAC_peak} . Please refer to FIG. 8A. FIG. 8A is a schematic diagram of the mapping relationship between the reference voltage Vref and the peak signal D _VAC _peak in one embodiment of the present invention. The horizontal axis of FIG. 8A represents the value of the peak signal D _VAC _peak in units. is volts (V); the vertical axis of Figure 8A represents the value of the reference voltage Vref, and the unit is volts. As shown in FIG. 8A , there are three segments S1-S3. In other words, in this embodiment, the mapping relationship between the reference voltage Vref and the peak signal D _VAC _peak is a piecewise linear mapping relationship. In segment S1, when the value of the peak signal D _{VAC_peak} is between 120 volts and 170 volts, the reference voltage generator 230 maps the value of the reference voltage Vref to 210 volts, where 210 volts is the reference voltage in this embodiment. The minimum value of voltage Vref. In segment S2, when the value of the peak signal D _{VAC_peak} is between 170 volts and 359 volts, the reference voltage generator 230 linearly maps the value of the reference voltage Vref to between 210 volts and 400 volts. In segment S3, when the value of the peak signal D _{VAC_peak} is between 359 volts and 375 volts, the reference voltage generator 230 maps the value of the reference voltage Vref to 400 volts, where 400 volts is the reference voltage in this embodiment. The maximum value of voltage Vref.

Please refer to FIG. 8B , which is a schematic diagram of the reference voltage generator 230 in an embodiment of the present invention. As shown in FIG. 8B , in some embodiments, the reference voltage generator 230 includes a lookup table 231 and a digital-to-analog converter 232 , where the lookup table 231 is coupled to the digital-to-analog converter 232 . The lookup table 231 is used to map the peak signal D _VAC _peak according to the mapping relationship to generate a mapped output signal D _Vo , and the digital-to-analog converter 232 is used to convert the mapped output signal D _Vo into a reference voltage Vref, where the mapped output The signal D _Vo is a digital signal, and the reference voltage Vref is an analog signal. In some embodiments, the lookup table 231 is a circuit composed of a read only memory (ROM), a random access memory (RAM), a flash memory (Flash), and combinations thereof. The structure and function of the digital-to-analog converter 232 are well known to those with ordinary knowledge in the technical field to which the present invention belongs, and therefore will not be described in detail.

In some embodiments, the error amplifier 240 is used to generate an error amplification signal VEOA based on the difference between the feedback signal VFB and the reference voltage Vref, where the error amplifier 240 has a gain such that the error amplification signal VEOA The value is the gain multiple of the difference between the feedback signal VFB and the reference voltage Vref. For example, assuming that the gain of the error amplifier 240 is 100, it means that the value of the error amplification signal VEOA is 100 times the difference between the feedback signal VFB and the reference voltage Vref. In some embodiments, the error amplifier 240 has a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the non-inverting input terminal is used to receive the reference voltage Vref, and the inverting input terminal is used to receive the feedback voltage Vref. The signal VFB is supplied, and the output terminal is used to output the error amplification signal VEOA. The structure and function of the error amplifier 240 are well known to those with ordinary knowledge in the technical field to which this invention belongs, and therefore will not be described in detail.

In some embodiments, the pulse width modulation circuit 250 is used to perform pulse-width modulation on the error amplification signal VEOA to generate a driving signal DRV. Pulse width modulation is a technology that converts an analog signal into a pulse signal. When the value of the analog signal is greater than the value of a triangle wave or a sawtooth wave, the pulse width modulation circuit 250 A driving signal DRV in a high potential state (for example, 1) will be output; when the value of the analog signal is smaller than the value of the triangle wave or the value of the sawtooth wave, the pulse width modulation circuit 250 will output a low potential. state (for example, 0) of the driving signal DRV. Pulse width modulation technology is well known to those with ordinary knowledge in the technical field to which this invention belongs, and therefore will not be described in detail.

In some embodiments, the power stage circuit 300 is used to convert the rectified voltage Vi into an output voltage Vo through a switched inductor conversion method, where the operation of the power stage circuit 300 is controlled by the driving signal DRV. . Since there is a linear or piecewise linear mapping relationship between the reference voltage Vref and the peak signal D _VAC _peak, the output voltage Vo corresponding to the reference voltage Vref and the rectified voltage Vi (or AC voltage Vac) corresponding to the peak signal D _VAC _peak There is also a corresponding linear or piecewise linear mapping relationship. In the application of the present invention, the output voltage Vo is higher than the rectified voltage Vi.

In some embodiments, the power stage circuit 300 includes at least one inductor, a plurality of switches, and at least one capacitor, wherein the plurality of switches may be a diode, a bipolar transistor (BJT), or a metal oxide semi-transistor. (MOSFET). Please refer to FIG. 9 , which is a schematic circuit diagram of a power stage circuit 300 in an embodiment of the present invention. As shown in FIG. 9 , the power stage circuit 300 is, for example, a boost power stage circuit, and includes, for example, an inductor L1 , a diode D1 , a transistor Q1 and a capacitor C1 , wherein the diode D1 And transistor Q1 is used as a switch. When the driving signal DRV is in a high potential state, the transistor Q1 is controlled to be in a conductive state and the diode D1 is in a non-conductive state. At this time, the rectified voltage Vi received by the power stage circuit 300 has an impact on the inductor. L1 is charged; when the driving signal DRV is in a low potential state, the transistor Q1 is controlled to be in the non-conducting state and the diode D1 is in the conductive state. At this time, the rectified voltage Vi received by the power stage circuit 300 will When the capacitor C1 is charged, the inductor L1 will also discharge and charge the capacitor C1 to generate the output voltage Vo, so that the output voltage Vo is higher than the rectified voltage Vi.

In some embodiments, the feedback circuit 400 is used to generate the feedback signal VFB according to the output voltage Vo, where there is a proportional relationship between the output voltage Vo and the feedback signal VFB. In some embodiments, the feedback circuit 400 includes a voltage dividing circuit formed by a plurality of resistors, wherein the value of each resistor affects the value of the proportional relationship. Please refer to FIG. 10 , which is a schematic circuit diagram of the feedback circuit 400 in one embodiment of the present invention. As shown in FIG. 10 , in this embodiment, the feedback circuit 400 includes two resistors R1 and R2. The value of the resistor R1 and the value of the resistor R2 determine the relationship between the output voltage Vo and the feedback signal VFB. Proportional relationship. For example, when the value of resistor R1 is 4 kiloohms (kΩ) and the value of resistor R2 is 1 kiloohm, the ratio between the output voltage Vo and the feedback signal VFB is 5 to 1, that is to say The value of the output voltage Vo is 5 times the value of the feedback signal VFB.

Please refer to FIGS. 11A to 11C at the same time. FIGS. 11A to 11C are flowcharts of a control method of the power factor correction converter 20 in an embodiment of the present invention. As shown in FIG. 11A , when the power factor correction converter 20 starts to operate, the rectifier 100 of the power factor correction converter 20 rectifies an AC voltage Vac to generate a rectified voltage Vi and a rectified signal VAC, where the rectified signal VAC is related to to the rectified voltage Vi (step S100). Next, the power factor correction controller 200 of the power factor correction converter 20 generates a driving signal DRV according to the rectified signal VAC and a feedback signal VFB (step S200). Subsequently, the power stage circuit 300 of the power factor correction converter 20 converts the rectified voltage Vi into an output voltage Vo through a switching inductive conversion method according to the driving signal DRV, where the driving signal DRV is used to control the power stage circuit 300 One switch to switch to achieve The switching inductive conversion method (step S300). Finally, the feedback circuit 400 of the power factor correction converter 20 generates the feedback signal VFB according to the output voltage Vo (step S400), so that the power factor correction converter 20 repeats steps S200 to step S400.

As shown in FIG. 11B , FIG. 11B is a detailed process of the power factor correction controller 200 generating the drive signal DRV according to the rectified signal VAC and the feedback signal VFB (ie, the detailed process of step S200 ). When the power factor correction controller 200 receives the rectified signal VAC and the feedback signal VFB, the analog-to-digital converter 210 of the power factor correction controller 200 converts the rectified signal VAC into a digital input signal D _VAC (step S210). Then, the digital peak hold circuit 220 of the power factor correction controller 200 generates a peak signal D _{VAC_peak} according to the digital input signal D _VAC (step S220). Subsequently, the reference voltage generator 230 of the power factor correction controller 200 will generate a reference voltage Vref according to the peak signal D _{VAC_peak} (step S230). At this time, the error amplifier 240 of the power factor correction controller 200 will generate a reference voltage Vref according to the feedback signal. The difference between VFB and the reference voltage Vref generates an error amplification signal VEOA (step S240). Finally, the pulse width modulation circuit 250 of the power factor correction controller 200 performs pulse width modulation on the error amplification signal VEOA to generate the driving signal DRV (step S250).

As shown in FIG. 11C , FIG. 11C is a detailed process of the digital peak hold circuit 220 generating the peak signal D _{VAC_peak} according to the digital input signal D _VAC (ie, the detailed process of step S220 ). When the digital peak hold circuit 220 receives the digital input signal D _VAC , the delay circuit 221 of the digital peak hold circuit 220 delays the digital input signal D _VAC to generate a delayed input signal DD _VAC (step S221). Then, the digital rising sensor 222 of the digital peak hold circuit 220 compares the digital input signal D _VAC with the delayed input signal DD _VAC to generate a rising signal D _VAC _rising (step S222), and when the rising signal D _VAC _rising transitions to consistent When in the enabled state, the tracking register 223 of the digital peak hold circuit 220 will latch the value of the digital input signal D _VAC to generate a tracking signal D _{VAC_tracking} (step S223); at the same time, the digital drop sensing of the digital peak hold circuit 220 The device 224 compares the digital input signal D _VAC with the delayed input signal DD _VAC to generate a falling signal D _{VAC_falling} (step S224). Finally, when the falling signal D _{VAC_falling} transitions to the enabled state, the holding register 225 of the digital peak holding circuit 220 will latch the value of the tracking signal D _{VAC_tracking} to generate the peak signal D _{VAC_peak} (step S225).

Please refer to FIG. 12. FIG. 12 is a waveform comparison diagram between the rectified voltage Vi and the output voltage Vo in the power factor correction converter 20 in one embodiment of the present invention. The waveform W7 is the waveform of the output voltage Vo, and the waveform W8 is The waveform of the rectified voltage Vi. As shown in FIG. 12 , since the value of the output voltage Vo output by the power factor correction converter 20 follows the peak value of the rectified voltage Vi (that is, the waveform W7 follows the peak value of the waveform W8 ), the output voltage Vo and the rectified voltage Vi are The voltage difference between them is not large, which allows the power factor correction converter 20 of this embodiment to use smaller energy storage components and switches, thereby reducing the circuit size, cost and operation efficiency of the power factor correction converter 20 . Overall power consumption.

In summary, compared with the prior art of FIG. 1A and FIG. 1B , since the power factor correction controller 200 of the present invention is provided with a digital peak hold circuit 220 , the reference voltage Vref of the present invention is limited to a range. , so that the value of the output voltage Vo output by the power factor correction converter 20 follows the peak value of the rectified voltage Vi to reduce the voltage difference between them. Therefore, compared with the prior art, the power factor correction converter 20 of the present invention has the advantages of smaller circuit size, cost and overall power consumption during operation. In addition, since the feedback circuit 400 is provided in the power factor correction converter 20 of the present invention, the power factor correction converter 20 of the present invention has the advantage that the output voltage Vo is relatively stable.

The present invention has been described above with reference to the preferred embodiments. The above description is only to make it easy for those familiar with the art to understand the contents of the present invention, and is not intended to limit the rights of the present invention. profit range. The various embodiments described are not limited to single application, but can also be used in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace those in another embodiment. Corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or computing according to a certain signal or generating a certain output result", which is not limited to Depending on the signal itself, it also includes performing voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion on the signal when necessary, and then processing or calculating the converted signal to produce an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. There are many combinations, and they are not listed here. Accordingly, the scope of the present invention is intended to cover the above and all other equivalent changes.

200:Power factor correction controller

210:Analog-to-digital converter

220: Digital peak hold circuit

230: Reference voltage generator

240: Error amplifier

250: Pulse width modulation circuit

DRV: drive signal

D _VAC : digital input signal

D _VAC _peak: peak signal

Vref: reference voltage

VAC: rectified signal

VEOA: error amplification signal

VFB: feedback signal

Claims (19)

A digital peak hold circuit for generating a peak signal according to a digital input signal, including: a delay circuit for delaying the digital input signal to generate a delayed input signal, wherein the delayed input signal is delayed from the digital input signal At least one clock cycle; a digital rising sensor for comparing the digital input signal and the delayed input signal to generate a rising signal, wherein when the digital input signal is greater than the delayed input signal, the digital rising sensor It is to control the rising signal to convert to an enabled state; a tracking register used to latch the value of the digital input signal to generate a tracking signal when the rising signal is in the enabled state; a digital falling sensor , used to compare the digital input signal and the delayed input signal to generate a falling signal, wherein when the digital input signal is smaller than the delayed input signal, the digital falling sensor controls the falling signal to transition to the enabled state; and a holding register for latching the value of the tracking signal to generate the peak signal at the time when the falling signal transitions to the enabled state. The digital peak hold circuit of claim 1, wherein when the tracking register receives a reset signal, the tracking register sets the tracking signal to a reset value, wherein the initial value of the tracking signal is the reset value; and/or when the holding register receives another reset signal, the holding register sets the peak signal to another reset value, where the initial value of the peak signal is Another reset value. The digital peak hold circuit of claim 1 further includes a hold signal generator for generating a hold signal, and the hold signal generator is used for converting the falling signal into A pulse of the holding signal is triggered when the enable state is triggered, and the holding register latches the value of the tracking signal at the triggering time of the pulse to generate the peak signal. The digital peak hold circuit as described in claim 1 further includes a digital filter, the digital filter is used to shield or filter the noise of the digital input signal, so that the value of the digital input signal is 1/1 of the digital input signal. Monotonically increasing or decreasing within 2 cycles or 1/4 cycles. The digital peak hold circuit according to any one of claims 1 to 4 is suitable for a power factor correction converter, wherein the power factor correction converter includes: a rectifier for rectifying an AC voltage to generate a rectifier voltage; a power stage circuit including at least one switch and an inductor for converting the rectified voltage into an output voltage through a switched inductor conversion method; a feedback circuit for converting the rectified voltage into an output voltage according to the output voltage; voltage to generate a feedback signal; an analog-to-digital converter for converting a rectified signal into a digital input signal, where the rectified signal is related to the rectified voltage; a reference voltage generator for generating a signal based on the peak signal Generate a reference voltage; an error amplifier used to generate an error amplification signal based on the difference between the feedback signal and the reference voltage; and a pulse width modulation circuit used to pulse the error amplification signal The width modulation generates a driving signal, wherein the driving signal is used to control the switching of the at least one switch. The digital peak hold circuit of claim 5, wherein the rectified signal has a full-wave rectification form or a half-wave rectification form. The digital peak hold circuit as described in claim 5, wherein the reference voltage and the peak signal have a linear or piecewise linear mapping relationship, such that the output voltage and the peak signal The value of the rectified voltage corresponding to the value signal has another corresponding linear or piecewise linear mapping relationship, in which the output voltage is always greater than the value of the rectified voltage corresponding to the peak signal. The digital peak hold circuit of claim 7, wherein the reference voltage generator includes: a lookup table for mapping the peak signal according to the mapping relationship to generate a mapping output signal; and a digital-to-analog converter for The mapping output signal is converted into the reference voltage, wherein the mapping output signal is a digital signal, and the reference voltage is an analog signal. The digital peak hold circuit of claim 8, wherein the lookup table includes a read only memory (ROM), a random access memory (RAM), a flash memory (Flash) and combinations thereof. A power factor correction controller, suitable for a power factor correction converter, used to generate a driving signal based on a rectified signal and a feedback signal, including: an analog-to-digital converter used to convert the rectified signal into a Digital input signal; a digital peak hold circuit for generating a peak signal according to the digital input signal, the digital peak hold circuit includes: a delay circuit for delaying the digital input signal to generate a delayed input signal, wherein the The delayed input signal is delayed by at least one clock cycle from the digital input signal; a digital rising sensor is used to compare the digital input signal and the delayed input signal to generate a rising signal, wherein when the digital input signal is greater than the delayed input When the signal is generated, the digital rising sensor controls the rising signal to transition to an enabled state; a tracking register is used to latch the value of the digital input signal at the time when the rising signal transitions to the enabled state. generate a tracking signal; A digital drop sensor for comparing the digital input signal and the delayed input signal to generate a drop signal, wherein when the digital input signal is smaller than the delayed input signal, the digital drop sensor controls the conversion of the drop signal is the enable state; and a holding register is used to latch the value of the tracking signal to generate the peak signal at the time when the falling signal transitions to the enable state; a reference voltage generator is used to generate the peak signal according to The peak signal generates a reference voltage; an error amplifier is used to generate an error amplification signal based on the difference between the feedback signal and the reference voltage; and a pulse width modulation circuit is used to calculate the error The amplified signal undergoes pulse width modulation to generate the driving signal, wherein the driving signal is used to control the switching of at least one switch. The power factor correction controller of claim 10, wherein the rectified signal has a full-wave rectification form or a half-wave rectification form. The power factor correction controller of claim 10, wherein there is a linear or piecewise linear mapping relationship between the reference voltage and the peak signal, such that the output voltage corresponds to the value of the rectified voltage corresponding to the peak signal. There is another corresponding linear or piecewise linear mapping relationship, in which the output voltage is always greater than the value of the rectified voltage corresponding to the peak signal. The power factor correction controller of claim 12, wherein the reference voltage generator includes: a lookup table for mapping the peak signal according to the mapping relationship to generate a mapping output signal; and a digital-to-analog converter, It is used to convert the mapping output signal into the reference voltage, wherein the mapping output signal is a digital signal and the reference voltage is an analog signal. The power factor correction controller of claim 13, wherein the lookup table includes a read only memory (ROM), a random access memory (RAM), a flash memory (Flash) and combinations thereof. A power factor correction converter used to convert an AC voltage into an output voltage, including: a rectifier used to rectify the AC voltage to generate a rectified voltage; a power factor correction controller used to generate a rectified voltage according to the rectified signal and a feedback signal to generate a driving signal, wherein the rectified signal is related to the rectified voltage. The power factor correction controller includes: an analog-to-digital converter for converting the rectified signal into a digital input signal; a digital A peak hold circuit is used to generate a peak signal according to the digital input signal. The digital peak hold circuit includes: a delay circuit for delaying the digital input signal to generate a delayed input signal, wherein the delayed input signal is delayed by the The digital input signal is at least one clock cycle; a digital rising sensor is used to compare the digital input signal and the delayed input signal to generate a rising signal, wherein when the digital input signal is greater than the delayed input signal, the digital rises The sensor controls the rising signal to convert to an enabled state; a tracking register is used to latch the value of the digital input signal to generate a tracking signal when the rising signal is in the enabled state; a digital falling signal A sensor is used to compare the digital input signal and the delayed input signal to generate a falling signal, wherein when the digital input signal is smaller than the delayed input signal, the digital falling sensor controls the falling signal to convert to a corresponding energy status; and a holding register for latching the value of the tracking signal to generate the peak signal when the falling signal transitions to the enabled state; a reference voltage generator for generating a reference based on the peak signal voltage; an error amplifier for generating an error amplification signal based on the difference between the feedback signal and the reference voltage; and a pulse width modulation circuit for pulse width modulation of the error amplification signal A driving signal is generated, wherein the driving signal is used to control the switching of at least one switch; a power stage circuit, including the at least one switch and an inductor, is used to convert the rectified voltage to the an output voltage; and a feedback circuit for generating the feedback signal according to the output voltage. The power factor correction converter of claim 15, wherein the rectified signal has a full-wave rectification form or a half-wave rectification form. The power factor correction converter of claim 15, wherein there is a linear or piecewise linear mapping relationship between the reference voltage and the peak signal, such that the output voltage corresponds to the value of the rectified voltage corresponding to the peak signal. There is another corresponding linear or piecewise linear mapping relationship, in which the output voltage is always greater than the value of the rectified voltage corresponding to the peak signal. The power factor correction converter of claim 17, wherein the reference voltage generator includes: a lookup table for mapping the peak signal according to the mapping relationship to generate a mapping output signal; and a digital-to-analog converter, It is used to convert the mapping output signal into the reference voltage, wherein the mapping output signal is a digital signal and the reference voltage is an analog signal. The power factor correction converter of claim 18, wherein the lookup table includes a read only memory (ROM), a random access memory (RAM), a flash memory (Flash) and combinations thereof.