TWI816920B - Manufacturing method of solar cell, solar cell, and solar cell module - Google Patents
Manufacturing method of solar cell, solar cell, and solar cell module Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H—ELECTRICITY
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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Abstract
本發明提供一種能夠簡化透明電極層之形成之太陽電池之製造方法。太陽電池之製造方法依序包含以下步驟：於基板11之背面側形成導電型半導體層25、35；於導電型半導體層25、35上形成透明導電膜；介隔透明導電膜於導電型半導體層25、35上分別形成金屬電極層29、39；及將透明導電膜圖案化，形成相互分離之透明電極層28、38。於金屬電極層形成步驟中，印刷包含金屬材料、樹脂材料及溶劑之印刷材料且使其硬化，形成金屬電極層29、39，於金屬電極層29、39之周緣形成偏集存在有樹脂材料之樹脂膜40，於透明電極層形成步驟中，將金屬電極層29及其周緣之樹脂膜40、及金屬電極層39及其周緣之樹脂膜40作為遮罩，將透明導電膜圖案化。The present invention provides a method for manufacturing a solar cell that can simplify the formation of a transparent electrode layer. The manufacturing method of a solar cell sequentially includes the following steps: forming conductive semiconductor layers 25 and 35 on the back side of the substrate 11; forming a transparent conductive film on the conductive semiconductor layers 25 and 35; interposing the transparent conductive film on the conductive semiconductor layer Metal electrode layers 29 and 39 are respectively formed on 25 and 35; and the transparent conductive film is patterned to form mutually separated transparent electrode layers 28 and 38. In the step of forming the metal electrode layer, a printing material containing a metal material, a resin material and a solvent is printed and hardened to form the metal electrode layers 29 and 39. The resin material is segregated around the edges of the metal electrode layers 29 and 39. For the resin film 40, in the step of forming the transparent electrode layer, the metal electrode layer 29 and the resin film 40 on its periphery, and the metal electrode layer 39 and the resin film 40 on its periphery are used as masks to pattern the transparent conductive film.
Description
本發明係關於一種背面電極型(背接觸型)太陽電池之製造方法、背面電極型太陽電池、及具備該太陽電池之太陽電池模組。The present invention relates to a manufacturing method of a back electrode type (back contact type) solar cell, a back electrode type solar cell, and a solar cell module including the solar cell.
作為使用半導體基板之太陽電池，存在於受光面側及背面側之兩面形成有電極之雙面電極型太陽電池、及僅於背面側形成有電極之背面電極型太陽電池。雙面電極型太陽電池係於受光面側形成電極，故由該電極將太陽光遮蔽。另一方面，背面電極型太陽電池係於受光面側未形成電極，故與雙面電極型太陽電池相比，太陽光之受光率更高。專利文獻1中揭示有一種背面電極型太陽電池。As solar cells using a semiconductor substrate, there are double-sided electrode solar cells in which electrodes are formed on both the light-receiving surface side and the back side, and back electrode type solar cells in which electrodes are formed only on the back side. In a double-sided electrode type solar cell, an electrode is formed on the light-receiving surface side, so the electrode blocks sunlight. On the other hand, back electrode type solar cells do not have electrodes formed on the light-receiving surface side, so compared with double-sided electrode type solar cells, the light reception rate of sunlight is higher. Patent Document 1 discloses a back electrode type solar cell.
專利文獻1中記載之太陽電池具備：半導體基板、依序積層於半導體基板之背面側之第1導電型半導體層及第1電極層、以及依序積層於半導體基板之背面側之另一部分之第2導電型半導體層及第2電極層。第1電極層與第2電極層相互分離以防止短路。 [先前技術文獻] [專利文獻]The solar cell described in Patent Document 1 includes a semiconductor substrate, a first conductive semiconductor layer and a first electrode layer sequentially laminated on the back side of the semiconductor substrate, and a third conductive type semiconductor layer and a first electrode layer sequentially laminated on another part of the back side of the semiconductor substrate. 2 conductive semiconductor layers and second electrode layers. The first electrode layer and the second electrode layer are separated from each other to prevent short circuit. [Prior technical literature] [Patent Document]
[專利文獻1]日本專利特開2013-131586號公報[Patent Document 1] Japanese Patent Application Laid-Open No. 2013-131586
[發明所欲解決之問題][Problem to be solved by the invention]
一般而言，第1電極層及第2電極層各自包含透明電極層與金屬電極層。金屬電極層係例如藉由使用銀膠之網版印刷法便可相對容易地分離形成。另一方面，透明電極層必須藉由使用遮罩之例如光微影法而分離地形成，從而其形成步驟相對複雜。Generally speaking, each of the first electrode layer and the second electrode layer includes a transparent electrode layer and a metal electrode layer. The metal electrode layer can be relatively easily separated and formed, for example, by screen printing using silver glue. On the other hand, the transparent electrode layer must be formed separately by using a mask, such as photolithography, so that its formation steps are relatively complicated.
本發明之目的在於提供一種能夠簡化透明電極層之形成之太陽電池之製造方法、太陽電池、及太陽電池模組。 [解決問題之技術手段]An object of the present invention is to provide a solar cell manufacturing method, solar cell, and solar cell module that can simplify the formation of a transparent electrode layer. [Technical means to solve problems]
本發明之太陽電池之製造方法係背面電極型之太陽電池之製造方法，該背面電極型太陽電池具備：具有2個主面之半導體基板、配置於半導體基板之一主面側之第1導電型半導體層及第2導電型半導體層、與第1導電型半導體層對應之第1透明電極層及第1金屬電極層、以及與第2導電型半導體層對應之第2透明電極層及第2金屬電極層，該太陽電池之製造方法依序包含：半導體層形成步驟，其係於半導體基板之一主面側之一部分形成第1導電型半導體層，於半導體基板之一主面側之另一部分形成第2導電型半導體層；透明導電膜形成步驟，其係於第1導電型半導體層及第2導電型半導體層之上跨及該等地形成透明導電膜；金屬電極層形成步驟，其係介隔透明導電膜於第1導電型半導體層之上形成第1金屬電極層，並介隔透明導電膜於第2導電型半導體層之上形成第2金屬電極層；及透明電極層形成步驟，其係藉由將透明導電膜圖案化而形成相互分離之第1透明電極層及第2透明電極層；於金屬電極層形成步驟中，藉由印刷包含粒子狀之金屬材料、樹脂材料及溶劑之印刷材料且使其硬化，而形成第1金屬電極層及第2金屬電極層，且於第1金屬電極層之周緣及第2金屬電極層之周緣形成偏集存在有樹脂材料之樹脂膜，於透明電極層形成步驟中，將第1金屬電極層及其周緣之樹脂膜、以及第2金屬電極層及其周緣之樹脂膜用作遮罩，將透明導電膜圖案化。The method for manufacturing a solar cell of the present invention is a method for manufacturing a back electrode type solar cell. The back electrode type solar cell includes a semiconductor substrate having two main surfaces, and a first conductivity type disposed on one main surface side of the semiconductor substrate. Semiconductor layer and second conductive type semiconductor layer, first transparent electrode layer and first metal electrode layer corresponding to the first conductive type semiconductor layer, and second transparent electrode layer and second metal corresponding to the second conductive type semiconductor layer The electrode layer, the manufacturing method of the solar cell sequentially includes: a semiconductor layer forming step, which is to form a first conductive type semiconductor layer on a part of one main surface side of the semiconductor substrate, and to form a first conductive type semiconductor layer on the other part of one main surface side of the semiconductor substrate. a second conductive type semiconductor layer; a transparent conductive film forming step, which is to form a transparent conductive film on the first conductive type semiconductor layer and the second conductive type semiconductor layer and across these areas; a metal electrode layer forming step, which is forming a first metal electrode layer on the first conductive type semiconductor layer through a transparent conductive film, and forming a second metal electrode layer on the second conductive type semiconductor layer through a transparent conductive film; and a transparent electrode layer forming step, which The first transparent electrode layer and the second transparent electrode layer that are separated from each other are formed by patterning the transparent conductive film; in the step of forming the metal electrode layer, printing includes particulate metal materials, resin materials and solvents. The material is then hardened to form a first metal electrode layer and a second metal electrode layer, and a resin film in which the resin material is dispersed is formed on the periphery of the first metal electrode layer and the periphery of the second metal electrode layer. In the electrode layer forming step, the first metal electrode layer and the resin film around its periphery, and the second metal electrode layer and the resin film around its periphery are used as masks to pattern the transparent conductive film.
本發明之太陽電池係背面電極型太陽電池，其具備：具有2個主面之半導體基板、配置於半導體基板之一主面側之第1導電型半導體層及第2導電型半導體層、與第1導電型半導體層對應之第1透明電極層及第1金屬電極層、以及與第2導電型半導體層對應之第2透明電極層及第2金屬電極層，第1透明電極層及第1金屬電極層呈現帶狀，且第1透明電極層之帶寬窄於第1金屬電極層之帶寬，第2透明電極層及第2金屬電極層呈現帶狀，且第2透明電極層之帶寬窄於第2金屬電極層之帶寬，於第1金屬電極層之周緣及第2金屬電極層之周緣，形成偏集存在有第1金屬電極層及第2金屬電極層之印刷材料中之樹脂材料之樹脂膜。The solar cell of the present invention is a back electrode solar cell, which includes a semiconductor substrate having two main surfaces, a first conductive semiconductor layer and a second conductive semiconductor layer arranged on one of the main surfaces of the semiconductor substrate, and a second conductive semiconductor layer. The first transparent electrode layer and the first metal electrode layer corresponding to the 1 conductive type semiconductor layer, the second transparent electrode layer and the second metal electrode layer corresponding to the second conductive type semiconductor layer, the first transparent electrode layer and the first metal The electrode layer is in a strip shape, and the bandwidth of the first transparent electrode layer is narrower than the bandwidth of the first metal electrode layer. The second transparent electrode layer and the second metal electrode layer are in a strip shape, and the bandwidth of the second transparent electrode layer is narrower than the bandwidth of the first metal electrode layer. 2. The bandwidth of the metal electrode layer forms a resin film that selectively collects the resin material in the printing material of the first metal electrode layer and the second metal electrode layer at the periphery of the first metal electrode layer and the periphery of the second metal electrode layer. .
本發明之太陽電池模組具備上述太陽電池。 [發明之效果]The solar cell module of the present invention includes the above-mentioned solar cell. [Effects of the invention]
根據本發明，能夠簡化太陽電池之透明電極層之形成。According to the present invention, the formation of the transparent electrode layer of the solar cell can be simplified.
以下，參照隨添圖式，對本發明之實施形態之一例進行說明。再者，各圖式中對於相同或相符之部分標註相同之符號。又，為方便起見，亦存在省略影線或構件符號等之情形，但該情形時，設為參照其他圖式。Hereinafter, an example of an embodiment of the present invention will be described with reference to the accompanying drawings. Furthermore, identical or corresponding parts in each drawing are marked with the same symbols. In addition, for the sake of convenience, hatching, component symbols, etc. may be omitted in some cases, but in this case, other drawings shall be referred to.
(太陽電池模組) 圖1係表示本實施形態之太陽電池模組之一例之側視圖。太陽電池模組100具備二維狀排列而成之複數個太陽電池單元1。(solar cell module) FIG. 1 is a side view showing an example of a solar cell module according to this embodiment. The solar cell module 100 includes a plurality of solar cell units 1 arranged two-dimensionally.
太陽電池單元1藉由配線構件2而串聯及/或並聯連接。具體而言，配線構件2連接於太陽電池單元1之電極層中之柵線部(下述)。配線構件2係例如接頭等公知之互連器。The solar battery cells 1 are connected in series and/or in parallel via the wiring member 2 . Specifically, the wiring member 2 is connected to a gate line portion (described below) in the electrode layer of the solar cell 1 . The wiring member 2 is a known interconnector such as a connector.
太陽電池單元1及配線構件2由受光面保護構件3與背面保護構件4夾住。於受光面保護構件3與背面保護構件4之間，填充有液體狀或固體狀之密封材5，藉此，將太陽電池單元1及配線構件2密封。受光面保護構件3係例如玻璃基板，背面保護構件4係玻璃基板或金屬板。密封材5係例如透明樹脂。 以下，對太陽電池單元(以下，稱為太陽電池)1詳細地進行說明。The solar cell 1 and the wiring member 2 are sandwiched between the light-receiving surface protection member 3 and the back surface protection member 4 . The liquid or solid sealing material 5 is filled between the light-receiving surface protection member 3 and the back surface protection member 4, whereby the solar cell unit 1 and the wiring member 2 are sealed. The light-receiving surface protection member 3 is, for example, a glass substrate, and the back surface protection member 4 is a glass substrate or a metal plate. The sealing material 5 is, for example, transparent resin. Hereinafter, the solar cell unit (hereinafter, referred to as a solar cell) 1 will be described in detail.
(太陽電池) 圖2係自背面側觀察本實施形態之太陽電池所得之圖。圖2所示之太陽電池1係背面電極型太陽電池。太陽電池1具備包含2個主面之半導體基板11，且於半導體基板11之主面具有第1導電型區域7與第2導電型區域8。(solar battery) FIG. 2 is a view of the solar cell of this embodiment viewed from the back side. Solar cell 1 shown in Figure 2 is a back electrode type solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and a first conductive type region 7 and a second conductive type region 8 on the main surface of the semiconductor substrate 11 .
第1導電型區域7呈所謂梳狀之形狀，具有相當於梳齒之複數個細柵線部7f、及相當於梳齒支持部之柵線部7b。柵線部7b沿半導體基板11之一邊部於第1方向(X方向)延伸，細柵線部7f自柵線部7b於與第1方向交叉之第2方向(Y方向)延伸。 同樣地，第2導電型區域8係所謂梳狀之形狀，具有相當於梳齒之複數個細柵線部8f、及相當於梳齒支持部之柵線部8b。柵線部8b沿半導體基板11之與一邊部對向之另一邊部於第1方向(X方向)延伸，細柵線部8f自柵線部8b於第2方向(Y方向)延伸。 細柵線部7f與細柵線部8f呈現於第2方向(Y方向)延伸之帶狀，且於第1方向(X方向)交替設置。 再者，第1導電型區域7及第2導電型區域8亦可形成為條紋狀。The first conductivity type region 7 has a so-called comb-like shape, and has a plurality of fine grid line portions 7f corresponding to comb teeth, and a grid line portion 7b equivalent to a comb tooth supporting portion. The gate line portion 7b extends in the first direction (X direction) along one edge of the semiconductor substrate 11, and the thin gate line portion 7f extends from the gate line portion 7b in the second direction (Y direction) intersecting the first direction. Similarly, the second conductive type region 8 has a so-called comb-like shape, and has a plurality of fine grid portions 8f corresponding to comb teeth, and a grid portion 8b equivalent to a comb tooth supporting portion. The gate line portion 8b extends in the first direction (X direction) along the other side portion of the semiconductor substrate 11 opposite to one side portion, and the thin gate line portion 8f extends in the second direction (Y direction) from the gate line portion 8b. The thin grating line portions 7f and the thin grating line portions 8f are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). Furthermore, the first conductivity type region 7 and the second conductivity type region 8 may be formed in a stripe shape.
圖3係圖2之太陽電池中之III-III線剖視圖。如圖3所示，太陽電池1具備於半導體基板11之主面中受光之側之主面即受光面側積層而成之鈍化層13。又，太陽電池1具備於半導體基板11之主面中之受光面之相反側之主面(一主面)即背面側之一部分(主要為第1導電型區域7)依序積層而成之鈍化層23、第1導電型半導體層25、及第1電極層27。又，太陽電池1具備依序積層於半導體基板11之背面側之另一部分(主要為第2導電型區域8)之鈍化層33、第2導電型半導體層35、及第2電極層37。FIG. 3 is a cross-sectional view of the solar cell in FIG. 2 taken along line III-III. As shown in FIG. 3 , the solar cell 1 includes a passivation layer 13 laminated on the light-receiving surface side of the main surface of the semiconductor substrate 11 . In addition, the solar cell 1 is provided with passivation formed by sequentially stacking a part of the back side (mainly the first conductive type region 7) of the main surface (one main surface) opposite to the light-receiving surface of the semiconductor substrate 11. layer 23, the first conductive type semiconductor layer 25, and the first electrode layer 27. Furthermore, the solar cell 1 includes a passivation layer 33 , a second conductivity type semiconductor layer 35 , and a second electrode layer 37 that are sequentially stacked on another part (mainly the second conductivity type region 8 ) of the back side of the semiconductor substrate 11 .
半導體基板11係由單晶矽或多晶矽等結晶矽材料形成。半導體基板11係例如於結晶矽材料中摻雜有n型摻雜劑之n型半導體基板。再者，半導體基板11亦可為例如於結晶矽材料中摻雜有p型摻雜劑之p型半導體基板。作為n型摻雜劑，例如可列舉磷(P)。作為p型摻雜劑，例如可列舉硼(B)。 半導體基板11係作為吸收來自受光面側之入射光產生光載子(電子及電洞)之光電轉換基板發揮功能。 藉由使用結晶矽作為半導體基板11之材料，即便暗電流相對較小，且入射光之強度較低之情形，亦可獲得相對高輸出(不依賴照度之穩定之輸出)。The semiconductor substrate 11 is made of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which crystalline silicon material is doped with an n-type dopant. Furthermore, the semiconductor substrate 11 may also be a p-type semiconductor substrate in which crystalline silicon material is doped with a p-type dopant. Examples of the n-type dopant include phosphorus (P). Examples of the p-type dopant include boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side and generates photocarriers (electrons and holes). By using crystalline silicon as the material of the semiconductor substrate 11, relatively high output (stable output independent of illumination) can be obtained even when the dark current is relatively small and the intensity of incident light is low.
半導體基板11亦可於背面側具有稱為紋理構造之稜錐形微細之凹凸構造。藉此，通過半導體基板11而未被吸收之光之回收效率提高。 又，半導體基板11亦可於受光面側具有稱為紋理構造之稜錐形微細之凹凸構造。藉此，於受光面入射光之反射降低，半導體基板11中之光封閉效果提昇。The semiconductor substrate 11 may have a pyramidal fine uneven structure called a texture structure on the back side. Thereby, the recovery efficiency of light that has passed through the semiconductor substrate 11 and has not been absorbed is improved. In addition, the semiconductor substrate 11 may have a pyramidal fine uneven structure called a texture structure on the light-receiving surface side. Thereby, the reflection of the incident light on the light-receiving surface is reduced, and the light confinement effect in the semiconductor substrate 11 is improved.
鈍化層13形成於半導體基板11之受光面側。鈍化層23形成於半導體基板11之背面側之第1導電型區域7。鈍化層33形成於半導體基板11之背面側之第2導電型區域8。鈍化層13、23、33例如由本徵(i型)非晶矽材料而形成。 鈍化層13、23、33抑制半導體基板11中產生之載子之再結合，提高載子之回收效率。The passivation layer 13 is formed on the light-receiving surface side of the semiconductor substrate 11 . The passivation layer 23 is formed in the first conductive type region 7 on the back side of the semiconductor substrate 11 . The passivation layer 33 is formed in the second conductive type region 8 on the back side of the semiconductor substrate 11 . The passivation layers 13, 23, and 33 are formed of, for example, intrinsic (i-type) amorphous silicon material. The passivation layers 13, 23, and 33 inhibit the recombination of carriers generated in the semiconductor substrate 11 and improve the carrier recovery efficiency.
於半導體基板11之受光面側之鈍化層13上，例如亦可設置由SiO、SiN、或SiON等材料形成之抗反射層。On the passivation layer 13 on the light-receiving surface side of the semiconductor substrate 11, an anti-reflection layer made of SiO, SiN, SiON or other materials may also be provided.
第1導電型半導體層25形成於鈍化層23上、即半導體基板11之背面側之第1導電型區域7。第1導電型半導體層25例如由非晶矽材料形成。第1導電型半導體層25係例如於非晶矽材料中摻雜有p型摻雜劑(例如，上述硼(B))之p型半導體層。The first conductive type semiconductor layer 25 is formed on the passivation layer 23 , that is, in the first conductive type region 7 on the back side of the semiconductor substrate 11 . The first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductive type semiconductor layer 25 is, for example, a p-type semiconductor layer made of an amorphous silicon material doped with a p-type dopant (for example, the above-mentioned boron (B)).
第2導電型半導體層35形成於鈍化層33上、即半導體基板11之背面側之第2導電型區域8。第2導電型半導體層35例如由非晶矽材料形成。第2導電型半導體層35係例如於非晶矽材料中摻雜有n型摻雜劑(例如，上述磷(P))之n型半導體層。 再者，第1導電型半導體層25係n型半導體層，第2導電型半導體層35係p型半導體層。The second conductive type semiconductor layer 35 is formed on the passivation layer 33 , that is, in the second conductive type region 8 on the back side of the semiconductor substrate 11 . The second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductive type semiconductor layer 35 is, for example, an n-type semiconductor layer made of an amorphous silicon material doped with an n-type dopant (for example, the above-mentioned phosphorus (P)). In addition, the first conductive type semiconductor layer 25 is an n-type semiconductor layer, and the second conductive type semiconductor layer 35 is a p-type semiconductor layer.
第1導電型半導體層25及鈍化層23、與第2導電型半導體層35及鈍化層33呈第2方向(Y方向)上延伸之帶狀，且交替排列於第1方向(X方向)。 第2導電型半導體層35及鈍化層33之一部分亦可重疊於相鄰之第1導電型半導體層25及鈍化層23之一部分之上(省略圖示)。The first conductive type semiconductor layer 25 and the passivation layer 23 and the second conductive type semiconductor layer 35 and the passivation layer 33 are in a strip shape extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). Parts of the second conductive type semiconductor layer 35 and the passivation layer 33 may also overlap on part of the adjacent first conductive type semiconductor layer 25 and the passivation layer 23 (not shown).
第1電極層27對應於第1導電型半導體層25，具體而言形成於半導體基板11之背面側之第1導電型區域7中之第1導電型半導體層25之上。第2電極層37對應於第2導電型半導體層35，具體而言形成於半導體基板11之背面側之第2導電型區域8中之第2導電型半導體層35之上。 第1電極層27具有依序積層於第1導電型半導體層25上之第1透明電極層28與第1金屬電極層29。第2電極層37具有依序積層於第2導電型半導體層35上之第2透明電極層38與第2金屬電極層39。The first electrode layer 27 corresponds to the first conductive type semiconductor layer 25 and is specifically formed on the first conductive type semiconductor layer 25 in the first conductive type region 7 on the back side of the semiconductor substrate 11 . The second electrode layer 37 corresponds to the second conductive type semiconductor layer 35 and is specifically formed on the second conductive type semiconductor layer 35 in the second conductive type region 8 on the back side of the semiconductor substrate 11 . The first electrode layer 27 includes a first transparent electrode layer 28 and a first metal electrode layer 29 which are sequentially laminated on the first conductive type semiconductor layer 25 . The second electrode layer 37 includes a second transparent electrode layer 38 and a second metal electrode layer 39 which are sequentially laminated on the second conductive type semiconductor layer 35 .
第1透明電極層28及第2透明電極層38係由透明之導電性材料形成。作為透明導電性材料，可列舉ITO(Indium Tin Oxide：氧化銦及氧化錫之複合氧化物)等。 第1金屬電極層29及第2金屬電極層39係由含有銀、銅、鋁等粒子狀之金屬材料、絕緣性樹脂材料及溶劑之導電性膠材料形成。The first transparent electrode layer 28 and the second transparent electrode layer 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide). The first metal electrode layer 29 and the second metal electrode layer 39 are formed of a conductive glue material containing particulate metal materials such as silver, copper, and aluminum, an insulating resin material, and a solvent.
第1電極層27及第2電極層37、即第1透明電極層28、第2透明電極層38、第1金屬電極層29及第2金屬電極層39呈第2方向(Y方向)上延伸之帶狀，且交替排列於第1方向(X方向)。 第1透明電極層28與第2透明電極層38相互分離，第1金屬電極層29與第2金屬電極層39亦相互分離。 第1透明電極層28之第1方向(X方向)之帶寬窄於第1金屬電極層29之第1方向(X方向)之帶寬，第2透明電極層38之第1方向(X方向)之帶寬窄於第2金屬電極層39之第1方向(X方向)之帶寬。The first electrode layer 27 and the second electrode layer 37, that is, the first transparent electrode layer 28, the second transparent electrode layer 38, the first metal electrode layer 29 and the second metal electrode layer 39 extend in the second direction (Y direction) strips, and are alternately arranged in the first direction (X direction). The first transparent electrode layer 28 and the second transparent electrode layer 38 are separated from each other, and the first metal electrode layer 29 and the second metal electrode layer 39 are also separated from each other. The bandwidth of the first transparent electrode layer 28 in the first direction (X direction) is narrower than the bandwidth of the first metal electrode layer 29 in the first direction (X direction), and the bandwidth of the second transparent electrode layer 38 in the first direction (X direction) The bandwidth is narrower than the bandwidth of the second metal electrode layer 39 in the first direction (X direction).
於第1金屬電極層29之周緣及第2金屬電極層39之周緣，形成偏集存在有第1金屬電極層29及第2金屬電極層39之導電性膠材料中之絕緣性樹脂材料之樹脂膜40(詳情以下敍述)。On the periphery of the first metal electrode layer 29 and the periphery of the second metal electrode layer 39, a resin of insulating resin material in the conductive adhesive material of the first metal electrode layer 29 and the second metal electrode layer 39 is formed. Membrane 40 (details described below).
第1金屬電極層29與第2金屬電極層39之間的第1導電型半導體層25之一部分及第2導電型半導體層35之一部分由樹脂膜40覆蓋。詳細而言，第1金屬電極層29與第2金屬電極層39之間的第1導電型半導體層25之凹凸構造(紋理構造)之谷部及第2導電型半導體層35之凹凸構造之谷部由樹脂膜40覆蓋。 另一方面，第1金屬電極層29與第2金屬電極層39之間的第1導電型半導體層25之凹凸構造之頂部及第2導電型半導體層35之凹凸構造之頂部未被樹脂膜40覆蓋而露出。A part of the first conductive type semiconductor layer 25 and a part of the second conductive type semiconductor layer 35 between the first metal electrode layer 29 and the second metal electrode layer 39 are covered with the resin film 40 . Specifically, the valleys of the uneven structure (texture structure) of the first conductive type semiconductor layer 25 and the valleys of the uneven structure of the second conductive type semiconductor layer 35 between the first metal electrode layer 29 and the second metal electrode layer 39 is covered with a resin film 40. On the other hand, the top of the uneven structure of the first conductive type semiconductor layer 25 and the top of the uneven structure of the second conductive type semiconductor layer 35 between the first metal electrode layer 29 and the second metal electrode layer 39 are not covered by the resin film 40 Covered and exposed.
於第1導電型半導體層25與樹脂膜40之層間及第2導電型半導體層35與樹脂膜40之層間，島狀(非連續)地配置有與第1透明電極層28及第2透明電極層38為相同材料之透明導電膜48。詳細而言，第1導電型半導體層25之凹凸構造之谷部與樹脂膜40之層間及第2導電型半導體層35之凹凸構造之谷部與樹脂膜40之層間，島狀地配置有透明導電膜48。Between the first conductive semiconductor layer 25 and the resin film 40 and between the second conductive semiconductor layer 35 and the resin film 40, the first transparent electrode layer 28 and the second transparent electrode are arranged in an island shape (discontinuously). Layer 38 is a transparent conductive film 48 of the same material. In detail, transparent islands are arranged in an island shape between the valleys of the uneven structure of the first conductive type semiconductor layer 25 and the resin film 40 and between the valleys of the uneven structure of the second conductive type semiconductor layer 35 and the resin film 40 . Conductive film 48.
第1金屬電極層29與第1導電型半導體層25之接觸面積為第1透明電極層28與第1導電型半導體層25之接觸面積之一半以下，第2金屬電極層39與第2導電型半導體層35之接觸面積為第2透明電極層38與第2導電型半導體層35之接觸面積之一半以下。The contact area between the first metal electrode layer 29 and the first conductive type semiconductor layer 25 is less than half of the contact area between the first transparent electrode layer 28 and the first conductive type semiconductor layer 25. The contact area of the semiconductor layer 35 is less than half of the contact area between the second transparent electrode layer 38 and the second conductive semiconductor layer 35 .
其次，參照圖4A～圖4D，對本實施形態之太陽電池之製造方法進行說明。圖4A係表示本實施形態之太陽電池之製造方法中之半導體層形成步驟之圖，圖4B係表示本實施形態之太陽電池之製造方法中之透明導電層形成步驟之圖。圖4C係表示本實施形態之太陽電池之製造方法中之金屬電極層形成步驟之圖，圖4D係表示本實施形態之太陽電池之製造方法中之透明電極層形成步驟之圖。圖4A～圖4D中，示出了半導體基板11之背面側而省略了半導體基板11之正面側。Next, the manufacturing method of the solar cell according to this embodiment will be described with reference to FIGS. 4A to 4D . FIG. 4A is a diagram illustrating a semiconductor layer forming step in the solar cell manufacturing method of this embodiment, and FIG. 4B is a diagram illustrating a transparent conductive layer forming step in the solar cell manufacturing method of this embodiment. 4C is a diagram illustrating the steps of forming a metal electrode layer in the method of manufacturing a solar cell according to this embodiment, and FIG. 4D is a diagram illustrating the steps of forming a transparent electrode layer in the method of manufacturing a solar cell according to this embodiment. In FIGS. 4A to 4D , the back side of the semiconductor substrate 11 is shown and the front side of the semiconductor substrate 11 is omitted.
首先，如圖4A所示，於至少背面側具有凹凸構造(紋理構造)之半導體基板11之背面側之一部分，具體而言於第1導電型區域7，形成鈍化層23及第1導電型半導體層25(半導體層形成步驟)。 例如，使用CVD(chemical vapor deposition，化學氣相沈積)法或PVD(Physical Vapor Deposition，物理氣相沈積)法，於半導體基板11之整個背面側將鈍化膜及第1導電型半導體膜製膜之後，亦可使用利用採用光微影技術產生之遮罩或金屬遮罩之蝕刻法，將鈍化層23及第1導電型半導體層25圖案化。再者，作為對p型半導體膜之蝕刻溶液，例如可列舉含有臭氧之氫氟酸、或如硝酸與氫氟酸之混合液般之酸性溶液，作為對n型半導體膜之蝕刻溶液，例如可列舉如氫氧化鉀水溶液般之鹼性溶液。 或者，於使用CVD法或PVD法，於半導體基板11之背面側積層鈍化層及第1導電型半導體層時，亦可使用遮罩，同時進行鈍化層23及p型半導體層25之製膜及圖案化。First, as shown in FIG. 4A , a passivation layer 23 and a first conductive type semiconductor are formed on a part of the back side of the semiconductor substrate 11 having an uneven structure (texture structure) at least on the back side, specifically in the first conductive type region 7 Layer 25 (semiconductor layer forming step). For example, a passivation film and a first conductive type semiconductor film are formed on the entire back side of the semiconductor substrate 11 using a CVD (chemical vapor deposition) method or a PVD (Physical Vapor Deposition) method. , the passivation layer 23 and the first conductive type semiconductor layer 25 can also be patterned using an etching method using a mask or a metal mask produced by photolithography technology. Furthermore, examples of the etching solution for the p-type semiconductor film include hydrofluoric acid containing ozone or an acidic solution such as a mixture of nitric acid and hydrofluoric acid. Examples of the etching solution for the n-type semiconductor film include: Examples include alkaline solutions such as potassium hydroxide aqueous solution. Alternatively, when the CVD method or the PVD method is used to stack the passivation layer and the first conductive type semiconductor layer on the back side of the semiconductor substrate 11, a mask can also be used to simultaneously form the passivation layer 23 and the p-type semiconductor layer 25. Patterning.
繼而，於半導體基板11之背面側之另一部分，具體而言於第2導電型區域8，形成鈍化層33及第2導電型半導體層35(半導體層形成步驟)。 例如，與上述同樣地，使用CVD法或PVD法，於半導體基板11之整個背面側將鈍化膜及第2導電型半導體膜製膜之後，亦可使用利用採用光微影技術產生之遮罩或金屬遮罩之蝕刻法，將鈍化層33及第2導電型半導體層35圖案化。 或者，於使用CVD法或PVD法，於半導體基板11之背面側積層鈍化層及第2導電型半導體層時，亦可使用遮罩，同時進行鈍化層33及第2導電型半導體層35之製膜及圖案化。Then, the passivation layer 33 and the second conductive type semiconductor layer 35 are formed on the other part of the back side of the semiconductor substrate 11, specifically in the second conductive type region 8 (semiconductor layer forming step). For example, in the same manner as described above, after the passivation film and the second conductive type semiconductor film are formed on the entire back side of the semiconductor substrate 11 using the CVD method or the PVD method, a mask produced by photolithography technology or the like can also be used. The passivation layer 33 and the second conductive type semiconductor layer 35 are patterned by etching the metal mask. Alternatively, when the CVD method or the PVD method is used to stack the passivation layer and the second conductive type semiconductor layer on the back side of the semiconductor substrate 11, a mask can also be used to simultaneously form the passivation layer 33 and the second conductive type semiconductor layer 35. Membranes and patterning.
再者，於該半導體層形成步驟中，亦可於半導體基板11之受光面側之整面形成鈍化層13(省略圖示)。Furthermore, in the semiconductor layer forming step, the passivation layer 13 (not shown) may also be formed on the entire surface of the light-receiving surface side of the semiconductor substrate 11 .
繼而，如圖4B所示，於第1導電型半導體層25及第2導電型半導體層35上，跨及該等地形成透明導電膜28Z(透明導電膜形成步驟)。作為透明導電膜28Z之形成方法，例如可使用CVD法或PVD法等。Next, as shown in FIG. 4B , a transparent conductive film 28Z is formed on the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 across these areas (transparent conductive film forming step). As a method of forming the transparent conductive film 28Z, for example, a CVD method or a PVD method can be used.
繼而，如圖4C所示，介隔透明導電膜28Z於第1導電型半導體層25上形成第1金屬電極層29，並介隔透明導電膜28Z於第2導電型半導體層35上形成第2金屬電極層39(金屬電極層形成步驟)。 第1金屬電極層29及第2金屬電極層39係藉由將印刷材料(例如油墨)進行印刷而形成。作為第1金屬電極層29及第2金屬電極層39之形成方法，可列舉網版印刷法、噴墨法、凹版塗佈法、或分注器法等。該等之中，較佳為網版印刷法。Then, as shown in FIG. 4C , the first metal electrode layer 29 is formed on the first conductive type semiconductor layer 25 via the transparent conductive film 28Z, and the second metal electrode layer 29 is formed on the second conductive type semiconductor layer 35 via the transparent conductive film 28Z. Metal electrode layer 39 (metal electrode layer forming step). The first metal electrode layer 29 and the second metal electrode layer 39 are formed by printing a printing material (eg, ink). Examples of methods for forming the first metal electrode layer 29 and the second metal electrode layer 39 include a screen printing method, an inkjet method, a gravure coating method, a dispenser method, and the like. Among these, the screen printing method is preferred.
印刷材料係於絕緣性樹脂材料中包含粒子狀(例如球狀)之金屬材料。為調整黏度或塗佈性，印刷材料亦可包含溶劑等。 作為絕緣性之樹脂材料，可列舉基質樹脂等。詳細而言，作為絕緣性樹脂，較佳為高分子化合物，尤佳為熱固型樹脂或紫外線硬化型樹脂，代表例為環氧、胺基甲酸酯、聚酯或聚矽氧系之樹脂等。 作為金屬材料，可列舉銀、銅、鋁等。該等之中，較佳為包含銀粒子之銀膠。 例如，印刷材料中含有之金屬材料之比例係相對於印刷材料整體之重量比為85%以上95%以下。The printing material contains a particulate (for example, spherical) metal material in an insulating resin material. In order to adjust the viscosity or coating properties, the printing material may also contain solvents, etc. Examples of the insulating resin material include matrix resin and the like. Specifically, as the insulating resin, a polymer compound is preferred, and a thermosetting resin or an ultraviolet curing resin is particularly preferred. Typical examples are epoxy, urethane, polyester, or polysiloxane-based resins. wait. Examples of metal materials include silver, copper, aluminum, and the like. Among these, preferred is a silver colloid containing silver particles. For example, the proportion of the metal material contained in the printing material is 85% or more and 95% or less based on the weight ratio of the entire printing material.
其次，於第1金屬電極層29及第2金屬電極層39之印刷後，藉由加熱處理或紫外線照射處理而使第1金屬電極層29及第2金屬電極層39中之絕緣性樹脂硬化。此時，絕緣性樹脂材料滲出至第1金屬電極層29及第2金屬電極層39之周緣，於第1金屬電極層29之周緣及第2金屬電極層39之周緣，形成偏集存在有絕緣性樹脂材料之樹脂膜40。Next, after the first metal electrode layer 29 and the second metal electrode layer 39 are printed, the insulating resin in the first metal electrode layer 29 and the second metal electrode layer 39 is cured by heat treatment or ultraviolet irradiation treatment. At this time, the insulating resin material exudes to the periphery of the first metal electrode layer 29 and the second metal electrode layer 39, and forms a partial set and insulation at the periphery of the first metal electrode layer 29 and the second metal electrode layer 39. Resin film 40 of flexible resin material.
此時，第1金屬電極層29與第2金屬電極層39之間之透明導電膜28Z之凹凸構造(紋理構造)之谷部由樹脂膜40覆蓋。另一方面，第1金屬電極層29與第2金屬電極層39之間之透明導電膜28Z之凹凸構造之頂部未被樹脂膜40覆蓋而露出。 再者，以此方式由導電性膠形成之第1金屬電極層29及第2金屬電極層39亦可具有胺基甲酸酯鍵。例如與環氧樹脂相比，胺基甲酸酯樹脂係交聯時之收縮較小，樹脂中不易產生龜裂。若樹脂不易產生龜裂，則可防止蝕刻溶液滲入至金屬電極，從而可防止由金屬電極層之下之透明導電膜被蝕刻引起之金屬電極層之剝落、或長期可靠性之惡化。At this time, the valley portion of the uneven structure (texture structure) of the transparent conductive film 28Z between the first metal electrode layer 29 and the second metal electrode layer 39 is covered with the resin film 40 . On the other hand, the top of the uneven structure of the transparent conductive film 28Z between the first metal electrode layer 29 and the second metal electrode layer 39 is not covered by the resin film 40 and is exposed. Furthermore, the first metal electrode layer 29 and the second metal electrode layer 39 formed of conductive glue in this manner may also have urethane bonds. For example, compared with epoxy resin, urethane resin shrinks less when cross-linked, and cracks are less likely to occur in the resin. If the resin is less likely to crack, the etching solution can be prevented from penetrating into the metal electrode, thereby preventing the metal electrode layer from peeling off or deteriorating long-term reliability caused by etching of the transparent conductive film under the metal electrode layer.
其次，如圖4D所示，使用將第1金屬電極層29及其周緣之樹脂膜40、以及第2金屬電極層39及其周緣之樹脂膜40用作遮罩之蝕刻法，將透明導電膜28Z圖案化，藉此，形成相互分離之第1透明電極層28及第2透明電極層38(透明電極層形成步驟)。作為蝕刻法例如可列舉濕式蝕刻法，作為蝕刻溶液可列舉鹽酸(HCl)等酸性溶液。Next, as shown in FIG. 4D , an etching method using the first metal electrode layer 29 and its peripheral resin film 40 and the second metal electrode layer 39 and its peripheral resin film 40 as masks is used to remove the transparent conductive film. 28Z patterning, thereby forming the first transparent electrode layer 28 and the second transparent electrode layer 38 that are separated from each other (transparent electrode layer forming step). Examples of the etching method include wet etching, and examples of the etching solution include acidic solutions such as hydrochloric acid (HCl).
此時，於第1金屬電極層29與第2金屬電極層39之間，透明導電膜28Z之蝕刻自凹凸構造(紋理構造)之頂部朝向谷部進行。 此處，為將第1透明電極層28與第2透明電極層38分離，該等之間之透明導電膜不連續即可，透明導電膜48亦可島狀地殘留於凹凸構造之谷部。若透明導電膜48以島狀殘留於凹凸構造之谷部，則凹凸構造之谷部中之樹脂膜40殘留於第1導電型半導體層25及第2導電型半導體層35上。 藉由以上步驟，完成本實施形態之背面電極型太陽電池1。At this time, etching of the transparent conductive film 28Z proceeds from the top of the uneven structure (textured structure) toward the valley between the first metal electrode layer 29 and the second metal electrode layer 39 . Here, in order to separate the first transparent electrode layer 28 and the second transparent electrode layer 38, the transparent conductive film between them may be discontinuous, and the transparent conductive film 48 may remain in the valleys of the uneven structure in an island shape. If the transparent conductive film 48 remains in the valley portion of the uneven structure in an island shape, the resin film 40 in the valley portion of the uneven structure remains on the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 . Through the above steps, the back electrode type solar cell 1 of this embodiment is completed.
此處，先前之太陽電池之製造方法係於透明導電膜形成步驟之後且金屬電極層形成步驟之前，包含透明電極層形成步驟。 於透明電極層形成步驟中，例如藉由使用光微影法將透明導電膜圖案化，而形成相互分離之第1透明電極層及第2透明電極層。於光微影法中， ∙於透明導電膜之上塗佈抗蝕劑， ∙藉由使抗蝕劑感光而於抗蝕劑形成開口， ∙將抗蝕劑作為遮罩，蝕刻於開口露出之透明導電膜，藉此，形成相互分離之第1透明電極層及第2透明電極層， ∙將抗蝕劑去除。Here, the previous solar cell manufacturing method includes a transparent electrode layer forming step after the transparent conductive film forming step and before the metal electrode layer forming step. In the step of forming the transparent electrode layer, for example, the transparent conductive film is patterned using a photolithography method to form a first transparent electrode layer and a second transparent electrode layer that are separated from each other. In photolithography, ∙Coat resist on the transparent conductive film, ∙ Form openings in the resist by exposing the resist to light, ∙Use the resist as a mask and etch the transparent conductive film exposed through the opening to form a first transparent electrode layer and a second transparent electrode layer that are separated from each other. ∙Remove the resist.
相對於此，根據本實施形態之太陽電池之製造方法，於透明導電膜形成步驟之後，依序包含金屬電極層形成步驟及透明電極層形成步驟，且於透明電極層形成步驟中，將由金屬電極層形成步驟形成之第1金屬電極層29及第2金屬電極層39用作遮罩，將透明導電膜28Z圖案化，藉此，形成相互分離之第1透明電極層28及第2透明電極層38。藉此，根據本實施形態之太陽電池之製造方法，無需如先前般使用利用遮罩之光微影法等，便可簡化及縮短透明電極層之形成。其結果，能夠實現太陽電池及太陽電池模組之低成本化。On the other hand, according to the method of manufacturing a solar cell according to this embodiment, after the transparent conductive film forming step, the metal electrode layer forming step and the transparent electrode layer forming step are sequentially included, and in the transparent electrode layer forming step, the metal electrode is formed. The first metal electrode layer 29 and the second metal electrode layer 39 formed in the layer formation step are used as masks to pattern the transparent conductive film 28Z, thereby forming the first transparent electrode layer 28 and the second transparent electrode layer that are separated from each other. 38. Therefore, according to the solar cell manufacturing method of this embodiment, the formation of the transparent electrode layer can be simplified and shortened without the need to use the photolithography method using a mask as before. As a result, the cost of solar cells and solar cell modules can be reduced.
此處，若將第1金屬電極層29及第2金屬電極層39用作遮罩，將透明導電膜28Z圖案化，則於蝕刻透明導電膜28Z時，存在第1金屬電極層29及第2金屬電極層39之下之透明導電膜28Z亦被蝕刻，導致第1透明電極層28及第1金屬電極層29、以及第2透明電極層38及第2金屬電極層39剝離之可能性。Here, if the first metal electrode layer 29 and the second metal electrode layer 39 are used as masks to pattern the transparent conductive film 28Z, when the transparent conductive film 28Z is etched, the first metal electrode layer 29 and the second metal electrode layer 29 will be present. The transparent conductive film 28Z under the metal electrode layer 39 is also etched, resulting in the possibility of peeling off of the first transparent electrode layer 28 and the first metal electrode layer 29 and the second transparent electrode layer 38 and the second metal electrode layer 39 .
關於該點，根據本實施形態之太陽電池之製造方法，於金屬電極層形成步驟中，藉由印刷包含粒子狀之金屬材料、樹脂材料及溶劑之印刷材料且使其硬化，而於第1金屬電極層29之周緣及第2金屬電極層39之周緣形成偏集存在有樹脂材料之樹脂膜40，且於透明電極層形成步驟中，將第1金屬電極層29及其周緣之樹脂膜40、以及第2金屬電極層39及其周緣之樹脂膜40用作遮罩，將透明導電膜28Z圖案化。藉此，可抑制第1金屬電極層29及第2金屬電極層39之下之透明導電膜28Z之蝕刻，從而可抑制第1透明電極層28及第1金屬電極層29之剝離、以及第2透明電極層38及第2金屬電極層39之剝離。In this regard, according to the solar cell manufacturing method of this embodiment, in the metal electrode layer forming step, a printing material containing a particulate metal material, a resin material, and a solvent is printed and hardened, so that the first metal is The periphery of the electrode layer 29 and the periphery of the second metal electrode layer 39 form a resin film 40 in which the resin material is present in a concentrated manner, and in the step of forming the transparent electrode layer, the first metal electrode layer 29 and the resin film 40 on its periphery are The second metal electrode layer 39 and the resin film 40 on its periphery are used as masks to pattern the transparent conductive film 28Z. Thereby, the etching of the transparent conductive film 28Z under the first metal electrode layer 29 and the second metal electrode layer 39 can be suppressed, thereby suppressing the peeling of the first transparent electrode layer 28 and the first metal electrode layer 29, and the second The transparent electrode layer 38 and the second metal electrode layer 39 are peeled off.
藉由此種製造方法製造之太陽電池1中，第1透明電極層28之帶寬窄於第1金屬電極層29之帶寬，第2透明電極層38之帶寬窄於第2金屬電極層39之帶寬，於第1金屬電極層29之周緣及第2金屬電極層39之周緣，形成偏集存在有第1金屬電極層29及第2金屬電極層39之印刷材料中之樹脂材料之樹脂膜。 再者，於由先前之太陽電池之製造方法製造之太陽電池中，一般而言，透明電極層之帶寬大於金屬電極層之帶寬。In the solar cell 1 manufactured by this manufacturing method, the bandwidth of the first transparent electrode layer 28 is narrower than the bandwidth of the first metal electrode layer 29, and the bandwidth of the second transparent electrode layer 38 is narrower than the bandwidth of the second metal electrode layer 39. , on the periphery of the first metal electrode layer 29 and the periphery of the second metal electrode layer 39, a resin film is formed that selectively collects the resin material in the printing material in which the first metal electrode layer 29 and the second metal electrode layer 39 are present. Furthermore, in solar cells manufactured by previous solar cell manufacturing methods, generally speaking, the bandwidth of the transparent electrode layer is larger than the bandwidth of the metal electrode layer.
又，由本實施形態之製造方法製造之太陽電池1中，第1金屬電極層29與第2金屬電極層39之間的第1導電型半導體層25之一部分及第2導電型半導體層35之一部分由樹脂膜40覆蓋。詳細而言，第1金屬電極層29與第2金屬電極層39之間的第1導電型半導體層25之凹凸構造(紋理構造)之谷部及第2導電型半導體層35之凹凸構造之谷部由樹脂膜40覆蓋。 又，於第1導電型半導體層25與樹脂膜40之層間及第2導電型半導體層35與樹脂膜40之層間，島狀(不連續)地配置有與第1透明電極層28及第2透明電極層38為相同材料之透明導電膜48。詳細而言，於第1導電型半導體層25之凹凸構造之谷部與樹脂膜40之層間及第2導電型半導體層35之凹凸構造之谷部與樹脂膜40之層間，島狀地配置有透明導電膜48。 藉此，第1導電型半導體層25及第2導電型半導體層35露出之面積變小。因此，可抑制太陽電池及太陽電池模組之劣化，從而太陽電池及太陽電池模組之可靠性(例如長期耐久性)提昇。In addition, in the solar cell 1 manufactured by the manufacturing method of this embodiment, a part of the first conductive type semiconductor layer 25 and a part of the second conductive type semiconductor layer 35 between the first metal electrode layer 29 and the second metal electrode layer 39 Covered with resin film 40 . Specifically, the valleys of the uneven structure (texture structure) of the first conductive type semiconductor layer 25 and the valleys of the uneven structure of the second conductive type semiconductor layer 35 between the first metal electrode layer 29 and the second metal electrode layer 39 is covered with a resin film 40. Furthermore, between the first conductive semiconductor layer 25 and the resin film 40 and between the second conductive semiconductor layer 35 and the resin film 40, the first transparent electrode layer 28 and the second transparent electrode layer 28 are arranged in an island shape (discontinuously). The transparent electrode layer 38 is a transparent conductive film 48 of the same material. Specifically, islands are arranged between the valleys of the uneven structure of the first conductive type semiconductor layer 25 and the resin film 40 and between the valleys of the uneven structure of the second conductive type semiconductor layer 35 and the resin film 40 . Transparent conductive film 48. Thereby, the exposed areas of the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 become smaller. Therefore, the deterioration of the solar cell and the solar cell module can be suppressed, thereby improving the reliability (eg, long-term durability) of the solar cell and the solar cell module.
以上，對本發明之實施形態進行了說明，但本發明並非限定於上述實施形態，而能夠進行各種變更及變形。例如，於上述實施形態中，如圖3所示，例示了異質接面型太陽電池1，但本發明並不限於異質接面型太陽電池，亦可適用於同質接面型太陽電池等各種太陽電池。The embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible. For example, in the above-mentioned embodiment, as shown in FIG. 3 , the heterojunction solar cell 1 is exemplified. However, the present invention is not limited to the heterojunction solar cell and can be applied to various solar cells such as homojunction solar cells. Battery.
又，於上述實施形態中，例示了具有結晶矽基板之太陽電池，但並非限定於此。例如，太陽電池亦可具有砷化鎵(GaAs)基板。 [實施例]Furthermore, in the above embodiment, a solar cell having a crystalline silicon substrate was exemplified, but the invention is not limited to this. For example, a solar cell may also have a gallium arsenide (GaAs) substrate. [Example]
以下，基於實施例具體地說明本發明，但本發明並非限定於以下實施例。Hereinafter, the present invention will be specifically described based on examples, but the present invention is not limited to the following examples.
如下所述，按照圖4A～圖4D所示之步驟製作圖2及圖3所示之太陽電池1。As described below, the solar cell 1 shown in FIGS. 2 and 3 is produced according to the steps shown in FIGS. 4A to 4D .
首先，藉由於單晶矽基板之背面側進行各向異性蝕刻，而獲得於背面側形成有稜錐形紋理構造之半導體基板11。First, by performing anisotropic etching on the back side of the single crystal silicon substrate, a semiconductor substrate 11 having a pyramidal texture structure formed on the back side is obtained.
其次，使用CVD法，於半導體基板11之整個背面側將鈍化膜及第1導電型半導體膜製膜之後，使用利用採用光微影技術產生之光阻(遮罩)之蝕刻法，於半導體基板11之背面側之一部分，形成鈍化層23及第1導電型半導體層25(半導體層形成步驟)。Next, a passivation film and a first conductive type semiconductor film are formed on the entire back side of the semiconductor substrate 11 using the CVD method, and then an etching method using a photoresist (mask) produced by photolithography technology is used to form a film on the semiconductor substrate. A passivation layer 23 and a first conductive type semiconductor layer 25 are formed on a part of the back side of 11 (semiconductor layer forming step).
其次，使用CVD法，於半導體基板11之整個背面側將鈍化膜及第2導電型半導體膜製膜之後，使用利用採用光微影技術產生之光阻(遮罩)之蝕刻法，於半導體基板11之背面側之另一部分，形成鈍化層33及第2導電型半導體層35(半導體層形成步驟)。Next, a passivation film and a second conductive type semiconductor film are formed on the entire back side of the semiconductor substrate 11 using the CVD method, and then an etching method using a photoresist (mask) produced by photolithography technology is used to form a film on the semiconductor substrate. On the other part of the back side of 11, the passivation layer 33 and the second conductive type semiconductor layer 35 are formed (semiconductor layer forming step).
其次，使用CVD法，於第1導電型半導體層25及第2導電型半導體層35上，跨及該等形成透明導電膜28Z(透明導電膜形成步驟)。Next, the CVD method is used to form a transparent conductive film 28Z on the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 across them (transparent conductive film forming step).
其次，使用利用銀膠之網版印刷法，介隔透明導電膜28Z於第1導電型半導體層25上形成第1金屬電極層29，並介隔透明導電膜28Z於第2導電型半導體層35上形成第2金屬電極層39(金屬電極層形成步驟)。 其後，將第1金屬電極層29及第2金屬電極層39於180℃之烘箱中進行1小時加熱處理。藉此，印刷材料中之絕緣性樹脂材料滲出至第1金屬電極層29之周緣及第2金屬電極層39之周緣，於第1金屬電極層29之周緣及第2金屬電極層39之周緣形成樹脂膜40。Next, a screen printing method using silver glue is used to form the first metal electrode layer 29 on the first conductive type semiconductor layer 25 with the transparent conductive film 28Z interposed, and the transparent conductive film 28Z is interposed with the second conductive type semiconductor layer 35 The second metal electrode layer 39 is formed on the second metal electrode layer 39 (metal electrode layer forming step). Thereafter, the first metal electrode layer 29 and the second metal electrode layer 39 were heated in an oven at 180° C. for 1 hour. Thereby, the insulating resin material in the printing material bleeds to the periphery of the first metal electrode layer 29 and the periphery of the second metal electrode layer 39, and is formed on the periphery of the first metal electrode layer 29 and the periphery of the second metal electrode layer 39. Resin film 40.
其次，使用將第1金屬電極層29及其周緣之樹脂膜40、以及第2金屬電極層39及其周緣之樹脂膜40用作遮罩之蝕刻法，將透明導電膜28Z圖案化，藉此，形成相互分離之第1透明電極層28及第2透明電極層38(透明電極層形成步驟)。作為蝕刻溶液，使用鹽酸(HCl)。Next, the transparent conductive film 28Z is patterned using an etching method using the first metal electrode layer 29 and the resin film 40 around it and the second metal electrode layer 39 and the resin film 40 around it as masks. , forming the first transparent electrode layer 28 and the second transparent electrode layer 38 that are separated from each other (transparent electrode layer forming step). As the etching solution, hydrochloric acid (HCl) is used.
於以上述方式製作實施例之太陽電池之過程中，使用SEM(Field Emission Scanning Electron Microscope，場發射掃描型電子顯微鏡S4800，日立高新技術公司製造)觀測透明導電膜形成步驟及金屬電極層形成步驟之後且透明電極層形成步驟前之太陽電池之背面側。其結果示於圖5A～圖5C。In the process of manufacturing the solar cells of the examples in the above manner, SEM (Field Emission Scanning Electron Microscope, Field Emission Scanning Electron Microscope S4800, manufactured by Hitachi High-Technology Co., Ltd.) was used to observe the transparent conductive film formation step and the metal electrode layer formation step. And the back side of the solar cell before the transparent electrode layer forming step. The results are shown in Figures 5A to 5C.
圖5A係使用SEM以100倍之倍率觀測實施例之太陽電池之背面側之金屬電極層及金屬電極層間所得之結果，圖5B係使用SEM以450倍之倍率觀測圖5A之金屬電極層間之部分A所得之結果。圖5C係使用SEM以5000倍之倍率觀測圖5B之金屬電極層間之部分B所得之結果。Figure 5A is the result of using SEM to observe the metal electrode layer and the space between the metal electrode layers on the back side of the solar cell of the example at a magnification of 100 times. Figure 5B is using a SEM to observe the part between the metal electrode layers of Figure 5A at a magnification of 450 times. The result obtained by A. Figure 5C is the result obtained by using SEM to observe the portion B between the metal electrode layers in Figure 5B at a magnification of 5000 times.
根據圖5A～圖5C，確認到於第1金屬電極層29之周緣及第2金屬電極層39之周緣，形成有偏集存在有絕緣性樹脂材料之樹脂膜40(黑色部分)。 又，確認到第1金屬電極層29與第2金屬電極層39之間之透明導電膜28Z之凹凸構造(紋理構造)之谷部由樹脂膜40(黑色部分)覆蓋。另一方面，確認到第1金屬電極層29與第2金屬電極層39之間之透明導電膜28Z之凹凸構造之頂部未被樹脂膜40覆蓋而露出。藉此，預測於其後之透明電極層形成步驟之蝕刻中，透明導電膜28Z之蝕刻自凹凸構造之頂部朝向谷部進行。According to FIGS. 5A to 5C , it is confirmed that the resin film 40 (black portion) in which the insulating resin material is dispersed is formed on the periphery of the first metal electrode layer 29 and the periphery of the second metal electrode layer 39 . Furthermore, it was confirmed that the valley portions of the uneven structure (textured structure) of the transparent conductive film 28Z between the first metal electrode layer 29 and the second metal electrode layer 39 were covered with the resin film 40 (black portion). On the other hand, it was confirmed that the top of the uneven structure of the transparent conductive film 28Z between the first metal electrode layer 29 and the second metal electrode layer 39 was not covered by the resin film 40 and was exposed. From this, it is predicted that in the subsequent etching of the transparent electrode layer formation step, the etching of the transparent conductive film 28Z proceeds from the top of the uneven structure toward the valley.
其次，於透明電極形成步驟之後，使用SEM觀測製作而成之實施例之太陽電池之背面側，確認到第1透明電極層28及第1金屬電極層29、以及第2透明電極層38及第2金屬電極層39未剝離。又，確認到於第1金屬電極層29與第2金屬電極層39之間之凹凸構造之谷部，樹脂膜40未被剝離而殘留。 進而，進行電極間之短路檢查，確認到電極層間無短路。 因樹脂膜40未被剝離，且電極層間無短路，故預測透明導電膜48以島狀殘留於第1導電型半導體層25之凹凸構造之谷部與樹脂膜40之層間、及第2導電型半導體層35之凹凸構造之谷部與樹脂膜40之層間，樹脂膜40得以保持。Next, after the transparent electrode formation step, the back side of the solar cell of the example produced was observed using SEM, and it was confirmed that the first transparent electrode layer 28 and the first metal electrode layer 29, as well as the second transparent electrode layer 38 and the 2. The metal electrode layer 39 is not peeled off. Furthermore, it was confirmed that the resin film 40 was not peeled off but remained in the valley portion of the uneven structure between the first metal electrode layer 29 and the second metal electrode layer 39 . Furthermore, short circuit inspection between electrodes was performed to confirm that there was no short circuit between electrode layers. Since the resin film 40 has not been peeled off and there is no short circuit between the electrode layers, it is expected that the transparent conductive film 48 remains in an island shape between the valleys of the uneven structure of the first conductivity type semiconductor layer 25 and the resin film 40 and between the second conductivity type The resin film 40 is maintained between the valleys of the uneven structure of the semiconductor layer 35 and the resin film 40 .
1:太陽電池 2:配線構件 3:受光面保護構件 4:背面保護構件 5:密封材 7:第1導電型區域 7b:柵線部 7f:細柵線部 8:第2導電型區域 8b:柵線部 8f:細柵線部 11:半導體基板 13:鈍化層 23:鈍化層 25:第1導電型半導體層 27:第1電極層 28:第1透明電極層 28Z:透明導電膜 29:第1金屬電極層 33:鈍化層 35:第2導電型半導體層 37:第2電極層 38:第2透明電極層 39:第2金屬電極層 40:樹脂膜 48:透明導電膜 100:太陽電池模組 A:部分1:Solar battery 2: Wiring components 3: Light-receiving surface protection component 4: Back protection component 5:Sealing material 7: 1st conductivity type area 7b:Grid line part 7f: Fine grid line part 8: 2nd conductivity type area 8b:Grid line part 8f: Fine grid line part 11:Semiconductor substrate 13: Passivation layer 23: Passivation layer 25: First conductive semiconductor layer 27: 1st electrode layer 28: 1st transparent electrode layer 28Z: Transparent conductive film 29: 1st metal electrode layer 33: Passivation layer 35: Second conductive type semiconductor layer 37: 2nd electrode layer 38: 2nd transparent electrode layer 39: 2nd metal electrode layer 40:Resin film 48:Transparent conductive film 100:Solar battery module A: part
圖1係表示本實施形態之太陽電池模組之一例之側視圖。 圖2係自背面側觀察本實施形態之太陽電池所得之圖。 圖3係圖2之太陽電池中之III-III線剖視圖。 圖4A係表示本實施形態之太陽電池之製造方法中之半導體層形成步驟之圖。 圖4B係表示本實施形態之太陽電池之製造方法中之透明導電膜形成步驟之圖。 圖4C係表示本實施形態之太陽電池之製造方法中之金屬電極層形成步驟之圖。 圖4D係表示本實施形態之太陽電池之製造方法中之透明電極層形成步驟之圖。 圖5A係使用SEM以100倍之倍率觀測實施例之太陽電池之背面側之金屬電極層及金屬電極層間所得之結果。 圖5B係使用SEM以450倍之倍率觀測圖5A之金屬電極層間之部分A所得之結果。 圖5C係使用SEM以5000倍之倍率觀測圖5B之金屬電極層間之部分B所得之結果。FIG. 1 is a side view showing an example of a solar cell module according to this embodiment. FIG. 2 is a view of the solar cell of this embodiment viewed from the back side. FIG. 3 is a cross-sectional view of the solar cell in FIG. 2 taken along line III-III. FIG. 4A is a diagram showing a semiconductor layer formation step in the solar cell manufacturing method of this embodiment. FIG. 4B is a diagram showing the steps of forming a transparent conductive film in the method of manufacturing a solar cell according to this embodiment. FIG. 4C is a diagram showing the metal electrode layer formation steps in the solar cell manufacturing method of this embodiment. FIG. 4D is a diagram showing the transparent electrode layer forming step in the solar cell manufacturing method of this embodiment. FIG. 5A is the result obtained by using SEM to observe the metal electrode layer and the space between the metal electrode layers on the back side of the solar cell of the example at a magnification of 100 times. Figure 5B is the result obtained by using SEM to observe the portion A between the metal electrode layers in Figure 5A at a magnification of 450 times. Figure 5C is the result obtained by using SEM to observe the portion B between the metal electrode layers in Figure 5B at a magnification of 5000 times.
7:第1導電型區域 7: 1st conductivity type area
7f:細柵線部 7f: Fine grid line part
8:第2導電型區域 8: 2nd conductivity type area
8f:細柵線部 8f: Fine grid line part
11:半導體基板 11:Semiconductor substrate
13:鈍化層 13: Passivation layer
23:鈍化層 23: Passivation layer
25:第1導電型半導體層 25: First conductive semiconductor layer
27:第1電極層 27: 1st electrode layer
28:第1透明電極層 28: 1st transparent electrode layer
29:第1金屬電極層 29: 1st metal electrode layer
33:鈍化層 33: Passivation layer
35:第2導電型半導體層 35: Second conductive type semiconductor layer
37:第2電極層 37: 2nd electrode layer
38:第2透明電極層 38: 2nd transparent electrode layer
39:第2金屬電極層 39: 2nd metal electrode layer
40:樹脂膜 40:Resin film
48:透明導電膜 48:Transparent conductive film
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