WO2021201030A1

WO2021201030A1 - Solar cell and solar cell manufacturing method

Info

Publication number: WO2021201030A1
Application number: PCT/JP2021/013687
Authority: WO
Inventors: 貴久藤本; 足立　大輔; 山本　憲治
Original assignee: 株式会社カネカ
Priority date: 2020-03-30
Filing date: 2021-03-30
Publication date: 2021-10-07
Also published as: JPWO2021201030A1

Abstract

Provided is a solar cell with improved reliability. In the solar cell, a textured structure having a pyramid-shaped microrelief structure is formed on the back surface side of a semiconductor substrate 11. In a first region-side boundary region of a second region on the back surface side of the semiconductor substrate 11, each slanting face of each pyramid 11A has a first slanting face SF1 from a pyramid foot 1A to a halfway point 2A, and a second slanting face SF2 from the halfway point 2A to a pyramid peak 3A. The slope of the second slanting face SF2 is gentler than the slope of the first slanting face SF1. The minimum angle θ formed by the straight line from the pyramid foot 1A to the pyramid peak 3A and the straight line from the pyramid foot 1A to the bending point of the halfway point 2A is 8 < θ ≤ 30. The pyramids 11A occupy 0.01-50% (inclusive) of the area of the back surface, and the thickness of a second semiconductor layer 35, 33 on the second slanting face SF2 is larger than the thickness of the second semiconductor layer 35, 33 on the first slanting face SF1.

Description

Solar cells and solar cell manufacturing methods

The present invention relates to a back electrode type (back contact type) solar cell and a method for manufacturing the solar cell.

As a solar cell using a semiconductor substrate, there are a double-sided electrode type solar cell in which electrodes are formed on both the light receiving surface side and the back surface side, and a back electrode type solar cell in which electrodes are formed only on the back surface side. In a double-sided electrode type solar cell, since an electrode is formed on the light receiving surface side, sunlight is shielded by this electrode. On the other hand, in the back electrode type solar cell, since the electrode is not formed on the light receiving surface side, the light receiving rate of sunlight is higher than that of the double-sided electrode type solar cell. Patent Document 1 discloses a back electrode type solar cell.

The solar cell described in Patent Document 1 includes a semiconductor substrate having a texture structure having a pyramid-shaped fine uneven structure formed on the light receiving surface side and the back surface side. The slope of the pyramid on the back surface side has a first slope from the foot of the mountain to the middle slope and a second slope from the middle slope to the top of the mountain, which has a different inclination angle from the first slope. As a result, in the light that has entered the semiconductor substrate from the light receiving surface side, for example, even if the light reflected on the first slope is transmitted to the outside, the light reflected on the second slope is difficult to be transmitted to the outside. Therefore, the photoelectric conversion efficiency of the solar cell can be improved.

International Publication No. 2018/179656

By the way, in the back electrode type solar cell, it is desired to improve the reliability due to the exposure of the semiconductor layer between the electrodes having different polarities.

An object of the present invention is to provide a solar cell having improved reliability and a method for manufacturing the solar cell.

In the solar cell according to the present invention, the semiconductor substrate and the first semiconductor layer and the first electrode layer which are sequentially laminated in the first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate. A back electrode type solar cell including a second semiconductor layer and a second electrode layer sequentially laminated in a second region which is another part of the other main surface side of the semiconductor substrate. A texture structure having a pyramid-shaped fine concavo-convex structure is formed on at least the other main surface side of the substrate, and the boundary on the first region side in the second region on the other main surface side of the semiconductor substrate. In the area
The slope of the pyramid has a first slope from the foot of the mountain to the middle of the mountain and a second slope from the middle of the mountain to the top of the mountain.
The slope of the second slope is gentler than the slope of the first slope.
A first virtual straight line from the foot of the mountain to the top of the mountain and a second virtual straight line from the foot of the mountain to the inflection point of the middle of the mountain in a cross section orthogonal to the foot of the mountain. The minimum angle θ [°] to be formed is 8 <θ ≦ 30.
The pyramid occupies 0.01% or more and 50% or less of the area of the other main surface.
The film thickness of the second semiconductor layer on the second slope is thicker than the film thickness of the second semiconductor layer on the first slope.

Another solar cell according to the present invention includes a semiconductor substrate, a first semiconductor layer and a first semiconductor layer sequentially laminated in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate. A back electrode type solar cell comprising an electrode layer and a second semiconductor layer and a second electrode layer sequentially laminated in a second region which is another part of the other main surface side of the semiconductor substrate. A texture structure having a pyramid-shaped fine concavo-convex structure is formed at least on the other main surface side of the semiconductor substrate, and the first region side in the second region on the other main surface side of the semiconductor substrate. In the boundary area of
The slope of the pyramid has a first slope from the foot of the mountain to the middle of the mountain and a second slope from the middle of the mountain to the top of the mountain.
The slope of the second slope is gentler than the slope of the first slope.
The first semiconductor layer and the second semiconductor layer are laminated in this order on at least a part of the first slope.
The film thickness of the second semiconductor layer on the second slope is thicker than the film thickness of the second semiconductor layer on the first slope.

The method for manufacturing a solar cell according to the present invention includes a semiconductor substrate, a first semiconductor layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a first semiconductor layer. A method for manufacturing a back electrode type solar cell comprising one electrode layer and a second semiconductor layer and a second electrode layer sequentially laminated in a second region which is another part of the other main surface side of the semiconductor substrate. A step of forming a texture structure having a pyramid-shaped fine concavo-convex structure on at least the other main surface side of the semiconductor substrate, and a step of forming the first semiconductor layer on the other main surface side of the semiconductor substrate. A first semiconductor layer material film forming step of forming a material film, a resist forming step of forming a resist on the material film of the first semiconductor layer in the first region, and the second region using the resist as a mask. The first semiconductor layer forming step of forming the patterned first semiconductor layer in the first region by removing the material film of the first semiconductor layer and removing the resist, and the second The region includes a second semiconductor layer forming step of forming the patterned second semiconductor layer. In the resist forming step, the resist is formed in the first region by printing and curing the printing material containing the resin material by using the pattern printing method, and the first region side in the second region is formed. An exuding film formed by exuding the printing material is formed on the first slope from the mountain hem to the middle of the pyramid in the boundary region (exuding region of the printing resist). In the first semiconductor layer forming step, the material film of the first semiconductor layer is etched with the resist and the exuding film on the periphery thereof as a mask, so that the boundary region on the first region side in the second region is formed. ,
The slope of the pyramid has a first slope from the foot of the mountain to the middle of the mountain and a second slope from the middle of the mountain to the top of the mountain.
The slope of the second slope is gentler than the slope of the first slope.
A first virtual straight line from the foot of the mountain to the top of the mountain and a second virtual straight line from the foot of the mountain to the inflection point of the middle of the mountain in a cross section orthogonal to the foot of the mountain. The minimum angle θ [°] to be formed is 8 <θ ≦ 30.
The pyramid occupies 0.01% or more and 50% or less of the area of the other main surface.
Form the pyramid. In the second semiconductor layer forming step, the film thickness on the second slope is thicker than the film thickness on the first slope in the boundary region (print resist exuding region) on the first region side in the second region. The second semiconductor layer is formed.

Another method for manufacturing a solar cell according to the present invention is a first semiconductor layer laminated in order on a semiconductor substrate and a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate. A back electrode type solar cell comprising the first electrode layer and the second semiconductor layer and the second electrode layer sequentially laminated in the second region which is another part of the other main surface side of the semiconductor substrate. In the manufacturing method, a step of forming a texture structure having a pyramid-shaped fine concavo-convex structure on at least the other main surface side of the semiconductor substrate, and the first semiconductor on the other main surface side of the semiconductor substrate. The first semiconductor layer material film forming step of forming the material film of the layer, the resist forming step of forming a resist on the material film of the first semiconductor layer in the first region, and the first step using the resist as a mask. The first semiconductor layer forming step of forming the patterned first semiconductor layer in the first region by removing the material film of the first semiconductor layer in the two regions and removing the resist, and the above-mentioned The second region includes a second semiconductor layer forming step of forming the patterned second semiconductor layer. In the resist forming step, the resist is formed in the first region by printing and curing the printing material containing the resin material by using the pattern printing method, and the first region side in the second region is formed. An exudate film formed by exuding the printing material is formed on the first slope from the mountain hem to the middle of the pyramid in the boundary region of the above. In the first semiconductor layer forming step, the material film of the first semiconductor layer is etched with the resist and the exuding film on the periphery thereof as a mask, so that the boundary region on the first region side in the second region is formed. ,
The slope of the pyramid has a first slope from the foot of the mountain to the middle of the mountain and a second slope from the middle of the mountain to the top of the mountain.
The slope of the second slope is gentler than the slope of the first slope.
The first semiconductor layer is laminated on at least a part of the first slope.
Form the pyramid. In the second semiconductor layer forming step, the second semiconductor layer is formed on the first semiconductor layer on the first slope in the boundary region on the first region side in the second region, and the second slope is formed. The second semiconductor layer is formed in which the film thickness is thicker than the film thickness on the first slope.

According to the present invention, it is possible to improve the reliability of the solar cell.

It is the figure which looked at the solar cell which concerns on 1st Embodiment from the back side. FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. FIG. 3 is an enlarged cross-sectional view of a boundary region III between the first region and the second region shown in FIG. It is an enlarged cross-sectional view of the back surface of the semiconductor substrate in a part VA of the boundary region (exudation region of the pattern printing resist) on the 1st region side in the 2nd region shown in FIG. It is an enlarged cross-sectional view of the back surface of the semiconductor substrate in a part VB other than the boundary region in the 2nd region shown in FIG. It is an enlarged cross-sectional view of the semiconductor layer in a part VA of the boundary region (exudation region of the pattern printing resist) on the 1st region side in the 2nd region shown in FIG. FIG. 3 is an enlarged cross-sectional view of a semiconductor layer in a part of VB other than the boundary region in the second region shown in FIG. It is a figure which shows the 1st semiconductor layer material film formation process and the lift-off layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 2nd semiconductor layer material film formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the optical adjustment layer forming process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is an enlarged view of the boundary region VIA between the first region and the second region shown in FIG. 6B. It is an enlarged view of the boundary region VIIB between the first region and the second region shown in FIG. 6C. FIG. 6 is an enlarged cross-sectional view of the boundary region VIIC between the first region and the second region shown in FIG. 6G. FIG. 7B is an enlarged cross-sectional view of a part of IVA of the boundary region on the first region side in the second region shown in FIG. 7B. It is sectional drawing of the solar cell which concerns on the modification of 1st Embodiment, and is the sectional view corresponding to line II-II in FIG. FIG. 9 is an enlarged cross-sectional view of a boundary region X between the first region and the second region shown in FIG. It is the figure which looked at the solar cell which concerns on 2nd Embodiment from the back side. FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. It is an enlarged cross-sectional view of the boundary region III between the 1st region and the 2nd region shown in FIG. It is an enlarged cross-sectional view of the back surface of the semiconductor substrate in a part VA of the boundary region (exudation region of the pattern printing resist) on the 1st region side in the 2nd region shown in FIG. It is an enlarged cross-sectional view of the back surface of the semiconductor substrate in a part VB other than the boundary region in the 2nd region shown in FIG. FIG. 3 is an enlarged cross-sectional view of a semiconductor layer in a part VA of a boundary region (exudation region of a pattern print resist) on the first region side in the second region shown in FIG. FIG. 3 is an enlarged cross-sectional view of a semiconductor layer in a part of VB other than the boundary region in the second region shown in FIG. It is a figure which shows the 1st semiconductor layer material film formation process and the lift-off layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 2nd semiconductor layer material film formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the optical adjustment layer forming process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. FIG. 16B is an enlarged view of the boundary region VIA between the first region and the second region shown in FIG. 16B. It is an enlarged view of the boundary region VIIB between the first region and the second region shown in FIG. 16C. It is an enlarged cross-sectional view of the boundary region VIIC between the first region and the second region shown in FIG. 16G. FIG. 17B is an enlarged cross-sectional view of a part of IVA of the boundary region on the first region side in the second region shown in FIG. 17B. It is sectional drawing of the solar cell which concerns on modification of 2nd Embodiment, and is the sectional view corresponding to line II-II in FIG. It is an enlarged cross-sectional view of the boundary region X between the 1st region and the 2nd region shown in FIG.

Hereinafter, an example of the embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each drawing. In addition, for convenience, hatching, member codes, and the like may be omitted, but in such cases, other drawings shall be referred to.

[First Embodiment]
(Solar cell)
FIG. 1 is a view of the solar cell according to the first embodiment as viewed from the back surface side. The solar cell 1 shown in FIG. 1 is a back electrode type (also referred to as a back contact type or back surface bonding type) solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.

The first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to the comb teeth and a bus bar portion 7b corresponding to the support portion of the comb teeth. The bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).

Similarly, the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).

The finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction). The first region 7 and the second region 8 may be formed in a striped shape.

FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. As shown in FIG. 2, the solar cell 1 is a heterojunction type solar cell. The solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and an optical adjustment layer 15 which are sequentially laminated on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side. Further, the solar cell 1 has the intrinsic semiconductor layer 23, which is sequentially laminated on a part of the back surface side (first region 7) which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface. 1 The conductive semiconductor layer 25 and the first electrode layer 27 are provided. Further, the solar cell 1 includes an intrinsic semiconductor layer 33, a second conductive semiconductor layer 35, and a second electrode layer 37, which are sequentially laminated on another part (second region 8) on the back surface side of the semiconductor substrate 11. .. Further, as will be described later, the region including both the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 in the vicinity of the boundary between the first region 7 and the second region 8 is referred to as the second region 8.
In the following, the intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 are also referred to as a first semiconductor layer, and the intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 are also referred to as a second semiconductor layer.

The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. The semiconductor substrate 11 may be, for example, a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant. Examples of the n-type dopant include phosphorus (P). Examples of the p-type dopant include boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).

By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output regardless of the illuminance) can be obtained even when the dark current is relatively small and the intensity of the incident light is low.

The semiconductor substrate 11 has a pyramid-shaped fine uneven structure called a texture structure on the back surface side. As a result, the recovery efficiency of light that has passed through without being absorbed by the semiconductor substrate 11 is increased.

Further, the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light receiving surface side. As a result, the reflection of incident light on the light receiving surface is reduced, and the light confinement effect on the semiconductor substrate 11 is improved.

The intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layers 13, 23, 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component. The intrinsic semiconductor layers 13, 23, 33 function as so-called passivation layers, suppress the recombination of carriers generated in the semiconductor substrate 11, and increase the carrier recovery efficiency.

The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13. The optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).

The first conductive semiconductor layer 25 is formed on the intrinsic semiconductor layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. The first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductive semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).

The second conductive semiconductor layer 35 is formed on the intrinsic semiconductor layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11. The second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductive semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above). The first conductive semiconductor layer 25 may be an n-type semiconductor layer, and the second conductive semiconductor layer 35 may be a p-type semiconductor layer.

The first electrode layer 27 is formed on the first conductive semiconductor layer 25, and the second electrode layer 37 is formed on the second conductive semiconductor layer 35. The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29, which are sequentially laminated on the first conductive semiconductor layer 25. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 which are sequentially laminated on the second conductive semiconductor layer 35.

The transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide). The metal electrode layers 29 and 39 are formed of a conductive paste material or copper containing a metal powder such as silver.

FIG. 3 is an enlarged cross-sectional view of the boundary region III between the first region 7 and the second region 8 shown in FIG. FIG. 4A is an enlarged cross-sectional view of the back surface of the semiconductor substrate 11 in a part VA of the boundary region 8A (exudation region of the pattern printing resist described later) on the side of the first region 7 in the second region 8 shown in FIG. FIG. 5A is an enlarged cross-sectional view of the semiconductor layers 35 and 33 in a part VA of the boundary region 8A (exudation region of the pattern printing resist described later) on the side of the first region 7 in the second region 8 shown in FIG. Further, FIG. 4B is an enlarged cross-sectional view of the back surface of the semiconductor substrate 11 in a part VB other than the boundary region 8A in the second region 8 shown in FIG. 3, and FIG. 5B is a boundary in the second region 8 shown in FIG. FIG. 5 is an enlarged cross-sectional view of semiconductor layers 35 and 33 in a part of VB other than the region 8A.

As shown in FIGS. 3 and 4A, the boundary region 8A (exudation region of the pattern print resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11 is composed of four slopes. A plurality of pyramids 11A are formed.

Each slope of the pyramid 11A has a first slope SF1 from the foot of the mountain 1A to the middle 2A and a second slope SF2 from the middle 2A to the summit 3A. The first slope SF1 and the second slope SF2 have different inclination angles with the bending point of the middle slope 2A as a boundary. The slope of the second slope SF2 is gentler than the slope of the first slope SF1.

In a cross section that passes through the mountaintop 3A and is orthogonal to the mountain hem 1A (that is, the cross section shown in FIG. The minimum angle θ [°] formed by the second virtual straight line L2 up to that point is 8 <θ ≦ 30.

Such a pyramid 11A occupies 0.01% or more and 50% or less with respect to the area of the back surface of the semiconductor substrate 11.

On the other hand, as shown in FIGS. 3 and 4B, a plurality of pyramids 11B composed of four slopes are formed in a region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11. In FIG. 4B, the first slope SF1 and the second slope SF2 of the pyramid 11A described above are shown by broken lines for comparison.

Each slope of the pyramid 11B has a third slope SF3 with no bending point from the foot of the mountain 1B to the top of the mountain 3B. The slope of the third slope SF3 is gentler than the slope of the first slope SF1 described above.

As a result, the following relationship holds for the inclinations of the first slope SF1 and the second slope SF2 of the pyramid 11A.
Slope of the second slope SF2 <Slope of the first slope SF1

As shown in FIG. 5A, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the second intrinsicity of the pyramid 11A on the second slope SF2. The thickness of the semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) is the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the first slope SF1 of the pyramid 11A. Thicker than the film thickness of.

The thickness of the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the second slope SF2 of the pyramid 11A is set to the thickness of the second intrinsic semiconductor layer 33 and the second conductive on the first slope SF1 of the pyramid 11A. The value divided by the film thickness of the type semiconductor layer 35 (second semiconductor layer) is preferably 1.02 or more and 1.80 or less, more preferably 1.03 or more and 1.60 or less, still more preferably 1.05 or more. It is 1.40 or less.

Here, the film thickness of the semiconductor layer is the film thickness in the direction orthogonal to the slope of the pyramid of the semiconductor substrate 11, and the film thickness on the first slope SF1 is the midpoint PA1 of the mountain hem 1A and the bending point (middle) 2A. The film thickness on the second slope SF2 shall be measured at the positions of the peak 3A of the pyramid and the midpoint PA2 of the bending point (middle) 2A. When there are two or more bending points, the bending point closest to the mountaintop shall be used for film thickness measurement.

The back electrode type solar cell has a first semiconductor region and a second semiconductor region on the back surface, and each has a structure adjacent to each other. The existence of the boundary between the first semiconductor region and the second semiconductor region on the back surface is a structure peculiar to the back contact type solar cell, and the structure around the boundary region greatly affects the reliability of the solar cell, and the boundary region The reliability can be improved by having the structure of the pyramid A even if the area is small and having the film thickness ratio of the first slope SF1 and the second slope SF2.

On the other hand, as shown in FIG. 5B, in the region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, the third slope SF3 of the pyramid 11B does not have a bend like the pyramid 11A, so that the third Of the three points PB1, PB2, and PB3 that divide the mountain hem 1B and the mountaintop 3B into four equal parts on the slope SF3, the film thickness of the first point PB3 and the third point PB1 from the mountaintop 3B shall be measured.

As a result, the film thicknesses of the second semiconductor layers 35 and 33 on the first slope SF1 and the second slope SF2 of the pyramid 11A and the film thickness of the second semiconductor layer on the third slope SF3 of the pyramid 11B have the following relationship. It holds.
The thickness of the second semiconductor layers 35 and 33 of the second slope SF2 / the thickness of the second semiconductor layers 35 and 33 of the first slope SF1> The thickness of the second semiconductor layers 35 and 33 at the midpoint PB3 position / the film of the second semiconductor layers 35 and 33 at the midpoint PB1 position between the midpoint PB2 and the midpoint 1B of the peak 1B and the peak 3B of the third slope SF3. Thick

As shown in FIG. 3, the boundary region 8A on the side of the first region 7 in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37. At the same time, it may be located below the transparent electrode layer 28 side of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37.

(Solar cell manufacturing method)

The manufacturing method of the solar cell 1 according to the first embodiment will be described below with reference to FIGS. 6A to 6H. FIG. 6A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the first embodiment, and FIGS. 6B to 6D show the solar cell according to the first embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of. Further, FIG. 6E is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the first embodiment, and FIG. 6F is a diagram showing a second in the method for manufacturing a solar cell according to the first embodiment. It is a figure which shows the semiconductor layer formation process. Further, FIG. 6G is a diagram showing an electrode layer forming step in the solar cell manufacturing method according to the first embodiment, and FIG. 6H is a diagram showing an optical adjustment layer forming step in the solar cell manufacturing method according to the first embodiment. It is a figure which shows.

First, by performing anisotropic etching on at least the back surface side of the semiconductor substrate 11, a texture structure having a pyramid-shaped fine uneven structure is formed. Examples of the etching solution include an alkaline solution such as an aqueous solution of potassium hydroxide.

Next, as shown in FIG. 6A, for example, by using a CVD method (chemical vapor deposition method), the intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film 25Z are applied to the entire back surface side of the semiconductor substrate 11. Are laminated (film-formed) in order (first semiconductor layer material film forming step).

Further, for example, using the CVD method, the intrinsic semiconductor layer 13 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side. The order of film formation of the intrinsic semiconductor layer material film 23Z, the first conductive semiconductor layer material film 25Z, and the intrinsic semiconductor layer 13 is not limited.

Further, the intrinsic semiconductor layer 13 on the light receiving surface side may be formed in the subsequent second semiconductor layer material film forming step. In this case, the intrinsic semiconductor layer on the light receiving surface side formed at this stage may be removed in a later first semiconductor layer forming step. Alternatively, the intrinsic semiconductor layer may not be formed on the light receiving surface side at this stage, that is, there may be no intrinsic semiconductor layer forming step at this stage.

Next, for example, by using a CVD method, a lift-off layer (sacrificial layer) 41 is laminated (film formation) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the first conductive semiconductor layer material film 25Z. ) (Lift-off layer forming process). The lift-off layer 41 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

Next, as shown in FIGS. 6B to 6D, on the back surface side of the semiconductor substrate 11, the intrinsic semiconductor layer material film 23Z, the first conductive semiconductor layer material film 25Z, and the first conductive semiconductor layer material film 25Z in the second region 8 are used. By removing the lift-off layer 41, a patterned intrinsic semiconductor layer 23, a first conductive semiconductor layer 25, and a lift-off layer 41 are formed in the first region 7 (first semiconductor layer forming step).

Specifically, as shown in FIG. 6B, a pattern printing resist 90 is formed on the first region 7 on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side of the semiconductor substrate 11 by using a pattern printing method (. Resist forming process).

Pattern printing is not printing that goes through processes such as exposure and development after forming a resist film (non-patterned resist film) before patterning, as in the photolithography method, but screen printing or gravure printing. It means a printing method in which a patterned resist (printing material) is directly adhered to a resist-adhering surface, such as press printing such as, or ejection printing such as inkjet printing.

As described above, in the patterning of the first conductive semiconductor layer (first patterning), by using the pattern printing resist by the pattern printing method, it is compared with the case where the photoresist by the spin coating method (photolithography method) is used. As a result, the number of exposure and development steps can be reduced, and the solar cell manufacturing process can be simplified.

The pattern printing resist 90 is obtained by printing and curing a printing material containing a resin material and an inorganic material. At this time, a part of the printing material exudes from the printing material printed in the first region 7. The printing material may contain a solvent component, and the curing process may be cured by light as well as by heating. Further, in the curing process, the resin component does not necessarily have to be cured by cross-linking or the like, and the shape is maintained at room temperature due to the increase in viscosity due to the volatilization of the solvent, and the resin component has solvent resistance, that is, it has a function as a resist. Point to that.

FIG. 7A is an enlarged view of the boundary region VIA between the first region 7 and the second region 8 shown in FIG. 6B. As shown in FIG. 7A, the exuded resist material covers the valley portion of the pyramid 11A in the boundary region 8A (the exuded region of the pattern printing resist) on the first region 7 side in the second region 8.

More specifically, as shown in FIG. 8, the exuding film 90A formed by exuding the printing material is a pyramid 11A in the boundary region 8A (exuding region of the pattern printing resist) on the first region 7 side in the second region 8. It is formed so as to cover the first slope SF1 from the mountain hem 1A to the middle 2A.

Here, the film thickness of the pattern printing resist 90 is 3 μm or more and 50 μm or less, while the height of the pyramid 11A is 0.1 μm or more and 15 μm or less. The height of the pyramid is the height from the foot of the mountain to the top of the mountain, and the film thickness of the pattern printing resist 90 is the film thickness from the foot of the pyramid.

After that, as shown in FIG. 6C, the lift-off layer 41, the first conductive semiconductor layer material film 25Z, and the intrinsic semiconductor layer material film 23Z in the second region 8 are used as a mask with the pattern printing resist 90 and the exuding film 90A around the pattern printing resist 90 as a mask. The patterned intrinsic semiconductor layer 23, the first conductive semiconductor layer 25, and the lift-off layer 41 are formed in the first region 7 by etching.

Examples of the etching solution for the lift-off layer 41 include a mixed solution in which ozone is dissolved in hydrofluoric acid, or an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid. Examples of the etching solution for the p-type semiconductor layer material film include an acidic solution such as a mixed solution of ozone dissolved in hydrofluoric acid or a mixed solution of hydrofluoric acid and nitric acid, and an n-type semiconductor layer material. Examples of the etching solution for the film include an alkaline solution such as an aqueous potassium hydroxide solution.

FIG. 7B is an enlarged view of the boundary region VIIB between the first region 7 and the second region 8 shown in FIG. 6C. As shown in FIG. 7B, in the boundary region 8A (exuding region of the pattern printing resist) on the first region 7 side in the second region 8 coated with the exuding film 90A, the lift-off layer 41 and the first Most of the conductive semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z are etched.

4A and 8 described above correspond to an enlarged cross-sectional view of a part of IVA of the boundary region 8A on the side of the first region 7 in the second region 8 shown in FIG. 7B, and FIG. 4B described above is shown in FIG. 7B. It corresponds to an enlarged cross-sectional view of a part of IVB other than the boundary region 8A in the two regions 8.

As shown in FIGS. 4A and 8, in the boundary region 8A (exuding region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the exuding film 90A in the pyramid 11A. The hem side covered with is not etched, and the top side not covered with the exudate film 90A is etched.

As a result, each slope of the pyramid 11A has a first slope SF1 from the foot of the mountain 1A to the middle 2A and a second slope SF2 from the middle 2A to the summit 3A. The first slope SF1 and the second slope SF2 have different inclination angles with the bending point of the middle slope 2A as a boundary. The slope of the second slope SF2 is gentler than the slope of the first slope SF1.

In a cross section that passes through the mountaintop 3A and is orthogonal to the mountain hem 1A (that is, the cross section shown in FIGS. 4A and 8), the first virtual straight line L1 from the mountain hem 1A to the mountain top 3A and the mountain hem 1A to the middle 2A The minimum angle θ [°] formed by the second virtual straight line L2 up to the bending point is 8 <θ ≦ 30.

On the other hand, as shown in FIG. 4B, in the region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, the pyramid 11B is not covered with the exuding film 90A, so that the pyramid 11B is entirely etched. ..

As a result, each slope of the pyramid 11B has a third slope SF3 having no bending point from the foot of the mountain 1B to the top of the mountain 3B. In the pyramid 11B, since the slope is entirely etched, the slope of the third slope SF3 is steeper than the slope of the first slope SF1.

After that, as shown in FIG. 6D, the pattern print resist 90 is removed. Examples of the etching solution for the pattern printing resist 90 include an alkaline solution such as an aqueous potassium hydroxide solution.

As described above, in the patterning of the first conductive semiconductor layer 25 (first patterning), the cost of the solar cell can be reduced by adopting an inexpensive alkaline solution as the solution for removing the pattern printing resist.

In the first semiconductor layer forming step, the first conductive semiconductor layer 25 may be patterned so as to leave a part or all of the intrinsic semiconductor layer material film 23Z in the second region 8 on the back surface side of the semiconductor substrate 11. good.

Next, both sides of the semiconductor substrate 11 are cleaned (first cleaning step). In the first cleaning step, for example, ozone treatment is followed by hydrofluoric acid treatment. The hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid and another kind of acid (for example, hydrochloric acid in the first washing step).

Next, as shown in FIG. 6E, for example, by using the CVD method, the intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z are laminated in order on the entire surface of the back surface side of the semiconductor substrate 11 (film formation). (Second semiconductor layer material film forming step).

Next, as shown in FIG. 6F, the intrinsic semiconductor layer material film 33Z and the second conductive type in the first region 7 on the back surface side of the semiconductor substrate 11 by using the lift-off method using the lift-off layer (sacrificial layer). By removing the semiconductor layer material film 35Z, a patterned intrinsic semiconductor layer 33 and a second conductive semiconductor layer 35 are formed in the second region 8 (second semiconductor layer forming step).

Specifically, by removing the lift-off layer 41, the intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z on the lift-off layer 41 are removed, and the intrinsic semiconductor layer 33 and the second region 8 are removed. 2 Conductive semiconductor layer 35 is formed. As the removal solution for the lift-off layer 41, for example, an acidic solution such as hydrofluoric acid is used.

As described above, by adopting the lift-off method using the lift-off layer (sacrificial layer) in the patterning (second patterning) of the second conductive semiconductor layer 35, the manufacturing process of the solar cell can be simplified. ..

FIG. 7C is an enlarged cross-sectional view of the boundary region VIIC between the first region 7 and the second region 8 shown in FIG. 6G. FIG. 5A described above corresponds to an enlarged cross-sectional view of a part of VA of the boundary region 8A on the side of the first region 7 in the second region 8 shown in FIG. 7C, and FIG. 5B described above corresponds to the second region 8 shown in FIG. 7C. Corresponds to the enlarged cross-sectional view of a part of VB other than the boundary region 8A in.

As shown in FIGS. 7C and 5A, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the second intrinsicity in the second slope SF2 The thickness of the semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) is the thickness of the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the first slope SF1. Is formed thicker than. It is presumed that this is because the gentler the inclination, the thicker the film thickness of the semiconductor layers to be laminated.

In the first semiconductor layer forming step, when all of the intrinsic semiconductor layer material film 23Z in the second region 8 on the back surface side of the semiconductor substrate 11 remains, in the second semiconductor layer material film forming step and the second semiconductor layer forming step. The second conductive semiconductor layer 35 may be patterned without laminating (forming) the intrinsic semiconductor layer material film. Further, in the first semiconductor layer forming step, when a part of the intrinsic semiconductor layer material film 23Z in the second region 8 on the back surface side of the semiconductor substrate 11 remains, the second semiconductor layer material film forming step and the second semiconductor layer forming step Then, the intrinsic semiconductor layer material film may be laminated (film-formed) by the amount removed, and the intrinsic semiconductor layer and the second conductive semiconductor layer 35 may be patterned.

Next, as shown in FIG. 6G, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).

Specifically, for example, using a PVD method (physical vapor deposition method) such as a sputtering method, a transparent electrode layer material film is laminated (film-formed) on the entire back surface side of the semiconductor substrate 11. Then, the patterned transparent electrode layers 28 and 38 are formed by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste. As the etching solution for the transparent electrode layer material film, for example, hydrochloric acid or an aqueous ferric chloride solution is used.

Then, for example, by forming a metal electrode layer 29 on the transparent electrode layer 28 and forming a metal electrode layer 39 on the transparent electrode layer 38 by using, for example, a pattern printing method or a coating method, the first electrode layer 27 and The second electrode layer 37 is formed.

FIG. 3 described above corresponds to an enlarged cross-sectional view of the boundary region III between the first region 7 and the second region 8 shown in FIG. 6G. As shown in FIG. 3, the boundary region 8A on the side of the first region 7 in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37. At the same time, it may be located below the transparent electrode layer 28 side of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37.

Next, as shown in FIG. 6H, the optical adjustment layer 15 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side.
Through the above steps, the back electrode type solar cell 1 according to the first embodiment is completed.

As described above, according to the solar cell 1 of the first embodiment and the method for manufacturing the solar cell 1, the boundary region 8A on the first region 7 side in the second region 8, that is, the pyramid 11A between the transparent electrode layers 28 and 38. The thickness of the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the second slope SF2 is large. Thereby, the reliability of the solar cell 1 can be improved. Further, the passivation performance is improved, and the performance of the solar cell 1 (for example, Voc) can be improved.

Further, according to the solar cell 1 of the first embodiment and the manufacturing method thereof, the boundary region 8A on the first region 7 side in the second region 8 is the transparent electrode layer 28 and the second electrode layer 37 of the first electrode layer 27. It is located between the transparent electrode layer 38 and the transparent electrode layer 28 of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37. As a result, even if there are manufacturing variations, the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the second slope SF2 are located in the second region 8 between the transparent electrode layers 28 and 38. The pyramid 11A having a large film thickness is arranged, and the reliability and performance of the solar cell 1 can be improved.

Further, according to the method for manufacturing a solar cell of the first embodiment, in the patterning of the first conductive semiconductor layer (first patterning), by using a pattern printing resist by a pattern printing method, a solar cell manufacturing process can be performed. As described above, the reliability and performance of the solar cell 1 can be improved by utilizing the exuding film of the resin material in the pattern printing resist while simplifying the process.

In a flat semiconductor substrate that does not have a pyramid-shaped fine uneven structure (texture structure), even if a pattern printing resist by the pattern printing method is used, the resin material hardly exudes from the pattern printing resist. That is, the characteristics of the solar cell 1 of the first embodiment described above can be realized by combining the use of a semiconductor substrate having a pyramid-shaped fine uneven structure (texture structure) and the use of a pattern printing resist by a pattern printing method. ..

Further, according to the solar cell 1 of the first embodiment and the manufacturing method thereof, the exuding width of the resin material in the pattern printing resist can be adjusted by adjusting the size of the pyramid and / or the component / viscosity of the pattern printing resist. Can be adjusted. This facilitates an optimization design for the features of the solar cell 1 of the first embodiment described above.

(Modification example)
FIG. 9 is a cross-sectional view of the solar cell according to the modified example of the first embodiment, and is a cross-sectional view corresponding to the line II-II in FIG. Further, FIG. 10 is an enlarged cross-sectional view of the boundary region X between the first region 7 and the second region 8 shown in FIG.

As shown in FIGS. 9 and 10, the boundary region 8A on the first region 7 side in the second region 8 is between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37. It does not have to be located below the transparent electrode layer 38 of the second electrode layer 37. As a result, the thick pyramid 11A of the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the second slope SF2 is positioned under the transparent electrode layer 38 of the second electrode layer 37. Therefore, an increase in resistance can be suppressed, and a decrease in carrier extraction efficiency can be suppressed.

In the first embodiment described above, as shown in FIGS. 3 and 5A, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8, the first intrinsic property is obtained by under-etching. The form in which the semiconductor layer 23 and the first conductive type semiconductor layer 25 (first semiconductor layer) do not remain has been illustrated. In the second embodiment below, as shown in FIGS. 13 and 15A described later, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8, depending on the degree of underetching. , The mode in which the first intrinsic semiconductor layer 23 and the first conductive type semiconductor layer 25 (first semiconductor layer) remain on the first slope SF1 of the pyramid 11A will be illustrated.

[Second Embodiment]
(Solar cell)
FIG. 11 is a view of the solar cell according to the second embodiment as viewed from the back surface side. The solar cell 1 shown in FIG. 11 is a back electrode type (also referred to as a back contact type or back surface bonding type) solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.

FIG. 12 is a sectional view taken along line II-II of the solar cell of FIG. As shown in FIG. 12, the solar cell 1 is a heterojunction type solar cell. The solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and an optical adjustment layer 15 which are sequentially laminated on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side. Further, the solar cell 1 has the intrinsic semiconductor layer 23, which is sequentially laminated on a part of the back surface side (first region 7) which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface. 1 The conductive semiconductor layer 25 and the first electrode layer 27 are provided. Further, the solar cell 1 includes an intrinsic semiconductor layer 33, a second conductive semiconductor layer 35, and a second electrode layer 37, which are sequentially laminated on another part (second region 8) on the back surface side of the semiconductor substrate 11. .. Further, as will be described later, the region including both the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 in the vicinity of the boundary between the first region 7 and the second region 8 is referred to as the second region 8.
In the following, the intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 are also referred to as a first semiconductor layer, and the intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 are also referred to as a second semiconductor layer.

FIG. 13 is an enlarged cross-sectional view of the boundary region III between the first region 7 and the second region 8 shown in FIG. FIG. 14A is an enlarged cross-sectional view of the back surface of the semiconductor substrate 11 in a part VA of the boundary region 8A (exudation region of the pattern printing resist described later) on the first region 7 side in the second region 8 shown in FIG. FIG. 15A is an enlarged cross-sectional view of a semiconductor layer in a part VA of a boundary region 8A (exudation region of a pattern printing resist described later) on the side of the first region 7 in the second region 8 shown in FIG. 14B is an enlarged cross-sectional view of the back surface of the semiconductor substrate 11 in a part of VB other than the boundary region 8A in the second region 8 shown in FIG. 13, and FIG. 15B is a boundary in the second region 8 shown in FIG. It is an enlarged cross-sectional view of the semiconductor layer in a part VB other than a region 8A.

As shown in FIGS. 13 and 14A, the boundary region 8A (exudation region of the pattern print resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11 is composed of four slopes. A plurality of pyramids 11A are formed.

In a cross section that passes through the mountaintop 3A and is orthogonal to the mountain hem 1A (that is, the cross section shown in FIG. 14A), the first virtual straight line L1 from the mountain hem 1A to the mountain top 3A and the inflection point from the mountain hem 1A to the middle 2A The minimum angle θ [°] formed by the second virtual straight line L2 up to that point is 8 <θ ≦ 30.

On the other hand, as shown in FIGS. 13 and 14B, a plurality of pyramids 11B composed of four slopes are formed in a region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11. In FIG. 14B, the first slope SF1 and the second slope SF2 of the pyramid 11A described above are shown by broken lines for comparison.

As shown in FIG. 15A, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the first slope SF1 of the pyramid 11A has a position on the first slope SF1. The 1 intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 (first semiconductor layer), and the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) are laminated (formed) in this order. There is. The first intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 (first semiconductor layer) may be laminated on all of the first slope SF1 of the pyramid 11A, or at least a part (for example, the foot of the mountain 1A). It may be laminated on the side, that is, the valley side).

On the other hand, the first intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 (first semiconductor layer) are not laminated (formed) on the second slope SF2 of the pyramid 11A, and the second intrinsic semiconductor layer 33 and the second intrinsic semiconductor layer 33 and the second. Only the two conductive semiconductor layer 35 (second semiconductor layer) is laminated (formed).

Further, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the second intrinsic semiconductor layer 33 and the second intrinsic semiconductor layer 33 in the second slope SF2 of the pyramid 11A. The thickness of the two conductive semiconductor layer 35 (second semiconductor layer) is larger than the thickness of the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the first slope SF1 of the pyramid 11A. thick.

On the other hand, as shown in FIG. 15B, in the region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, the third slope SF3 of the pyramid 11B does not have a bend like the pyramid 11A, so that the third Of the three points PB1, PB2, and PB3 that divide the mountain hem 1B and the mountaintop 3B into four equal parts on the slope SF3, the film thickness of the first point PB3 and the third point PB1 from the mountaintop 3B shall be measured.

As shown in FIG. 13, the boundary region 8A on the first region 7 side in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37. At the same time, it may be located below the transparent electrode layer 28 side of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37.

(Solar cell manufacturing method)

The manufacturing method of the solar cell 1 according to the second embodiment will be described below with reference to FIGS. 16A to 16H. 16A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the second embodiment, and FIGS. 16B to 16D are views of the solar cell according to the second embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of. Further, FIG. 16E is a diagram showing a second semiconductor layer material film forming step in the solar cell manufacturing method according to the second embodiment, and FIG. 16F is a diagram showing a second semiconductor layer material film forming step in the solar cell manufacturing method according to the second embodiment. It is a figure which shows the semiconductor layer formation process. Further, FIG. 16G is a diagram showing an electrode layer forming step in the solar cell manufacturing method according to the second embodiment, and FIG. 16H is a diagram showing an optical adjustment layer forming step in the solar cell manufacturing method according to the second embodiment. It is a figure which shows.

Next, as shown in FIG. 16A, for example, by using a CVD method (chemical vapor deposition method), the intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film 25Z are applied to the entire back surface side of the semiconductor substrate 11. Are laminated (film-formed) in order (first semiconductor layer material film forming step).

Next, as shown in FIGS. 16B to 16D, the intrinsic semiconductor layer material film 23Z, the first conductive semiconductor layer material film 25Z, and the first conductive semiconductor layer material film 25Z in the second region 8 are used on the back surface side of the semiconductor substrate 11 using the pattern printing resist. By removing the lift-off layer 41, a patterned intrinsic semiconductor layer 23, a first conductive semiconductor layer 25, and a lift-off layer 41 are formed in the first region 7 (first semiconductor layer forming step).

Specifically, as shown in FIG. 16B, a pattern printing resist 90 is formed on the first region 7 on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side of the semiconductor substrate 11 by using a pattern printing method (. Resist forming process).

FIG. 17A is an enlarged view of the boundary region VIA between the first region 7 and the second region 8 shown in FIG. 16B. As shown in FIG. 17A, the exuded resist material covers the valley portion of the pyramid 11A in the boundary region 8A (the exuded region of the pattern printing resist) on the first region 7 side in the second region 8.

More specifically, as shown in FIG. 18, the exuding film 90A formed by exuding the printing material is a pyramid 11A in the boundary region 8A (exuding region of the pattern printing resist) on the first region 7 side in the second region 8. It is formed so as to cover the first slope SF1 from the mountain hem 1A to the middle 2A.

Then, as shown in FIG. 16C, the lift-off layer 41, the first conductive semiconductor layer material film 25Z, and the intrinsic semiconductor layer material film 23Z in the second region 8 are used as a mask with the pattern printing resist 90 and the exuding film 90A around the pattern printing resist 90 as a mask. The patterned intrinsic semiconductor layer 23, the first conductive semiconductor layer 25, and the lift-off layer 41 are formed in the first region 7 by etching.

FIG. 17B is an enlarged view of the boundary region VIIB between the first region 7 and the second region 8 shown in FIG. 16C. As shown in FIG. 17B, in the boundary region 8A (the exuding region of the pattern printing resist) on the first region 7 side in the second region 8, the first slope SF1 of the pyramid 11A coated with the exuding film 90A has a surface SF1. The first intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 (first semiconductor layer) remain.

14A and 18 described above correspond to an enlarged cross-sectional view of a part of IVA of the boundary region 8A on the side of the first region 7 in the second region 8 shown in FIG. 17B, and FIG. 14B described above is shown in FIG. 17B. It corresponds to an enlarged cross-sectional view of a part of IVB other than the boundary region 8A in the two regions 8.

As shown in FIGS. 14A and 18, in the boundary region 8A (exuding region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the exuding film 90A in the pyramid 11A. The hem side covered with is not etched, and the top side not covered with the exudate film 90A is etched.

In a cross section that passes through the mountaintop 3A and is orthogonal to the mountain hem 1A (that is, the cross section shown in FIGS. 14A and 18), the first virtual straight line L1 from the mountain hem 1A to the mountain top 3A and the mountain hem 1A to the middle 2A The minimum angle θ [°] formed by the second virtual straight line L2 up to the bending point is 8 <θ ≦ 30.

On the other hand, as shown in FIG. 14B, in the region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, the pyramid 11B is not covered with the exuding film 90A, so that the pyramid 11B is entirely etched. ..

As a result, each slope of the pyramid 11B has a third slope SF3 having no bending point from the foot of the mountain 1B to the top of the mountain 3B. In the pyramid 11B, since the slope is entirely etched, the slope of the third slope SF3 is steeper than the slope of the second slope SF2.

Further, the lift-off layer 41, the first intrinsic semiconductor layer 23, and the first conductive semiconductor layer 25 (first semiconductor layer) remain on the first slope SF1 of the pyramid 11A. The lift-off layer 41, the first intrinsic semiconductor layer 23, and the first conductive semiconductor layer 25 (first semiconductor layer) may remain on all of the first slope SF1 of the pyramid 11A, or at least a part (for example, for example). It may remain on the mountain hem 1A side, that is, the valley side).

After that, as shown in FIG. 16D, the pattern print resist 90 is removed. Examples of the etching solution for the pattern printing resist 90 include an alkaline solution such as an aqueous potassium hydroxide solution.

Next, clean both sides of the semiconductor substrate 11X (first cleaning step). In the first cleaning step, for example, ozone treatment is followed by hydrofluoric acid treatment. The hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid and another kind of acid (for example, hydrochloric acid in the first washing step).

Next, as shown in FIG. 16E, for example, using the CVD method, the intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z are laminated in order on the entire surface of the back surface side of the semiconductor substrate 11 (film formation). (Second semiconductor layer material film forming step).

Next, as shown in FIG. 16F, the intrinsic semiconductor layer material film 33Z and the second conductive type in the first region 7 on the back surface side of the semiconductor substrate 11 by using the lift-off method using the lift-off layer (sacrificial layer). By removing the semiconductor layer material film 35Z, a patterned intrinsic semiconductor layer 33 and a second conductive semiconductor layer 35 are formed in the second region 8 (second semiconductor layer forming step).

FIG. 17C is an enlarged cross-sectional view of the boundary region VIIC between the first region 7 and the second region 8 shown in FIG. 16G. FIG. 15A described above corresponds to an enlarged cross-sectional view of a part of VA of the boundary region 8A on the side of the first region 7 in the second region 8 shown in FIG. 17C, and FIG. 15B described above corresponds to the second region 8 shown in FIG. 17C. Corresponds to the enlarged cross-sectional view of a part of VB other than the boundary region 8A in.

As shown in FIGS. 17C and 15A, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the first slope SF1 of the pyramid 11A Is a stack (formation) of a first intrinsic semiconductor layer 23 and a first conductive semiconductor layer 25 (first semiconductor layer), and a second intrinsic semiconductor layer 33 and a second conductive semiconductor layer 35 (second semiconductor layer) in order. ). The first intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 (first semiconductor layer) may be laminated on all of the first slope SF1 of the pyramid 11A, or at least a part (for example, the foot of the mountain 1A). It may be laminated on the side, that is, the valley side).

Further, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the second intrinsic semiconductor layer 33 and the second conductive type on the second slope SF2 The thickness of the semiconductor layer 35 (second semiconductor layer) is formed to be thicker than the thickness of the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the first slope SF1. It is presumed that this is because the gentler the inclination, the thicker the film thickness of the semiconductor layers to be laminated.

Next, as shown in FIG. 16G, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).

FIG. 13 described above corresponds to an enlarged cross-sectional view of the boundary region III between the first region 7 and the second region 8 shown in FIG. 16G. As shown in FIG. 13, the boundary region 8A on the first region 7 side in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37. At the same time, it may be located below the transparent electrode layer 28 side of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37.

Next, as shown in FIG. 16H, the optical adjustment layer 15 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side.
Through the above steps, the back electrode type solar cell 1 according to the second embodiment is completed.

As described above, according to the solar cell 1 of the second embodiment and the method for manufacturing the solar cell 1, the boundary region 8A on the first region 7 side in the second region 8, that is, the pyramid 11A between the transparent electrode layers 28 and 38. The thickness of the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the second slope SF2 is large. Further, in the first slope SF1 of the pyramid 11A in the boundary region 8A on the first region 7 side in the second region 8, that is, between the transparent electrode layers 28 and 38, the first intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 Since the (first semiconductor layer) remains, the first intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 (first semiconductor layer), the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor) The total film thickness with the layer) is thick. Thereby, the reliability of the solar cell 1 can be improved. Further, the passivation performance is improved, and the performance of the solar cell 1 (for example, Voc) can be improved.

Further, according to the solar cell 1 of the second embodiment and the manufacturing method thereof, the boundary region 8A on the first region 7 side in the second region 8 is the transparent electrode layer 28 and the second electrode layer 37 of the first electrode layer 27. It is located between the transparent electrode layer 38 and the transparent electrode layer 28 of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37. As a result, even if there are manufacturing variations, the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the second slope SF2 are located in the second region 8 between the transparent electrode layers 28 and 38. The first intrinsic semiconductor layer 23, the first conductive semiconductor layer 25 (first semiconductor layer), the second intrinsic semiconductor layer 33, and the second conductive semiconductor layer 35 (the first) on the first slope SF1 are thick. A pyramid 11A having a large total thickness with the two semiconductor layers) is arranged, and the reliability and performance of the solar cell 1 can be improved.

Further, according to the method for manufacturing a solar cell of the second embodiment, in the patterning of the first conductive semiconductor layer (first patterning), by using a pattern printing resist by a pattern printing method, a solar cell manufacturing process can be performed. As described above, the reliability and performance of the solar cell 1 can be improved by utilizing the exuding film of the resin material in the pattern printing resist while simplifying the process.

In a flat semiconductor substrate that does not have a pyramid-shaped fine uneven structure (texture structure), even if a pattern printing resist by the pattern printing method is used, the resin material hardly exudes from the pattern printing resist. That is, the characteristics of the solar cell 1 of the second embodiment described above can be realized by combining the use of a semiconductor substrate having a pyramid-shaped fine uneven structure (texture structure) and the use of a pattern printing resist by a pattern printing method. ..

Further, according to the solar cell 1 of the second embodiment and the manufacturing method thereof, the exuding width of the resin material in the pattern printing resist can be adjusted by adjusting the size of the pyramid and / or the component / viscosity of the pattern printing resist. Can be adjusted. By protecting the vicinity of the mountain hem of the pyramid in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the semiconductor layer is formed even after the first semiconductor layer is patterned. The thickness of the semiconductor layer at the foot of the mountain, which tends to be thin, is increased to improve reliability, and the first semiconductor layer laminated on the mountaintop is removed, resulting in a large resistance loss from the mountaintop. The optimum structure can be used so that the current can be recovered without any trouble. This facilitates an optimization design for the features of the solar cell 1 of the second embodiment described above.

(Modification example)
FIG. 19 is a cross-sectional view of the solar cell according to the modified example of the second embodiment, and is a cross-sectional view corresponding to the line II-II in FIG. Further, FIG. 20 is an enlarged cross-sectional view of the boundary region X between the first region 7 and the second region 8 shown in FIG.

As shown in FIGS. 19 and 20, the boundary region 8A on the first region 7 side in the second region 8 is between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37. It does not have to be located below the transparent electrode layer 38 of the second electrode layer 37. As a result, the thickness of the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the second slope SF2 is thick under the transparent electrode layer 38 of the second electrode layer 37, and the second is The total thickness of the first intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 (first semiconductor layer) and the second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 (second semiconductor layer) on the slope SF1. Since the thick pyramid 11A is not located, an increase in resistance can be suppressed, and a decrease in carrier extraction efficiency can be suppressed.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made. For example, in the above-described embodiment, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the middle part from the mountain hem 1A to the mountain peak 3A. In 2A, a form having a pyramid 11A having one inflection point was illustrated. However, the present invention is not limited to this, and in the boundary region (exudation region of the pattern printing resist) on the first region side in the second region on the back surface side of the semiconductor substrate, two or more from the foot of the mountain to the top of the mountain. It may be in the form of having a pyramid having an inflection point.

In this case, each slope of the pyramid has three or more slopes with different inclination angles from the foot of the mountain to the top of the mountain. As a result, in the boundary region 8A (exudation region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the second intrinsic semiconductor layer 33 and the second conductive semiconductor on each slope. The film thickness of the layer 35 (second semiconductor layer) is different.

1

Solar cell

1A, 1B Mountain hem 2A Mountainside 3A, 3B Mountain peak 7

1st area

7b, 8b

Bus bar part

7f, 8f Finger part 8 2nd area 8A Boundary area in 2nd area 11

Semiconductor substrate

11A, 11B Pyramid 13 Intrinsic semiconductor layer 15

Optical adjustment layer

23,33

Intrinsic semiconductor layer

23Z, 33Z Intrinsic semiconductor layer Material film 25 First conductive semiconductor layer 25Z First conductive semiconductor layer Material film 27

First electrode layer

28,38 Transparent electrode layer 28Z Transparent electrode

layer Material film

29, 39 Metal electrode layer 35 2nd conductive semiconductor layer 35Z 2nd conductive semiconductor layer Material film 37 2nd electrode layer 41 Lift-off layer 90 Pattern printing resist 90A Exud film L1 1st virtual straight line L2 2nd virtual straight line SF1 1st 1 slope SF2 2nd slope SF3 3rd slope

Claims

A semiconductor substrate, a first semiconductor layer and a first electrode layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the other of the semiconductor substrate. A back electrode type solar cell including a second semiconductor layer and a second electrode layer that are sequentially laminated in a second region that is another part of the main surface side.
A texture structure having a pyramid-shaped fine uneven structure is formed on at least the other main surface side of the semiconductor substrate.
In the boundary region on the first region side in the second region on the other main surface side of the semiconductor substrate,
The slope of the pyramid has a first slope from the foot of the mountain to the middle of the mountain and a second slope from the middle of the mountain to the top of the mountain.
The slope of the second slope is gentler than the slope of the first slope.
A first virtual straight line from the foot of the mountain to the top of the mountain and a second virtual straight line from the foot of the mountain to the inflection point of the middle of the mountain in a cross section orthogonal to the foot of the mountain. The minimum angle θ [°] to be formed is 8 <θ ≦ 30.
The pyramid occupies 0.01% or more and 50% or less of the area of the other main surface.
The film thickness of the second semiconductor layer on the second slope is thicker than the film thickness of the second semiconductor layer on the first slope.
Solar cell.
A semiconductor substrate, a first semiconductor layer and a first electrode layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the other of the semiconductor substrate. A back electrode type solar cell including a second semiconductor layer and a second electrode layer that are sequentially laminated in a second region that is another part of the main surface side.
A texture structure having a pyramid-shaped fine uneven structure is formed on at least the other main surface side of the semiconductor substrate.
In the boundary region on the first region side in the second region on the other main surface side of the semiconductor substrate,
The slope of the pyramid has a first slope from the foot of the mountain to the middle of the mountain and a second slope from the middle of the mountain to the top of the mountain.
The slope of the second slope is gentler than the slope of the first slope.
The first semiconductor layer and the second semiconductor layer are laminated in this order on at least a part of the first slope.
The film thickness of the second semiconductor layer on the second slope is thicker than the film thickness of the second semiconductor layer on the first slope.
Solar cell.
The solar cell according to claim 1 or 2, wherein the boundary region is located between the first electrode layer and the second electrode layer and is not located below the second electrode layer.
The solar cell according to claim 1 or 2, wherein the boundary region is located between the first electrode layer and the second electrode layer, and below the first electrode layer side of the second electrode layer.
A semiconductor substrate, a first semiconductor layer and a first electrode layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the other of the semiconductor substrate. A method for manufacturing a back electrode type solar cell including a second semiconductor layer and a second electrode layer which are sequentially laminated in a second region which is another part of the main surface side.
A step of forming a texture structure having a pyramid-shaped fine uneven structure on at least the other main surface side of the semiconductor substrate.
A first semiconductor layer material film forming step of forming a material film of the first semiconductor layer on the other main surface side of the semiconductor substrate,
A resist forming step of forming a resist on the material film of the first semiconductor layer in the first region,
By removing the material film of the first semiconductor layer in the second region using the resist as a mask, a patterned first semiconductor layer is formed in the first region, and the resist is removed. 1 Semiconductor layer forming process and
A second semiconductor layer forming step of forming the patterned second semiconductor layer in the second region,
Including
In the resist forming step, the resist is formed in the first region by printing and curing the printing material containing the resin material by using the pattern printing method, and the first region side in the second region is formed. An exuding film formed by exuding the printing material is formed on the first slope from the mountain hem to the middle of the pyramid in the boundary region (exuding region of the printing resist).
In the first semiconductor layer forming step, the material film of the first semiconductor layer is etched with the resist and the exuding film on the periphery thereof as a mask, so that the boundary region on the first region side in the second region is formed. ,
The slope of the pyramid has a first slope from the foot of the mountain to the middle of the mountain and a second slope from the middle of the mountain to the top of the mountain.
The slope of the second slope is gentler than the slope of the first slope.
A first virtual straight line from the foot of the mountain to the top of the mountain and a second virtual straight line from the foot of the mountain to the inflection point of the middle of the mountain in a cross section orthogonal to the foot of the mountain. The minimum angle θ [°] to be formed is 8 <θ ≦ 30.
The pyramid occupies 0.01% or more and 50% or less of the area of the other main surface.
Forming the pyramid
In the second semiconductor layer forming step, the film thickness on the second slope is thicker than the film thickness on the first slope in the boundary region (print resist exuding region) on the first region side in the second region. Forming the second semiconductor layer,
How to manufacture solar cells.
A semiconductor substrate, a first semiconductor layer and a first electrode layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the other of the semiconductor substrate. A method for manufacturing a back electrode type solar cell including a second semiconductor layer and a second electrode layer which are sequentially laminated in a second region which is another part of the main surface side.
A step of forming a texture structure having a pyramid-shaped fine uneven structure on at least the other main surface side of the semiconductor substrate.
A first semiconductor layer material film forming step of forming a material film of the first semiconductor layer on the other main surface side of the semiconductor substrate,
A resist forming step of forming a resist on the material film of the first semiconductor layer in the first region,
By removing the material film of the first semiconductor layer in the second region using the resist as a mask, a patterned first semiconductor layer is formed in the first region, and the resist is removed. 1 Semiconductor layer forming process and
A second semiconductor layer forming step of forming the patterned second semiconductor layer in the second region,
Including
In the resist forming step, the resist is formed in the first region by printing and curing the printing material containing the resin material by using the pattern printing method, and the first region side in the second region is formed. On the first slope from the mountain hem to the middle of the pyramid in the boundary region of the above, an exudate film formed by exuding the printing material is formed.
In the first semiconductor layer forming step, the material film of the first semiconductor layer is etched with the resist and the exuding film on the periphery thereof as a mask, so that the boundary region on the first region side in the second region is formed. ,
The slope of the pyramid has a first slope from the foot of the mountain to the middle of the mountain and a second slope from the middle of the mountain to the top of the mountain.
The slope of the second slope is gentler than the slope of the first slope.
The first semiconductor layer is laminated on at least a part of the first slope.
Forming the pyramid
In the second semiconductor layer forming step, the second semiconductor layer is formed on the first semiconductor layer on the first slope in the boundary region on the first region side in the second region, and the second slope is formed. To form the second semiconductor layer whose film thickness is thicker than the film thickness on the first slope.
How to manufacture solar cells.
An electrode layer forming step of forming the first electrode layer in the first region and forming the second electrode layer in the second region is further provided.
In the electrode layer forming step, the first electrode layer and the first electrode layer and the boundary region are located between the first electrode layer and the second electrode layer and not below the second electrode layer. Forming the second electrode layer,
The method for manufacturing a solar cell according to claim 5 or 6.
An electrode layer forming step of forming the first electrode layer in the first region and forming the second electrode layer in the second region is further provided.
In the electrode layer forming step, the first electrode layer is located between the first electrode layer and the second electrode layer and below the first electrode layer side of the second electrode layer. Forming one electrode layer and the second electrode layer,
The method for manufacturing a solar cell according to claim 5 or 6.
After the first semiconductor layer material film forming step, a lift-off layer forming step of forming a lift-off layer on the material film of the first semiconductor layer is further provided.
In the resist forming step, the resist is formed on the lift-off layer in the first region.
In the first semiconductor layer forming step, the lift-off layer patterned in the first region is removed by removing the material film of the lift-off layer and the first semiconductor layer in the second region using the resist as a mask. The layer and the first semiconductor layer are formed, the resist is removed, and the film is removed.
Prior to the second semiconductor layer forming step, a second semiconductor layer material film forming step of forming the material film of the second semiconductor layer on the lift-off layer in the first region and on the second region is further provided. ,
In the second semiconductor layer forming step, the material film of the second semiconductor layer in the first region is removed by removing the lift-off layer, and the second semiconductor layer patterned in the second region. Form,
The method for manufacturing a solar cell according to any one of claims 5 to 8.