TWI815682B - High efficiency light emitting diode driver circuit and control method thereof - Google Patents

Abstract

A light emitting diode (LED) driver circuit is configured to drive plural LED beads which are respectively coupled to m scan-line nodes and n data-line nodes, wherein m and n are both integers greater than or equal to 1. During a driving stage, each of the LED beads is controlled to emit light according to the electrical characteristics on the corresponding scan-line node and on the corresponding data-line node where the LED bead is coupled to. The LED driver circuit includes: a power saving control circuit which includes a storage capacitor; a pre-discharge circuit configured to pre-discharge the charges on the m scan-line nodes to the storage capacitor during a pre-discharge stage; and a pre-charge circuit configured to pre-charge the n data-line nodes by the charges stored in the storage capacitor during a pre-charge stage.

Description

High-efficiency light-emitting diode drive circuit and control method thereof

The present invention relates to a light-emitting diode driving circuit, in particular to a high-efficiency light-emitting diode driving circuit that can reduce energy consumption.

The prior technologies related to this case include: US8659514B2, US9552794B2, US9818338B2, US10692422B2.

Please refer to FIG. 1 , which is a schematic diagram of a light emitting diode driving circuit in the prior art. As shown in FIG. 1 , a prior art light emitting diode (LED, Light Emitting Diode) driving circuit 1000 includes a plurality of LED lamp beads, a precharge circuit 110 , a predischarge circuit 120 , a data line control circuit 130 and a scan line control circuit 140 . The plurality of LED lamp beads are arranged in m rows and n columns, and are respectively coupled to m scan lines and n data lines. In the driving stage, the scan line control circuit 140 provides power to the m scan lines in sequence, and the data line control circuit 130 provides corresponding drive currents to the n data lines, so that the plurality of LED lamp beads generate corresponding brightness in sequence. Due to the scanning Both the line and the data line have parasitic capacitance, so the residual charge on the parasitic capacitance will cause a ghost image. In order to avoid the generation of ghosts, the prior art uses precharge circuits 110 and predischarge circuits 120 to precharge and predischarge data lines and scan lines respectively in the precharge stage and predischarge stage, thereby eliminating ghosts.

In the above-mentioned prior art, the precharge circuit 110 includes n amplifiers 11 and operates corresponding to n data lines. The following description takes one of the amplifiers 11 as an example. As shown in Figure 1, the amplifier 11 is used in the precharge stage. Through the precharge path Pc01, the power supply Vs (high power supply) of the amplifier 11 is precharged to the corresponding data line, thereby adjusting the voltage of the corresponding data line to Reference voltage Vrc. The pre-discharge circuit 120 includes an amplifier 12 for discharging the charges on the m scan lines to the ground potential (low power end of the amplifier 12) through the pre-discharge path Pdc01 during the pre-discharge stage, thereby reducing the voltage of the m scan lines. Adjust to the reference voltage Vrdc.

Although the above-mentioned prior art can avoid the generation of ghost images, its disadvantage is that an additional power supply is required for precharging, and the remaining charge is directly discharged to the ground potential during pre-discharge, thus causing additional energy consumption.

In view of this, the present invention aims at the above-mentioned shortcomings of the prior art and proposes an LED driving circuit that can store pre-discharged charges and provide the required charges for pre-charging, thereby saving energy and improving efficiency.

In one aspect, the present invention provides a light emitting diode (LED, Light Emitting Diode) driving circuit for driving a plurality of LED lamp beads (beads), wherein the plurality of LED lamp beads are respectively coupled to m scanning lines and n data lines, where n and m are both integers greater than or equal to 1. In a driving stage, each LED lamp bead is controlled according to the electrical characteristics of the corresponding coupled scan line and the corresponding coupled data line. To emit light, the LED drive circuit includes: an energy-saving control circuit including a storage capacitor; a pre-discharge circuit for pre-discharging the charges on the m scanning lines to the storage capacitor in a pre-discharge stage; and a pre-charge The circuit is used to precharge the n data lines with the charge stored in the storage capacitor in a precharge stage.

In one embodiment, the LED driving circuit further includes: a scan line control circuit for sequentially providing a power supply to the m scan lines in a driving stage; and a data line control circuit for the In the driving stage, corresponding driving currents are provided to the n data lines according to the corresponding data, thereby causing the corresponding LED lamp beads to emit corresponding brightness.

In one embodiment, the pre-discharge circuit includes a discharge amplifier, which pre-discharges and adjusts the voltage on the m scan lines to a pre-discharge voltage during the pre-discharge stage; the pre-charge circuit includes a charge amplifier, which In the precharge stage, the voltages on the n data lines are precharged and adjusted to a precharge voltage; a low power end of the discharge amplifier is coupled to the storage capacitor, and the voltage of the storage capacitor is used as the discharge amplifier Low power supply, thereby pre-discharging the charges on the m scan lines to the storage capacitor; wherein a high power supply terminal of the charging amplifier is coupled to the storage capacitor, and the voltage of the storage capacitor is used as the high power supply of the charging amplifier , thereby precharging n data lines with the charge stored in the storage capacitor.

In one embodiment, the energy-saving control circuit further includes a first clamp circuit and a second clamp circuit, wherein the first clamp circuit is used to clamp the voltage of the storage capacitor so that it is not lower than a first Clamping voltage, wherein the second clamping circuit is used to clamp the voltage of the storage capacitor so that it is not higher than a second clamping voltage, wherein the first clamping voltage is lower than the second clamping voltage.

In one embodiment, the first clamping circuit includes: a first diode forwardly coupled between a first reference voltage and the storage capacitor, wherein the first clamping voltage is the first reference The difference between the voltage and the forward conduction voltage of the first diode; wherein the second clamp circuit includes: a second diode forwardly coupled between the storage capacitor and the first reference voltage, The second clamping voltage is the sum of the first reference voltage and the forward conducting voltage of the second diode.

In one embodiment, the first clamping circuit includes: a first transistor coupled to the storage capacitor; and a first amplifier configured to operate according to a difference between the first clamping voltage and the voltage of the storage capacitor. value to control the first transistor to clamp the voltage of the storage capacitor so that it is not lower than the first clamping voltage; wherein the second clamping circuit includes: a second transistor coupled to the storage capacitor ; and a second amplifier for controlling the second transistor according to the difference between the second clamping voltage and the voltage of the storage capacitor to clamp the voltage of the storage capacitor so that it is no higher than the second clamping voltage; bit voltage.

In one embodiment, the pre-discharge circuit further includes a third clamping circuit for clamping an amplifier power supply voltage between a high power terminal of the discharge amplifier and the low power terminal of the discharge amplifier so that no higher than a third clamping voltage.

In one embodiment, the third clamp circuit includes: a third transistor coupled between the storage capacitor and the low power terminal of the discharge amplifier; and a voltage offset circuit coupled to the third Between one of the control terminals of the three transistors and the high and low power terminals of the discharge amplifier, it is used to control the third transistor to clamp the power supply voltage of the amplifier so that it is not higher than the third clamping voltage, wherein the third clamp The bit voltage is related to an offset voltage of the voltage offset circuit and a conduction threshold of the third transistor.

In one embodiment, the maximum rated voltage of the third transistor is higher than the maximum rated voltage of the discharge amplifier, and/or the maximum rated voltage of the third transistor is higher than the maximum rated voltage of the energy-saving control circuit. Rated voltage.

In one embodiment, the energy-saving control circuit further includes: a current balancing circuit for controlling a bias current required by the precharge circuit based on the difference between the voltage of the storage capacitor and a second reference voltage, and thereby The static current consumption of the precharge circuit is adjusted so that in a steady state, the charges used to pre-discharge the voltages on the m scan lines and the charges used to precharge the voltages on the n data lines are controlled to be balanced.

In one embodiment, the current balancing circuit includes: a comparison circuit for comparing the voltage of the storage capacitor with the second reference voltage to generate a comparison result; an integrating circuit for controlling an upper voltage regulator according to the comparison result. a pull-down current source and a pull-down current source, thereby generating an integrated voltage on an integrating capacitor; and a bias current generating circuit for generating the bias current according to the integrated voltage, wherein the bias current is related to the integral voltage.

In another aspect, the present invention provides a control method for controlling an LED (Light Emitting Diode) driving circuit, wherein the LED driving circuit includes a plurality of LED beads, wherein the plurality of LED lamps The beads are respectively coupled to m scan lines and n data lines, where n and m are both integers greater than or equal to 1. The control method includes: in a driving stage, controlling each LED lamp bead according to the corresponding coupled The scan lines emit light according to the electrical characteristics of the corresponding coupled data lines; in a pre-discharge stage, the charges on the m scan lines are pre-discharged to a storage capacitor; and in a pre-charge stage, the charges stored in the storage capacitor are The charge precharges the n data lines.

In one embodiment, the control method further includes: in a driving stage, sequentially providing a power supply to the m scan lines; and in the driving stage, providing respective power supplies to the n data lines according to a corresponding data. The corresponding driving current causes the corresponding LED lamp beads to emit corresponding brightness.

In one embodiment, the control method further includes: clamping the voltage of the storage capacitor so that it is not lower than a first clamping voltage; and clamping the voltage of the storage capacitor so that it is not higher than a second clamping voltage. ; wherein the first clamping voltage is lower than the second clamping voltage.

In one embodiment, the control method further includes: controlling a bias current according to the difference between the voltage of the storage capacitor and a reference voltage to adjust the static current consumption of a precharge circuit, thereby achieving a stable In this state, the charge of pre-discharging the voltage on the m scan lines and the charge of pre-charging the voltage on the n data lines are controlled to be balanced; the precharge circuit is used in the precharge stage to use the storage capacitor The stored charge is a circuit that precharges the n data lines.

In one embodiment, the step of controlling the bias current includes: comparing the voltage of the storage capacitor with the reference voltage to generate a comparison result; and controlling a pull-up current source and a pull-down current source according to the comparison result, thereby An integrated voltage is generated in an integrating capacitor; and the bias current is generated according to the integrated voltage, wherein the bias current is related to the integrated voltage.

The following will be described in detail through specific embodiments to make it easier to understand the purpose, technical content, characteristics and achieved effects of the present invention.

The diagrams in the present invention are schematic and are mainly intended to represent the coupling relationship between circuits and the relationship between signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale. For the sake of clear explanation, many practical details will be explained in the following description, but this is not intended to limit the patentable scope of the present invention.

Please refer to FIG. 2A. FIG. 2A is a block diagram of a light emitting diode driving circuit according to an embodiment of the present invention. In one embodiment, the light emitting diode (LED, Light Emitting Diode) driving circuit 2000 of FIG. 2A includes: a pre-power supply circuit 40, a scan line control circuit 50 and a data line control circuit 60. In one embodiment, the main control circuit 20 controls the LED driving circuit 2000 to drive a plurality of LED lamp beads, wherein the plurality of LED lamp beads are configured in m rows and n columns, and m and n are both greater than or equal to 1. integer. In the embodiment of FIG. 2A , the plurality of LED lamp beads are configured as diodes D11 (column 1, row 1) to diodes Dmn (column m, row n). In one embodiment, a plurality of LED lamp beads are respectively coupled to m scan lines and n data lines. In the driving stage, each LED lamp bead is configured according to the electrical characteristics of the corresponding coupled scan line and the corresponding coupled data line. As for controlled light emission, for example, the diode D11 is controlled to emit light according to the electrical characteristics on the scan line SL1 and the data line DL1. The above-mentioned columns and rows are only examples of a two-dimensional arrangement and are not intended to limit the arrangement of the physical directions of the LED lamp beads within the maximum patent scope claimed in this case.

In one embodiment, as shown in FIG. 2A , the scan line control circuit 50 includes a gate drive circuit 51 and m switches (switches S1 to Sm). In this embodiment, the switches S1 to Sm are configured as P-type. Metal oxide semiconductor (MOS) components. In one embodiment, during the driving phase, the gate driving circuit 51 is used to generate the scan signals Scan1 ~ the scan signals Scanm according to the control of the main control circuit 20 , and the scan signals Scan1 ~ the scan signals Scanm are used to control the switches S1 ~ the switches Sm accordingly. Sequential conduction, thereby providing supply power VLED to m scan lines in sequence. In one embodiment, the data line control circuit 60 is used in the driving stage to provide corresponding driving currents to the n data lines according to the corresponding data provided by the main control circuit 20 and stored in the memory circuit 30, thereby So that the corresponding LED lamp beads emit corresponding brightness. Specifically, in this embodiment, when the power supply VLED is supplied to the scan line corresponding to the LED lamp bead, and the data line corresponding to the LED lamp bead is driven by the driving current, the LED lamp bead will be conductive in the forward direction, and according to The intensity of the driving current emits light with corresponding brightness.

Please continue to refer to Figure 2A. Since each scan line has a parasitic capacitance, such as the parasitic capacitance Cpp1 ~ parasitic capacitance Cppm shown in Figure 2A, and each data line also has a parasitic capacitance, such as the parasitic capacitance Cpn1 ~ parasitic capacitance shown in Figure 2A The capacitance Cpnn, therefore when the scan line control circuit 50 and the data line control circuit 60 respectively control the corresponding LED lamp beads to emit light, the residual charge of the parasitic capacitance may cause the non-corresponding LED lamp beads to temporarily conduct forward and emit light, thus causing ghosts. shadow phenomenon. In one embodiment, the pre-power supply circuit 40 includes an energy-saving control circuit 410, a pre-discharge circuit 420 and a pre-charge circuit 430. In one embodiment, the energy-saving control circuit 410 includes a storage capacitor Cs. The pre-discharge circuit 420 is used in the pre-discharge stage to pre-discharge the charges on the m scan lines to the storage capacitor Cs through the pre-discharge current Ipdc. The pre-charge circuit 430 It is used in the precharge stage to precharge n data lines with the charge stored in the storage capacitor Cs through the precharge current Ipc, thereby eliminating ghosts. It should be noted that the present invention uses the storage capacitor Cs to store the pre-discharged charge and provide the charge required for pre-charging, so it can achieve energy saving and high efficiency.

Please refer to FIG. 2A and FIG. 2B at the same time. FIG. 2B is a partial operation waveform diagram corresponding to the light emitting diode driving circuit of FIG. 2A. It should be noted that FIG. 2B only shows the operation waveforms VS1 and VS2 corresponding to the scanning line SL1 in the first column and the scanning line SL2 in the second column, and the other waveforms can be deduced in the same way. As shown in the first to fourth waveform diagrams of FIG. 2B , the switch S1 is turned on during the period T1 according to the control of the scan signal Scan1, so that the voltage VS1 corresponding to the scan line SL1 rises to a high level (such as VLED) during the period T1. The switch S2 is turned on during the period T2 according to the control of the scan signal Scan2, so that the voltage VS2 corresponding to the scan line SL2 rises to a high level (eg VLED) during the period T2. During the period T1, the switch S1 corresponding to the first column scan line SL1 is turned on, and the voltage VS1 has a high level. The data line control circuit 60 sequentially provides the driving current IDr1 to the driving current IDrn during the period T1, thereby controlling the diode D11. ~The diodes D1n are turned on sequentially to emit corresponding brightness. During the period T1, the pre-discharge current Ipdc has a high level, thereby pre-discharging the charges on the m scanning lines, for example, through the discharge resistors Rdc1~Rdcm in Figure 2A. to storage capacitor Cs. Specifically, during the period T1, when one of the m scan lines (that is, SL1) is a high-level VLED due to the turn-on of the corresponding switch (such as S1), the remaining m-1 scan lines (ie, SL1) are high-level VLEDs. For example, SL2 ~ SLm) have corresponding voltages determined by their respective residual charges. The pre-discharge circuit 420 pre-discharges the charges on the scan lines SL2 ~ SLm through the pre-discharge current Ipdc, and stores them in the storage capacitor Cs. In the embodiment, the pre-discharge circuit 420, for example, pre-discharges the scan lines SL2~SLm to a low level (such as VS2 at the low level of T1). The operation details of the pre-discharge circuit 420 will be described in detail later.

On the other hand, during the period T1, the data line control circuit 60 provides driving currents IDr1~IDrn to the data lines DL1~DLn in sequence, thereby controlling the diodes D11~D1n to conduct in sequence and emit corresponding brightness. , in detail, as shown in Figure 2B, the currents ID11~ID1n of the diodes D11~D1n sequentially reach the high levels corresponding to the driving currents IDr1~IDrn in the period T1. When the n data lines When one of them (for example, DL1) has a high level due to the corresponding driving current IDr1 and the current ID11 of the diode D11 has a high level, the voltage of the data line DL1 is VLED-Vf, where Vf is the forward conduction voltage of the diode. , in addition, the remaining n-1 data lines (such as DL2~DLn) have corresponding voltages determined by their respective residual charges. At this time, the precharge circuit 430 charges the data line DL2 with the precharge currents Ipc2~Ipcn. ~DLn precharge. In one embodiment, the aforementioned precharge current Ipc is the sum of the precharge currents (such as Ipc1~Ipcn) of precharge n-1 data lines, where the charge used to precharge the data lines is Provided by the storage capacitor Cs, in one embodiment, the precharge circuit 430 precharges n-1 data lines DL2 to DLn to a high level, for example. The operation details of the precharge circuit 430 will be described in detail later.

It should be noted that each pulse wave of the precharge current Ipc corresponds to the corresponding precharge current Ipc1 ~ Ipcn after the diode currents ID11 ~ ID1n turn to a low level (for example, 0). In addition, in an embodiment During this period, the voltage Vst of the storage capacitor Cs rises slowly. In one embodiment, when the pre-discharge current Ipdc is equal to the pre-charge current Ipc, the average value of the voltage Vst of the storage capacitor Cs can be maintained within a range or within a range. Definitely worth it.

In the period T2, the switch S2 corresponding to the second column scan line SL2 is turned on, and the operation waveforms of each signal are similar to the above-mentioned period T1, which will not be described again here.

It should be noted that for the scan line (for example, SL1), the aforementioned pre-discharge stage corresponds to other times other than the driven period (for example, T1). For the data line (for example, DL1), the aforementioned pre-discharge stage The phase, for example, corresponds to other times than the period when the data line DL1 is driven (for example, ID11 is at a high level in FIG. 3 ).

Please refer to FIG. 3. FIG. 3 is a schematic diagram of a light emitting diode driving circuit according to an embodiment of the present invention. The LED driving circuit 3000 of FIG. 3 is similar to the LED driving circuit 2000 of FIG. 2A . The pre-power supply circuit 41 of FIG. 3 includes an energy-saving control circuit 411 , a pre-discharge circuit 421 and a pre-charge circuit 431 . In the embodiment of Figure 3, the pre-power supply circuit 41 and the data line control circuit 60 are integrated into an integrated circuit 415. In one embodiment, the pre-discharge circuit 421 is coupled to the scan line through the pin Ppdc of the integrated circuit 415. SL1 ~ SLm (via Rdc1 ~ Rdcm), the precharge circuit 431 is coupled to the data lines DL1 ~ DLn respectively through the pins Ppc1 ~ Ppcn of the integrated circuit 415. It should be noted that Figure 3 only depicts the scan line SL1 in the first column, the scan line SLm in the m-th column, the data line DL1 in the first row, and the data line DLn in the n-th row, and the scans in the second to m-1th columns are omitted. Lines and data lines from row 2 to row n-1 are explained below using the part shown in Figure 3.

In one embodiment, the pre-discharge circuit 421 includes a discharge amplifier 70. In the pre-discharge stage, the discharge amplifier 70 uses the pre-discharge current Ipdc to flow through the pre-discharge path Pdc to pre-discharge the voltages on the m scan lines and adjust them to the pre-discharge level. voltage. In one embodiment, the discharge amplifier 70 is configured as a unity gain amplifier circuit as shown in FIG. 3 , and adjusts the voltage on the scan line to the pre-discharge voltage according to the reference voltage Vpdc. In one embodiment, the precharge circuit 431 includes charge amplifiers 81~8n. In the precharge stage, the precharge circuit 431 precharges and adjusts the voltages on n data lines to the precharge voltage. Specifically, the charge amplifiers 81~8n 8n uses the precharge current Ipc to flow through the precharge paths Pc1 ~ Pcn respectively, correspondingly precharging and adjusting the voltages on the data lines DL1 ~ DLn to the precharge voltage. In one embodiment, the charging amplifiers 81 to 8n are configured as unity gain amplifier circuits as shown in FIG. 3 , which adjust the voltage on the corresponding data line to the precharge voltage according to the reference voltage Vpc.

In this embodiment, the high power terminal of the discharge amplifier 70 is coupled to an internal power supply VII, and the low power terminal is coupled to the storage capacitor Cs. The voltage Vst of the storage capacitor Cs is used as the low power supply of the discharge amplifier 70. , when the discharge amplifier 70 pre-discharges the charges on the m scanning lines, the charges can be stored in the storage capacitor Cs. On the other hand, in this embodiment, the low power terminals of the charging amplifiers 81 to 8n are coupled to the ground potential, and the high power terminals of the charging amplifiers 81 to 8n are coupled to the storage capacitor Cs, and the voltage Vst of the storage capacitor Cs is used as It is the high power supply of the charging amplifier, thereby precharging the corresponding data lines with the charge stored in the storage capacitor Cs.

It should be noted that, in one embodiment, the aforementioned pre-discharge current Ipdc also provides the operating current required by the pre-discharge circuit, such as the bias current required by the discharge amplifier 70. On the other hand, in one embodiment, , the aforementioned precharge current Ipc also provides the operating current required by the precharge circuit, such as the bias current required by the charging amplifiers 81~8n.

As shown in FIG. 3 , in one embodiment, the energy-saving control circuit 411 further includes a clamp circuit 440 and a clamp circuit 450 . In one embodiment, the clamping circuit 440 is used to clamp the voltage Vst of the storage capacitor Cs so that it is not lower than the first clamping voltage, and the clamping circuit 450 is used to clamp the voltage Vst of the storage capacitor Cs so that it is not higher than the first clamping voltage. A second clamping voltage, wherein the first clamping voltage is lower than the second clamping voltage. In other words, in the above embodiment, the clamp circuit 440 and the clamp circuit 450 are used to clamp the voltage Vst of the storage capacitor Cs between the first clamping voltage and the second clamping voltage. It is worth noting that, in one embodiment, the voltage of the aforementioned internal power supply VII is higher than the second clamping voltage, and the difference between the two is greater than the minimum operating voltage required by the discharge amplifier 70. On the other hand, in one embodiment, , the first clamping voltage is greater than the minimum operating voltage required by the charging amplifiers 81~8n.

In one embodiment, the aforementioned discharge amplifier 70 and charge amplifiers 81 to 8n can be configured as an operational amplifier, which has the aforementioned high power terminal and low power terminal. In one embodiment, each stage circuit in the operational amplifier (such as differential stage, gain stage, power amplifier stage), etc., are coupled between the high power supply terminal and the low power supply terminal, and operate with the voltage coupled between the high power supply terminal and the low power supply terminal as the power supply. Details of the operational amplifier The circuit and operation can be inferred by those skilled in the art based on the teachings of the present invention, and will not be limited or described in detail here.

Please refer to FIG. 4 , which is a schematic diagram of a pre-power supply circuit in a light-emitting diode driving circuit according to a specific embodiment of the present invention. The pre-power supply circuit 42 of FIG. 4 is similar to the pre-power supply circuit 41 of FIG. 3 . In one embodiment, the energy-saving control circuit 412 of FIG. 4 includes a clamp circuit 441 and a clamp circuit 451 . In one embodiment, the clamping circuit 441 includes a diode D1, which is forwardly coupled between the reference voltage Vcc and the storage capacitor Cs. The clamping circuit 441 is used to clamp the voltage Vst of the storage capacitor Cs so that it is not lower than The first clamping voltage. In this embodiment, the first clamping voltage is the difference between the reference voltage Vcc and the forward conducting voltage of the diode D1. In one embodiment, the clamping circuit 451 includes a diode D2, which is forwardly coupled between the storage capacitor Cs and the reference voltage Vcc. The clamping circuit 451 is used to clamp the voltage Vst of the storage capacitor Cs so that it is no higher than The second clamping voltage. In this embodiment, the second clamping voltage is the sum of the reference voltage Vcc and the forward conducting voltage of the diode D2. In the above embodiment, the clamp circuit 441 and the clamp circuit 451 are used to clamp the voltage Vst of the storage capacitor Cs between the first clamping voltage and the second clamping voltage.

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of an energy-saving control circuit in a light-emitting diode driving circuit according to a specific embodiment of the present invention. In one embodiment, the energy-saving control circuit 413 of FIG. 5 includes a clamp circuit 442 and a clamp circuit 452. In one embodiment, the clamp circuit 442 includes: a transistor N1 and an amplifier 74. In this embodiment, the transistor N1 is an N-type metal oxide semiconductor (MOS) device, and the source coupling of the transistor N1 is connected to the storage capacitor Cs, and the gate of the transistor N1 is coupled to the output end of the amplifier 74. The amplifier 74 is used to control the transistor N1 according to the difference between the clamping voltage Vref1 and the voltage Vst of the storage capacitor Cs to clamp The voltage Vst of the storage capacitor Cs is not lower than the clamping voltage Vref1 (corresponding to the aforementioned first clamping voltage). In one embodiment, the clamp circuit 452 includes: a transistor P1 and an amplifier 75. In this embodiment, the transistor P1 is a P-type metal oxide semiconductor (MOS) device, and the source coupling of the transistor P1 is connected to the storage capacitor Cs, and the gate of the transistor P1 is coupled to the output terminal of the amplifier 75. The amplifier 75 is used to control the transistor P1 according to the difference with the voltage Vst of the storage capacitor Cs to clamp the voltage Vst of the storage capacitor Cs. The voltage Vst is not higher than the clamping voltage Vref2 (corresponding to the aforementioned second clamping voltage). In the above embodiment, the clamp circuit 442 and the clamp circuit 452 are used to clamp the voltage Vst of the storage capacitor Cs between the clamp voltage Vref1 and the clamp voltage Vref2.

Please refer to FIG. 6 , which is a schematic diagram of a pre-discharge circuit in a light-emitting diode driving circuit according to a specific embodiment of the present invention. In one embodiment, the pre-discharge circuit 422 of FIG. 6 further includes a clamp circuit 460 for clamping the amplifier power supply voltage Va between the high power terminal of the discharge amplifier 70 and the low power terminal of the discharge amplifier 70 so that it cannot higher than the third clamping voltage. Specifically, in one embodiment, the clamp circuit 460 includes a transistor P2 and a voltage offset circuit 471 . In one embodiment, the transistor P2 is, for example, a high voltage P-type metal oxide semiconductor (HV PMOS) device, coupled between the storage capacitor Cs and the low power terminal of the discharge amplifier 70 . In one embodiment, as shown in FIG. 6 , the voltage offset circuit 471 includes a diode D3 and a current source Is, where the diode D3 is, for example, but not limited to, a Zener diode. In the embodiment of FIG. 6, the diode D3 is coupled between the control terminal of the transistor P2 (in this embodiment, the gate of the transistor P2) and the high and low power terminals of the discharge amplifier 70, and the current source Is is coupled. Connected between the control terminal of transistor P2 and the ground potential. In this embodiment, the voltage offset circuit 471 is used to control the transistor P2 to clamp the amplifier power supply voltage Va so that it is not higher than a third clamping voltage, where the third clamping voltage is related to the bias of the voltage offset circuit 471 The shift voltage (in this embodiment, the offset voltage Vz of the diode D3) and the conduction threshold Vth of the transistor P2. Specifically, in this embodiment, the third clamping voltage is Vz-|Vth|. It should be noted that the maximum rated voltage of the transistor P2 is higher than the maximum rated voltage of the discharge amplifier 70 , and/or the maximum rated voltage of the transistor P2 is higher than the maximum rated voltage of the energy-saving control circuit 411 .

Please refer to FIG. 7 . FIG. 7 is a schematic diagram of a pre-power supply circuit in a light-emitting diode driving circuit according to a specific embodiment of the present invention. The pre-power supply circuit 43 of FIG. 7 is similar to the pre-power supply circuit 42 of FIG. 4 . In one embodiment, the energy-saving control circuit 414 in the pre-power supply circuit 43 further includes a current balancing circuit 480 . In one embodiment, the current balancing circuit 480 is used to control the bias current Ibias required by the precharge circuit 431 according to the difference between the voltage Vst of the storage capacitor Cs and the reference voltage Vref3, thereby adjusting the static state of the aforementioned precharge circuit 431. The current consumption (such as Iq1 or Iqn) is used to control the charge of pre-discharging the voltage on the m scan lines and the charge of pre-charging the voltage on the n data lines to be balanced in a steady state. In one embodiment, the bias current Ibias is used, for example, to provide the bias current required for the operation of the charging amplifiers 81 to 8n. In other words, the static current consumption of the precharge circuit is controlled by the bias current Ibias.

In detail, in one embodiment, the current balancing circuit 480 includes: a comparison circuit 90 , an integrating circuit 91 and a bias current generating circuit 92 . In one embodiment, the comparison circuit 90 is used to compare the voltage Vst of the storage capacitor Cs with the reference voltage Vref3 to generate a comparison result. The integration circuit 91 is used to control the pull-up current source and the pull-down current source according to the comparison result, thereby integrating The capacitor Ci generates the integrated voltage Vi. For example, when the reference voltage Vref3 is greater than the voltage Vst of the storage capacitor Cs, the integrating circuit 91 controls the pull-down current source to discharge the integrating capacitor Ci, thereby causing the integrated voltage Vi to decrease. When the reference voltage Vref3 is less than When the voltage Vst of the storage capacitor Cs is stored, the integrating circuit 91 controls the pull-up current source to charge the integrating capacitor Ci, thereby increasing the integrating voltage Vi. In one embodiment, the bias current generating circuit 92 is used to generate the bias current Ibias according to the integrated voltage Vi, where the bias current Ibias is related (eg, positively related) to the integrated voltage Vi. In a preferred embodiment, in the steady state, the level of the voltage Vst of the storage capacitor Cs will be equal to the level of the reference voltage Vref3.

Please refer to FIG. 4 and FIG. 7 simultaneously. In one embodiment, the first clamping voltage is lower than the reference voltage Vref3, and the reference voltage Vref3 is lower than the second clamping voltage. Please refer to FIG. 5 and FIG. 7 simultaneously. In one embodiment, the clamping voltage Vref1 is lower than the reference voltage Vref3, and the reference voltage Vref3 is lower than the clamping voltage Vref2.

The present invention has been described above with reference to the preferred embodiments. However, the above description is only to make it easy for those familiar with the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The various embodiments described are not limited to single application, but can also be used in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace those in another embodiment. Corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating according to a certain signal or generating a certain output result", which is not limited to Depending on the signal itself, it also includes performing voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion on the signal when necessary, and then processing or calculating the converted signal to produce an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. There are many combinations, and they are not listed here. Accordingly, the scope of the present invention is intended to cover the above and all other equivalent changes.

11:Amplifier 110: Precharge circuit 1000, 2000, 3000: LED driver circuit 12:Amplifier 120: Pre-discharge circuit 130: Data line control circuit 140: Scan line control circuit 20: Main control circuit 30:Memory circuit 40: Pre-power supply circuit 41: Pre-power supply circuit 42,43: Pre-power supply circuit 410~414: Energy-saving control circuit 415:Integrated circuits 420~423: Pre-discharge circuit 430,431: Precharge circuit 440~442: clamp circuit 450~452: clamp circuit 460,461: clamp circuit 471,472: Voltage offset circuit 480:Current balancing circuit 50: Scan line control circuit 51: Gate drive circuit 60: Data line control circuit 70: Discharge amplifier 74,75: amplifier 81,8n:Charging amplifier 90: Comparison circuit 91: Integral circuit 92: Bias current generation circuit Ci: integrating capacitor Cpp1~Cppm: parasitic capacitance Cpn1~Cpnn: parasitic capacitance Cs: storage capacitor D1~D3: Diode D11~Dmn: Diode DL1, DL2, DLn: data line Ibias: bias current IDr1~IDrn: drive current Ipc: precharge current Ipc1~Ipcn: precharge current Ipdc: pre-discharge current Iq1, Iqn: static current consumption Is: current source N1, N2: transistor P1, P2: transistor Pc01: Precharge path Pc1,Pcn: precharge path Pdc: pre-discharge path Pdc01: Pre-discharge path Ppc1,Ppcn,Ppdc: pins Rdc1~Rdcm: discharge resistance S1~Sm: switch Scan1~Scanm: Scan signal SL1, SL2, SLm: scan line T1, T2: time period Va: amplifier power supply voltage Vcc: reference voltage Vi: integrated voltage VLED: power supply Vpc: precharge voltage Vpdc: pre-discharge voltage Vrc: reference voltage Vrdc: reference voltage Vref1: clamp voltage Vref2: clamping voltage Vref3: reference voltage Vs: power supply VS1, VS2: voltage Vst: voltage Vth: conduction threshold Vz: offset voltage

FIG. 1 is a schematic diagram of a light emitting diode driving circuit in the prior art.

FIG. 2A is a block diagram of a light emitting diode driving circuit according to an embodiment of the present invention.

FIG. 2B is a partial operation waveform diagram corresponding to the light emitting diode driving circuit of FIG. 2A.

FIG. 3 is a schematic diagram of an embodiment of a light emitting diode driving circuit according to the present invention.

FIG. 4 is a schematic diagram of a specific embodiment of the pre-power supply circuit in the light-emitting diode driving circuit according to the present invention.

FIG. 5 is a schematic diagram of a specific embodiment of the energy-saving control circuit in the light-emitting diode driving circuit according to the present invention.

FIG. 6 is a schematic diagram of a specific embodiment of the pre-discharge circuit in the light-emitting diode driving circuit according to the present invention.

FIG. 7 is a schematic diagram of a specific embodiment of the pre-power supply circuit in the light-emitting diode driving circuit according to the present invention.

3000: Light emitting diode drive circuit

41: Pre-power supply circuit

411: Energy-saving control circuit

415:Integrated circuits

421: Pre-discharge circuit

431: Precharge circuit

440: First clamp circuit

450: Second clamp circuit

60: Data line control circuit

70: Discharge amplifier

81,8n:Charging amplifier

Cpp1~Cppm: parasitic capacitance

Cpn1~Cpnn: parasitic capacitance

Cs: storage capacitor

D11~Dmn: light emitting diode

DL1, DLn: data line

IDr1~IDrn: drive current

Ipc: precharge current

Ipc1~Ipcn: precharge current

Ipdc: pre-discharge current

Pc1: precharge path

Pcn: precharge path

Pdc: pre-discharge path

Ppc1,Ppcn,Ppdc: pins

Rdc1~Rdcm: discharge resistance

S1~Sm: switch

SL1, SLm: scan line

VLED: power supply

Vpc: precharge voltage

Vpdc: pre-discharge voltage

Claims (16)

A light emitting diode (LED, Light Emitting Diode) driving circuit used to drive a plurality of LED lamp beads (beads), wherein the plurality of LED lamp beads are respectively coupled to m scan lines and n data lines, where m, n is an integer greater than or equal to 1. In a driving stage, each LED lamp bead is controlled to emit light according to the electrical characteristics of the corresponding coupled scan line and the corresponding coupled data line. The LED driving circuit includes: An energy-saving control circuit includes a storage capacitor; A pre-discharge circuit for pre-discharging the charges on the m scan lines to the storage capacitor in a pre-discharge stage; and A precharge circuit is used to precharge the n data lines with the charge stored in the storage capacitor in a precharge stage. The LED driving circuit as described in claim 1 further includes: A scan line control circuit used to provide a power supply to the m scan lines in sequence during a driving stage; and A data line control circuit is used in the driving stage to provide corresponding driving currents to the n data lines according to a corresponding data, thereby causing the corresponding LED lamp beads to emit corresponding brightness. The LED driving circuit as described in claim 1, wherein: The pre-discharge circuit includes a discharge amplifier, which pre-discharges and adjusts the voltages on the m scan lines to a pre-discharge voltage during the pre-discharge stage; The precharge circuit includes a charge amplifier, which precharges and adjusts the voltages on the n data lines to a precharge voltage during the precharge stage; wherein a low power terminal of the discharge amplifier is coupled to the storage capacitor, and the voltage of the storage capacitor is used as the low power supply of the discharge amplifier, thereby pre-discharging the charges on the m scan lines to the storage capacitor; A high power terminal of the charging amplifier is coupled to the storage capacitor, and the voltage of the storage capacitor is used as the high power supply of the charging amplifier, thereby precharging the n data lines with the charge stored in the storage capacitor. The LED driving circuit of claim 1, wherein the energy-saving control circuit further includes a first clamp circuit and a second clamp circuit, wherein the first clamp circuit is used to clamp the voltage of the storage capacitor so that Not lower than a first clamping voltage, wherein the second clamping circuit is used to clamp the voltage of the storage capacitor so that it is not higher than a second clamping voltage, wherein the first clamping voltage is lower than the second clamping voltage. The LED driving circuit of claim 4, wherein the first clamp circuit includes: A first diode is forwardly coupled between a first reference voltage and the storage capacitor, wherein the first clamping voltage is the first reference voltage and the forward conduction voltage of the first diode. difference; The second clamp circuit includes: a second diode forward coupled between the storage capacitor and the first reference voltage, wherein the second clamping voltage is the first reference voltage and the forward conduction voltage of the second diode and. The LED driving circuit of claim 4, wherein the first clamp circuit includes: a first transistor coupled to the storage capacitor; and A first amplifier for controlling the first transistor according to the difference between the first clamping voltage and the voltage of the storage capacitor to clamp the voltage of the storage capacitor so that it is not lower than the first clamping voltage. ; The second clamp circuit includes: a second transistor coupled to the storage capacitor; and A second amplifier for controlling the second transistor according to the difference between the second clamping voltage and the voltage of the storage capacitor to clamp the voltage of the storage capacitor so that it is not higher than the second clamping voltage. . The LED driving circuit of claim 3, wherein the pre-discharge circuit further includes a third clamp circuit for clamping a high power terminal of the discharge amplifier and the low power terminal of the discharge amplifier. amplifier supply voltage so that it is no higher than a third clamping voltage. The LED driving circuit of claim 7, wherein the third clamp circuit includes: a third transistor coupled between the storage capacitor and the low power terminal of the discharge amplifier; and A voltage offset circuit, coupled between a control terminal of the third transistor and the high and low power terminals of the discharge amplifier, is used to control the third transistor to clamp the power supply voltage of the amplifier so that it is not higher than the A third clamping voltage, wherein the third clamping voltage is related to an offset voltage of the voltage offset circuit and a conduction threshold of the third transistor. The LED driving circuit of claim 8, wherein the maximum rated voltage of the third transistor is higher than the maximum rated voltage of the discharge amplifier, and/or the maximum rated voltage of the third transistor is higher than The maximum rated voltage of the energy-saving control circuit. The LED drive circuit as described in claim 1, wherein the energy-saving control circuit further includes: A current balancing circuit is used to control a bias current required by the precharge circuit based on the difference between the voltage of the storage capacitor and a second reference voltage, thereby adjusting the static current consumption of the precharge circuit, thereby making In a steady state, the charge for pre-discharging the voltage on the m scan lines and the charge for pre-charging the voltage on the n data lines are controlled to be balanced. The LED driving circuit of claim 10, wherein the current balancing circuit includes: a comparison circuit for comparing the voltage of the storage capacitor with the second reference voltage to generate a comparison result; An integrating circuit for controlling a pull-up current source and a pull-down current source based on the comparison result, thereby generating an integrated voltage on an integrating capacitor; and A bias current generating circuit is used to generate the bias current according to the integrated voltage, wherein the bias current is related to the integrated voltage. A control method for controlling a light emitting diode (LED, Light Emitting Diode) drive circuit, wherein the LED drive circuit includes a plurality of LED lamp beads (beads), wherein the plurality of LED lamp beads are respectively coupled to m scans line and n data lines, where n and m are both integers greater than or equal to 1. The control method includes: In a driving stage, each LED lamp bead is controlled to emit light according to the electrical characteristics of the corresponding coupled scan line and the corresponding coupled data line; In a pre-discharge stage, pre-discharge the charges on the m scan lines to a storage capacitor; and In a precharge stage, the n data lines are precharged with the charge stored in the storage capacitor. The control method as described in request 12 further includes: In a driving phase, provide a power supply to the m scan lines in sequence; and In the driving stage, corresponding driving currents are provided to the n data lines according to a corresponding piece of data, thereby causing the corresponding LED lamp beads to emit corresponding brightness. The control method as described in request 12 further includes: Clamping the voltage of the storage capacitor to not less than a first clamping voltage; and Clamping the voltage of the storage capacitor so that it is no higher than a second clamping voltage; The first clamping voltage is lower than the second clamping voltage. The control method as described in request 12 further includes: A bias current is controlled according to the difference between the voltage of the storage capacitor and a reference voltage to adjust the static current consumption of a precharge circuit, thereby presetting the voltage on the m scan lines in a steady state. The discharged charges and the charges that precharge the voltages on the n data lines are controlled to be balanced; The precharge circuit is a circuit used to precharge the n data lines with the charge stored in the storage capacitor during the precharge stage. The control method as claimed in claim 15, wherein the step of controlling the bias current includes: Comparing the voltage of the storage capacitor with the reference voltage to generate a comparison result; Control a pull-up current source and a pull-down current source according to the comparison result, thereby generating an integrated voltage on an integrating capacitor; and The bias current is generated according to the integrated voltage, wherein the bias current is related to the integrated voltage.

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