TWI813435B - 製造碳化矽半導體功率元件的方法 - Google Patents
製造碳化矽半導體功率元件的方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910044991 metal oxide Inorganic materials 0.000 claims description 22
- 150000004706 metal oxides Chemical class 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 210000000746 body region Anatomy 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 8
- 239000004020 conductor Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
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Abstract
一種製造碳化矽半導體功率元件的方法。在所述方法中,高壓(HV)區的功率元件和低壓(LV)區的CMOS裝置一起形成,因此可以顯著地節省成本並且顯著地改進系統效率。首先,在基板上形成第一漂移層,然後在第一漂移層中形成屏蔽區。屏蔽區包括LV區中的連續區。然後,在第一漂移層上形成第二漂移層。在第二漂移層中形成拾取區,拾取區連接到屏蔽區的連續區,同時形成LV區的NMOS和PMOS以及HV區的功率元件。NMOS和PMOS被拾取區和連續區包圍,從而最大限度地減少本體效應。
Description
本發明是有關於一種功率元件製造技術,且特別是有關於一種製造碳化矽半導體功率元件的方法。
高壓場效電晶體,也稱為功率電晶體或碳化矽半導體功率電晶體,在半導體領域是眾所周知的。碳化矽半導體功率元件(垂直構造的結構)在高溫和高壓應用中變得非常普及。
一般來說,碳化矽(SiC)半導體功率元件包括用於低壓(LV)電路的裝置和用於高壓(HV)電路的裝置,其中碳化矽互補式金屬氧化物半導體(CMOS)的低電源電壓可以應用於類比或數位電路中,在高溫環境下為可靠的金屬氧化物半導體(MOS)電路提供了最大的機會,而高壓MOS功率電晶體在高壓應用中具有很高的驅動能力。
然而,在同一基板上製造高壓電路和低壓電路的製程過於複雜,無法降低製造成本和時間。
本發明提供一種製造碳化矽半導體功率元件的方法,以減少成本,同時獲得更好的電特性和有效過濾垂直功率溝槽MOS產生的雜訊。
本發明的一種製造碳化矽半導體功率元件的方法,包括:在碳化矽基底的上表面上形成第一導電類型第一漂移層,其中,所述碳化矽基底包括低壓區和高壓區;在所述第一導電類型第一漂移層中形成第二導電類型屏蔽區,其中所述第二導電類型屏蔽區包括位於所述低壓區的連續區和位於所述高壓區的多個條狀區;在所述第一導電類型第一漂移層上形成第一導電類型第二漂移層;在所述第一導電類型第二漂移層中同時形成第二導電類型第一井區和第二導電類型第二井區,其中所述第二導電類型第一井區形成在所述低壓區的第一導電類型金屬氧化物半導體區中,並且所述第二導電類型第二井區形成在所述高壓區中;在所述第一導電類型第二漂移層中同時形成與所述連續區連接的第二導電類型第一拾取(pick-up)區和與所述條狀區連接的第二導電類型第二拾取區,其中所述第一導電類型金屬氧化物半導體區和所述低壓區中的第二導電類型金屬氧化物半導體區被所述第二導電類型第一拾取區包圍,所述第二導電類型第二拾取區形成在所述高壓區內;在所述高壓區的所述第一導電類型第二漂移層中形成多個溝槽;在所述低壓區內的所述第一導電類型第二漂移層上形成第一閘極介電層,在每個所述溝槽的表面上形成第二閘極介電
層;同時在所述第一閘極介電層上形成多個閘極以及在所述多個溝槽中形成多個溝槽式閘極,其中所述多個閘極分別設置在所述第一導電類型金屬氧化物半導體區和所述第二導電類型金屬氧化物半導體區,且所述多個溝槽式閘極分別形成於所述條狀區上;同時在所述溝槽式閘極之間的所述第二導電類型第二井區中形成多個高壓源極區以及在所述第二導電類型第一井區中形成多個第一源/汲極區;以及同時形成第二導電類型第一重摻雜區、多個第二導電類型第二重摻雜區和多個第二源/汲極區,其中所述第二導電類型第一重摻雜區形成於所述第一導電類型第二漂移層中並與所述第二導電類型第二拾取區連接,所述多個第二導電類型第二重摻雜區形成在所述溝槽式閘極之間並與所述第二導電類型第二井區連接,所述多個第二源/汲極區形成於所述第二導電類型金屬氧化物半導體區內的所述第一導電類型第二漂移層中。
在本發明的一實施例中,上述第一導電類型第二漂移層的摻雜濃度為所述第一導電類型第一漂移層的摻雜濃度的1.2至3倍。
在本發明的一實施例中,每個所述條狀區的一端延伸到所述第二導電類型第二井區的區域之外。
在本發明的一實施例中,每個所述條狀區的所述端通過所述第二導電類型第二拾取區與所述第二導電類型第一重摻雜區連接。
在本發明的一實施例中,上述第一導電類型第一漂移層
的摻雜濃度範圍為1E15/cm3至5E16/cm3,所述第二導電類型屏蔽區的摻雜濃度範圍為1E17/cm3到5E18cm3。
在本發明的一實施例中,上述第二導電類型屏蔽區的厚度範圍為0.1μm至0.4μm。
在本發明的一實施例中,上述第二導電類型第一井區和所述第二導電類型第二井區的摻雜濃度範圍為1E17/cm3至6E17/cm3,以及所述第二導電類型第一井區和所述第二導電類型第二井區的厚度範圍為1μm至2μm。
在本發明的一實施例中,上述第二導電類型第一拾取區和所述第二導電類型第二拾取區的摻雜濃度範圍為2E17/cm3至5E18/cm3。
在本發明的一實施例中,在形成所述第二導電類型第一拾取區和所述第二導電類型第二拾取區的步驟之後,更包括在所述高壓區內的所述第二導電類型第二井區形成第一導電類型第一輕摻雜汲極區。
在本發明的一實施例中,上述第一導電類型第一輕摻雜汲極區的摻雜濃度範圍為5E17/cm3至5E18/cm3。
在本發明的一實施例中,上述第二閘極介電層的厚度範圍為400Å至2000Å。
在本發明的一實施例中,上述第一閘極介電層的厚度範圍為100Å至600Å。
在本發明的一實施例中,上述第二閘極介電層在形成所
述第一閘極介電層之前形成。
在本發明的一實施例中,形成所述多個閘極和所述多個溝槽式閘極的步驟包括:在所述第一閘極介電層上沉積多晶矽層並填充所述溝槽;形成圖案化罩幕以覆蓋所述低壓區內的部分所述多晶矽層;以所述圖案化罩幕作為刻蝕罩幕,去除暴露的所述多晶矽層,同時回蝕所述高壓區內的所述多晶矽層;以及去除所述圖案化罩幕。
在本發明的一實施例中,形成所述第二導電類型第二重摻雜區的步驟包括在所述第二導電類型第一井區中形成第一體區。
在本發明的一實施例中,形成所述多個高壓源極區的步驟包括在所述第二導電類型金屬氧化物半導體區內的所述第一導電類型第二漂移層中形成第二體區。
在本發明的一實施例中,在形成所述多個閘極的步驟之後,更包括在所述第一導電類型金屬氧化物半導體區內的所述第二導電類型第一井區內形成第一導電類型第二輕摻雜汲極區。
在本發明的一實施例中,在形成所述多個閘極的步驟之後,更包括在所述第二導電類型金屬氧化物半導體區內的所述第一導電類型第二漂移層中形成第二導電類型輕摻雜汲極區。
在本發明的一實施例中,上述第一導電類型為n型,上述第二導電類型為p型。
基於上述,根據本發明的方法,可以將HV區的功率元
件和LV區的CMOS集成在同一個SiC基底上,可以顯著降低製造成本,提高高溫可靠性性能進而改進系統效能。此外,在溝槽式閘極下方形成的拾取區可以避免高電場,並降低有效Cgd值,從而有利於高壓功率元件工作的AC性能;而與前述拾取區一起在低壓區形成的拾取區可以濾除HV區功率元件產生的雜訊。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所圖式式作詳細說明如下。
100:SiC基底
100a:上表面
100b:底表面
102:第一導電類型第一漂移層
104:第二導電類型屏蔽區
106:連續區
108:條狀區
108a:一端
110:第一導電類型第二漂移層
112a:第二導電類型第一拾取區
112b:第二導電類型第二拾取區
114:第一導電類型第一LDD區
116:溝槽
118:第二閘極介電層
120:第一閘極介電層
122:第二體區
124a:第二導電類型第二重摻雜區
124b:第二導電類型第一重摻雜區
126:第一體區
128:絕緣層
130:導電材料
200:連接部分
D:HV汲極
G1、G2:閘極
HS:HV源極區
HV:高壓區
LV:低壓區
O1、O2:開口
PL:多晶矽層
S/D1:第一源/汲極區
S/D2:第二源/汲極區
TG:溝槽式閘極
t1、t2、t3、t4:厚度
W1:第二導電類型第一井區
W2:第二導電類型第二井區
圖1A至圖1I是根據本發明的一實施例的一種製造碳化矽半導體功率元件的流程剖面示意圖。
圖2是根據所述實施例中的一例的碳化矽半導體功率元件的高壓區(HV)的俯視圖。
圖3是沿圖2的線III-III'的剖面圖。
圖4是根據所述實施例中的一例的碳化矽半導體功率元件的低壓區(LV)的俯視圖。
本發明將通過以下實施例配合圖示說明。然而,本發明可以以許多不同的形式來體現,並不應被解釋為限於本文所闡述的實施例。在圖式中,為清楚和具體的目的,各層和區域的尺寸
和相對尺寸可能並未按照準確的比例呈現。
圖1A至圖1I是根據本發明的一實施例的一種製造碳化矽半導體功率元件的流程剖面示意圖。
請參照圖1A,使用碳化矽(SiC)基底100,並且SiC基底100可以是第一導電類型基底,並且第一導電類型例如是n型。SiC基底100包括低壓區LV和高壓區HV。然後在SiC基底100的上表面100a上形成第一導電類型第一漂移層102。在第一導電類型第一漂移層102中形成第二導電類型屏蔽區(shielding region)104。在本實施例中,第二導電類型是p型。第二導電類型屏蔽區104至少包括低壓區LV中的連續區106和高壓區HV中的多個條狀區108。在本實施例中,第一導電類型第一漂移層102的摻雜濃度範圍例如為1E15/cm3至5E16/cm3,第二導電類型屏蔽區104的摻雜濃度範圍例如為1E17/cm3至5E18/cm3。注入於第二導電類型屏蔽區104的摻雜劑例如為選自鋁、硼及錫中的至少一種。然而,本發明不限於此。在一個實施例中,第二導電類型屏蔽區104的厚度t1例如為0.1μm至0.4μm。然而,本發明不限於此。
然後,請參照圖1B,在第一導電類型第一漂移層102上形成第一導電類型第二漂移層110。在一個實施例中,第一導電類型第二漂移層110的摻雜濃度為第一導電類型第一漂移層102的摻雜濃度的1.2至3倍。
接著,請參照圖1C,在第一導電類型第二漂移層110
中同時形成第二導電類型第一井區W1和第二導電類型第二井區W2,其中第二導電類型第一井區W1形成在第一導電類型的MOS區中的低壓區LV(例如NMOS區),並且第二導電類型第二井區W2形成在高壓區HV中。在一個實施例中,第二導電類型第一井區W1和第二導電類型第二井區W2的摻雜濃度範圍為1E17/cm3至6E17/cm3,第二導電類型第一井區W1和第二導電類型第二井區W1的厚度t2範圍例如為1μm至2μm。然而,本發明不限於此。在一個實施例中,第二導電類型第一井區W1與連續區106之間的距離例如為0.5μm至4μm。在第一導電類型第二漂移層110中同時形成第二導電類型第一拾取區112a和第二導電類型第二拾取區(如圖2所示),第二導電類型第一拾取區112a是連接至連續區106,其中低壓區LV中的第一導電類型MOS區(例如NMOS)和第二導電類型MOS區(例如PMOS)被第二導電類型第一拾取區112a包圍。第二導電類型第二拾取區形成在高壓區HV內並在其他截面處連接到條狀區108。在一個實施例中,第二導電類型第一拾取區112a和第二導電類型第二拾取區的摻雜濃度例如為2E17/cm3至5E18/cm3。然而,本發明不限於此。
接著,請參照圖1D,如有必要,在形成第二導電類型第一拾取區112a和第二導電類型第二拾取區的步驟之後,可以在高壓區HV內的第二導電類型第二井區W2中形成第一導電類型第一輕摻雜汲極(LDD)區114。在一個實施例中,第一導電類型第一LDD區114的摻雜濃度例如為5E17/cm3至5E18/cm3。第一導
電類型第一LDD區114的深度例如為0.1μm至0.4μm。然而,本發明不限於此。
接著,請參照圖1E,在高壓區HV的第一導電類型第二漂移層110中形成多個溝槽116,然後在每個溝槽116的表面上形成第二閘極介電層118。每個溝槽116在垂直方向形成在每個條狀區108上。在一個實施例中,第二閘極介電層118的厚度t3例如為400Å至2000Å。然而,本發明不限於此。
接著,請參照圖1F,在低壓區LV內的第一導電類型第二漂移層110上形成第一閘極介電層120。在一個實施例中,第一閘極介電層120的厚度t4例如為100Å至600Å。然而,本發明不限於此。第二閘極介電層118是在形成第一閘極介電層120之前形成。然而,本發明不限於此。在另一實施例中,第一閘極介電層120可在形成第二閘極介電層118之前形成。對於低壓區LV中的閘極和高壓區HV中的溝槽式閘極的形成,多晶矽層PL沉積在第一閘極介電層120上並填充溝槽116。
接著,請參照圖1G,可以形成圖案化罩幕(未示出)以覆蓋低壓區LV內的部分多晶矽層PL,然後使用圖案化罩幕作為刻蝕罩幕去除暴露的多晶矽層PL,同時回刻蝕高壓區HV內的多晶矽層PL。因此,閘極G1和G2分別形成在第一導電類型MOS區域(例如NMOS)和第二導電類型MOS區域(例如PMOS)內的第一閘極介電層120上,並且多個溝槽式閘極TG分別形成在條狀區108上方的溝槽116。由於第二導電類型屏蔽區104的每個條
狀區108設置在形成溝槽式閘極TG的每個溝槽116的底部下方,所以溝槽116底部的第二閘極介電層118高電場的問題可以解決,有效Cgd值也可以顯著降低。因此,在高壓區HV的功率垂直MOSFET的工作中,可以實現更好的電特性,同時也提高了溝槽116底部的氧化物可靠性。接著,可以去除圖案化罩幕。
接著,請參照圖1H,同時形成多個HV源極區HS和多個第一源/汲極區S/D1,其中HV源極區HS形成在溝槽式閘極TG之間的第二導電類型第二井區W2中,第一源/汲極區S/D1形成在第二導電類型第一井區W1中。在一個實施例中,形成多個HV源極區HS的步驟包括在第二導電類型MOS區(例如PMOS)內的第一導電類型第二漂移層110中形成第二體區122。同時形成第二導電類型第一重摻雜區(如圖2所示)、多個第二導電類型第二重摻雜區124a和多個第二源/汲極區S/D2,其中第二導電類型第二重摻雜區124a形成在溝槽式閘極TG之間並連接到第二導電類型第二井區W2,並且第二源/汲極區S/D2形成在第二導電類型的MOS區中的第一導電類型第二漂移層110。在一個實施例中,形成第二導電類型第二重摻雜區124a的步驟包括在第二導電類型第一井區W1中形成第一體區126。
接著,請參照圖1I,在第一導電類型第二漂移層110上選擇性地形成絕緣層128,然後在絕緣層128中形成開口O1和O2,然後在開口O1和O2中沉積導電材料(例如金屬或合金)130。HV汲極D形成在SiC基底100的底表面100b上。
根據本實施例的碳化矽半導體功率元件,由於第一導電類型第一漂移層102和第一導電類型第二漂移層110是由低壓區LV中的第二導電類型屏蔽區104的連續區106隔離,第一導電類型第一漂移層102中的電位與第一導電類型第二漂移層110中的電位不同。第一導電類型第二漂移層110是對PMOS源極的體偏壓。第二導電類型第一井區W1被第一導電類型第二漂移層110和第二導電類型屏蔽區104的連續區106隔離,可以有效地過濾高壓區HV中的功率垂直MOSFET產生的雜訊。
圖2是根據所述實施例中的一例的碳化矽半導體功率元件的高壓區(HV)的俯視圖。圖3是沿圖2的線III-III'的截面圖。在圖2和圖3中,與圖1I相同或相似的標號用於表示相同或相似的部件,相同或相似部件的內容也與圖1I中的內容相同,故在此不再贅述。然而,這些部件的相對位置可以被調整並且與圖1I中所示的不同。
請參照圖2和圖3,存在三個溝槽式閘極TG,並且形成連接部分200以連接溝槽式閘極TG。連接部分200可以通過使用在關於圖1G的步驟中所述的圖案化罩幕來形成。如圖1G所示,覆蓋溝槽116外的多晶矽層。然而,本發明不限於此。可以根據需要改變溝槽式閘極TG的數量和形成連接部分200的方法。第二導電類型第一重摻雜區124b形成在第一導電類型第二漂移層110中並且連接到第二導電類型第二拾取區112b。每一條狀區108的一端108a延伸至第二導電類型第二井區W2的區域外。在一個實
施例中,每個條狀區108的一端108a通過第二導電類型第二拾取區112b連接到第二導電類型第一重摻雜區124b。
圖4是根據所述實施例中的一例的碳化矽半導體功率元件的低壓區(LV)的俯視圖,其中與圖1I中相同或相似的標號用於表示相同或相似的部件,相同或相似部件的內容也與圖1I中的內容相同,在此不再贅述。然而,這些部件的相對位置可以被調整並且與圖1I中所示的不同。
如圖4所示,PMOS區和NMOS區構成CMOS。在PMOS區域中,第二源/汲極區S/D2形成在每個閘極G2的兩側,並且在一個實施例中,在形成閘極G2的步驟之後(圖1G的步驟之後),可以在閘極G2與第二源/汲極區S/D2之間的第一導電類型第二漂移層中形成第二導電類型的LDD區(未示出)。在NMOS區域中,第一源/汲極區S/D1形成在每個閘極G1的兩側,並且在一個實施例中,在形成閘極G1的步驟之後(圖1G的步驟之後),第一導電類型第二LDD區(未示出)可以形成在第二導電類型第一井區W1中的閘極G1和第一源/汲極區S/D1之間。即使閘極G1和G2的排列方向與圖1中閘極G1和G2的排列方向不同,如圖1G的碳化矽半導體功率元件結構中的CMOS製程流程仍然可以通過調整光罩幕圖案製造。此外,第二體區122設置在PMOS區的一側,閘極G1和第一源/汲極區S/D1被第一體區126包圍。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的
精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100:SiC基底
100b:底表面
102:第一導電類型第一漂移層
106:連續區
108:條狀區
110:第一導電類型第二漂移層
112a:第二導電類型第一拾取區
124a:第二導電類型第二重摻雜區
128:絕緣層
130:導電材料
D:HV汲極
HV:高壓區
LV:低壓區
O1、O2:開口
Claims (19)
- 一種製造碳化矽半導體功率元件的方法,包括: 在碳化矽基底的上表面上形成第一導電類型第一漂移層,其中,所述碳化矽基底包括低壓區和高壓區; 在所述第一導電類型第一漂移層中形成第二導電類型屏蔽區,其中所述第二導電類型屏蔽區包括位於所述低壓區的連續區和位於所述高壓區的多個條狀區; 在所述第一導電類型第一漂移層上形成第一導電類型第二漂移層; 在所述第一導電類型第二漂移層中同時形成第二導電類型第一井區和第二導電類型第二井區,其中所述第二導電類型第一井區形成在所述低壓區的第一導電類型金屬氧化物半導體區中,並且所述第二導電類型第二井區形成在所述高壓區中; 在所述第一導電類型第二漂移層中同時形成與所述連續區連接的第二導電類型第一拾取區和與所述條狀區連接的第二導電類型第二拾取區,其中所述第一導電類型金屬氧化物半導體區和所述低壓區中的第二導電類型金屬氧化物半導體區被所述第二導電類型第一拾取區包圍,所述第二導電類型第二拾取區形成在所述高壓區內; 在所述高壓區的所述第一導電類型第二漂移層中形成多個溝槽; 在所述低壓區內的所述第一導電類型第二漂移層上形成第一閘極介電層,在每個所述溝槽的表面上形成第二閘極介電層; 同時在所述第一閘極介電層上形成多個閘極以及在所述多個溝槽中形成多個溝槽式閘極,其中所述多個閘極分別設置在所述第一導電類型金屬氧化物半導體區和所述第二導電類型金屬氧化物半導體區,且所述多個溝槽式閘極分別形成於所述條狀區上; 同時在所述溝槽式閘極之間的所述第二導電類型第二井區中形成多個高壓源極區以及在所述第二導電類型第一井區中形成多個第一源/汲極區;以及 同時形成第二導電類型第一重摻雜區、多個第二導電類型第二重摻雜區和多個第二源/汲極區,其中所述第二導電類型第一重摻雜區形成於所述第一導電類型第二漂移層中並與所述第二導電類型第二拾取區連接,所述多個第二導電類型第二重摻雜區形成在所述溝槽式閘極之間並與所述第二導電類型第二井區連接,且所述多個第二源/汲極區形成於所述第二導電類型金屬氧化物半導體區內的所述第一導電類型第二漂移層中。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中所述第一導電類型第二漂移層的摻雜濃度為所述第一導電類型第一漂移層的摻雜濃度的1.2至3倍。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中每個所述條狀區的一端延伸到所述第二導電類型第二井區的區域之外。
- 如請求項3所述的製造碳化矽半導體功率元件的方法,其中每個所述條狀區的所述端通過所述第二導電類型第二拾取區與所述第二導電類型第一重摻雜區連接。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中所述第一導電類型第一漂移層的摻雜濃度範圍為1E15/cm 3至5E16/ cm 3,所述第二導電類型屏蔽區的摻雜濃度範圍為1E17/ cm 3到5E18 cm 3。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中所述第二導電類型屏蔽區的厚度範圍為0.1μm至0.4μm。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中所述第二導電類型第一井區和所述第二導電類型第二井區的摻雜濃度範圍為1E17/ cm 3至6E17/ cm 3,以及所述第二導電類型第一井區和所述第二導電類型第二井區的厚度範圍為1μm至2μm。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中所述第二導電類型第一拾取區和所述第二導電類型第二拾取區的摻雜濃度範圍為2E17/ cm 3至5E18/ cm 3。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中在形成所述第二導電類型第一拾取區和所述第二導電類型第二拾取區的步驟之後,更包括在所述高壓區內的所述第二導電類型第二井區形成第一導電類型第一輕摻雜汲極區。
- 如請求項9所述的製造碳化矽半導體功率元件的方法,其中所述第一導電類型第一輕摻雜汲極區的摻雜濃度範圍為5E17/ cm 3至5E18/ cm 3。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中所述第二閘極介電層的厚度範圍為400 Å至2000 Å。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中所述第一閘極介電層的厚度範圍為100 Å至600 Å。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中所述第二閘極介電層在形成所述第一閘極介電層之前形成。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中形成所述多個閘極和所述多個溝槽式閘極的步驟包括: 在所述第一閘極介電層上沉積多晶矽層並填充所述多個溝槽; 形成圖案化罩幕以覆蓋所述低壓區內的部分所述多晶矽層; 以所述圖案化罩幕作為刻蝕罩幕,去除暴露的所述多晶矽層,同時回刻蝕所述高壓區內的所述多晶矽層;以及 去除所述圖案化罩幕。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中形成所述第二導電類型第二重摻雜區的步驟包括在所述第二導電類型第一井區中形成第一體區。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中形成所述多個高壓源極區的步驟包括在所述第二導電類型金屬氧化物半導體區內的所述第一導電類型第二漂移層中形成第二體區。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中在形成所述多個閘極的步驟之後,更包括在所述第一導電類型金屬氧化物半導體區內的所述第二導電類型第一井區形成第一導電類型第二輕摻雜汲極區。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中在形成所述多個閘極的步驟之後,更包括在所述第二導電類型金屬氧化物半導體區內的所述第一導電類型第二漂移層中形成第二導電類型輕摻雜汲極區。
- 如請求項1所述的製造碳化矽半導體功率元件的方法,其中所述第一導電類型為n型,所述第二導電類型為p型。
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US20200161133A1 (en) * | 2011-02-02 | 2020-05-21 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
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