CN117438311A - 碳化硅半导体功率装置的制造方法 - Google Patents

碳化硅半导体功率装置的制造方法 Download PDF

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CN117438311A
CN117438311A CN202211111882.XA CN202211111882A CN117438311A CN 117438311 A CN117438311 A CN 117438311A CN 202211111882 A CN202211111882 A CN 202211111882A CN 117438311 A CN117438311 A CN 117438311A
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陈伟梵
蔡国基
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Leap Semiconductor Corp
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Abstract

本发明提供一种碳化硅半导体功率装置的制造方法。在所述制造方法中，高压(HV)区的功率装置和低压(LV)区的CMOS装置一起形成，因此可以显著地节省成本并且显着地改进系统效率。首先，在基板上形成第一漂移层，然后在第一漂移层中形成屏蔽区。屏蔽区包括LV区中的连续区。然后，在第一漂移层上形成第二漂移层。在第二漂移层中形成拾取区，拾取区连接到屏蔽区的连续区，同时形成LV区的NMOS和PMOS以及HV区的功率装置。NMOS和PMOS被拾取区和连续区包围，从而最大限度地减少本体效应。

Description

碳化硅半导体功率装置的制造方法
技术领域
本发明涉及一种功率装置制造技术，尤其涉及一种碳化硅半导体功率装置的制造方法。
背景技术
高压场效应晶体管，也称为功率晶体管或碳化硅半导体功率晶体管，在半导体领域是众所周知的。碳化硅半导体功率装置(垂直构造的结构)在高温和高压应用中变得非常普及。
一般来说，碳化硅(SiC)半导体功率装置包括用于低压(LV)电路的装置和用于高压(HV)电路的装置，其中碳化硅互补式金属氧化物半导体(CMOS)的低电源电压可以应用于仿真或数字电路中，在高温环境下为可靠的金属氧化物半导体(MOS)电路提供了最大的机会，而高压MOS功率晶体管在高压应用中具有很高的驱动能力。
然而，在同一基板上制造高压电路和低压电路的工艺过于复杂，无法降低制造成本和时间。
发明内容
本发明是针对一种碳化硅半导体功率装置的制造方法，以减少成本，同时获得更好的电特性和有效过滤垂直功率沟槽MOS产生的杂讯。
根据本发明的实施例，碳化硅半导体功率装置的制造方法，包括：在碳化硅衬底的上表面上形成第一导电类型第一漂移层，其中，所述碳化硅衬底包括低压区和高压区；在所述第一导电类型第一漂移层中形成第二导电类型屏蔽区，其中所述第二导电类型屏蔽区包括位于所述低压区的连续区和位于所述高压区的多个条状区；在所述第一导电类型第一漂移层上形成第一导电类型第二漂移层；在所述第一导电类型第二漂移层中同时形成第二导电类型第一阱区和第二导电类型第二阱区，其中所述第二导电类型第一阱区形成在所述低压区的第一导电类型金属氧化物半导体区中，并且所述第二导电类型第二阱区形成在所述高压区中；在所述第一导电类型第二漂移层中同时形成与所述连续区连接的第二导电类型第一拾取区和与所述条状区连接的第二导电类型第二拾取区，其中所述第一导电类型金属氧化物半导体区和所述低压区中的第二导电类型金属氧化物半导体区被所述第二导电类型第一拾取区包围，所述第二导电类型第二拾取区形成在所述高压区内；在所述高压区的所述第一导电类型第二漂移层中形成多个沟槽；在所述低压区内的所述第一导电类型第二漂移层上形成第一栅极介质层，在每个所述沟槽的表面上形成第二栅极介质层；同时在所述第一栅极介电层上形成多个栅极以及在所述多个沟槽中形成多个沟槽栅极，其中所述多个栅极分别设置在所述第一导电类型金属氧化物半导体区和所述第二导电类型金属氧化物半导体区，且所述多个沟槽栅极分别形成于所述条状区上；同时在所述沟槽栅极之间的所述第二导电类型第二阱区中形成多个高压源极区以及在所述第二导电类型第一阱区中形成多个第一源/漏极区；以及同时形成第二导电类型第一重掺杂区、多个第二导电类型第二重掺杂区和多个第二源/漏极区，其中所述第二导电类型第一重掺杂区形成于所述第一导电类型第二漂移层中并与所述第二导电类型第二拾取区连接，所述多个第二导电类型第二重掺杂区形成在所述沟槽栅极之间并与所述第二导电类型第二阱区连接，所述多个第二源/漏极区形成于所述第二导电类型金属氧化物半导体区内的所述第一导电类型第二漂移层中。
根据本发明的实施例，所述第一导电类型第二漂移层的掺杂浓度为所述第一导电类型第一漂移层的掺杂浓度的1.2至3倍。
根据本发明的实施例，每个所述条状区的一端延伸到所述第二导电类型第二阱区的区域之外。
根据本发明的实施例，每个所述条状区的所述端通过所述第二导电类型第二拾取区与所述第二导电类型第一重掺杂区连接。
根据本发明的实施例，所述第一导电类型第一漂移层的掺杂浓度范围为1E15/cm3至5E16/cm3，所述第二导电类型屏蔽区的掺杂浓度范围为1E17/cm3到5E18/cm3。
根据本发明的实施例，所述第二导电类型屏蔽区的厚度范围为0.1μm至0.4μm。
根据本发明的实施例，所述第二导电类型第一阱区和所述第二导电类型第二阱区的掺杂浓度范围为1E17/cm3至6E17/cm3，以及所述第二导电类型第一阱区和所述第二导电类型第二阱区的厚度范围为1μm至2μm。
根据本发明的实施例，所述第二导电类型第一拾取区和所述第二导电类型第二拾取区的掺杂浓度范围为2E17/cm3至5E18/cm3。
根据本发明的实施例，在形成所述第二导电类型第一拾取区和所述第二导电类型第二拾取区的步骤之后，还包括在所述高压区内的所述第二导电类型第二阱区形成第一导电类型第一轻掺杂漏极区。
根据本发明的实施例，所述第一导电类型第一轻掺杂漏极区的掺杂浓度范围为5E17/cm3至5E18/cm3。
根据本发明的实施例，所述第二栅极介质层的厚度范围为至/>
根据本发明的实施例，所述第一栅极介质层的厚度范围为至/>
根据本发明的实施例，所述第二栅极介质层在形成所述第一栅极介质层之前形成。
根据本发明的实施例，形成所述多个栅极和所述多个沟槽栅极的步骤包括：在所述第一栅极介质层上沉积多晶硅层并填充所述沟槽；形成图案化掩膜以覆盖所述低压区内的部分所述多晶硅层；以所述图案化掩膜作为刻蚀掩膜，去除暴露的所述多晶硅层，同时回蚀所述高压区内的所述多晶硅层；以及去除所述图案化掩膜。
根据本发明的实施例，形成所述第二导电类型第二重掺杂区的步骤包括在所述第二导电类型第一阱区中形成第一体区。
根据本发明的实施例，其中形成所述多个高压源极区的步骤包括在所述第二导电类型金属氧化物半导体区内的所述第一导电类型第二漂移层中形成第二体区。
根据本发明的实施例，在形成所述多个栅极的步骤之后，还包括在所述第一导电类型金属氧化物半导体区内的所述第二导电类型第一阱区内形成第一导电类型第二轻掺杂漏极区。
根据本发明的实施例，在形成所述多个栅极的步骤之后，还包括在所述第二导电类型金属氧化物半导体区内的所述第一导电类型第二漂移层中形成第二导电类型轻掺杂漏极区。
根据本发明的实施例，所述第一导电类型为n型，所述第二导电类型为p型。
综上所述，根据本发明的方法，可以将HV区的功率装置和LV区的CMOS集成在同一个SiC衬底上，可以显着降低制造成本，提高高温可靠性性能进而改进系统效能。此外，在沟槽栅极下方形成的拾取区可以避免高电场，并降低有效Cgd值，从而有利于高压功率装置工作的AC性能；而与前述拾取区一起在低压区形成的拾取区可以滤除HV区功率装置产生的杂讯。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A至图1I是根据本发明的一实施例的一种碳化硅半导体功率装置的制造方法的步骤的截面图。
图2是根据所述实施例中的一例的碳化硅半导体功率装置的高压区(HV)的俯视图。
图3是沿图2的线III-III'的截面图。
图4是根据所述实施例中的一例的碳化硅半导体功率装置的低电区(LV)的俯视图。
附图标记说明
100：SiC衬底
100a：上表面
102：第一导电类型第一漂移层
104：第二导电类型屏蔽区
106：连续区
108：条状区
108a：一端
110：第一导电类型第二漂移层
112a：第二导电类型第一拾取区
112b：第二导电类型第二拾取区
114：第一导电类型第一LDD区
116：沟槽
118：第二栅极介电层
120：第一栅极介电层
122：第二体区
124a：第二导电类型第二重掺杂区
124b：第二导电类型第一重掺杂区
126：第一体区
128：绝缘层
130：导电材料
200：连接部分
D：HV漏电极
G1、G2：栅极
HS：HV源极区
HV：高压区
LV：低压区
O1、O2：开口
PL：多晶硅层
S/D1：第一源/漏极区
S/D2：第二源/漏极区
TG：沟槽栅极
t1、t2、t3、t4：厚度
W1：第二导电类型第一阱区
W2：第二导电类型第二阱区
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同附图标记在附图和描述中用来表示相同或相似部分。
参考附图，将通过以下实施例来描述本发明。然而，本发明可以以许多不同的形式来体现并且不应被解释为限于本文所阐述的实施例。在附图中，为了清楚和具体的目的，各层和区域的大小和相对大小可能没有按照准确的比例来说明。
图1A至图1I是根据本发明的一实施例的一种碳化硅半导体功率装置的制造方法的步骤的截面图。
参考图1A，使用碳化硅(SiC)衬底100，并且SiC衬底100可以是第一导电类型衬底，并且第一导电类型例如是n型。SiC衬底100包括低压区LV和高压区HV。然后在SiC衬底100的上表面100a上形成第一导电类型第一漂移层102。在第一导电类型第一漂移层102中形成第二导电类型屏蔽区104。在本实施例中，第二导电类型是p型。第二导电类型屏蔽区104至少包括低压区LV中的连续区106和高压区HV中的多个条状区108。在本实施例中，第一导电类型第一漂移层102的掺杂浓度范围例如为1E15/cm3至5E16/cm3，第二导电类型屏蔽区104的掺杂浓度范围例如为1E17/cm3至5E18/cm3。注入于第二导电类型屏蔽区104的掺杂剂例如为选自铝、硼及锡中的至少一种。然而，本发明不限于此。在一个实施例中，第二导电类型屏蔽区104的厚度t1例如为0.1μm至0.4μm。然而，本发明不限于此。
然后，参照图1B，在第一导电类型第一漂移层102上形成第一导电类型第二漂移层110。在一个实施例中，第一导电类型第二漂移层110的掺杂浓度为第一导电类型第一漂移层102的掺杂浓度的1.2至3倍。
接着，参考图1C，在第一导电类型第二漂移层110中同时形成第二导电类型第一阱区W1和第二导电类型第二阱区W2，其中第二导电类型第一阱区W1形成在第一导电类型的MOS区中的低压区LV(例如NMOS区)，并且第二导电类型第二阱区W2形成在高压区HV中。在一个实施例中，第二导电类型第一阱区W1和第二导电类型第二阱区W2的掺杂浓度范围为1E17/cm3至6E17/cm3，第二导电类型第一阱区W1和第二导电类型第二阱区W1的厚度t2范围例如为1μm至2μm。然而，本发明不限于此。在一个实施例中，第二导电类型第一阱区W1与连续区106之间的距离例如为0.5μm至4μm。在第一导电类型第二漂移层110中同时形成第二导电类型第一拾取区112a和第二导电类型第二拾取区(如图2所示)，第二导电类型第一拾取区112a是连接至连续区106，其中低压区LV中的第一导电类型MOS区(例如NMOS)和第二导电类型MOS区(例如PMOS)被第二导电类型第一拾取区112a包围。第二导电类型第二拾取区形成在高压区HV内并在其他截面处连接到条状区108。在一个实施例中，第二导电类型第一拾取区112a和第二导电类型第二拾取区的掺杂浓度例如为2E17/cm3至5E18/cm3。然而，本发明不限于此。
接着，参考图1D，如有必要，在形成第二导电类型第一拾取区112a和第二导电类型第二拾取区的步骤之后，可以在高压区HV内的第二导电类型第二阱区W2中形成第一导电类型第一轻掺杂漏极(LDD)区114。在一个实施例中，第一导电类型第一LDD区114的掺杂浓度例如为5E17/cm3至5E18/cm3。第一导电类型第一LDD区114的深度例如为0.1μm至0.4μm。然而，本发明不限于此。
接着，参照图1E，在高压区HV的第一导电类型第二漂移层110中形成多个沟槽116，然后在每个沟槽116的表面上形成第二栅极介质层118。每个沟槽116在垂直方向形成在每个条状区108上。在一个实施例中，第二栅极介电层118的厚度t3例如为至/>然而，本发明不限于此。
接着，参照图1F，在低压区LV内的第一导电类型第二漂移层110上形成第一栅极介电层120。在一个实施例中，第一栅极介电层120的厚度t4例如为至/>然而，本发明不限于此。第二栅极介电层118是在形成第一栅极介电层120之前形成。然而，本发明不限于此。在另一实施例中，第一栅极介电层120可在形成第二栅极介电层118之前形成。对于低压区LV中的栅极和高压区HV中的沟槽栅极的形成，多晶硅层PL沉积在第一栅极介质层120上并填充沟槽116。
接着，参照图1G，可以形成图案化掩膜(未示出)以覆盖低压区LV内的部分多晶硅层PL，然后使用图案化掩膜作为刻蚀掩膜去除暴露的多晶硅层PL，同时回刻蚀高压区HV内的多晶硅层PL。因此，栅极G1和G2分别形成在第一导电类型MOS区域(例如NMOS)和第二导电类型MOS区域(例如PMOS)内的第一栅极介质层120上，并且多个沟槽栅极TG分别形成在条状区108上方的沟槽116。由于第二导电类型屏蔽区104的每个条状区108设置在形成沟槽栅极TG的每个沟槽116的底部下方，所以沟槽116底部的第二栅极介质层118高电场的问题可以解决，有效Cgd值也可以显着降低。因此，在高压区HV的功率垂直MOSFET的工作中，可以实现更好的电特性，同时也提高了沟槽116底部的氧化物可靠性。接着，可以去除图案化掩膜。
接着，参照图1H，同时形成多个HV源极区HS和多个第一源/漏极区S/D1，其中HV源极区HS形成在沟槽栅极TG之间的第二导电类型第二阱区W2中，第一源/漏极区S/D1形成在第二导电类型第一阱区W1中。在一个实施例中，形成多个HV源极区HS的步骤包括在第二导电类型MOS区(例如PMOS)内的第一导电类型第二漂移层110中形成第二体区122。同时形成第二导电类型第一重掺杂区(如图2所示)、多个第二导电类型第二重掺杂区124a和多个第二源/漏极区S/D2，其中第二导电类型第二重掺杂区124a形成在沟槽栅极TG之间并连接到第二导电类型第二阱区W2，并且第二源/漏极区S/D2形成在第二导电类型的MOS区中的第一导电类型第二漂移层110。在一个实施例中，形成第二导电类型第二重掺杂区124a的步骤包括在第二导电类型第一阱区W1中形成第一体区126。
接着，参照图1I，在第一导电类型第二漂移层110上选择性地形成绝缘层128，然后在绝缘层128中形成开口O1和O2，然后在开口O1和O2中沉积导电材料(例如金属或合金)130。HV漏电极D形成在SiC衬底100的底表面100b上。
根据本实施例的碳化硅半导体功率装置，由于第一导电类型第一漂移层102和第一导电类型第二漂移层110是由低压区LV中的第二导电类型屏蔽区104的连续区106隔离，第一导电类型第一漂移层102中的电位与第一导电类型第二漂移层110中的电位不同。第一导电类型第二漂移层110是对PMOS源极的体偏压。第二导电类型第一阱区W1被第一导电类型第二漂移层110和第二导电类型屏蔽区104的连续区106隔离，可以有效地过滤高压区HV中的功率垂直MOSFET产生的杂讯。
图2是根据所述实施例中的一例的碳化硅半导体功率装置的高压区(HV)的俯视图。图3是沿图2的线III-III'的截面图。在图2和图3中，与图1I相同或相似的标号用于表示相同或相似的部件，相同或相似部件的内容也与图1中的内容相同，故在此不再赘述。然而，这些部件的相对位置可以被调整并且与图1I中所示的不同。
参考图2和图3，存在三个沟槽栅极TG，并且形成连接部分200以连接沟槽栅极TG。连接部分200可以通过使用在关于图1G的步骤中所述的图案化掩膜来形成。如图1G所示，覆盖沟槽116外的多晶硅层。然而，本发明不限于此。可以根据需要改变沟槽栅极TG的数量和形成连接部分200的方法。第二导电类型第一重掺杂区124b形成在第一导电类型第二漂移层110中并且连接到第二导电类型第二拾取区112b。每一条状区108的一端108a延伸至第二导电类型第二阱区W2的区域外。在一个实施例中，每个条状区108的一端108a通过第二导电类型第二拾取区112b连接到第二导电类型第一重掺杂区124b。
图4是根据所述实施例中的一例的碳化硅半导体功率装置的低电区(LV)的俯视图，其中与图1I中相同或相似的标号用于表示相同或相似的部件，相同或相似部件的内容也与图1I中的内容相同，在此不再赘述。然而，这些部件的相对位置可以被调整并且与图1I中所示的不同。
如图4所示，PMOS区和NMOS区构成CMOS。在PMOS区域中，第二源/漏极区S/D2形成在每个栅极G2的两侧，并且在一个实施例中，在形成栅极G2的步骤之后(图1G的步骤之后)，可以在栅极G2与第二源/漏极区S/D2之间的第一导电类型第二漂移层中形成第二导电类型的LDD区(未示出)。在NMOS区域中，第一源/漏极区S/D1形成在每个栅极G1的两侧，并且在一个实施例中，在形成栅极G1的步骤之后(图1G的步骤之后)，第一导电类型第二LDD区(未示出)可以形成在第二导电类型第一阱区W1中的栅极G1和第一源/漏极区S/D1之间。即使栅极G1和G2的排列方向与图1中栅极G1和G2的排列方向不同，如图1G的碳化硅半导体功率装置结构中的CMOS工艺流程仍然可以通过调整光掩膜图案制造。此外，第二体区122设置在PMOS区的一侧，栅极G1和第一源/漏极区S/D1被第一体区126包围。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (19)

1.一种碳化硅半导体功率装置的制造方法，其特征在于，包括：
在碳化硅衬底的上表面上形成第一导电类型第一漂移层，其中，所述碳化硅衬底包括低压区和高压区；
在所述第一导电类型第一漂移层中形成第二导电类型屏蔽区，其中所述第二导电类型屏蔽区包括位于所述低压区的连续区和位于所述高压区的多个条状区；
在所述第一导电类型第一漂移层上形成第一导电类型第二漂移层；
在所述第一导电类型第二漂移层中同时形成第二导电类型第一阱区和第二导电类型第二阱区，其中所述第二导电类型第一阱区形成在所述低压区的第一导电类型金属氧化物半导体区中，并且所述第二导电类型第二阱区形成在所述高压区中；
在所述第一导电类型第二漂移层中同时形成与所述连续区连接的第二导电类型第一拾取区和与所述条状区连接的第二导电类型第二拾取区，其中所述第一导电类型金属氧化物半导体区和所述低压区中的第二导电类型金属氧化物半导体区被所述第二导电类型第一拾取区包围，所述第二导电类型第二拾取区形成在所述高压区内；
在所述高压区的所述第一导电类型第二漂移层中形成多个沟槽；
在所述低压区内的所述第一导电类型第二漂移层上形成第一栅极介质层，在每个所述沟槽的表面上形成第二栅极介质层；
同时在所述第一栅极介电层上形成多个栅极以及在所述多个沟槽中形成多个沟槽栅极，其中所述多个栅极分别设置在所述第一导电类型金属氧化物半导体区和所述第二导电类型金属氧化物半导体区，且所述多个沟槽栅极分别形成于所述条状区上；
同时在所述沟槽栅极之间的所述第二导电类型第二阱区中形成多个高压源极区以及在所述第二导电类型第一阱区中形成多个第一源/漏极区；以及
同时形成第二导电类型第一重掺杂区、多个第二导电类型第二重掺杂区和多个第二源/漏极区，其中所述第二导电类型第一重掺杂区形成于所述第一导电类型第二漂移层中并与所述第二导电类型第二拾取区连接，所述多个第二导电类型第二重掺杂区形成在所述沟槽栅极之间并与所述第二导电类型第二阱区连接，且所述多个第二源/漏极区形成于所述第二导电类型金属氧化物半导体区内的所述第一导电类型第二漂移层中。
2.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第一导电类型第二漂移层的掺杂浓度为所述第一导电类型第一漂移层的掺杂浓度的1.2至3倍。
3.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，每个所述条状区的一端延伸到所述第二导电类型第二阱区的区域之外。
4.根据权利要求3所述的碳化硅半导体功率装置的制造方法，其特征在于，每个所述条状区的所述端通过所述第二导电类型第二拾取区与所述第二导电类型第一重掺杂区连接。
5.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第一导电类型第一漂移层的掺杂浓度范围为1E15/cm3至5E16/cm3，所述第二导电类型屏蔽区的掺杂浓度范围为1E17/cm3到5E18/cm3。
6.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第二导电类型屏蔽区的厚度范围为0.1μm至0.4μm。
7.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第二导电类型第一阱区和所述第二导电类型第二阱区的掺杂浓度范围为1E17/cm3至6E17/cm3，以及所述第二导电类型第一阱区和所述第二导电类型第二阱区的厚度范围为1μm至2μm。
8.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第二导电类型第一拾取区和所述第二导电类型第二拾取区的掺杂浓度范围为2E17/cm3至5E18/cm3。
9.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，在形成所述第二导电类型第一拾取区和所述第二导电类型第二拾取区的步骤之后，还包括在所述高压区内的所述第二导电类型第二阱区形成第一导电类型第一轻掺杂漏极区。
10.根据权利要求9所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第一导电类型第一轻掺杂漏极区的掺杂浓度范围为5E17/cm3至5E18/cm3。
11.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第二栅极介质层的厚度范围为至/>
12.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第一栅极介质层的厚度范围为至/>
13.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第二栅极介质层在形成所述第一栅极介质层之前形成。
14.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，形成所述多个栅极和所述多个沟槽栅极的步骤包括：
在所述第一栅极介质层上沉积多晶硅层并填充所述多个沟槽；
形成图案化掩膜以覆盖所述低压区内的部分所述多晶硅层；
以所述图案化掩膜作为刻蚀掩膜，去除暴露的所述多晶硅层，同时回刻蚀所述高压区内的所述多晶硅层；以及
去除所述图案化掩膜。
15.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，形成所述第二导电类型第二重掺杂区的步骤包括在所述第二导电类型第一阱区中形成第一体区。
16.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，其中形成所述多个高压源极区的步骤包括在所述第二导电类型金属氧化物半导体区内的所述第一导电类型第二漂移层中形成第二体区。
17.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，在形成所述多个栅极的步骤之后，还包括在所述第一导电类型金属氧化物半导体区内的所述第二导电类型第一阱区形成第一导电类型第二轻掺杂漏极区。
18.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，在形成所述多个栅极的步骤之后，还包括在所述第二导电类型金属氧化物半导体区内的所述第一导电类型第二漂移层中形成第二导电类型轻掺杂漏极区。
19.根据权利要求1所述的碳化硅半导体功率装置的制造方法，其特征在于，所述第一导电类型为n型，所述第二导电类型为p型。
CN202211111882.XA 2022-07-13 2022-09-13 碳化硅半导体功率装置的制造方法 Pending CN117438311A (zh)

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