TWI813348B - 3d flash memory device - Google Patents

Abstract

A three-dimensional flash memory device includes: a substrate, a gate stack structure, a plurality of slit structures, a plurality of memory arrays, and a plurality of heating pillars. The gate stack structure is located above the substrate. The plurality of slit structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structure of the plurality of blocks. The plurality of heating pillars extends through the gate stack structure in the plurality of blocks, and disposed between the plurality of memory arrays and between the plurality of slit structures.

Description

3D flash memory device

The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular, to a flash memory element and a manufacturing method thereof.

Non-volatile memory has the advantage that stored data will not disappear even after a power outage, so it is widely used in personal computers and other electronic devices. Currently, three-dimensional memories commonly used in the industry include NOR (NOR) memory and NAND (NAND) memory. In addition, another type of three-dimensional memory is AND memory, which can be used in multi-dimensional memory arrays to have high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become a current trend. However, there are still many challenges associated with 3D memory devices.

Embodiments of the present invention propose a three-dimensional flash memory element that can form a heater between multiple memory arrays.

Embodiments of the present invention propose a manufacturing method for three-dimensional flash memory devices that can be integrated with existing processes to form heaters between multiple memory arrays.

A three-dimensional flash memory device according to an embodiment of the present invention includes: a substrate, a gate stack structure, a plurality of separation structures, a plurality of memory arrays and a plurality of conductive pillars. The gate stack structure is located above the substrate. The plurality of separation structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structures of the plurality of blocks. The plurality of conductive pillars extend through the gate stack structure in the plurality of blocks and between the plurality of memory arrays and the plurality of separation structures.

One embodiment of the present invention is a three-dimensional flash memory device with a heater that can sandwich multiple memory arrays between them.

The above-mentioned three-dimensional flash memory device may be a three-dimensional AND flash memory device, a three-dimensional NAND flash memory device or a three-dimensional NOR flash memory device.

10:Memory array

10U, 10U1, 10U2, 10U3, 10U4: Module unit

12: Charge storage layer

14: Tunnel layer

16:Channel column

20:Memory unit

28:Insulation column

32a, 32a: first conductive pillar/source pillar

32b, 32b: Second conductive pillar/drain pillar

36: Barrier layer

38: Gate layer

38: character line

40:Charge storage structure

48: Base

50:Dielectric substrate

50s: surface

54:Insulation layer

56:Middle layer

60:arrow

62: Lining

64:Barrier layer

66: Conductor layer

99:Flash memory chip

100:Heater

AR: memory array area

B. BLOCK: block

BD0, BD1, BD2, BD3, BD4: lower dielectric layer

BD2’, MD: dielectric layer

D1, D2, D3: direction

E1: first end

E2: Second end

GBL: global bit line

GSK: gate stack structure

GSL: global source line

HP: conductive pillar

LBL: local bit line

LIT: lower interconnect structure

LM1: first lower conductor layer

LM2: Second lower conductor layer

LP: lower heating plate

LP1: first lower conductor block

LP2: Second lower conductor block

LSL: local source line

LW1, LW2, UW1, UW2: Wires

P1:Part One

P2:Part Two

P3:Part Three

PR:surrounding area

SC: ladder structure

SK1: Middle stack structure

SLT: separated structure

SR: Staircase area

T: block element

T1: The first dollar

T2: The second dollar

TAV1, TAV2: array perforation

TD0, TD1, TD2, TD3: upper dielectric layer

UIT: upper inner wiring structure

UM1: first upper conductor layer

UM2: Second upper conductor layer

UP: upper heating plate

UP1: The first upper conductor block

UP2: Second upper conductor block

V1: first via window

V2: Second via window

VAA: via window

I-I’, II-II’: Tangent line

BLOCK, BLOCK ⁽ⁱ⁾ , BLOCK ⁽ⁱ⁺¹⁾ : block

BL _n , BL _n+1 : bit lines

SP ⁽ⁱ⁾ _n , SP ⁽ⁱ⁾ _n+1 , SP ⁽ⁱ⁺¹⁾ _n , SP ⁽ⁱ⁺¹⁾ _n+1 : source pillar

DP ⁽ⁱ⁾ _n , DP ⁱ⁾ _n+1 , DP ⁱ⁺¹⁾ _n , DP ⁽ⁱ⁺¹⁾ _n+1 : source column

WL ⁽ⁱ⁾ _m , WL ⁽ⁱ⁾ _m+1 , WL ⁽ⁱ⁺¹⁾ _m , WL ⁽ⁱ⁺¹⁾ _m+1 : character line

Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments of the invention.

FIG. 1B shows a partial three-dimensional view of part of the memory array of FIG. 1A.

1C and 1D show cross-sectional views along the tangent line I-I' in FIG. 1B.

Figure 1E shows a top view along the tangent line II-II' of Figures 1B, 1C and 1D.

1F-1K show various schematic diagrams of a 3D AND flash memory with a heater according to some embodiments of the present invention.

2A to 2G are a three-dimensional AND flash according to an embodiment of the present invention. Schematic cross-section of the memory device manufacturing process.

Figure 3 shows a schematic diagram of portions of a 3D AND flash memory with a heater according to some embodiments of the invention.

Figure 4 shows a top view of a three-dimensional AND flash memory wafer according to some embodiments of the present invention.

Figure 1A shows a circuit diagram of a 3D AND flash memory array in accordance with some embodiments. FIG. 1B shows a partial three-dimensional view of part of the memory array of FIG. 1A. 1C and 1D show cross-sectional views along the tangent line I-I' in FIG. 1B. Figure 1E shows a top view along the tangent line II-II' of Figures 1B, 1C and 1D.

FIG. 1A is a schematic diagram of two blocks BLOCK ⁽ⁱ⁾ and BLOCK ⁽ⁱ⁺¹⁾ including a vertical AND memory array 10 configured in columns and rows. Block BLOCK ⁽ⁱ⁾ includes memory array A ⁽ⁱ⁾ . One column (for example, the m+1-th column) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common word line (for example, WL ⁽ⁱ⁾ _m+1 ). The AND memory cells 20 in each column (for example, the m+1th column) of the memory array A ⁽ⁱ ) correspond to a common word line (for example, WL ⁽ⁱ⁾ _m+1 ) and are coupled to different source columns. (for example, SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain posts (for example, DP ⁽ⁱ⁾ _n and DP (i) _n+1 ), so that the AND memory cells 20 are along a common word line (for example, DP (i) n and DP ⁽ⁱ⁾ n+1 ). WL ⁽ⁱ⁾ _m+1 ) are logically arranged in one column.

One row (for example, the nth row) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common source column (for example, SP ⁽ⁱ⁾ _n ) and a common drain column (for example, DP ⁽ⁱ⁾ _n ). The AND memory cells 20 of each row (for example, the nth row) of the memory array A ⁽ⁱ⁾ correspond to different word lines (for example, WL ⁽ⁱ⁾ _m+1 and WL ⁽ⁱ⁾ _m ), and are coupled to a common The source column (such as SP ⁽ⁱ⁾ _n ) and the common drain column (such as DP ⁽ⁱ⁾ _n ). Therefore, the AND memory cells 20 of memory array A ⁽ⁱ⁾ are logically arranged in a row along a common source column (eg, SP ⁽ⁱ⁾ _n ) and a common drain column (eg, DP ⁽ⁱ⁾ _n ). In a physical layout, depending on the manufacturing method applied, rows or columns may be twisted, configured in a honeycomb pattern or otherwise for high density or other reasons.

In FIG. 1A , in block BLOCK ⁽ⁱ⁾ , the AND memory cells 20 in the nth row of memory array A ⁽ⁱ⁾ share a common source column (for example, SP ⁽ⁱ⁾ _n ) and a common drain column. (e.g. DP ⁽ⁱ⁾ _n ). The AND memory cells 20 in the n+1th row share a common source column (for example, SP ⁽ⁱ⁾ _n+1 ) and a common drain column (for example, DP ⁽ⁱ⁾ _n+1 ).

A common source pillar (eg SP ⁽ⁱ⁾ _n ) is coupled to a common source line (eg SL _n ); a common drain pillar (eg DP ⁽ⁱ⁾ _n ) is coupled to a common bit line (eg BL _n ). A common source column (such as SP ⁽ⁱ⁾ _n+1 ) is coupled to a common source line (such as SL _n+1 ); a common drain column (such as DP ⁽ⁱ⁾ _n+1 ) is coupled to a common bit line (for example, BL _n+1 ).

Similarly, block BLOCK ⁽ⁱ⁺¹⁾ includes memory array A ⁽ⁱ⁺¹⁾ , which is similar to memory array A ^{(i) in block BLOCK(i) .} One column (for example, the m+1th column ^{) of the memory array A (i+1} ) is a set of AND memory cells 20 having a common word line (for example, WL ⁽ⁱ⁺¹⁾ _m+1 ). The AND memory cells 20 of each column (for example, the m+1th column) of the memory array A ⁽ⁱ⁺¹ ) correspond to a common word line (for example, WL ⁽ⁱ⁺¹⁾ _m+1 ) and are coupled to different The source pillars (such as SP ⁽ⁱ⁺¹⁾ _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and the drain pillars (such as DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (for example, the nth row) of the memory array A ⁽ⁱ⁺¹⁾ has a common source column (for example, SP ⁽ⁱ⁺¹⁾ _n ) and a common drain column (for example, DP ⁽ⁱ⁺¹⁾ _n ). A set of AND memory units 20, which are connected in parallel with each other, are also called memory strings. The AND memory cells 20 of each row (for example, the nth row) of the memory array A ⁽ⁱ⁺¹⁾ correspond to different word lines (for example, WL ⁽ⁱ⁺¹⁾ _m+1 and WL ⁽ⁱ⁺¹⁾ _m ). , and coupled to a common source post (eg SP ⁽ⁱ⁺¹⁾ _n ) and a common drain post (eg DP ⁽ⁱ⁺¹⁾ _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁺¹⁾ are logically configured along the common source column (for example, SP ⁽ⁱ⁺¹⁾ _n ) and the common drain column (for example, DP ⁽ⁱ⁺¹⁾ _n ). One line.

Block BLOCK ⁽ⁱ⁺¹⁾ and block BLOCK ⁽ⁱ⁾ share source lines (eg, SL _n and SL _n+1 ) and bit lines (eg, BL _n and BL _n+1 ). Therefore, the source line SL _n and the bit line BL _n are coupled to the nth row of AND memory cells 20 in the AND memory array A (i) of the block BLOCK ^{( i)} , and are coupled to the block BLOCK ^{(i +1)} and the nth row AND memory cell 20 in the AND memory array A ⁽ⁱ⁺¹⁾ . Similarly, the source line SL _n+1 and the bit line BL _n+1 are coupled to the n+1th row AND memory cell 20 in the AND memory array A ⁽ⁱ⁾ of the block BLOCK ⁽ⁱ ), and are coupled to To the n+1th row AND memory unit 20 in the AND memory array A ( ^{i+1) in the block BLOCK ( i+1} ).

Referring to FIGS. 1B-1D , the memory array 10 may be disposed on an interconnect structure of a semiconductor die, such as one or more active devices (eg, transistors) formed on a semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed over a metal interconnect structure on a silicon substrate. The memory array 10 may include a gate stack structure GSK, a plurality of channel pillars 16, a plurality of first conductive pillars (also called source pillars) 32a, and a plurality of second conductive pillars (also called drain pillars) 32b and a plurality of charge storage structures 40.

Referring to FIG. 1B , the gate stack structure GSK is formed on the dielectric substrate 50 in the memory array area. The gate stack structure GSK is included on the surface 50s of the dielectric substrate 50 A plurality of vertically stacked gate layers (also called word lines) 38 and a multi-layer insulating layer 54 are formed on the substrate. In the Z direction, the gate layers 38 are electrically isolated by the insulating layer 54 disposed between them. Gate layer 38 extends in a direction parallel to the surface of dielectric substrate 50 . Gate layer 38 may have a stepped structure (not shown). Therefore, the lower gate layer 38 is longer than the upper gate layer 38 , and the end of the lower gate layer 38 laterally extends beyond the end of the upper gate layer 38 . Contacts (not shown) for connecting the gate layers 38 may land on the ends of the gate layers 38 to connect each gate layer 38 to the respective conductors.

Referring to FIGS. 1B to 1D , the memory array 10 further includes a plurality of channel columns 16 stacked in the Z direction. In some embodiments, channel post 16 may have an annular profile when viewed from above. The material of the channel pillar 16 may be a semiconductor material, such as undoped polycrystalline silicon.

Referring to FIGS. 1B to 1D , the memory array 10 further includes an insulating pillar 28 , a plurality of first conductive pillars 32 a and a plurality of second conductive pillars 32 b. In this example, the first conductive pillar 32a serves as the source pillar; the second conductive pillar 32b serves as the drain pillar. The first conductive pillar 32a, the second conductive pillar 32b and the insulating pillar 28 each extend in a direction perpendicular to the surface of the gate layer 38 (ie, the Z direction). The first conductive pillar 32a and the second conductive pillar 32b are separated by the insulating pillar 28. The first conductive pillar 32a and the second conductive pillar 32b are electrically connected to the channel pillar 16. The first conductive pillar 32a and the second conductive pillar 32b include doped polycrystalline silicon or metal material. The insulating pillar 28 is made of silicon nitride, for example.

Referring to FIG. 1C and FIG. 1D , the charge storage structure 40 is disposed between the channel pillar 16 and the multi-layer gate layer 38 . The charge storage structure 40 may include a tunnel layer (also known as a bandgap engineered tunnel oxide layer) 14 , a charge storage layer 12 and a barrier layer 36 . The charge storage layer 12 is located between the tunneling layer 14 and the barrier layer 36 . In some embodiments, tunneling layer 14 and barrier layer 36 include silicon oxide. Charge storage layer 12 includes silicon nitride, or other materials that can capture electrical charges. In some embodiments, as shown in FIG. 1C , a portion of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12 ) continuously extends in a direction perpendicular to the gate layer 38 (ie, the Z direction), and the charge storage Another portion of structure 40 (barrier layer 36 ) surrounds gate layer 38 . In other embodiments, as shown in FIG. 1D , the charge storage layer 12 and barrier layer 36 of the charge storage structure 40 surround the gate layer 38 .

Referring to FIG. 1E , the charge storage structure 40 , the channel pillar 16 , the source pillar 32 a and the drain pillar 32 b are surrounded by the gate layer 38 and define the memory cell 20 . The memory unit 20 can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column 32a and the drain column 32b, since the source column 32a and the drain column 32b are connected to the channel column 16, electrons can be transported along the channel column 16 and stored in the entire charge storage. In the structure 40, in this way, a 1-bit operation can be performed on the memory unit 20. In addition, for operations utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and the drain post 32b. . For source side injection, channel-hot-electron injection or band-to-band tunneling hot carrier injection operations, the electrons can be Or the holes are locally trapped in the charge storage structure 40 adjacent to one of the two source pillars 32a and drain pillars 32b, so that the memory cell 20 can be processed into unit cell (SLC, 1 bit) or multiple Bit unit cell (MLC, greater than or equal to 2 bits) operations.

Referring to FIGS. 1A and 1B , during operation, a voltage is applied to the selected word line (gate layer) 38 , for example, when a voltage higher than the corresponding starting voltage (V _th ) of the corresponding memory cell 20 is applied, and The channel pillar 16 intersecting the selected word line 38 is turned on, allowing current from the bit line BL _n or BL _n+1 (shown in FIG. 1B ) to enter the drain pillar 32 b and flow to the source through the turned on channel region. Post 32a (eg, in the direction indicated by arrow 60), ultimately flows to source line _SLn or SLn ₊₁ (shown in Figure 1B).

1F to 1K show various schematic diagrams of a 3D AND flash memory with a heater 100 according to some embodiments of the present invention. For the sake of clarity, some components are not shown in Figures 1F to 1K.

Referring to FIG. 1F , the 3D AND flash memory according to the embodiment of the present invention further includes a heater 100 . The heater 100 is a micro heater, which is disposed in the memory array area AR. The heater 100 surrounds the plurality of memory arrays 10 in the memory array area AR to heat the plurality of memory cells of the plurality of memory arrays 10 nearby. Damaged memory cells can be repaired through heating and tempering by the heater 100 .

Referring to FIG. 1I , the heater 100 passes through the gate stack structure GSK having a plurality of memory arrays 10 and then extends above and below the gate stack structure GSK. The heater 100 can heat a single block B or multiple blocks B at the same time, such as 4 blocks, 8 blocks (as shown in Figure 1K), 16 blocks or 32 blocks, but not Limited to this.

Referring to FIG. 1F and FIG. 1G , the heater 100 is, for example, in the shape of a snake. More specifically, the heater 100 includes a plurality of first parts P1, a plurality of second parts P2, and a plurality of third parts P3 connected to each other. The second part P2 is located between the first part P1 and the third part P3. The first part P1 and the third part P3 partially overlap, and the overlapping parts are connected by a plurality of second parts P2. The first part P1 includes the lower heating plate LP. The second part P2 includes conductive pillars (also called heating pillars) HP. The third part P3 includes the upper heating plate UP.

Referring to Figure 1F and Figure 1G, the plurality of conductive pillars HP are arranged in the memory array Column 10 around. The plurality of conductive pillars HP sandwich the plurality of memory arrays 10 therebetween. In some embodiments, in the first direction D1, the plurality of conductive pillars HP and the plurality of memory arrays 10 are alternately arranged.

Referring to FIGS. 1H and 1K , the plurality of conductive pillars HP are separated by a plurality of separation structures SLT and are laterally adjacent to the plurality of separation structures SLT. The plurality of separation structures SLT extend in the first direction D1 and divide the gate stack structure GSK into a plurality of blocks B (for example, B1, B2, B3, and B4). A plurality of conductive pillars HP of the heater 100 are located in the plurality of blocks B (for example, B1, B2, B3, B4) and extend through the gate stack structure GSK. In some embodiments, in the second direction D2, the plurality of conductive pillars HP and the plurality of separation structures SLT are alternately arranged. The second direction D2 is different from the first direction D1. The second direction D2 and the first direction D1 are, for example, perpendicular to each other. The first direction D1 is, for example, the X direction, and the second direction D2 is, for example, the Y direction.

1F and 1H, in some embodiments, each memory array 10 and the two rows of conductive pillars HP on both sides and the lower interconnection structure LIT and the upper interconnection structure UIT above and below can be called a module. Group unit 10U. Therefore, in Figure 1H, there are four module units 10U1, 10U2, 10U3 and 10U4 between the ladder structures SC. However, the present invention is not limited thereto. In each module unit 10U, more or fewer rows of conductive pillars HP may be included on both sides of each memory array 10 . In addition, the number of conductive pillars HP on both sides of each module unit 10U may be the same or different. The plurality of conductive pillars HP on both sides of each module unit 10U can be arranged in an array or in a non-array.

Referring to FIGS. 1I and 1J , the plurality of conductive pillars HP are disposed in the memory array area AR between the ladder structures SC. The conductive pillar HP and the plurality of source electrodes Post 32a is laterally adjacent the plurality of drain posts 32b. The plurality of conductive pillars HP sandwich the plurality of source pillars 32a and the plurality of drain pillars 32b therebetween.

Refer to Figure 1H and Figure 1J. The step of forming the plurality of conductive pillars HP can be performed simultaneously with other processes. For example, in some embodiments, the 3D AND flash memory further includes a plurality of array through holes TAV1 and TAV2. The plurality of array through holes TAV1 are disposed in the step region SR and pass through the step structure SC of the gate stack structure GSK. The plurality of array through holes TAV2 are disposed in the peripheral region PR and pass through the insulating material or dielectric material in the peripheral region PR. The plurality of conductive pillars HP may be formed at the same time or not at the same time as the plurality of array through holes TAV1 and TAV2.

Referring to FIG. 1G , the lower heating plate LP of the heater 100 is disposed below the conductive pillar HP and the gate stack structure GSK. The lower heating plate LP may be part of the lower interconnect structure LIT disposed below the gate stack structure GSK. The upper heating plate UP of the heater 100 is disposed above the conductive pillar HP and the gate stack structure GSK. The upper heating plate UP may be part of the upper interconnect structure UIT disposed above the gate stack structure GSK.

Referring to FIGS. 1F and 1G , in some embodiments, the lower heating plate LP may be part of a single conductor layer of the lower interconnect structure LIT. The upper heating plate UP may be part of a single conductor layer of the upper interconnect structure UIT. In other embodiments, the lower heating plate LP includes a portion of two or more conductor layers of the lower interconnect structure LIT and a plurality of via windows (not shown) located between the conductor layers. The upper heating plate UP includes a portion of two or more conductor layers of the upper interconnect structure UIT and a plurality of via windows (not shown) located between the conductor layers.

1I and 1J, specifically, the lower heating plate LP includes a portion of the first lower conductor layer LM1 and the second lower conductor layer LM2 of the lower interconnect structure LIT. and a plurality of first vias V1. The upper heating plate UP includes a part of the first upper conductor layer UM1 and a part of the second upper conductor layer UM2 of the lower interconnect structure LIT and a plurality of second via windows V2.

Referring to FIG. 1J , the first lower conductor layer LM1 is located between the substrate 48 and the gate stack structure GSK. The second lower conductor layer LM2 is located between the first lower conductor layer LM1 and the gate stack structure GSK. No other conductor layer may be included between the first lower conductor layer LM1 and the base 48 . However, the present invention is not limited to this. Other conductor layers (not shown) may also be included between the first lower conductor layer LM1 and the substrate 48 .

Referring to FIG. 1K and FIG. 2A , the first lower conductor layer LM1 includes a plurality of first lower conductor blocks LP1 separated from each other. Each first lower conductor block LP1 extends in the first direction D1 and the second direction D2. In some embodiments, each first lower conductor block LP1 spans the plurality of blocks B (for example, B1 to B8), so that part of the plurality of memory arrays in the plurality of blocks B 10. Part of the plurality of conductive pillars HP and part of the plurality of separation structures SLT may be disposed directly above it, as shown in Figure 2D. In other embodiments, each first lower conductor block LP1 spans a single block B. In some embodiments, each first lower conductor block LP1 spans other numbers of blocks B, such as 16 blocks.

Referring to FIGS. 1K and 2C , the second lower conductor layer LM2 includes a plurality of second lower conductor blocks LP2 separated from each other. Each second lower conductor block LP2 extends in the first direction D1 and the second direction D2. In some embodiments, each second lower conductor block LP2 spans the plurality of blocks B (for example, B1 to B8), so that part of the plurality of memory arrays 10 in the plurality of blocks B , part of the plurality of conductive pillars HP and part of the plurality of separation structures SLT may be disposed directly above them and make the plurality of conductive Pillars HP land on each second lower conductor block LP2 as shown in Figure 2D. In other embodiments, each second lower conductor block LP2 spans a single block B. In some embodiments, each second lower conductor block LP2 spans other numbers of blocks B, such as 16 blocks.

Referring to FIGS. 1I and 1J , the plurality of first vias V1 are located between the plurality of first lower conductor blocks LP1 and the plurality of second lower conductor blocks LP2 and are connected to each other. In other words, the plurality of first lower conductor blocks LP1 and the plurality of second lower conductor blocks LP2 are connected in parallel through the plurality of first via windows V1. The plurality of first lower conductive blocks LP1 , the plurality of second lower conductive blocks LP2 and the plurality of first vias V1 form the lower heating plate LP of the heater 100 .

Referring to FIG. 1J , the lower dielectric layer BD4 is located between the gate stack structure GSK and the second lower conductor layer LM2. The upper dielectric layer TDO is located between the gate stack structure GSK and the first upper conductor layer UM1. The plurality of source pillars 32a and the plurality of drain pillars 32b are located between the lower dielectric layer BD4 and the upper dielectric layer TDO. The plurality of conductive pillars HP also extend through the lower dielectric layer BD4 and the upper dielectric layer TDO. The length of the conductive pillar HP is greater than the length of the source pillar 32a and the drain pillar 32b. Therefore, the conductive pillars HP laterally adjacent to the plurality of source pillars 32a and the plurality of drain pillars 32b may connect the plurality of source pillars 32a, the plurality of drain pillars 32b to a plurality of The memory cell 20 formed by the intersection of the gate layers 38 is completely heated.

Referring to FIGS. 1I to 1K , the upper interconnect structure UIT includes upper dielectric layers TD1, TD2, TD3 and a first upper conductor layer UM1, a second upper conductor layer UM2 and a plurality of second via windows located therein. V2. The first upper conductor layer UM1 is located above the gate stack structure GSK. The second upper conductor layer UM2 is located above the first upper conductor layer UM1. The plurality of second vias V2 are located in the The first upper conductor layer UM1 and the second upper conductor layer UM2 are electrically connected to each other.

Referring to FIGS. 1J and 1K , the first upper conductor layer UM1 includes a plurality of first upper conductor blocks UP1 separated from each other, and the plurality of first upper conductor blocks UP1 are electrically connected to the plurality of conductive pillars HP below. sexual connection. Referring to FIGS. 1K and 2E , each first upper conductor block UP1 extends in the first direction D1 and the second direction D2. In some embodiments, each first upper conductor block UP1 spans the plurality of blocks B (for example, B1 ~ B8) to cover the plurality of blocks B shown in FIG. 1K and FIG. 2D . Part of the plurality of memory arrays 10 , part of the plurality of conductive pillars HP and part of the plurality of separation structures SLT. In other embodiments, each first upper conductor block UP1 spans a single block B. In some embodiments, each first upper conductor block UP1 spans other numbers of blocks B, such as 16 blocks.

Referring to FIG. 1I , in some embodiments, each second lower conductor block LP2 is covered by two first upper conductor blocks UP1 that are separated from each other. The area of the first upper conductive block UP1 is smaller than the area of the corresponding second lower conductive block LP2.

Referring to FIGS. 1I and 2E , the first upper conductor layer UM1 further includes a plurality of local source lines LSL and a plurality of local bit lines LBL extending in the second direction D2. A plurality of local source lines LSL connects the plurality of source pillars 32a shown in FIG. 1I or 2D. A plurality of local bit lines LBL are connected to the plurality of drain posts 32b shown in FIG. 1I or 2D. A plurality of local source lines LSL and a plurality of local bit lines LBL are located between the plurality of first upper conductor blocks UP1. In Figures 1J and 2E, in some embodiments, each memory array 10 and the two rows of conductive pillars HP on both sides and the lower interconnection structure LIT and the upper interconnection structure UIT above and below can be called a module. Group unit 10U. The present invention is not limited thereto. In each module unit 10U, more or fewer rows of conductive pillars HP may be included on both sides of each memory array 10 . every The two rows of conductive pillars HP on both sides of the module unit 10U are connected to the two first upper conductor blocks UP1. Two rows of conductive pillars HP on both sides of each module unit 10U are connected to a second lower conductor block LP2.

In Figure 1H, in some embodiments, four module units 10U1, 10U2, 10U3 and 10U4 are included between two ladder structures SC. However, the embodiments of the present invention are not limited thereto. In other embodiments, fewer (eg, 2) module units 10U may be included between the two ladder structures SC. In other embodiments, more (for example, 4, 8, 16 or 32) module units 10U may be included between the two ladder structures SC.

Referring to FIG. 1K and FIG. 2G, the second upper conductor layer UM2 is located above the first upper conductor layer UM1. The second upper conductor layer UM2 includes a plurality of second upper conductor blocks UP2 separated from each other. Each second upper conductive block UP2 extends in the first direction D1 and the second direction D2. In some embodiments, each second upper conductor block UP2 spans the plurality of blocks B (for example, B1 to B8) in the second direction D2. In this way, the plurality of second upper conductor blocks UP2 covers the plurality of first upper conductor blocks UP1. In some embodiments, each second upper conductor block UP2 spans a single block B (for example, B1~B8). In this way, the plurality of second upper conductor blocks UP2 cover the plurality of first blocks B. Upper conductor block UP1. In some embodiments, each second upper conductor block UP2 spans other numbers of blocks B, such as 16 blocks. In this way, the plurality of second upper conductor blocks UP2 cover the plurality of blocks B. The first upper conductor block UP1. Furthermore, in some embodiments, each second upper conductor block UP2 in the central area covers two adjacent first upper conductor blocks UP1 of two adjacent module units 10U; each second upper conductor block UP1 in the edge area covers Two upper conductor blocks UP2 cover a single first upper conductor block UP1.

Referring to Figure 1I, Figure 1J, Figure 1K and Figure 2F, a plurality of second via windows V2 It is located between and connected to the plurality of first upper conductor blocks UP1 and the plurality of second upper conductor blocks UP2. In other words, the plurality of first upper conductive blocks UP1 and the plurality of second upper conductive blocks UP2 are connected in parallel with each other through the plurality of second vias V2. The plurality of first upper conductor blocks UP1 , the plurality of second upper conductor blocks UP2 and the plurality of second vias V2 form an upper heating plate UP of the heater 100 . In other words, each upper heating plate UP is shared by two adjacent module units 10U.

Referring to FIGS. 1J and 2G , the second upper conductor layer UM2 further includes a plurality of global source lines GSL and a plurality of global bit lines GBL extending in the second direction D2. A plurality of global source lines GSL are connected to the local source lines LSL through the second via window V2. A plurality of global bit lines GBL are connected to the local bit lines LBL through the second via window V2. The plurality of global source lines GSL and the plurality of global bit lines GBL are located between the plurality of second upper conductor blocks UP2.

Referring to FIG. 1K , FIG. 2C and FIG. 2F , the area of the first upper conductor block UP1 is smaller than the area of the corresponding second lower conductor block LP2 .

Referring to FIG. 2B , the plurality of first vias V1 connected to each first lower conductor block LP1 may be arranged in a first array. Referring to FIG. 2F , the plurality of second vias V2 connected to each first upper conductor block UP1 may be arranged into a second array. The number of the plurality of first vias V1 in the first array is greater than the number of the plurality of second vias V2 in the second array. However, the present invention is not limited to this. The plurality of first vias V1 may be arranged in a non-array, and the plurality of second vias V2 may also be arranged in a non-array.

Each lower heating plate LP is connected in series with the upper heating plate UP via a plurality of conductive pillars HP. The upper heating plate UP connects the plurality of conductive pillars HP of the two adjacent module units 10U1. Thereby, the plurality of lower heating plates LP, the plurality of conductive pillars HP and the plurality of upper heating plates UP may form the heater 100.

Referring to FIG. 1J , the heater 100 is shaped like a greedy snake and can surround multiple memory arrays 10 in multiple module units 10U to heat these memory arrays 10 nearby. During the repair process, the current may enter from the first end E1 of the heater 100, pass through the heater 100, and then flow out from the second end E2 of the heater 100.

2A to 2G are schematic cross-sectional views of a manufacturing process of a three-dimensional AND flash memory device according to an embodiment of the present invention.

Referring to Figures 1J and 2A, a substrate 48 is provided. The substrate 48 may also include a component layer (not shown) on the semiconductor substrate. The component layer may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide half (NMOS) transistor, a P-type metal oxide half (PMOS) transistor, or a complementary metal oxide half element (CMOS). For example, the component layer may include a page buffer.

Referring to FIG. 1J , a lower interconnect structure LIT is formed on the element layer of the substrate 48 . First, a lower dielectric layer BD0 is formed on the element layer, and a plurality of conductor plugs (not shown) are formed in the lower dielectric layer BD0. The lower dielectric layer BDO is, for example, silicon oxide. The plurality of conductor plugs may extend through the lower dielectric layer BDO to connect the component layer. The conductor plug includes a conductor layer and a barrier layer surrounding the conductor layer. The conductor layer is, for example, tungsten. The barrier layer may be titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof.

Referring to FIGS. 1J and 2A , a conductor layer is then formed on the lower dielectric layer BD0 and patterned through photolithography and etching processes to form a first lower conductor layer. LM1. The first lower conductor layer LM1 includes a plurality of first lower conductor blocks LP1 and a plurality of conductive lines LW1 that are separated from each other. The material of the conductor layer includes metal, such as copper.

Referring to FIG. 1J , a lower dielectric layer BD1 is formed on the first lower conductor layer LM1. The lower dielectric layer BD1 is, for example, silicon oxide. Afterwards, a chemical mechanical polishing process may be performed to planarize the lower dielectric layer BD1.

Referring to FIG. 1J , next, a lower dielectric layer BD2 is formed on the lower dielectric layer BD1 and the first lower conductor layer LM1 . Next, referring to FIGS. 1J and 2B , a plurality of first via windows V1 connected to the plurality of first lower conductive blocks LP1 are formed in the lower dielectric layer BD2 . The plurality of first vias V1 include conductor material, such as tungsten. The formation method of the plurality of first via windows V1 is, for example, forming a plurality of via holes in the lower dielectric layer BD2, and then forming a conductor material on the lower dielectric layer BD2 and filling the in multiple via holes. Afterwards, a chemical mechanical polishing process or an etch-back process is performed to remove excess conductive material on the lower dielectric layer BD2.

Referring to FIGS. 1J and 2C , a conductor layer is formed on the lower dielectric layer BD2 and the plurality of first via windows V1 , and is patterned through a photolithography and etching process to form a second lower conductor layer LM2 . The second lower conductor layer LM2 includes a plurality of second lower conductor blocks LP2 and a plurality of conductive wires LW2 that are separated from each other. The material of the conductor layer includes metal, such as copper.

Referring to FIG. 1J, after that, a lower dielectric layer BD3 is formed on the second lower conductor layer LM2. The lower dielectric layer BD3 can be planarized through a chemical mechanical polishing process. The lower dielectric layer BD3 is, for example, silicon oxide. After that, a lower dielectric layer BD4 is formed on the lower dielectric layer BD3 and the second lower conductor layer LM2. The lower dielectric layer BD4 can be planarized through a chemical mechanical polishing process. The lower dielectric layer BD4 is, for example, silicon oxide. At this point, the manufacturing of the lower interconnect structure LIT is completed. However, the embodiments of the present invention are not limited thereto. The formation method of the lower interconnect structure LIT is not limited to the above. In other embodiments, the second lower conductor layer LM2 and the plurality of first vias V1 may be formed using a dual damascene method. That is, the dielectric layer BD2' may be formed first. Afterwards, an opening with a trench and a via hole is formed in the dielectric layer BD2'. After that, barrier material and conductor material are backfilled in the opening to simultaneously form the second lower conductor layer LM2 and the plurality of first via windows V1. The conductor material is, for example, tungsten. The barrier material is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. In addition, the lower interconnect structure LIT may include more lower conductor layers and lower dielectric layers.

1J and 2D, then, a plurality of memory arrays 10 and a plurality of separation structures SLT are formed on the lower dielectric layer BD4. The memory array 10 includes a gate stack structure GSK. The gate stack structure GSK in the step region SR has a plurality of step structures SC, and the step structures SC are covered by the dielectric layer MD (as shown in FIG. 1J ). The memory array 10 also includes a plurality of charge storage structures 40, a plurality of channel pillars 16, a plurality of source pillars 32a and a plurality of drain pillars 32b. The plurality of channel pillars 16 , the plurality of source pillars 32 a and the plurality of drain pillars 32 b extend through the gate stack structure GSK of the memory array area AR between the plurality of ladder structures SC. The charge storage structures 40 are located between the gate layers 38 and the channel pillars 16 . The plurality of separation structures SLT extend in the first direction D1 and divide the gate stack structure GSK into a plurality of blocks B. The memory array 10 and the plurality of partition structures SLT may It can be formed by any known method and will not be described in detail here.

Referring to FIGS. 1J and 2E , an upper dielectric layer TD0 of the upper interconnect structure UIT is formed above the substrate 48 . The upper dielectric layer TDO covers the memory array 10 in the memory array area AR and the dielectric layer MD in the step area SR.

Referring to FIG. 3 , the upper dielectric layer TDO also covers the middle stack structure SK1 in the peripheral region PR. The intermediate stack structure SK1 includes a plurality of intermediate layers 56 and the plurality of insulating layers 54 that are alternately stacked. The plurality of intermediate layers 56 in the memory array area AR undergoes a replacement process to form the plurality of gate layers 38 . The plurality of intermediate layers 56 in the peripheral region PR are not replaced during the replacement process but remain. The upper dielectric layer TDO is, for example, silicon oxide.

1J, 2D and 3, then, a plurality of via windows VAA (shown in FIG. 1J), a plurality of contact windows (not shown), a plurality of conductive pillars HP and a plurality of array through holes TAV1 (shown in Figure 1J and Figure 2), TAV2 (shown in Figure 3, similar to TAV2 in Figure 1H).

Referring to FIG. 1J, the plurality of via windows VAA extend through the upper dielectric layer TDO in the memory array area AR, and land on the plurality of source pillars 32a and the plurality of drain pillars 32b. and electrically connected to it.

The plurality of contact windows (not shown) extend through the upper dielectric layer TDO and the dielectric layer MD in the stepped region SR, and land on the ends of the plurality of gate layers 38 of the stepped structure SC and with them. Electrical connection.

Referring to FIGS. 1J , 2D and 3 , the plurality of array through holes TAV1 extend through the upper dielectric layer TD0, the dielectric layer MD, and the ladder structure SC in the step region SR. The plurality of gate layers 38, the plurality of insulating layers 54 and the lower dielectric layer BD4. Each array through hole TAV1 can land on one of the plurality of conductive lines LW2 of the second lower conductor layer LM2 and be electrically connected thereto.

Referring to FIG. 3 , a plurality of array through holes TAV2 extends through the upper dielectric layer TD0 on the peripheral region PR, the plurality of intermediate layers 56 of the middle stack structure SK1 and the plurality of insulating layers 54 and the lower dielectric layer BD4. Each array through hole TAV2 may land on and be electrically connected to another one of the conductive lines LW2 of the second lower conductor layer LM2.

1J, 2D and 3, the plurality of conductive pillars HP extend through the upper dielectric layer TDO in the memory array area AR, the plurality of gate layers 38 and the gate stack structure GSK. The plurality of insulating layers 54 and the lower dielectric layer BD4 land on the plurality of second lower conductor blocks LP2 of the second lower conductor layer LM2 and are electrically connected thereto.

In some embodiments, the plurality of vias VAA, the plurality of contact windows (not shown), and the plurality of array through holes TAV2 may include conductor layers. In other embodiments, the plurality of vias VAA, the plurality of contact windows (not shown), and the plurality of array through holes TAV2 may include a conductor layer 66 and a barrier surrounding the conductor layer 66 Layer 64. Conductor layer 66 is, for example, tungsten. Barrier layer 64 is, for example, titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof. Since the plurality of via windows VAA, the plurality of contact windows (not shown), and the plurality of array through holes TAV2 are surrounded by insulating materials (ie: the upper dielectric layer TDO, the middle stack structure The plurality of intermediate layers 56 of SK1, the plurality of insulating layers 54 and the lower dielectric layer BD4), therefore, in the conductive There is no need to form a liner around the body layer 66 (or further including the barrier layer 64). The plurality of vias VAA, the plurality of contact windows (not shown), and the plurality of array through holes TAV2 can be formed simultaneously or individually, and the method of forming them can be the same as that of the plurality of first vias. The formation methods of window V1 are similar or different.

Referring to FIG. 3 , since the plurality of conductive pillars HP and the plurality of array through holes TAV1 extend through the plurality of gate layers 38 , in addition to the conductor layer 66 (or further including the barrier layer 64 ), A liner layer 62 is also included to electrically insulate the plurality of gate layers 38 . The lining layer 62 is, for example, silicon oxide, silicon nitride or a combination thereof.

The formation method of the plurality of conductive pillars HP and the plurality of array through holes TAV1 is, for example, forming extending through the upper dielectric layer TDO and the plurality of gate electrode layers in the memory array area AR and the step area SR. 38. The plurality of insulating layers 54 and the plurality of openings in the lower dielectric layer BD4. Next, a lining material, a barrier material and a conductor material are first formed in the upper dielectric layer TDO and the plurality of openings. Afterwards, an etch back or chemical mechanical polishing process is performed to remove excess lining material, barrier material and conductor material.

Referring to FIGS. 1J and 2E , other parts of the upper interconnect structure UIT are then formed above the substrate 48 . A conductor layer is formed on the upper dielectric layer TD0 and patterned through photolithography and etching processes to form a first upper conductor layer UM1. The first upper conductive layer UM1 includes a plurality of first upper conductive blocks UP1 separated from each other, a plurality of local source lines LSL, a plurality of local bit lines LBL, and a plurality of conductive lines UW1. The material of the conductor layer includes metal, such as copper.

A plurality of first upper conductor blocks UP1 are located in the memory array area AR, And connected to the plurality of conductive pillars HP. A plurality of local source lines LSL and a plurality of local bit lines LBL are respectively connected to the plurality of source pillars 32a and the plurality of drain pillars 32b through vias VAA. The plurality of wires UW1 are respectively connected to the plurality of array through holes TAV1 in the step region SR and the plurality of array through holes TAV2 in the peripheral region PR (as shown in FIG. 3 ).

Referring to FIG. 1J, upper dielectric layers TD1 and TD2 are formed around and over the first upper conductor layer UM1. The upper dielectric layers TD1 and TD2 are made of silicon oxide, for example. After that, a chemical mechanical polishing process can be performed respectively to planarize the upper dielectric layers TD1 and TD2.

1J and 2F, then, a plurality of second via windows V2 are formed in the upper dielectric layer TD2. Part of the plurality of second vias V2 is connected to the plurality of first upper conductive blocks UP1, as shown in FIG. 1J. Another part of the second vias V2 is connected to the local source lines LSL and the local bit lines LBL, as shown in FIG. 2F . Another part of the plurality of second vias V2 is connected to the plurality of wires UW1, as shown in FIG. 2F. The plurality of second vias V2 include conductor material, such as tungsten. The plurality of second via windows V2 are formed by, for example, forming via holes in the upper dielectric layer TD2, and then forming conductor materials on the upper dielectric layer TD2 and filling the via holes. middle. Afterwards, a chemical mechanical polishing process or an etch-back process is performed to remove excess conductor material on the upper dielectric layer TD2.

Referring to FIGS. 1J and 2C , a conductor layer is formed on the upper dielectric layer TD2 and the plurality of second via windows V2, and is patterned through a photolithography and etching process to form a second upper conductor layer UM2. The second upper conductor layer UM2 includes a plurality of The second upper conductive block UP2, a plurality of global source lines GSL, a plurality of global bit lines GBL, and a plurality of wires UW2. The material of the conductor layer includes metal, such as copper. The plurality of second upper conductive blocks UP2 are connected to the plurality of first upper conductive blocks UP1 via the plurality of second vias V2. The plurality of global source lines GSL and the plurality of global bit lines GBL are respectively connected to the plurality of local source lines LSL and the plurality of local bit lines via the plurality of second vias V2 LBL connection. The plurality of conductive lines UW2 are respectively connected to the plurality of array through holes TAV1 and TAV2 via the plurality of second vias V2 and the plurality of conductive lines UW1.

Afterwards, an upper dielectric layer TD3 is formed on the second upper conductor layer UM2 and the upper dielectric layer TD2, as shown in FIG. 1J. The upper dielectric layer TD3 can be planarized through a chemical mechanical polishing process. The upper dielectric layer TD3 is, for example, silicon oxide. At this point, the manufacturing of the upper interconnection structure UIT is completed. However, the embodiments of the present invention are not limited thereto. The upper interconnect structure UIT may include more upper conductor layers and upper dielectric layers. In other embodiments, the second upper conductor layer UM2 and the plurality of second vias V2 may be formed using a dual damascene method. In addition, the method of forming the upper interconnect structure UIT is not limited to the above.

Figure 4 shows a top view of a flash memory die.

Referring to FIG. 4, the flash memory chip 99 includes a plurality of tiles T. As shown in FIG. These blocks T may include first blocks T1 and second blocks T2.

Each first block T1 has a plurality of first memory cells located in the first gate stack structure. The second block T2 has a plurality of first memory cells and heaters and is located in the second gate stack structure. The heater of the second block element T2 is set at the second gate In the stacked structure, multiple memory arrays composed of multiple memory cells are heated nearby. The second block T2 may include a single heater or multiple heaters according to the design. A single heater can heat the entire memory array. Multiple heaters can locally heat specific areas of the memory array as needed.

In some embodiments, a heater is disposed in the second gate stack structure of the second block T2, but no heater is disposed in the first gate stack structure of the first block T1. In other embodiments, heaters are provided in both the second gate stack structure of the second block T2 and the first gate stack structure of the first block T1, but the second gate stack structure of the second block T2 The density of the conductive pillars of the heater provided in the stacked structure is higher than the density of the conductive pillars of the heater provided in the first gate stack structure of the first block T1.

Because the second block element T2 is provided with a heater, or because the density of the conductive pillars of the heater set by the second block element T2 is higher than the density of the conductive pillars of the heater set by the first block element T1, the first block element T1 T1 and the second block T2 have different memory cell densities, and the density of the memory cells of the second block T2 is lower than the density of the memory cells of the first block T1. For example, the density of memory cells in the first block T1 is 10 to 20 times that of the memory cells in the second block T2.

The number of first tiles T1 and the number of second tiles T2 are different for each wafer. The number of elements in the first block T1 is greater than the number of elements in the second block T2. In FIG. 4 , each wafer may include a plurality of first blocks T1 and a single second block T2 . However, the present invention is not limited thereto. In other embodiments, each wafer may include a plurality of first tiles T1 and two second tiles T2 or more second tiles T2 .

The position of the first block element T1 is different from the position of the second block element T2. The second element T2 is set close to the switch pad to provide better heating efficiency. The second block T2 is disposed at the edge of the wafer, but is not limited to this.

The second block T2 can improve the endurance and retention of the memory unit through the setting of the heater, so it can be applied to the user's special key status register (status register), and the status register does not need to use wear averaging (wear leveling). -leveling) technology to evenly use each storage block or block in the flash memory to avoid the formation of bad blocks or blocks due to overuse of certain "specific" storage blocks or blocks. Therefore, by using a flash memory with a heater, the product life can be extended to an optimal level to meet system requirements.

Based on the above, in embodiments of the present invention, the array perforations around the memory cells are used as conductive pillars. The conductive pillars can provide local micro-heating of the flash memory cells nearby. The multiple conductor layers above and below the gate stack structure can be connected in parallel to form multiple upper heating plates and multiple lower heating plates. These upper heating plates and lower heating plates are connected in series through conductive pillars to increase the resistance value. In some embodiments, the heater has a resistance value of approximately 50 ohms to 1000 ohms. In other embodiments, the resistance of the heater is about 100 ohms to 200 ohms.

When Vdd (~3V) is applied to the heater, Joule heating can be provided to provide high temperature (>400C) to the local part of the 3D flash memory in a small area (about 7um * 100um area) to heat thousands of cells simultaneously memory unit. Experimental results demonstrate the simple and robust physics of self-heating flash memory, enabling ultra-high endurance (~1G P/E cycle) and good retention.

Embodiments of the present invention can design a special array for the status register in the 3D AND chip, and provide a "perfect" NVM to record the user's most critical information, such as almost unlimited durability and retention. And this critical array does not need to use wear leveling technology. Compared with MRAM, this flash memory with TAV heater can form higher density (>Mb) arrays and has ultra-high tolerance and retention, so it can compete with MRAM.

The third embodiment of the present invention is that the flash memory device is not limited to three-dimensional AND flash memory devices, but can also be applied to three-dimensional NAND or NOR flash memory devices.

P1:Part One

LP: lower heating plate

LIT: lower interconnect structure

P2:Part Two

HP: conductive pillar

P3:Part Three

UP: upper heating plate

UIT: upper inner wiring structure

10:Memory array

10U, 10U1, 10U2, 10U3, 10U4: Module unit

D1, D2, D3: direction

Claims (10)

A three-dimensional flash memory element, including: a substrate; a gate stack structure located above the substrate; a plurality of separation structures extending through the gate stack structure and dividing the gate stack structure into multiple block; a plurality of memory arrays disposed in the gate stack structure of the plurality of blocks; a plurality of conductive pillars extending through the gate stack structure located in the plurality of blocks, The plurality of conductive pillars are disposed between the plurality of memory arrays and the plurality of separation structures; the lower interconnection structure is located below the gate stack structure; and the upper interconnection structure is located at the Above the gate stack structure, the plurality of conductive pillars are connected to part of the lower interconnect structure and part of the upper interconnect structure, and the plurality of conductive pillars arranged in the same block pass through the The lower interconnection structure and the upper interconnection structure are electrically connected. The three-dimensional flash memory device of claim 1, wherein the plurality of memory arrays include a plurality of source posts and a plurality of drain posts, and the plurality of source posts and a plurality of drain posts extend through through the gate stack structure and laterally adjacent to the plurality of conductive pillars. The three-dimensional flash memory device according to claim 1, wherein a plurality of the conductive pillars disposed in the same block are electrically connected through the lower interconnect structure and the upper interconnect structure to form a greedy Serpentine structure. The three-dimensional flash memory device of claim 1, wherein the lower interconnect structure includes: a first lower conductor layer located between the substrate and the gate stack structure, wherein the first lower conductor layer The conductor layer includes a plurality of first lower conductor blocks separated from each other; a second lower conductor layer is located between the first lower conductor layer and the gate stack structure, wherein the second lower conductor layer includes a plurality of first lower conductor blocks separated from each other. a plurality of second lower conductor blocks located on the plurality of first lower conductor blocks, and the plurality of conductive posts landing on the plurality of second lower conductor blocks; and A plurality of first vias are located between and connected to the plurality of first lower conductor blocks and the plurality of second lower conductor blocks. The three-dimensional flash memory device of claim 4, wherein the plurality of separation structures extend in the first direction and are laterally adjacent to the plurality of conductive pillars. The three-dimensional flash memory device of claim 5, wherein each first lower conductor block extends in the second direction across the plurality of blocks, such that some of the plurality of blocks A plurality of memory arrays, a portion of the plurality of conductive pillars and a portion of the plurality of separation structures are disposed above it, and the second direction is different from the first direction. The three-dimensional flash memory device according to claim 6, wherein the upper interconnection structure includes: A first upper conductor layer is located above the gate stack structure, wherein the first upper conductor layer includes a plurality of first upper conductor blocks separated from each other, and the plurality of first upper conductor blocks are connected to the plurality of first upper conductor blocks. The conductive pillars are electrically connected; a second upper conductor layer is located above the first upper conductor layer, wherein the second upper conductor layer includes a plurality of second upper conductor blocks separated from each other and is located on the plurality of first upper conductor blocks. above the conductor block; and a plurality of second via windows located between and connected to the plurality of first upper conductor blocks and the plurality of second upper conductor blocks, wherein the plurality of conductive pillars, the plurality of second upper conductor blocks a first lower conductor block, a plurality of second lower conductor blocks, a plurality of first via windows, a plurality of first upper conductor blocks, a plurality of second upper conductor blocks, and a plurality of second upper conductor blocks. The second vias are electrically coupled to each other. The three-dimensional flash memory device of claim 7, wherein each first upper conductor block extends in the second direction across the plurality of blocks to cover all of the plurality of blocks. part of the plurality of conductive pillars and part of the plurality of separation structures. The three-dimensional flash memory device according to claim 8, wherein the first upper conductor layer further includes: a plurality of local bit lines and a plurality of local source lines extending in the second direction and connecting the A plurality of memory arrays are located between the plurality of first upper conductor blocks. The three-dimensional flash memory device according to claim 8, wherein the area of the first upper conductor block is smaller than the area of the corresponding second lower conductor block.