TWI809855B - Memory device, semiconductor device, and method of fabricating the same - Google Patents

Abstract

A memory device may be applicated in 3D AND flash memory device. The memory device includes a dielectric substrate, a plurality of memory cells, a slit structure, and a middle section of a seal ring. The dielectric substrate has a first region and a second region surrounding the first region. The composite stack structure disposed on the dielectric substrate in the first region and the second region. The plurality of memory cells disposed in the composite stack structure. The slit structure extends through the composite stack structure in first region. The composite stack structure is divided into a plurality of blocks. The middle section of a seal ring extends through the composite stack structure in the second region. The middle section of the seal ring includes a body part extending through the composite stack structure in the second region and a liner layer located between the body part and the composite stack structure.

Description

Memory element, semiconductor element and manufacturing method thereof

The present invention relates to a semiconductor element and its manufacturing method, and in particular to a memory element and its manufacturing method.

Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it is widely used in personal computers and other electronic devices. The 3D memory commonly used in the industry currently includes a Negative-Or (NOR) memory and a Negative-And (NAND) memory. In addition, another type of three-dimensional memory is AND memory, which can be applied in a multi-dimensional memory array and has high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become a current trend.

The present invention proposes a memory element that can effectively isolate the stacked structure of two adjacent cell areas, reduce or avoid the leakage path between the substrate and the ground conductor layer to increase the off-current I _off , and reduce the impact on the operation of the memory unit.

The present invention proposes a manufacturing method of a memory element, which can form a sealing ring on the periphery of the block region while forming the memory element, so that it can be integrated with the existing manufacturing process without increasing the steps of the manufacturing process.

An embodiment of the present invention provides a memory device, including: a dielectric substrate, a composite stack structure, a plurality of memory cells, a separation structure, and a middle section of a sealing ring. The dielectric substrate includes a first region and a second region surrounding the first region. The composite stack structure is over the dielectric substrate in the first region and the second region. The plurality of memory cells are located in the composite stack structure. The separation structure extends through the composite stacked structure located in the first region, separating the composite stacked structure into a plurality of blocks. A middle section of the seal ring extends through the composite stack structure in the second region. The intermediate section of the seal ring includes a body portion and a liner. The body portion extends through the composite stack structure located in the second region. The liner is located between the body portion and the composite stack structure.

An embodiment of the present invention provides a manufacturing method of a memory device, which includes the following steps. A dielectric substrate is provided, including a first region and a second region surrounding the first region. A stack structure is formed above the dielectric substrate in the first region and the second region, wherein the stack structure includes a plurality of insulating layers and a plurality of intermediate layers stacked alternately. Form the middle section of the separation structure and the sealing ring. The separation structure is located in the stacked structure in the first zone, and the intermediate section of the sealing ring is located in the stacked structure in the second zone.

An embodiment of the present invention provides a semiconductor device, including a composite stack structure, a middle section, an upper section and a lower section of a sealing ring. The composite stack structure is in a dielectric above the substrate. The composite stack structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately. The middle section extends through the composite stack structure and is electrically insulated from the plurality of conductor layers. The upper section is located above and connected to the middle section. The lower section is located below the middle section and connected with the middle section.

Based on the above, the sealing ring of the memory in the embodiment of the present invention can extend upwards from the surface of the substrate through the grounding conductor layer, and continuously extend to the top surface of the upper interconnection structure. Therefore, the memory of the embodiment of the present invention can effectively isolate the stack structure of two adjacent cell areas, reduce or avoid the leakage path between the substrate and the ground conductor layer to increase the off-current I _off , and reduce the operation of the memory cell. Influence.

The manufacturing method of the memory according to the embodiment of the present invention can form a sealing ring on the periphery of the block region while forming the memory element, so it can be integrated with the existing manufacturing process without increasing the steps of the manufacturing process.

10. A ⁽ⁱ⁾ , A ⁽ⁱ⁺¹⁾ : memory array

10: Memory array

12: Charge storage layer

14: Tunneling layer

16: Channel column

20: memory unit

24: insulating filling layer

28: Insulation column

62, 62a, 62b, 68, 68a, 68b: dielectric layer

32a: source post/conductor post/first conductor post

32b: drain pole/conductor column/second conductor column

36: barrier layer

38:Gate layer/word line

40:Charge storage structure

50, 100: Dielectric substrate

50s: surface

52. GSK: gate stack structure

103: conductor layer

54, 101, 104: insulating layer

60: Arrow

64a, 64b: Plugs

66a, 66b, 72a, 72b, 236a, 236b: wire

70a, 70b: vias

99: base

106: middle layer

130: Upper inner connection structure

133: make ditches

133a, 133b: ditches

138:Gate layer

142a, 142b: lining

144a, 144b: main body

220: Circuit structure

230: Bottom inner connection structure

233: Conductor interconnection

236a, 236b: wires

CSK: composite stack structure

DS: sealing ring

DSM: middle segment

DSU: upper segment

M1: the first conductor layer

M2: second conductor layer

P1: part one

P2: Part Two

R1: Region 1

R2: second area

SK1, SK2: stacked structure

SLT: Separation Structure

T1: the first meta area

T2: The second meta area

VC: columnar structure

WL(i)m, WL(i)m+1, WL(i+1)m, WL(i+1)m+1: word line

X, Y, Z: direction

I-I', II-II', III-III', IV-IV', V-V', VI-VI': line

B, B1, B2, BLOCK, BLOCK ⁽ⁱ⁾ , BLOCK ⁽ⁱ⁺¹⁾ : sub-blocks

BL _n , BL _n+1 : bit lines

SP ⁽ⁱ⁾ _n , SP ⁽ⁱ⁾ _n+1 , SP ⁽ⁱ⁺¹⁾ _n , SP ⁽ⁱ⁺¹⁾ _n+1 : source pole

DP ⁽ⁱ⁾ _n , DP ⁱ⁾ _n+1 , DP ⁱ⁺¹⁾ _n , DP ⁽ⁱ⁺¹⁾ _n+1 : source pole

WL ⁽ⁱ⁾ _m , WL ⁽ⁱ⁾ _m+1 , WL ⁽ⁱ⁺¹⁾ _m , WL ⁽ⁱ⁺¹⁾ _m+1 : word line

CSK: composite stack structure

DS: sealing ring

DSM: middle section

SLT: Separation Structure

M1: the first conductor layer

M2: second conductor layer

P1: part one

P2: Part Two

SLT: Separation Structure

X, Y, Z: direction

I-I', II-II', III-III', IV-IV', V-V', VI-VI': line

Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments.

FIG. 1B shows a partial three-dimensional view of a portion of the memory array in FIG. 1A .

FIG. 1C and FIG. 1D show cross-sectional views of the line I-I' in FIG. 1B.

Fig. 1E shows a top view of the line II-II' of Fig. 1B, Fig. 1C, Fig. 1D.

FIG. 1F shows a top view of a 3D AND flash memory.

2A to FIG. 2J illustrate the 3D AND flash memory according to some embodiments Top view of the manufacturing process.

3A to 3J are shown as cross-sectional views along line III-III' of FIGS. 2A to 2J .

4A to 4J are shown as cross-sectional views along line IV-IV' of FIGS. 2A to 2J .

FIG. 5 shows a top view of a 3D AND flash memory according to other embodiments.

Fig. 6 is a cross-sectional view taken along line V-V' of Fig. 5 .

Fig. 7 is a cross-sectional view taken along line VI-VI' of Fig. 5 .

The sealing ring of this embodiment extends through the composite stack structure. The composite stack structure can be used to form various semiconductor devices, such as memory devices. For the sake of brevity, 3D AND flash memory is used for description below, however, the present invention is not limited thereto.

Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a partial three-dimensional view of a portion of the memory array in FIG. 1A . FIG. 1C and FIG. 1D show cross-sectional views of the line I-I' in FIG. 1B. Fig. 1E shows a top view of the line II-II' of Fig. 1B, Fig. 1C and Fig. 1D.

FIG. 1A is a schematic diagram of two blocks BLOCK ⁽ⁱ⁾ and BLOCK ⁽ⁱ⁺¹⁾ including vertical AND memory arrays 10 arranged in columns and rows. Block BLOCK ⁽ⁱ⁾ includes memory array A ⁽ⁱ⁾ . A column (eg column m+1) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common word line (eg WL ⁽ⁱ⁾ _m+1 ). The AND memory cells 20 of each column (eg column m+1) of the memory array A ⁽ⁱ⁾ correspond to a common word line (eg WL ⁽ⁱ⁾ _m+1 ), and are coupled to different source columns (such as SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain poles (such as DP ⁽ⁱ⁾ _n and DP ⁽ⁱ⁾ _n+1 ), so that the AND memory cell 20 is along a common word line (such as WL ⁽ⁱ⁾ _m+1 ) are logically arranged in a column.

A row (eg row n ^{) of the memory array A(i)} is a set of AND memory cells 20 having a common source column (eg SP ⁽ⁱ⁾ _n ) and a common drain column (eg DP ⁽ⁱ⁾ _n ). The AND memory cells 20 of each row (eg row n) of the memory array A ⁽ⁱ⁾ correspond to different word lines (eg WL ⁽ⁱ⁾ _m+1 and WL ⁽ⁱ⁾ _m ), and are coupled to a common source posts (eg SP ⁽ⁱ⁾ _n ) and common drain posts (eg DP ⁽ⁱ⁾ _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁾ are logically arranged in a row along a common source column (eg SP ⁽ⁱ⁾ _n ) and a common drain column (eg DP ⁽ⁱ⁾ _n ). In a physical layout, the rows or columns may be distorted, arranged in a honeycomb pattern or otherwise, for high density or for other reasons, depending on the fabrication method applied.

In FIG. 1A, in the block BLOCK ⁽ⁱ⁾ , the AND memory cells 20 in the nth row of the memory array A ⁽ⁱ⁾ share a common source column (for example, SP ⁽ⁱ⁾ _n ) and a common drain column. (eg DP ⁽ⁱ⁾ _n ). The AND memory cells 20 in the n+1th row share a common source column (eg SP ⁽ⁱ⁾ _n+1 ) and a common drain column (eg DP ⁽ⁱ⁾ _n+1 ).

A common source post (eg SP ⁽ⁱ⁾ _n ) is coupled to a common source line (eg SL _n ); a common drain post (eg DP ⁽ⁱ⁾ _n ) is coupled to a common bit line (eg BL _n ). A common source post (eg SP ⁽ⁱ⁾ _n+1 ) is coupled to a common source line (eg SL _n+1 ); a common drain post (eg DP ⁽ⁱ⁾ _n+1 ) is coupled to a common bit line (eg BL _n+1 ).

Similarly, block BLOCK ⁽ⁱ⁺¹⁾ includes memory array A ⁽ⁱ⁺¹⁾ which is similar to memory array A ^{(i) in block BLOCK (i) .} A column (eg column m ^{+1) of the memory array A (i} +1) is a set of AND memory cells 20 having a common word line (eg WL ⁽ⁱ⁺¹⁾ _m+1 ). The AND memory cells 20 of each column (eg column m+1) of the memory array A ⁽ⁱ +1) correspond to a common word line (eg WL ⁽ⁱ⁺¹⁾ _m+1 ), and are coupled to different source columns (eg SP ⁽ⁱ⁺¹⁾ _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and drain columns (eg DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (eg row n) of the memory array A ⁽ⁱ⁺¹⁾ has a common source column (eg SP ⁽ⁱ⁺¹⁾ _n ) and a common drain column (eg DP ⁽ⁱ⁺¹⁾ _n ). A set of AND memory units 20 is connected in parallel with each other, which is also called a memory string. The AND memory cells 20 of each row (eg row n) of the memory array A ⁽ⁱ⁺¹⁾ correspond to different word lines (eg WL ⁽ⁱ⁺¹⁾ _m+1 and WL ⁽ⁱ⁺¹⁾ _m ) , and coupled to a common source post (eg SP ⁽ⁱ⁺¹⁾ _n ) and a common drain post (eg DP ⁽ⁱ⁺¹⁾ _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁺¹⁾ are logically configured along a common source column (eg SP ⁽ⁱ⁺¹⁾ _n ) and a common drain column (eg DP ⁽ⁱ⁺¹⁾ _n ). one line.

Block BLOCK ⁽ⁱ⁺¹⁾ and block BLOCK ⁽ⁱ⁾ share source lines (such as SL _n and SL _n+1 ) and bit lines (such as BL _n and BL _n+1 ). Therefore, the source line SL _n and the bit line BL _n are coupled to the nth row of AND memory cells 20 in the AND memory array A (i) of the block BLOCK ^{( i)} , and are coupled to the block BLOCK ^{(i +1)} in the AND memory cell 20 in the nth row of the AND memory array A ⁽ⁱ⁺¹⁾ . Similarly, the source line SL _n+1 and the bit line BL _n+1 are coupled to the n+1th row of AND memory cells 20 in the AND memory array A ⁽ⁱ⁾ of the block BLOCK ⁽ⁱ ), and are coupled to To the AND memory unit 20 in the n+1th row of the AND memory array A ^{( i+1) in the block BLOCK (i} +1).

Referring to FIG. 1B to FIG. 1D , the memory array 10 can be disposed on the interconnect structure of the semiconductor die, such as disposed on one or more active devices (such as transistors) formed on the semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed above the metal interconnect structure on the silicon substrate. remember The memory array 10 may include a gate stack structure 52, a plurality of channel pillars 16, a plurality of first conductive pillars (also called source pillars) 32a, and a plurality of second conductive pillars (also called drain pillars). 32b and a plurality of charge storage structures 40.

Referring to FIG. 1B , the gate stack structure 52 is formed on the dielectric substrate 50 in the array area (not shown) and the step area (not shown). The gate stack structure 52 includes a plurality of gate layers (also referred to as word lines) 38 and multiple layers of insulating layers 54 vertically stacked on the surface 50 s of the dielectric substrate 50 . In the Z direction, the gate layers 38 are electrically isolated by an insulating layer 54 disposed between them. The gate layer 38 extends in a direction parallel to the surface of the dielectric substrate 50 . The gate layer 38 of the stepped region may have a stepped structure (not shown). Therefore, the lower gate layer 38 is longer than the upper gate layer 38 , and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38 . Contacts (not shown) for connecting to the gate layer 38 may be landed at the ends of the gate layer 38 to connect each gate layer 38 to each wire.

Referring to FIG. 1B to FIG. 1D , the memory array 10 further includes a plurality of channel pillars 16 extending in a direction (ie, Z direction) perpendicular to the surface of the gate layer 38 (ie, XY plane). In some embodiments, the channel pillar 16 extends continuously through the gate stack structure 52 of the first region R1. In some embodiments, the channel pillar 16 discontinuously extends through the gate stack structure 52 of the first region R1. In some embodiments, the channel post 16 may have a ring shape when viewed from above (as shown in FIG. 1B ). The material of the channel pillar 16 can be semiconductor, such as undoped polysilicon. The channel post 16 may also be called a vertical channel.

Referring to FIG. 1B to FIG. 1D , the memory array 10 further includes an insulating filling layer 24 , an insulating pillar 28 , a plurality of first conductive pillars 32 a and a plurality of second conductive pillars 32 b. exist In this example, the first conductive column 32a is used as a source column; the second conductive column 32b is used as a drain column. The first conductive pillar 32a, the second conductive pillar 32b and the insulating pillar 28 each extend in a direction (ie, a Z direction) perpendicular to a surface of the gate layer 38 (ie, an XY plane). The first conductor column 32 a and the second conductor column 32 b are separated by the insulating column 28 . The first conductive post 32 a and the second conductive post 32 b are electrically connected to the channel post 16 . The first conductive pillar 32a and the second conductive pillar 32b include doped polysilicon or metal material. The insulating filling layer 24 is, for example, silicon oxide. The insulating pillar 28 is, for example, silicon nitride or silicon oxide.

Referring to FIG. 1C and FIG. 1D , the charge storage structure 40 is disposed between the channel pillar 16 and the multilayer gate layer 38 . The charge storage structure 40 may include a tunneling layer (or called a bandgap engineered tunneling oxide layer) 14 , a charge storage layer 12 and a blocking layer 36 . The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36 . In some embodiments, the tunneling layer 14 and the barrier layer 36 include silicon oxide. The charge storage layer 12 includes silicon nitride, or other materials that can trap charges. In some embodiments, as shown in FIG. 1C , a part of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12 ) extends continuously in the direction perpendicular to the gate layer 38 (ie, the Z direction), and the charge storage Another portion of structure 40 (barrier layer 36 ) surrounds gate layer 38 . In other embodiments, as shown in FIG. 1D , the charge storage structure 40 (the tunneling layer 14 , the charge storage layer 12 and the blocking layer 36 ) surrounds the gate layer 38 .

Referring to FIG. 1E , the charge storage structure 40 , the channel column 16 , the source column 32 a and the drain column 32 b are surrounded by the gate layer 38 and define the memory cell 20 . The memory unit 20 can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column 32a and the drain column 32b, since the source column 32a and the drain column 32b are connected to the channel column 16, electrons can be transmitted along the channel column 16 and stored in the entire charge storage In the structure 40, the memory unit 20 can be Perform 1-bit operations. In addition, for the operation using Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and the drain post 32b. . For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electron Or the holes are locally trapped in the charge storage structure 40 adjacent to one of the two source posts 32a and drain posts 32b, so that the memory cell 20 can be unit cell (SLC, 1 bit) or more Bit cell (MLC, greater than or equal to 2 bits) operations.

Referring to FIG. 1A and FIG. 1B, during operation, a voltage is applied to the selected word line (gate layer) 38, for example, when applying a corresponding starting voltage (V _th ) higher than the corresponding memory cell 20, and The channel pillar 16 intersected by the selected wordline 38 is turned on, allowing current to enter the drain pillar 32b from the bitline _BLn or BLn ₊₁ (shown in FIG. 1B ) and flow to the source through the turned on channel region. Pole 32a (eg, in the direction indicated by arrow 60), eventually flows to source line _SLn or SLn ₊₁ (shown in FIG. 1B ).

Please refer to 1F, in some embodiments of the present invention, the stacked structure in the first area R1 of the first block meta area T1 or the second block meta area T2 is divided into a plurality of blocks by at least one partition structure SLT (for example B1 and B2). While forming the separation structure SLT, the middle section DSM of the seal ring DS is also formed in the stacked structure of the second region (eg, the peripheral region) R2. The methods for forming the separation structure SLT and the middle section DSM of the sealing ring DS can refer to those shown in FIGS. 2A to 2J , 3A to 3J , and 4A to 4J .

2A-2J illustrate top views of the fabrication flow of a 3D AND flash memory according to some embodiments. Fig. 3A to Fig. 3J are the line III-III' of Fig. 2A to Fig. 2J sectional view. 4A to 4J are cross-sectional views of line IV-IV' in FIGS. 2A to 2J . Additionally, for clarity, some layers or components are not shown in FIGS. 2A-2J and 3F.

Referring to FIG. 2A , FIG. 3A and FIG. 4A , a dielectric substrate 100 is provided. The dielectric substrate 100 is, for example, a dielectric layer, such as a silicon oxide layer, formed on a lower interconnection structure on a silicon substrate. The dielectric substrate 100 includes a first region R1 and a second region R2 surrounding the first region R1. The first area R1 may also be called a block element area, and the second area R2 may also be called a peripheral area. A stack structure SK1 is formed on the dielectric substrate 100 in the first region R1 and the second region R2. The stack structure SK1 can also be called an insulating stack structure SK1. In the present embodiment, the stacked structure SK1 is composed of insulating layers 104 and intermediate layers 106 stacked alternately on the dielectric substrate 100 . In other embodiments, the stack structure SK1 may be formed by interleaved interlayers 106 and insulating layers 104 stacked on the dielectric substrate 100 . The insulating layer 104 is, for example, silicon oxide. The middle layer 106 is, for example, silicon nitride. The middle layer 106 can be used as a sacrificial layer, which is completely or partially removed in subsequent processes. In this embodiment, the stack structure SK1 has 8 insulating layers 104 and 7 intermediate layers 106 , but the invention is not limited thereto. In other embodiments, more insulating layers 104 and more intermediate layers 106 can be formed according to actual needs.

In some embodiments, before forming the stack structure SK1 , the conductor layer 103 is first formed on the dielectric substrate 100 . The insulating layer 101 is, for example, silicon oxide. The conductive layer 103 is, for example, a grounded polysilicon layer. The conductive layer 103 can also be called a dummy gate, which can be used to close the leakage path.

The stacked structure SK1 is patterned so that in the step region of the first region R1 (not shown) to form a ladder structure (not shown).

Next, referring to FIG. 2B , FIG. 3B and FIG. 4B , a plurality of columnar structures VC are formed in the stacked structure SK1 in the first region R1 . In some embodiments, each pillar structure VC may include the channel pillar 16 shown in FIG. 1C , the first conductor pillar 32a, the second conductor pillar 32b, the tunneling layer 14 and the charge storage layer 12 of the charge storage structure 40, and an insulating pillar. 28 and insulating filling layer 24. In some other embodiments, each pillar structure VC may include the channel pillar 16 , the first conductor pillar 32 a , the second conductor pillar 32 b , the insulating pillar 28 and the insulating filling layer 24 shown in FIG. 1D . For the sake of brevity, only the columnar structure VC is used to represent it, and its detailed components are not shown one by one. The channel column 16, the first conductive column 32a, the second conductive column 32b, the tunneling layer 14 and the charge storage layer 12 of the charge storage structure 40, the insulating column 28 and the insulating filling layer 24 can be formed by any known method. This will not be described in detail.

Referring to FIGS. 2C to 2E , FIGS. 3C to 3E , and FIGS. 4C to 4E , a replacement process is performed to replace the multilayer intermediate layer 106 with the multilayer gate layer 138 . First, referring to FIG. 2C , FIG. 3C and FIG. 4C , a patterning process, such as lithography and etching process, is performed on the stacked structure SK1 to form trenches 133 a and 133 b in the first region R1 and the second region R2 respectively. During the etching process, the conductive layer 103 can be used as an etching stop layer, so that the trench 133 exposes the conductive layer 103 .

Referring to FIG. 2C , from a top view, the trench 133 a extends along the X direction, so that the stacked structure SK1 of the first region R1 is divided into a plurality of blocks B1 and B2 . Seen from the top view, the ditch 133b has a ring shape, is separated from the first region R1 by a non-zero distance, and surrounds the first region R1.

Next, referring to FIG. 2D , FIG. 3D and FIG. 4D , the etching process is continued to remove the exposed conductor layer 103 of the trenches 133 a and 133 b until the trenches 133 a and 133 b extend through the conductor layer 103 . Bottoms of the trenches 133a and 133b may expose the dielectric substrate 100 .

After that, referring to FIG. 2E , FIG. 3E and FIG. 4E , an etching process, such as a wet etching process, is performed to remove part of the multi-layer intermediate layer 106 . The etchant (such as hot phosphoric acid) used in the etching process is injected into the trenches 133a and 133b, and then the contacted part of the multi-layer intermediate layer 106 is removed. By time mode control, most of the multi-layer intermediate layer 106 closer to the trenches 133a and 133b can be removed to form a plurality of horizontal openings (not shown). Most of the multilayer intermediate layer 106 that is farther away from the trenches 133a and 133b is left.

Please refer to FIG. 2E, FIG. 3E and FIG. 4E. In some embodiments, the gate layer 138 and the barrier layer (not shown) of the charge storage structure are formed in a plurality of horizontal openings, such as the barrier layer 36 shown in FIG. 1C. . In other embodiments, in addition to the gate layer 138, a tunneling layer (not shown), a charge storage layer (not shown) and a blocking layer (not shown) of the charge storage structure are formed, as shown in FIG. 1D The tunneling layer 14, the charge storage layer 12 and the blocking layer 36 are shown. The forming method of the gate layer 138 is, for example, filling the trenches 133a and 133b and a plurality of horizontal openings (not shown) with conductive material first, and then performing an etch-back process to remove the conductors in the trenches 133a and 133b Material.

Referring to FIG. 3E and FIG. 4E , the unremoved intermediate layer 106 , the multilayer gate layer 138 and the multilayer insulating layer 104 form a stack structure SK2 . Referring to FIG. 3E , the intermediate layer 106 around the trench 133 a is replaced by a gate layer 138 . multilayer gate layer 138 A gate stack structure GSK is formed with the multi-layer insulating layer 104 . Where the gate layer 138 intersects with the columnar structure VC can form a memory cell. Therefore, a plurality of memory cells are included in the gate stack structure GSK. The stack structure SK2 and the gate stack structure GSK form a composite stack structure CSK.

Referring to FIG. 4E , the intermediate layer 106 around the trench 133 b is replaced by a gate layer 138 . The multi-layer intermediate layer 106 away from the trench 133b is preserved. In the second region R2, the multi-layer gate layers 138 and the multi-layer insulating layers 104 are alternately stacked to form the first part P1 of the stack structure SK2. In the second region R2, the remaining interlayer layers 106 and the insulating layers 104 are alternately stacked to form the second part P2 of the stack structure SK2.

Referring to FIG. 2F , FIG. 3F and FIG. 4F , the separation structure SLT and the middle section DSM of the sealing ring DS are formed in the trenches 133 a and 133 b. The gate stack structure GSK is divided into a plurality of blocks B1, B2 by the separation structure SLT. The middle section DSM of the sealing ring DS is surrounded by and contacts the first part P1 of the stack structure SK2.

In some embodiments, the separation structure SLT may include a liner 142a and a main body 144a. The middle section DSM of the sealing ring DS may include a liner 142b and a main body 144b. The main parts 144a and 144b can provide support and prevent the separation structure SLT from bending. The liners 142a and 142b include insulating materials such as silicon oxide. The main parts 144a and 144b include conductive material, such as polysilicon. The method for forming the separation structure SLT and the middle section DSM of the sealing ring DS includes filling the liner material and the body material on the stack structure SK2 and the trenches 133a and 133b, and then removing the stack structure SK2 through an etch-back process or a planarization process. Excess lining material and body material. lining 142a can electrically isolate the gate layer 138 from the main body portion 144a. The lining layer 142b can electrically isolate the gate layer 138 from the main body portion 144b, and can block moisture and reduce the stress of the main body portion 144b.

Referring to FIG. 2J , FIG. 3J and FIG. 4J , an upper interconnection structure (or called a first interconnection structure) 130 is formed on the stack structure SK2 . The upper interconnection structure 130 includes source lines and bit lines connecting a plurality of columnar structures VC (for example, a plurality of first conductor columns 32a and a plurality of second conductor columns 32b shown in FIG. 1C or FIG. 1D ) and connecting Middle section DSM of sealing ring DS Upper section DSU of sealing ring DS. More specifically, the upper interconnect structure 130 includes dielectric layers 62 and 68, a plurality of plugs 64a, 64b, a first conductor layer M1 (including a plurality of wires 66a, 66b), a plurality of vias 70a and 70b. And the second conductor layer M2 (including a plurality of wires 72a, 72b). A plurality of wires 66a can be used as source lines and bit lines, and are electrically connected to a plurality of columnar structures VC (for example, a plurality of first conductor columns 32a and a plurality of second conductor columns 32a shown in FIG. 1C or FIG. 1D ) via plugs 64a. conductor post 32b). The plug 64b, the wire 66b of the first conductor layer M1, the via 70b and the wire 72b of the second conductor layer M2 together form the upper section DSU of the sealing ring DS, which is electrically connected to the middle section DSM of the lower sealing ring DS. The components and forming methods of the upper interconnection structure 130 are described in detail as follows.

Referring to FIG. 2G , FIG. 3G and FIG. 4G , a dielectric layer 62 a and a stacked structure 52 of plugs 64 a and 64 b are formed on the stacked structure SK2 of the first region R1 and the second region R2 . Plugs 64a and 64b are buried in dielectric layer 62a. The plug 64a lands on the first conductor post 32a and the second conductor post 32b in the first region R1 and is electrically connected thereto. The plug 64b lands on the middle section DSM of the sealing ring of the second region R2. Seen from the top view, the plug 64a has an island-like or dot-like outline, and the plug 64b has a ring-like outline as shown in FIG. 2G shown. The size (path length) of the plug 64a may be smaller than or equal to the size of the first conductor post 32a and the second conductor post 32b shown in FIG. 1C or FIG. 1D . The size (line width) of the plug (or called first plug) 64b may be greater than, equal to, or smaller than the size (line width) of the middle section DSM of the seal ring DS.

Referring to FIG. 2H , FIG. 3H and FIG. 4H , a dielectric layer 62 b and a first conductive layer M1 are formed on the dielectric layer 62 a. The first conductor layer M1 is buried in the dielectric layer 62b. The first conductor layer M1 refers to the first conductor layer of the upper interconnect structure 130 above the stack structure SK2 . The first conductive layer M1 includes a plurality of wires 66a and 66b. The wires 66a and 66b are electrically connected to the plugs 64a and 64b respectively. In some embodiments, the plurality of wires 66 a of the second conductor layer M2 can serve as source lines and bit lines. Seen from above, the wire 66a has a shape of a straight line or a broken line (not shown). The wire (or referred to as the first wire) 66b has a circular outline. The size (line width) of the wire 66a may be smaller than or equal to the size of the underlying plug 64a. The size (line width) of the wire 66b may be greater than, equal to, or smaller than the size (line width) of the underlying plug 64b.

Referring to FIG. 3H and FIG. 4H, the plugs 64a and 64b and the plurality of wires 66a and 66b are, for example, metal layers such as tungsten or copper. In some embodiments, the plugs 64a and 64b further include a barrier layer between the metal layer and the dielectric layer 62a and 62b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. The plugs 64a and 64b and the plurality of wires 66a and 66b can be formed through a single damascene or dual damascene process, but is not limited thereto. The following uses the dual damascene process as an example.

Referring to FIGS. 3H and 4H , a dielectric layer 62 is formed on the stack structure 52 and the stack structure SK2 . The dielectric layer 62 includes dielectric layers 62a and 62b. There may be an interface or no interface between the dielectric layers 62a and 62b. The dielectric layer 62 is, for example, silicon oxide. A plurality of trenches (not shown) and a plurality of insertions are formed in the dielectric layer 62 through lithography and etching processes. Plug holes (not shown), and then backfill the barrier layer and the metal filling layer, and then remove the excess barrier layer and metal filling layer on the dielectric layer 62 through an etch-back process or a chemical mechanical polishing process, so as to Plugs 64a and 64b and a plurality of wires 66a and 66b are formed.

Referring to FIG. 2I, FIG. 3I and FIG. 3I, a dielectric layer 68a and vias 70a and 70b are formed on the dielectric layer 62 and a plurality of wires 66a and 66b. Vias 70a and 70b are buried in dielectric layer 68a. Via 70a lands on and is electrically connected to wire 66a; via 70b lands on and is electrically connected to wire 66b. From the top view, the via 70a has an island-like or dot-like outline, as shown in FIG. 2I . The via 70b has a circular profile. The size (path length) of the via 70a may be smaller than or equal to the size of the underlying wire 66a. The size (line width) of via 70b may be greater than, equal to, or smaller than the size (line width) of underlying wire 66b.

Referring to FIG. 2J , FIG. 3J and FIG. 4J , a dielectric layer 68 b and a second conductor layer M2 are formed on the dielectric layer 68 a. The second conductor layer M2 is buried in the dielectric layer 68b. The second conductor layer M2 refers to the second conductor layer of the upper interconnect structure 130 above the stack structure SK2. The second conductor layer M2 includes a plurality of wires 72a and 72b. The wires 72 a and 72 b extend along the direction Y and are arranged along the direction X respectively. Wires 72a and 72b are electrically connected to vias 70a and 70b, respectively. In the Z direction, conductors 72a and 72b overlap conductors 66a and 66b, respectively. The wire 72b can also be called a second wire.

Referring to FIG. 3J and FIG. 4J, the vias 70a and 70b and the plurality of wires 72a and 72b are, for example, metal filling layers such as tungsten or copper. In some embodiments, vias 70a and 70b further include a barrier layer between the metal fill layer and dielectric layers 68a and 68b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. Vias 70a and 70b And the plurality of wires 72a and 72b can be formed through a single damascene or dual damascene process, but is not limited thereto. The following uses the dual damascene process as an example.

Referring to FIG. 3J , firstly, a dielectric layer 68 is formed on the dielectric layer 62 and the first conductive layer M1 . The dielectric layer 68 includes dielectric layers 68a and 68b. Dielectric layers 68a and 68b may have an interface or no interface. The dielectric layer 68 is, for example, silicon oxide. In some embodiments, a plurality of trenches and a plurality of plug holes are formed in the dielectric layer 68 through patterning processes, such as lithography and etching processes. In other embodiments, a plurality of trenches (not shown) and a plurality of plug holes (not shown) may be formed through a self-aligned double patterning (SADP) process. After that, the barrier layer and the metal fill layer are backfilled. Then, the excess barrier layer and the metal filling layer on the dielectric layer 68 are removed through an etch-back process or a chemical mechanical polishing process to form vias 70a and 70b and a plurality of wires 72a and 72b.

FIG. 5 shows a top view of a 3D AND flash memory according to other embodiments. Fig. 6 is a cross-sectional view taken along line V-V' of Fig. 5 . Fig. 7 is a cross-sectional view taken along line VI-VI' of Fig. 5 .

Referring to FIG. 5 , FIG. 6 and FIG. 7 , in other embodiments, a circuit structure 220 and a lower interconnection structure (or called a second interconnection structure) 230 are further formed between the substrate 99 and the stack structure SK2 . The dielectric substrate 100 is located between the conductive layer 103 and the substrate 99 . The substrate 99 includes, for example, a semiconductor. The circuit structure 220 may include active components or passive components. Active elements are, for example, transistors, diodes, and the like. Passive components are, for example, capacitors, inductors, and the like. The transistor can be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor or a complementary metal oxide semiconductor device (CMOS). In some embodiments, the circuit structure 220 may include a plane buffer (Plane-Buffer).

Referring to FIG. 5 , FIG. 6 and FIG. 7 , the lower interconnection structure 230 may include a multilayer dielectric layer 230 and a conductor interconnection 233 formed in the multilayer dielectric layer 230 . The conductor interconnection 233 includes a plurality of plugs 234a, 234b, a plurality of wires 236a, 236b, and the like. The wire 236a can be connected to the circuit structure 220 through the plug 234a. The wire (or called as the third wire) 236b and the plug (or called as the second plug) 234b can jointly form the lower section DSL of the sealing ring DS to electrically connect the middle section DSM of the lower sealing ring DS. Viewed from the top view, the wire 236b and the plug 234b have a circular outline. The size (diameter length) of the wire 236b and the plug 234b may be greater than, equal to or smaller than the size (line width) of the middle section DSM of the sealing ring DS.

Based on the above, the sealing ring of the 3D flash memory according to the embodiment of the present invention can extend upwards from the surface of the substrate through the ground conductor layer, and continuously extend to the top surface of the upper interconnection structure. Therefore, the three-dimensional flash memory of the embodiment of the present invention can effectively isolate the stack structure of two adjacent cell areas, reduce or avoid the leakage path between the substrate and the ground conductor layer to increase the off-current I _off , and reduce the impact on the memory. Effects of unit operations.

The manufacturing method of the three-dimensional flash memory of the embodiment of the present invention can form a sealing ring on the periphery of the block region while forming the memory element, so it can be integrated with the existing manufacturing process without increasing the steps of the manufacturing process.

100: Dielectric substrate

103: conductor layer

104: insulation layer

R2: second area

SK2: stacked structure

106: middle layer

138:Gate layer

P1: part one

P2: Part Two

142b: lining

144b: Main body

DS: sealing ring

DSM: middle section

Claims (17)

A memory element, comprising: a dielectric substrate including a first area and a second area surrounding the first area; a composite stack structure, the dielectric in the first area and the second area above the electrical substrate; a plurality of memory cells located in the composite stack structure; a separation structure extending through the composite stack structure located in the first region to separate the composite stack structure into a plurality of blocks; and an intermediate section of a seal ring extending through the composite stack in the second region, wherein the intermediate section of the seal ring includes a main body extending through the composite stack in the second region a stack structure; and a liner between the body portion and the composite stack structure, wherein the intermediate section of the seal ring hermetically surrounds the first region. The memory device according to claim 1, wherein the main body portion of the sealing ring and the composite stack structure are electrically insulated by the liner of the sealing ring. The memory device according to claim 1, wherein the lining layer of the sealing ring includes an insulating material, and the main body portion includes a conductive material. The memory device according to claim 1, further comprising: a conductor layer located between the composite stack structure and the dielectric substrate, wherein the middle section of the sealing ring extends through the conductor layer. The memory device according to claim 4, wherein the sealing ring further includes: a lower section, located below the middle section and connected to the middle section, wherein the lower section is a part of the first inner line, the The first interconnection line is located between the dielectric base and the base; and the upper section is located above the middle section and connected to the middle section, wherein the upper section is a part of the second interconnection line, and the second Interconnects are located above the composite stack structure. A method of manufacturing a memory element, comprising: providing a dielectric substrate including a first region and a second region surrounding the first region; forming a stack structure in the first region and the second region above the dielectric substrate, wherein the stack structure includes a plurality of insulating layers and a plurality of intermediate layers stacked alternately; and an intermediate segment forming a separation structure and a seal ring, wherein the separation structure is located in the first region In the stacked structure, the middle section of the sealing ring is located in the stacked structure in the second zone, wherein the middle section of the sealing ring is hermetically wrapped around the first zone. The manufacturing method of the memory device according to claim 6, wherein the sealing ring further comprises: wherein the intermediate section forming the separation structure and the sealing ring comprises: forming a first ditch and a second ditch, wherein the first ditch is located in the stacked structure in the first region, and the second ditch is located in the stacked structure in the second region; forming a first liner a layer and a second liner, wherein the first liner is located on a sidewall of the first trench, and the second liner is located on a sidewall of the second trench; and forming a first body portion and a second body portion , wherein the first main body part is located in the remaining space of the first ditch, and the second main body part is located in the remaining space of the second ditch. The manufacturing method of the memory device according to claim 7, further comprising: before forming the first liner and the second liner, forming the first trench and the surrounding area of the second trench The intermediate layers are replaced by gate conductor layers. The method for manufacturing a memory device according to claim 8, further comprising: forming a conductor layer between the stacked structure and the dielectric substrate, wherein the first trench and the second trench also extend through through the conductor layer. The manufacturing method of the memory device according to claim 6, further comprising: forming a first interconnection between the dielectric substrate and the substrate, wherein part of the first interconnection forms the a lower section of the sealing ring; and forming a second interconnection above the stack structure, wherein part of the second interconnection forms an upper section of the sealing ring. A semiconductor element comprising: A composite stacked structure above a dielectric substrate, wherein the composite stacked structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately, wherein the dielectric substrate includes a first region and a surrounding area around the first region a second region of the composite stack structure, wherein the composite stack structure is over the dielectric substrate in the first region and the second region; a seal ring comprising: a middle section extending through the composite stack structure, and electrically insulated from the plurality of conductor layers; an upper section, located above and connected to the middle section; and a lower section, located below the middle section and connected to the middle section, wherein the sealing ring Said intermediate section of said first region is hermetically wrapped around said first zone. The semiconductor element as claimed in claim 11, wherein said intermediate section of said seal ring comprises: a main body extending through said composite stack structure; and a liner between said main body and said composite stack structure between. The semiconductor element according to claim 12, wherein the main body portion and the liner have a ring-shaped profile. The semiconductor element according to claim 11, wherein the upper section includes: a first plug located on the main body part and electrically connected to the main body part; a first wire located on the first plug and electrically connected to the first plug; a via located on the first wire and electrically connected to the first wire; and a second wire located on the via and connected to the via The layer windows are electrically connected. The semiconductor device of claim 14, wherein the first plug, the first wire, the via, and the second wire have a ring-shaped profile. The semiconductor element according to claim 11, wherein the lower section includes: a third wire located under the main body part and electrically connected to the main body part; and a second plug located under the third wire and connected to the main body part The third wire is electrically connected. The semiconductor device as claimed in claim 16, wherein the third lead and the second plug have ring-shaped contours.

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