TWI809855B - Memory device, semiconductor device, and method of fabricating the same - Google Patents

Memory device, semiconductor device, and method of fabricating the same Download PDF

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TWI809855B
TWI809855B TW111116898A TW111116898A TWI809855B TW I809855 B TWI809855 B TW I809855B TW 111116898 A TW111116898 A TW 111116898A TW 111116898 A TW111116898 A TW 111116898A TW I809855 B TWI809855 B TW I809855B
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region
stack structure
layer
sealing ring
composite stack
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TW202345362A (en
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吳孟晏
曾碧山
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旺宏電子股份有限公司
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Abstract

A memory device may be applicated in 3D AND flash memory device. The memory device includes a dielectric substrate, a plurality of memory cells, a slit structure, and a middle section of a seal ring. The dielectric substrate has a first region and a second region surrounding the first region. The composite stack structure disposed on the dielectric substrate in the first region and the second region. The plurality of memory cells disposed in the composite stack structure. The slit structure extends through the composite stack structure in first region. The composite stack structure is divided into a plurality of blocks. The middle section of a seal ring extends through the composite stack structure in the second region. The middle section of the seal ring includes a body part extending through the composite stack structure in the second region and a liner layer located between the body part and the composite stack structure.

Description

記憶體元件、半導體元件及其製造方法Memory element, semiconductor element and manufacturing method thereof

本發明是有關於一種半導體元件及其製造方法,且特別是有關於一種記憶體元件及其製造方法。 The present invention relates to a semiconductor element and its manufacturing method, and in particular to a memory element and its manufacturing method.

非揮發性記憶體具有可使得存入的資料在斷電後也不會消失的優點,因此廣泛採用於個人電腦和其他電子設備中。目前業界較常使用的三維記憶體包括反或式(NOR)記憶體以及反及式(NAND)記憶體。此外,另一種三維記憶體為及式(AND)記憶體,其可應用在多維度的記憶體陣列中而具有高積集度與高面積利用率,且具有操作速度快的優點。因此,三維記憶體元件的發展已逐漸成為目前的趨勢。 Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it is widely used in personal computers and other electronic devices. The 3D memory commonly used in the industry currently includes a Negative-Or (NOR) memory and a Negative-And (NAND) memory. In addition, another type of three-dimensional memory is AND memory, which can be applied in a multi-dimensional memory array and has high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become a current trend.

本發明提出一種記憶體元件可以將相鄰的兩塊元區的堆疊結構有效隔絕,減少或避免基底和接地導體層之間的漏電路徑而增加關閉電流Ioff,降低對於記憶單元操作的影響。 The present invention proposes a memory element that can effectively isolate the stacked structure of two adjacent cell areas, reduce or avoid the leakage path between the substrate and the ground conductor layer to increase the off-current I off , and reduce the impact on the operation of the memory unit.

本發明提出一種記憶體元件的製造方法可以在形成記憶體元件的同時在塊元區的外圍形成密封環,因此,可以與現有的製程整合,而不會增加製程的步驟。 The present invention proposes a manufacturing method of a memory element, which can form a sealing ring on the periphery of the block region while forming the memory element, so that it can be integrated with the existing manufacturing process without increasing the steps of the manufacturing process.

本發明的一實施例提出一種記憶體元件,包括:介電基底、複合堆疊結構、多個記憶單元、分隔結構以及密封環的中間段。所述介電基底包括第一區與環繞在所述第一區周圍的第二區。所述複合堆疊結構在所述第一區與所述第二區中的所述介電基底上方。所述多個記憶單元位於所述複合堆疊結構中。所述分隔結構延伸穿過位於所述第一區的所述複合堆疊結構,將所述複合堆疊結構分隔為多個區塊。所述密封環的中間段延伸穿過位於所述第二區的所述複合堆疊結構。所述密封環的所述中間段包括主體部與襯層。所述主體部延伸穿過位於所述第二區的所述複合堆疊結構。所述襯層位於所述主體部與所述複合堆疊結構之間。 An embodiment of the present invention provides a memory device, including: a dielectric substrate, a composite stack structure, a plurality of memory cells, a separation structure, and a middle section of a sealing ring. The dielectric substrate includes a first region and a second region surrounding the first region. The composite stack structure is over the dielectric substrate in the first region and the second region. The plurality of memory cells are located in the composite stack structure. The separation structure extends through the composite stacked structure located in the first region, separating the composite stacked structure into a plurality of blocks. A middle section of the seal ring extends through the composite stack structure in the second region. The intermediate section of the seal ring includes a body portion and a liner. The body portion extends through the composite stack structure located in the second region. The liner is located between the body portion and the composite stack structure.

本發明的一實施例提出一種記憶體元件的製造方法,包括以下步驟。提供介電基底,介電基底包括第一區與環繞在所述第一區周圍的第二區。形成堆疊結構於所述第一區與所述第二區中的所述介電基底上方,其中所述堆疊結構包括交替堆疊的多個絕緣層與多個中間層。形成分隔結構與密封環的中間段。所述分隔結構位於所述第一區中的所述堆疊結構中,所述密封環的所述中間段位於所述第二區中的所述堆疊結構中。 An embodiment of the present invention provides a manufacturing method of a memory device, which includes the following steps. A dielectric substrate is provided, including a first region and a second region surrounding the first region. A stack structure is formed above the dielectric substrate in the first region and the second region, wherein the stack structure includes a plurality of insulating layers and a plurality of intermediate layers stacked alternately. Form the middle section of the separation structure and the sealing ring. The separation structure is located in the stacked structure in the first zone, and the intermediate section of the sealing ring is located in the stacked structure in the second zone.

本發明的一實施例提出一種半導體元件,包括複合堆疊結構、密封環的中間段、上段與下段。所述複合堆疊結構在介電 基底上方。所述複合堆疊結構包括多個導體層與多個絕緣層交替堆疊而成。所述中間段延伸穿過所述複合堆疊結構,且與所述多個導體層電性絕緣。所述上段位於所述中間段上方且與所述中間段連接。所述下段位於所述中間段下方且與所述中間段連接。 An embodiment of the present invention provides a semiconductor device, including a composite stack structure, a middle section, an upper section and a lower section of a sealing ring. The composite stack structure is in a dielectric above the substrate. The composite stack structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately. The middle section extends through the composite stack structure and is electrically insulated from the plurality of conductor layers. The upper section is located above and connected to the middle section. The lower section is located below the middle section and connected with the middle section.

基於上述,本發明實施例之記憶體的密封環可以從基底的表面向上穿過接地導體層,而連續延伸至上內連線結構的頂面。因此,本發明實施例之記憶體可以將相鄰的兩塊元區的堆疊結構有效隔絕,減少或避免基底和接地導體層之間的漏電路徑而增加關閉電流Ioff,降低對於記憶單元操作的影響。 Based on the above, the sealing ring of the memory in the embodiment of the present invention can extend upwards from the surface of the substrate through the grounding conductor layer, and continuously extend to the top surface of the upper interconnection structure. Therefore, the memory of the embodiment of the present invention can effectively isolate the stack structure of two adjacent cell areas, reduce or avoid the leakage path between the substrate and the ground conductor layer to increase the off-current I off , and reduce the operation of the memory cell. Influence.

本發明實施例之記憶體的製造方法可以在形成記憶體元件的同時在塊元區的外圍形成密封環,因此,可以與現有的製程整合,而不會增加製程的步驟。 The manufacturing method of the memory according to the embodiment of the present invention can form a sealing ring on the periphery of the block region while forming the memory element, so it can be integrated with the existing manufacturing process without increasing the steps of the manufacturing process.

10、A(i)、A(i+1):記憶體陣列 10. A (i) , A (i+1) : memory array

10:記憶體陣列 10: Memory array

12:電荷儲存層 12: Charge storage layer

14:穿隧層 14: Tunneling layer

16:通道柱 16: Channel column

20:記憶單元 20: memory unit

24:絕緣填充層 24: insulating filling layer

28:絕緣柱 28: Insulation column

62、62a、62b、68、68a、68b:介電層 62, 62a, 62b, 68, 68a, 68b: dielectric layer

32a:源極柱/導體柱/第一導體柱 32a: source post/conductor post/first conductor post

32b:汲極柱/導體柱/第二導體柱 32b: drain pole/conductor column/second conductor column

36:阻擋層 36: barrier layer

38:閘極層/字元線 38:Gate layer/word line

40:電荷儲存結構 40:Charge storage structure

50、100:介電基底 50, 100: Dielectric substrate

50s:表面 50s: surface

52、GSK:閘極堆疊結構 52. GSK: gate stack structure

103:導體層 103: conductor layer

54、101、104:絕緣層 54, 101, 104: insulating layer

60:箭頭 60: Arrow

64a、64b:插塞 64a, 64b: Plugs

66a、66b、72a、72b、236a、236b:導線 66a, 66b, 72a, 72b, 236a, 236b: wire

70a、70b:介層窗 70a, 70b: vias

99:基底 99: base

106:中間層 106: middle layer

130:上內連線結構 130: Upper inner connection structure

133:使得溝渠 133: make ditches

133a、133b:溝渠 133a, 133b: ditches

138:閘極層 138:Gate layer

142a、142b:襯層 142a, 142b: lining

144a、144b:主體部 144a, 144b: main body

220:電路結構 220: Circuit structure

230:下內連線結構 230: Bottom inner connection structure

233:導體內連線 233: Conductor interconnection

236a、236b:導線 236a, 236b: wires

CSK:複合堆疊結構 CSK: composite stack structure

DS:密封環 DS: sealing ring

DSM:中間段 DSM: middle segment

DSU:上段 DSU: upper segment

M1:第一導體層 M1: the first conductor layer

M2:第二導體層 M2: second conductor layer

P1:第一部分 P1: part one

P2:第二部分 P2: Part Two

R1:第一區 R1: Region 1

R2:第二區 R2: second area

SK1、SK2:堆疊結構 SK1, SK2: stacked structure

SLT:分隔結構 SLT: Separation Structure

T1:第一塊元區 T1: the first meta area

T2:第二塊元區 T2: The second meta area

VC:柱狀結構 VC: columnar structure

WL(i)m、WL(i)m+1、WL(i+1)m、WL(i+1)m+1:字元線 WL(i)m, WL(i)m+1, WL(i+1)m, WL(i+1)m+1: word line

X、Y、Z:方向 X, Y, Z: direction

I-I’、II-II’、III-III’、IV-IV’、V-V’、VI-VI’:線 I-I', II-II', III-III', IV-IV', V-V', VI-VI': line

B、B1、B2、BLOCK、 BLOCK(i)、BLOCK(i+1):子區塊 B, B1, B2, BLOCK, BLOCK (i) , BLOCK (i+1) : sub-blocks

BLn、BLn+1:位元線 BL n , BL n+1 : bit lines

SP(i) n、SP(i) n+1、SP(i+1) n、SP(i+1) n+1:源極柱 SP (i) n , SP (i) n+1 , SP (i+1) n , SP (i+1) n+1 : source pole

DP(i) n、DPi) n+1、DPi+1) n、DP(i+1) n+1:源極柱 DP (i) n , DP i) n+1 , DP i+1) n , DP (i+1) n+1 : source pole

WL(i) m、WL(i) m+1、WL(i+1) m、WL(i+1) m+1:字元線 WL (i) m , WL (i) m+1 , WL (i+1) m , WL (i+1) m+1 : word line

CSK:複合堆疊結構 CSK: composite stack structure

DS:密封環 DS: sealing ring

DSM:中間段 DSM: middle section

SLT:分隔結構 SLT: Separation Structure

M1:第一導體層 M1: the first conductor layer

M2:第二導體層 M2: second conductor layer

P1:第一部分 P1: part one

P2:第二部分 P2: Part Two

SLT:分隔結構 SLT: Separation Structure

X、Y、Z:方向 X, Y, Z: direction

I-I’、II-II’、III-III’、IV-IV’、V-V’、VI-VI’:線 I-I', II-II', III-III', IV-IV', V-V', VI-VI': line

圖1A示出根據一些實施例的3D AND快閃記憶體陣列的電路圖。 Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments.

圖1B示出圖1A中部分的記憶體陣列的局部三維視圖。 FIG. 1B shows a partial three-dimensional view of a portion of the memory array in FIG. 1A .

圖1C與圖1D示出圖1B的切線I-I’的剖面圖。 FIG. 1C and FIG. 1D show cross-sectional views of the line I-I' in FIG. 1B.

圖1E示出圖1B、圖1C、圖1D的切線II-II’的上視圖。 Fig. 1E shows a top view of the line II-II' of Fig. 1B, Fig. 1C, Fig. 1D.

圖1F示出3D AND快閃記憶體的上視圖。 FIG. 1F shows a top view of a 3D AND flash memory.

圖2A至圖2J示出根據一些實施例的3D AND快閃記憶體的 製造流程的上視圖。 2A to FIG. 2J illustrate the 3D AND flash memory according to some embodiments Top view of the manufacturing process.

圖3A至圖3J示出為圖2A至圖2J的線III-III’的剖面圖。 3A to 3J are shown as cross-sectional views along line III-III' of FIGS. 2A to 2J .

圖4A至圖4J示出為圖2A至圖2J的線IV-IV’的剖面圖。 4A to 4J are shown as cross-sectional views along line IV-IV' of FIGS. 2A to 2J .

圖5示出根據另一些實施例的3D AND快閃記憶體的上視圖。 FIG. 5 shows a top view of a 3D AND flash memory according to other embodiments.

圖6示出為圖5的線V-V’的剖面圖。 Fig. 6 is a cross-sectional view taken along line V-V' of Fig. 5 .

圖7示出為圖5的線VI-VI’的剖面圖。 Fig. 7 is a cross-sectional view taken along line VI-VI' of Fig. 5 .

本實施例之密封環延伸穿過複合堆疊結構。此複合堆疊結構可以用來形成各種半導體元件,例如是記憶體元件。為簡要起見,以下以3D AND快閃記憶體來說明,然而,本發明並不限於此。 The sealing ring of this embodiment extends through the composite stack structure. The composite stack structure can be used to form various semiconductor devices, such as memory devices. For the sake of brevity, 3D AND flash memory is used for description below, however, the present invention is not limited thereto.

圖1A示出根據一些實施例的3D AND快閃記憶體陣列的電路圖。圖1B示出圖1A中部分的記憶體陣列的局部三維視圖。圖1C與圖1D示出圖1B的切線I-I’的剖面圖。圖1E示出圖1B、圖1C與圖1D的切線II-II’的上視圖。 Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a partial three-dimensional view of a portion of the memory array in FIG. 1A . FIG. 1C and FIG. 1D show cross-sectional views of the line I-I' in FIG. 1B. Fig. 1E shows a top view of the line II-II' of Fig. 1B, Fig. 1C and Fig. 1D.

圖1A為包括配置成列及行的垂直AND記憶體陣列10的2個區塊BLOCK(i)與BLOCK(i+1)的示意圖。區塊BLOCK(i)中包括記憶體陣列A(i)。記憶體陣列A(i)的一列(例如是第m+1列)是具有共同字元線(例如WL(i) m+1)的AND記憶單元20集合。記憶體陣列A(i)的每一列(例如是第m+1列)的AND記憶單元20對應於共同字元線(例如WL(i) m+1),且耦接至不同的源極柱(例如 SP(i) n與SP(i) n+1)與汲極柱(例如DP(i) n與DP(i) n+1),從而使得AND記憶單元20沿共同字元線(例如WL(i) m+1)邏輯地配置成一列。 FIG. 1A is a schematic diagram of two blocks BLOCK (i) and BLOCK (i+1) including vertical AND memory arrays 10 arranged in columns and rows. Block BLOCK (i) includes memory array A (i) . A column (eg column m+1) of the memory array A (i) is a set of AND memory cells 20 having a common word line (eg WL (i) m+1 ). The AND memory cells 20 of each column (eg column m+1) of the memory array A (i) correspond to a common word line (eg WL (i) m+1 ), and are coupled to different source columns (such as SP (i) n and SP (i) n+1 ) and drain poles (such as DP (i) n and DP (i) n+1 ), so that the AND memory cell 20 is along a common word line (such as WL (i) m+1 ) are logically arranged in a column.

記憶體陣列A(i)的一行(例如是第n行)是具有共同源極柱(例如SP(i) n)與共同汲極柱(例如DP(i) n)的AND記憶單元20集合。記憶體陣列A(i)的每一行(例如是第n行)的AND記憶單元20對應於不同字元線(例如WL(i) m+1與WL(i) m),且耦接至共同的源極柱(例如SP(i) n)與共同的汲極柱(例如DP(i) n)。因此,記憶體陣列A(i)的AND記憶單元20沿共同源極柱(例如SP(i) n)與共同汲極柱(例如DP(i) n)邏輯地配置成一行。在實體佈局中,根據所應用的製造方法,行或列可經扭曲,以蜂巢式模式或其他方式配置,以用於高密度或其他原因。 A row (eg row n ) of the memory array A(i) is a set of AND memory cells 20 having a common source column (eg SP (i) n ) and a common drain column (eg DP (i) n ). The AND memory cells 20 of each row (eg row n) of the memory array A (i) correspond to different word lines (eg WL (i) m+1 and WL (i) m ), and are coupled to a common source posts (eg SP (i) n ) and common drain posts (eg DP (i) n ). Therefore, the AND memory cells 20 of the memory array A (i) are logically arranged in a row along a common source column (eg SP (i) n ) and a common drain column (eg DP (i) n ). In a physical layout, the rows or columns may be distorted, arranged in a honeycomb pattern or otherwise, for high density or for other reasons, depending on the fabrication method applied.

在圖1A中,在區塊BLOCK(i)中,記憶體陣列A(i)的第n行的AND記憶單元20共用共同的源極柱(例如SP(i) n)與共同的汲極柱(例如DP(i) n)。第n+1行的AND記憶單元20共用共同的源極柱(例如SP(i) n+1)與共同的汲極柱(例如DP(i) n+1)。 In FIG. 1A, in the block BLOCK (i) , the AND memory cells 20 in the nth row of the memory array A (i) share a common source column (for example, SP (i) n ) and a common drain column. (eg DP (i) n ). The AND memory cells 20 in the n+1th row share a common source column (eg SP (i) n+1 ) and a common drain column (eg DP (i) n+1 ).

共同的源極柱(例如SP(i) n)耦接至共同的源極線(例如SLn);共同的汲極柱(例如DP(i) n)耦接至共同的位元線(例如BLn)。共同的源極柱(例如SP(i) n+1)耦接至共同的源極線(例如SLn+1);共同的汲極柱(例如DP(i) n+1)耦接至共同的位元線(例如BLn+1)。 A common source post (eg SP (i) n ) is coupled to a common source line (eg SL n ); a common drain post (eg DP (i) n ) is coupled to a common bit line (eg BL n ). A common source post (eg SP (i) n+1 ) is coupled to a common source line (eg SL n+1 ); a common drain post (eg DP (i) n+1 ) is coupled to a common bit line (eg BL n+1 ).

相似地,區塊BLOCK(i+1)包括記憶體陣列A(i+1),其與在區塊BLOCK(i)中的記憶體陣列A(i)相似。記憶體陣列A(i+1)的一列(例如是第m+1列)是具有共同字元線(例如WL(i+1) m+1)的AND 記憶單元20集合。記憶體陣列A(i+1)的每一列(例如是第m+1列)的AND記憶單元20對應於共同字元線(例如WL(i+1) m+1),且耦接至不同的源極柱(例如SP(i+1) n與SP(i+1) n+1)與汲極柱(例如DP(i+1) n與DP(i+1) n+1)。記憶體陣列A(i+1)的一行(例如是第n行)是具有共同源極柱(例如SP(i+1) n)與共同汲極柱(例如DP(i+1) n)的AND記憶單元20集合,這些AND記憶單元20集合彼此並聯,又稱為記憶體串。記憶體陣列A(i+1)的每一行(例如是第n行)的AND記憶單元20對應於不同字元線(例如WL(i+1) m+1與WL(i+1) m),且耦接至共同的源極柱(例如SP(i+1) n)與共同的汲極柱(例如DP(i+1) n)。因此,記憶體陣列A(i+1)的AND記憶單元20沿共同源極柱(例如SP(i+1) n)與共同汲極柱(例如DP(i+1) n)邏輯地配置成一行。 Similarly, block BLOCK (i+1) includes memory array A (i+1) which is similar to memory array A (i) in block BLOCK (i) . A column (eg column m +1) of the memory array A (i +1) is a set of AND memory cells 20 having a common word line (eg WL (i+1) m+1 ). The AND memory cells 20 of each column (eg column m+1) of the memory array A (i +1) correspond to a common word line (eg WL (i+1) m+1 ), and are coupled to different source columns (eg SP (i+1) n and SP (i+1) n+1 ) and drain columns (eg DP (i+1) n and DP (i+1) n+1 ). A row (eg row n) of the memory array A (i+1) has a common source column (eg SP (i+1) n ) and a common drain column (eg DP (i+1) n ). A set of AND memory units 20 is connected in parallel with each other, which is also called a memory string. The AND memory cells 20 of each row (eg row n) of the memory array A (i+1) correspond to different word lines (eg WL (i+1) m+1 and WL (i+1) m ) , and coupled to a common source post (eg SP (i+1) n ) and a common drain post (eg DP (i+1) n ). Therefore, the AND memory cells 20 of the memory array A (i+1) are logically configured along a common source column (eg SP (i+1) n ) and a common drain column (eg DP (i+1) n ). one line.

區塊BLOCK(i+1)與區塊BLOCK(i)共用源極線(例如是SLn與SLn+1)與位元線(例如BLn與BLn+1)。因此,源極線SLn與位元線BLn耦接至區塊BLOCK(i)的AND記憶體陣列A(i)中的第n行AND記憶單元20,且耦接至區塊BLOCK(i+1)中的AND記憶體陣列A(i+1)中的第n行AND記憶單元20。同樣,源極線SLn+1與位元線BLn+1耦接至區塊BLOCK(i)的AND記憶體陣列A(i)中的第n+1行AND記憶單元20,且耦接至區塊BLOCK(i+1)中的AND記憶體陣列A(i+1)中的第n+1行AND記憶單元20。 Block BLOCK (i+1) and block BLOCK (i) share source lines (such as SL n and SL n+1 ) and bit lines (such as BL n and BL n+1 ). Therefore, the source line SL n and the bit line BL n are coupled to the nth row of AND memory cells 20 in the AND memory array A (i) of the block BLOCK ( i) , and are coupled to the block BLOCK (i +1) in the AND memory cell 20 in the nth row of the AND memory array A (i+1) . Similarly, the source line SL n+1 and the bit line BL n+1 are coupled to the n+1th row of AND memory cells 20 in the AND memory array A (i) of the block BLOCK (i ), and are coupled to To the AND memory unit 20 in the n+1th row of the AND memory array A ( i+1) in the block BLOCK (i +1).

請參照圖1B至圖1D,記憶體陣列10可安置於半導體晶粒的內連線結構上,諸如,安置於在半導體基底上形成的一或多個主動元件(例如電晶體)上方。因此,介電基底50例如是形成於矽基底上的金屬內連線結構上方的介電層,例如氧化矽層。記 憶體陣列10可包括閘極堆疊結構52、多個通道柱16、多個第一導體柱(又可稱為源極柱)32a與多個第二導體柱(又可稱為汲極柱)32b和多個電荷儲存結構40。 Referring to FIG. 1B to FIG. 1D , the memory array 10 can be disposed on the interconnect structure of the semiconductor die, such as disposed on one or more active devices (such as transistors) formed on the semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed above the metal interconnect structure on the silicon substrate. remember The memory array 10 may include a gate stack structure 52, a plurality of channel pillars 16, a plurality of first conductive pillars (also called source pillars) 32a, and a plurality of second conductive pillars (also called drain pillars). 32b and a plurality of charge storage structures 40.

請參照圖1B,閘極堆疊結構52形成在陣列區(未示出)與階梯區(未示出)的介電基底50上。閘極堆疊結構52包括在介電基底50的表面50s上垂直堆疊的多個閘極層(又稱為字元線)38與多層的絕緣層54。在Z方向上,這些閘極層38藉由設置在其彼此之間的絕緣層54電性隔離。閘極層38在與介電基底50的表面平行的方向上延伸。階梯區的閘極層38可具有階梯結構(未示出)。因此,下部的閘極層38比上部閘極層38長,且下部的閘極層38的末端橫向延伸出上部閘極層38的末端。用於連接閘極層38的接觸窗(未示出)可著陸於閘極層38的末端,藉以將各層閘極層38連接至各個導線。 Referring to FIG. 1B , the gate stack structure 52 is formed on the dielectric substrate 50 in the array area (not shown) and the step area (not shown). The gate stack structure 52 includes a plurality of gate layers (also referred to as word lines) 38 and multiple layers of insulating layers 54 vertically stacked on the surface 50 s of the dielectric substrate 50 . In the Z direction, the gate layers 38 are electrically isolated by an insulating layer 54 disposed between them. The gate layer 38 extends in a direction parallel to the surface of the dielectric substrate 50 . The gate layer 38 of the stepped region may have a stepped structure (not shown). Therefore, the lower gate layer 38 is longer than the upper gate layer 38 , and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38 . Contacts (not shown) for connecting to the gate layer 38 may be landed at the ends of the gate layer 38 to connect each gate layer 38 to each wire.

請參照圖1B至圖1D,記憶體陣列10還包括在垂直於閘極層38的表面(即XY平面)的方向(即Z方向)上延伸的多個通道柱16。在一些實施例中,通道柱16連續延伸穿過第一區R1的閘極堆疊結構52。在一些實施例中,通道柱16不連續延伸穿過第一區R1的閘極堆疊結構52。在一些實施例中,通道柱16於上視角度來看可具有環形的形狀(如圖1B所示)。通道柱16的材料可以是半導體,例如是未摻雜的多晶矽。通道柱16也可稱為垂直通道(vertical channel)。 Referring to FIG. 1B to FIG. 1D , the memory array 10 further includes a plurality of channel pillars 16 extending in a direction (ie, Z direction) perpendicular to the surface of the gate layer 38 (ie, XY plane). In some embodiments, the channel pillar 16 extends continuously through the gate stack structure 52 of the first region R1. In some embodiments, the channel pillar 16 discontinuously extends through the gate stack structure 52 of the first region R1. In some embodiments, the channel post 16 may have a ring shape when viewed from above (as shown in FIG. 1B ). The material of the channel pillar 16 can be semiconductor, such as undoped polysilicon. The channel post 16 may also be called a vertical channel.

請參照圖1B至圖1D,記憶體陣列10還包括絕緣填充層24、絕緣柱28、多個第一導體柱32a與多個第二導體柱32b。在 此例中,第一導體柱32a做為源極柱;第二導體柱32b做為汲極柱。第一導體柱32a與第二導體柱32b以及絕緣柱28各自在垂直於閘極層38的表面(即XY平面)的方向(即Z方向)上延伸。第一導體柱32a與第二導體柱32b藉由絕緣柱28分隔。第一導體柱32a與第二導體柱32b電性連接該通道柱16。第一導體柱32a與第二導體柱32b包括摻雜的多晶矽或金屬材料。絕緣填充層24例如是氧化矽。絕緣柱28例如是氮化矽或是氧化矽。 Referring to FIG. 1B to FIG. 1D , the memory array 10 further includes an insulating filling layer 24 , an insulating pillar 28 , a plurality of first conductive pillars 32 a and a plurality of second conductive pillars 32 b. exist In this example, the first conductive column 32a is used as a source column; the second conductive column 32b is used as a drain column. The first conductive pillar 32a, the second conductive pillar 32b and the insulating pillar 28 each extend in a direction (ie, a Z direction) perpendicular to a surface of the gate layer 38 (ie, an XY plane). The first conductor column 32 a and the second conductor column 32 b are separated by the insulating column 28 . The first conductive post 32 a and the second conductive post 32 b are electrically connected to the channel post 16 . The first conductive pillar 32a and the second conductive pillar 32b include doped polysilicon or metal material. The insulating filling layer 24 is, for example, silicon oxide. The insulating pillar 28 is, for example, silicon nitride or silicon oxide.

請參照圖1C與圖1D,電荷儲存結構40設置於通道柱16與多層閘極層38之間。電荷儲存結構40可以包括穿隧層(或稱為能隙工程穿隧氧化層)14、電荷儲存層12以及阻擋層36。電荷儲存層12位於穿隧層14與阻擋層36之間。在一些實施例中,穿隧層14以及阻擋層36包括氧化矽。電荷儲存層12包括氮化矽,或其他包括可以捕捉以電荷的材料。在一些實施例中,如圖1C所示,電荷儲存結構40的一部分(穿隧層14與電荷儲存層12)在垂直於閘極層38的方向(即Z方向)上連續延伸,而電荷儲存結構40的另一部分(阻擋層36)環繞於閘極層38的周圍。在另一些實施例中,如圖1D所示,電荷儲存結構40(穿隧層14、電荷儲存層12與阻擋層36)環繞於閘極層38的周圍。 Referring to FIG. 1C and FIG. 1D , the charge storage structure 40 is disposed between the channel pillar 16 and the multilayer gate layer 38 . The charge storage structure 40 may include a tunneling layer (or called a bandgap engineered tunneling oxide layer) 14 , a charge storage layer 12 and a blocking layer 36 . The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36 . In some embodiments, the tunneling layer 14 and the barrier layer 36 include silicon oxide. The charge storage layer 12 includes silicon nitride, or other materials that can trap charges. In some embodiments, as shown in FIG. 1C , a part of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12 ) extends continuously in the direction perpendicular to the gate layer 38 (ie, the Z direction), and the charge storage Another portion of structure 40 (barrier layer 36 ) surrounds gate layer 38 . In other embodiments, as shown in FIG. 1D , the charge storage structure 40 (the tunneling layer 14 , the charge storage layer 12 and the blocking layer 36 ) surrounds the gate layer 38 .

請參照圖1E,電荷儲存結構40、通道柱16以及源極柱32a與汲極柱32b被閘極層38環繞,並且界定出記憶單元20。記憶單元20可藉由不同的操作方法進行1位元操作或2位元操作。舉例來說,在對源極柱32a與汲極柱32b施加電壓時,由於源極柱32a與汲極柱32b與通道柱16連接,因此電子可沿著通道柱16傳送並儲存在整個電荷儲存結構40中,如此可對記憶單元20進 行1位元的操作。此外,對於利用福勒-諾德漢穿隧(Fowler-Nordheim tunneling)的操作來說,可使電子或是電洞被捕捉在源極柱32a與汲極柱32b之間的電荷儲存結構40中。對於源極側注入(source side injection)、通道熱電子(channel-hot-electron)注入或帶對帶穿隧熱載子(band-to-band tunneling hot carrier)注入的操作來說,可使電子或電洞被局部地捕捉在鄰近兩個源極柱32a與汲極柱32b中的一者的電荷儲存結構40中,如此可對記憶單元20進行單位晶胞(SLC,1位元)或多位晶胞(MLC,大於或等於2位元)的操作。 Referring to FIG. 1E , the charge storage structure 40 , the channel column 16 , the source column 32 a and the drain column 32 b are surrounded by the gate layer 38 and define the memory cell 20 . The memory unit 20 can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column 32a and the drain column 32b, since the source column 32a and the drain column 32b are connected to the channel column 16, electrons can be transmitted along the channel column 16 and stored in the entire charge storage In the structure 40, the memory unit 20 can be Perform 1-bit operations. In addition, for the operation using Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and the drain post 32b. . For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electron Or the holes are locally trapped in the charge storage structure 40 adjacent to one of the two source posts 32a and drain posts 32b, so that the memory cell 20 can be unit cell (SLC, 1 bit) or more Bit cell (MLC, greater than or equal to 2 bits) operations.

請參照圖1A與圖1B,在進行操作時,將電壓施加至所選擇的字元線(閘極層)38,例如施加高於對應記憶單元20的相應起始電壓(Vth)時,與所選擇的字元線38相交的通道柱16被導通,而允許電流從位元線BLn或BLn+1(示於圖1B)進入汲極柱32b,並經由導通的通道區流至源極柱32a(例如,在由箭頭60所指示的方向上),最後流到源極線SLn或SLn+1(示於圖1B)。 Referring to FIG. 1A and FIG. 1B, during operation, a voltage is applied to the selected word line (gate layer) 38, for example, when applying a corresponding starting voltage (V th ) higher than the corresponding memory cell 20, and The channel pillar 16 intersected by the selected wordline 38 is turned on, allowing current to enter the drain pillar 32b from the bitline BLn or BLn +1 (shown in FIG. 1B ) and flow to the source through the turned on channel region. Pole 32a (eg, in the direction indicated by arrow 60), eventually flows to source line SLn or SLn +1 (shown in FIG. 1B ).

請參照1F,在本發明的一些實施例中,在第一塊元區T1或第二塊元區T2的第一區R1中的堆疊結構被至少一分隔結構SLT區分為多個區塊(例如B1與B2)。在形成分隔結構SLT的同時,也在第二區(例如周邊區)R2的堆疊結構中形成密封環DS的中間段DSM。分隔結構SLT以及密封環DS的中間段DSM的形成方法可以參照圖2A至圖2J、圖3A至圖3J所示以及圖4A至圖4J所示。 Please refer to 1F, in some embodiments of the present invention, the stacked structure in the first area R1 of the first block meta area T1 or the second block meta area T2 is divided into a plurality of blocks by at least one partition structure SLT (for example B1 and B2). While forming the separation structure SLT, the middle section DSM of the seal ring DS is also formed in the stacked structure of the second region (eg, the peripheral region) R2. The methods for forming the separation structure SLT and the middle section DSM of the sealing ring DS can refer to those shown in FIGS. 2A to 2J , 3A to 3J , and 4A to 4J .

圖2A至圖2J示出根據一些實施例的3D AND快閃記憶體的製造流程的上視圖。圖3A至圖3J為圖2A至圖2J的線III-III’ 的剖面圖。圖4A至圖4J為圖2A至圖2J的線IV-IV’的剖面圖。此外,為清楚起見,有一些層或構件未示出於圖2A至圖2J以及圖3F中。 2A-2J illustrate top views of the fabrication flow of a 3D AND flash memory according to some embodiments. Fig. 3A to Fig. 3J are the line III-III' of Fig. 2A to Fig. 2J sectional view. 4A to 4J are cross-sectional views of line IV-IV' in FIGS. 2A to 2J . Additionally, for clarity, some layers or components are not shown in FIGS. 2A-2J and 3F.

請參照圖2A、圖3A與圖4A,提供介電基底100。介電基底100例如是形成於矽基底上的下內連線結構之上的介電層,例如氧化矽層。介電基底100包括第一區R1與環繞在第一區R1周圍的第二區R2。第一區R1又可以稱為塊元區,第二區R2又可以稱為周邊區。於第一區R1與第二區R2的介電基底100上形成堆疊結構SK1。堆疊結構SK1又可稱為絕緣堆疊結構SK1。在本實施例中,堆疊結構SK1由交錯堆疊於介電基底100上的絕緣層104與中間層106所構成。在其他實施例中,堆疊結構SK1可由交錯堆疊於介電基底100上的中間層106與絕緣層104所構成。絕緣層104例如為氧化矽。中間層106例如為氮化矽。中間層106可作為犧牲層,在後續的製程中被全部或局部移除。在本實施例中,堆疊結構SK1具有8層絕緣層104與7層中間層106,但本發明不限於此。在其他實施例中,可視實際需求來形成更多層的絕緣層104與更多層的中間層106。 Referring to FIG. 2A , FIG. 3A and FIG. 4A , a dielectric substrate 100 is provided. The dielectric substrate 100 is, for example, a dielectric layer, such as a silicon oxide layer, formed on a lower interconnection structure on a silicon substrate. The dielectric substrate 100 includes a first region R1 and a second region R2 surrounding the first region R1. The first area R1 may also be called a block element area, and the second area R2 may also be called a peripheral area. A stack structure SK1 is formed on the dielectric substrate 100 in the first region R1 and the second region R2. The stack structure SK1 can also be called an insulating stack structure SK1. In the present embodiment, the stacked structure SK1 is composed of insulating layers 104 and intermediate layers 106 stacked alternately on the dielectric substrate 100 . In other embodiments, the stack structure SK1 may be formed by interleaved interlayers 106 and insulating layers 104 stacked on the dielectric substrate 100 . The insulating layer 104 is, for example, silicon oxide. The middle layer 106 is, for example, silicon nitride. The middle layer 106 can be used as a sacrificial layer, which is completely or partially removed in subsequent processes. In this embodiment, the stack structure SK1 has 8 insulating layers 104 and 7 intermediate layers 106 , but the invention is not limited thereto. In other embodiments, more insulating layers 104 and more intermediate layers 106 can be formed according to actual needs.

在一些實施例中,在形成堆疊結構SK1之前,在介電基底100上先形成導體層103。絕緣層101例如是氧化矽。導體層103例如是接地的多晶矽層。導體層103又可以稱為虛設閘極,其可以用來關閉漏電路徑。 In some embodiments, before forming the stack structure SK1 , the conductor layer 103 is first formed on the dielectric substrate 100 . The insulating layer 101 is, for example, silicon oxide. The conductive layer 103 is, for example, a grounded polysilicon layer. The conductive layer 103 can also be called a dummy gate, which can be used to close the leakage path.

將堆疊結構SK1圖案化,以在第一區R1的階梯區(未 示出)形成階梯結構(未示出)。 The stacked structure SK1 is patterned so that in the step region of the first region R1 (not shown) to form a ladder structure (not shown).

接著,請參照圖2B、圖3B與圖4B,於第一區R1的堆疊結構SK1中形成多個柱狀結構VC。在一些實施例中,每一柱狀結構VC可以包括圖1C的通道柱16、第一導體柱32a、第二導體柱32b、電荷儲存結構40的穿隧層14與電荷儲存層12、絕緣柱28以及絕緣填充層24。在另一些實施例中,每一柱狀結構VC可以包括圖1D的通道柱16、第一導體柱32a、第二導體柱32b、絕緣柱28以及絕緣填充層24。為簡要起見,僅以柱狀結構VC來表示,而不一一示出其詳細的構件。通道柱16、第一導體柱32a、第二導體柱32b、電荷儲存結構40的穿隧層14與電荷儲存層12、絕緣柱28以及絕緣填充層24可以採用任何已知的方法來形成,於此不再詳述。 Next, referring to FIG. 2B , FIG. 3B and FIG. 4B , a plurality of columnar structures VC are formed in the stacked structure SK1 in the first region R1 . In some embodiments, each pillar structure VC may include the channel pillar 16 shown in FIG. 1C , the first conductor pillar 32a, the second conductor pillar 32b, the tunneling layer 14 and the charge storage layer 12 of the charge storage structure 40, and an insulating pillar. 28 and insulating filling layer 24. In some other embodiments, each pillar structure VC may include the channel pillar 16 , the first conductor pillar 32 a , the second conductor pillar 32 b , the insulating pillar 28 and the insulating filling layer 24 shown in FIG. 1D . For the sake of brevity, only the columnar structure VC is used to represent it, and its detailed components are not shown one by one. The channel column 16, the first conductive column 32a, the second conductive column 32b, the tunneling layer 14 and the charge storage layer 12 of the charge storage structure 40, the insulating column 28 and the insulating filling layer 24 can be formed by any known method. This will not be described in detail.

請參照圖2C至圖2E、圖3C至圖3E以及圖4C至圖4E,進行取代製程,以將多層中間層106取代為多層閘極層138。首先,參照圖2C、圖3C與圖4C,對堆疊結構SK1進行圖案化製程,例如是微影與蝕刻製程,以在第一區R1與第二區R2分別形成溝渠133a與133b。在進行蝕刻製程時,可以導體層103做為蝕刻停止層,使得溝渠133裸露出導體層103。 Referring to FIGS. 2C to 2E , FIGS. 3C to 3E , and FIGS. 4C to 4E , a replacement process is performed to replace the multilayer intermediate layer 106 with the multilayer gate layer 138 . First, referring to FIG. 2C , FIG. 3C and FIG. 4C , a patterning process, such as lithography and etching process, is performed on the stacked structure SK1 to form trenches 133 a and 133 b in the first region R1 and the second region R2 respectively. During the etching process, the conductive layer 103 can be used as an etching stop layer, so that the trench 133 exposes the conductive layer 103 .

請參照圖2C,從上視圖觀之,溝渠133a沿著X方向延伸,使第一區R1的堆疊結構SK1分割成多個區塊B1與B2。從上視圖觀之,溝渠133b具有環形輪廓,與第一區R1相隔非零距離,而環繞在第一區R1的周圍。 Referring to FIG. 2C , from a top view, the trench 133 a extends along the X direction, so that the stacked structure SK1 of the first region R1 is divided into a plurality of blocks B1 and B2 . Seen from the top view, the ditch 133b has a ring shape, is separated from the first region R1 by a non-zero distance, and surrounds the first region R1.

接著,請參照圖2D、圖3D與圖4D,繼續進行蝕刻製程,以移除溝渠133a與133b所裸露的導體層103,直到溝渠133a與133b延伸穿過導體層103。溝渠133a與133b的底部可以裸露出介電基底100。 Next, referring to FIG. 2D , FIG. 3D and FIG. 4D , the etching process is continued to remove the exposed conductor layer 103 of the trenches 133 a and 133 b until the trenches 133 a and 133 b extend through the conductor layer 103 . Bottoms of the trenches 133a and 133b may expose the dielectric substrate 100 .

之後,請參照圖2E、圖3E與圖4E,進行蝕刻製程,例如濕式蝕刻製程,將部分的多層中間層106移除。由於蝕刻製程所採用的蝕刻液(例如是熱磷酸)注入於溝渠133a與133b之中,再將所接觸的部分的多層中間層106移除。藉由時間模式的控制,可以將較靠近溝渠133a與133b的大部分的多層中間層106移除,以形成多個水平開口(未示出)。較遠離溝渠133a與133b的大部分的多層中間層106被留下來。 After that, referring to FIG. 2E , FIG. 3E and FIG. 4E , an etching process, such as a wet etching process, is performed to remove part of the multi-layer intermediate layer 106 . The etchant (such as hot phosphoric acid) used in the etching process is injected into the trenches 133a and 133b, and then the contacted part of the multi-layer intermediate layer 106 is removed. By time mode control, most of the multi-layer intermediate layer 106 closer to the trenches 133a and 133b can be removed to form a plurality of horizontal openings (not shown). Most of the multilayer intermediate layer 106 that is farther away from the trenches 133a and 133b is left.

請參照圖2E、圖3E與圖4E,在一些實施例中,在多個水平開口中形成閘極層138與電荷儲存結構的阻擋層(未示出),如圖1C所示的阻擋層36。在另一些實施例中,除了閘極層138之外還形成電荷儲存結構的穿隧層(未示出)、電荷儲存層(未示出)與阻擋層(未示出),如圖1D所示的穿隧層14、電荷儲存層12與阻擋層36。閘極層138的形成方法例如是先在溝渠133a與133b以及多個水平開口(未示出)中填入導體材料,之後,再進行回蝕刻製程,以移除溝渠133a與133b之中的導體材料。 Please refer to FIG. 2E, FIG. 3E and FIG. 4E. In some embodiments, the gate layer 138 and the barrier layer (not shown) of the charge storage structure are formed in a plurality of horizontal openings, such as the barrier layer 36 shown in FIG. 1C. . In other embodiments, in addition to the gate layer 138, a tunneling layer (not shown), a charge storage layer (not shown) and a blocking layer (not shown) of the charge storage structure are formed, as shown in FIG. 1D The tunneling layer 14, the charge storage layer 12 and the blocking layer 36 are shown. The forming method of the gate layer 138 is, for example, filling the trenches 133a and 133b and a plurality of horizontal openings (not shown) with conductive material first, and then performing an etch-back process to remove the conductors in the trenches 133a and 133b Material.

請參照圖3E與圖4E,未被移除的中間層106、多層閘極層138與多層絕緣層104形成堆疊結構SK2。請參照圖3E,在溝渠133a周圍的中間層106被取代為閘極層138。多層閘極層138 與多層絕緣層104形成閘極堆疊結構GSK。閘極層138與柱狀結構VC交錯之處均可形成一個記憶單元。因此,在閘極堆疊結構GSK中包括多個記憶單元。堆疊結構SK2與閘極堆疊結構GSK形成複合堆疊結構CSK。 Referring to FIG. 3E and FIG. 4E , the unremoved intermediate layer 106 , the multilayer gate layer 138 and the multilayer insulating layer 104 form a stack structure SK2 . Referring to FIG. 3E , the intermediate layer 106 around the trench 133 a is replaced by a gate layer 138 . multilayer gate layer 138 A gate stack structure GSK is formed with the multi-layer insulating layer 104 . Where the gate layer 138 intersects with the columnar structure VC can form a memory cell. Therefore, a plurality of memory cells are included in the gate stack structure GSK. The stack structure SK2 and the gate stack structure GSK form a composite stack structure CSK.

請參照圖4E,在溝渠133b周圍的中間層106被取代為閘極層138。遠離溝渠133b的多層中間層106被保留下來。在第二區R2中,多層閘極層138與多層絕緣層104彼此交替堆疊而形成堆疊結構SK2的第一部分P1。在第二區R2中,被保留下來的多層中間層106與多層絕緣層104彼此交替堆疊而形成堆疊結構SK2的第二部分P2。 Referring to FIG. 4E , the intermediate layer 106 around the trench 133 b is replaced by a gate layer 138 . The multi-layer intermediate layer 106 away from the trench 133b is preserved. In the second region R2, the multi-layer gate layers 138 and the multi-layer insulating layers 104 are alternately stacked to form the first part P1 of the stack structure SK2. In the second region R2, the remaining interlayer layers 106 and the insulating layers 104 are alternately stacked to form the second part P2 of the stack structure SK2.

參照圖2F、圖3F與圖4F,在溝渠133a與133b中形成分隔結構SLT與密封環DS的中間段DSM。閘極堆疊結構GSK被分隔結構SLT分割成多個區塊B1、B2。密封環DS的中間段DSM被堆疊結構SK2的第一部分P1環繞且接觸。 Referring to FIG. 2F , FIG. 3F and FIG. 4F , the separation structure SLT and the middle section DSM of the sealing ring DS are formed in the trenches 133 a and 133 b. The gate stack structure GSK is divided into a plurality of blocks B1, B2 by the separation structure SLT. The middle section DSM of the sealing ring DS is surrounded by and contacts the first part P1 of the stack structure SK2.

在一些實施例中,分隔結構SLT可以包括襯層142a與主體部144a。密封環DS的中間段DSM可以包括襯層142b與主體部144b。主體部144a與144b可以提供支撐性,避免分隔結構SLT彎曲。襯層142a與142b包括絕緣材料,例如氧化矽。主體部144a與144b包括導體材料,例如是多晶矽。分隔結構SLT與密封環DS的中間段DSM的形成方法包括在堆疊結構SK2上以及溝渠133a與133b中填入襯材料與主體材料,然後經由回蝕刻製程或是平坦化製程移除堆疊結構SK2上多餘的襯材料與主體材料。襯層 142a可以電性隔離閘極層138與主體部144a。襯層142b可以電性隔離閘極層138與主體部144b,並且可以阻隔水氣,降低主體部144b的應力。 In some embodiments, the separation structure SLT may include a liner 142a and a main body 144a. The middle section DSM of the sealing ring DS may include a liner 142b and a main body 144b. The main parts 144a and 144b can provide support and prevent the separation structure SLT from bending. The liners 142a and 142b include insulating materials such as silicon oxide. The main parts 144a and 144b include conductive material, such as polysilicon. The method for forming the separation structure SLT and the middle section DSM of the sealing ring DS includes filling the liner material and the body material on the stack structure SK2 and the trenches 133a and 133b, and then removing the stack structure SK2 through an etch-back process or a planarization process. Excess lining material and body material. lining 142a can electrically isolate the gate layer 138 from the main body portion 144a. The lining layer 142b can electrically isolate the gate layer 138 from the main body portion 144b, and can block moisture and reduce the stress of the main body portion 144b.

請參照圖2J、圖3J以及圖4J,在堆疊結構SK2上形成上內連線結構(或稱為第一內連線結構)130。上內連線結構130包括連接多個柱狀結構VC(例如圖1C或圖1D所示的多個第一導體柱32a與多個第二導體柱32b)的源極線與位元線以及連接密封環DS的中間段DSM的密封環DS的上段DSU。更具體地說,上內連線結構130包括介電層62與68、多個插塞64a、64b、第一導體層M1(包括多個導線66a、66b)、多個介層窗70a與70b以及第二導體層M2(包括多個導線72a、72b)。多個導線66a可做為源極線與位元線,經由插塞64a電性連接多個柱狀結構VC(例如圖1C或圖1D所示的多個第一導體柱32a與多個第二導體柱32b)。插塞64b、第一導體層M1的導線66b、介層窗70b以及第二導體層M2的導線72b可共同形成密封環DS的上段DSU,與下方的密封環DS的中間段DSM電性連接。上內連線結構130的各構件與形成方法詳細說明如下。 Referring to FIG. 2J , FIG. 3J and FIG. 4J , an upper interconnection structure (or called a first interconnection structure) 130 is formed on the stack structure SK2 . The upper interconnection structure 130 includes source lines and bit lines connecting a plurality of columnar structures VC (for example, a plurality of first conductor columns 32a and a plurality of second conductor columns 32b shown in FIG. 1C or FIG. 1D ) and connecting Middle section DSM of sealing ring DS Upper section DSU of sealing ring DS. More specifically, the upper interconnect structure 130 includes dielectric layers 62 and 68, a plurality of plugs 64a, 64b, a first conductor layer M1 (including a plurality of wires 66a, 66b), a plurality of vias 70a and 70b. And the second conductor layer M2 (including a plurality of wires 72a, 72b). A plurality of wires 66a can be used as source lines and bit lines, and are electrically connected to a plurality of columnar structures VC (for example, a plurality of first conductor columns 32a and a plurality of second conductor columns 32a shown in FIG. 1C or FIG. 1D ) via plugs 64a. conductor post 32b). The plug 64b, the wire 66b of the first conductor layer M1, the via 70b and the wire 72b of the second conductor layer M2 together form the upper section DSU of the sealing ring DS, which is electrically connected to the middle section DSM of the lower sealing ring DS. The components and forming methods of the upper interconnection structure 130 are described in detail as follows.

請參照圖2G、圖3G與圖4G,在第一區R1與第二區R2的堆疊結構SK2上形成介電層62a與插塞64a與64b堆疊結構52。插塞64a與64b埋在介電層62a中。插塞64a著陸在第一區R1的第一導體柱32a與第二導體柱32b上並與其電性連接。插塞64b著陸在第二區R2的密封環的中間段DSM上。從上視圖觀之,插塞64a具有島狀或點狀的輪廓,插塞64b具有環狀的輪廓如圖2G 所示。插塞64a的尺寸(徑長)可以小於或等於圖1C或圖1D所示的第一導體柱32a與第二導體柱32b的尺寸。插塞(或稱為第一插塞)64b的尺寸(線寬)可以大於、等於或小於密封環DS的中間段DSM的尺寸(線寬)。 Referring to FIG. 2G , FIG. 3G and FIG. 4G , a dielectric layer 62 a and a stacked structure 52 of plugs 64 a and 64 b are formed on the stacked structure SK2 of the first region R1 and the second region R2 . Plugs 64a and 64b are buried in dielectric layer 62a. The plug 64a lands on the first conductor post 32a and the second conductor post 32b in the first region R1 and is electrically connected thereto. The plug 64b lands on the middle section DSM of the sealing ring of the second region R2. Seen from the top view, the plug 64a has an island-like or dot-like outline, and the plug 64b has a ring-like outline as shown in FIG. 2G shown. The size (path length) of the plug 64a may be smaller than or equal to the size of the first conductor post 32a and the second conductor post 32b shown in FIG. 1C or FIG. 1D . The size (line width) of the plug (or called first plug) 64b may be greater than, equal to, or smaller than the size (line width) of the middle section DSM of the seal ring DS.

請參照圖2H、圖3H與圖4H,在介電層62a上形成介電層62b與第一導體層M1。第一導體層M1埋在介電層62b中。第一導體層M1是指在堆疊結構SK2上方的上內連線結構130的第一導體層。第一導體層M1包括多個導線66a與66b。導線66a與66b分別與插塞64a與64b電性連接。在一些實施例中,第二導體層M2的多個導線66a可以做為源極線與位元線。從上視圖觀之,導線66a具有直線或是折線(未示出)的形狀。導線(或稱為第一導線)66b具有環狀的輪廓。導線66a的尺寸(線寬)可以小於或等於下方的插塞64a的尺寸。導線66b的尺寸(線寬)可以大於、等於或小於下方的插塞64b的尺寸(線寬)。 Referring to FIG. 2H , FIG. 3H and FIG. 4H , a dielectric layer 62 b and a first conductive layer M1 are formed on the dielectric layer 62 a. The first conductor layer M1 is buried in the dielectric layer 62b. The first conductor layer M1 refers to the first conductor layer of the upper interconnect structure 130 above the stack structure SK2 . The first conductive layer M1 includes a plurality of wires 66a and 66b. The wires 66a and 66b are electrically connected to the plugs 64a and 64b respectively. In some embodiments, the plurality of wires 66 a of the second conductor layer M2 can serve as source lines and bit lines. Seen from above, the wire 66a has a shape of a straight line or a broken line (not shown). The wire (or referred to as the first wire) 66b has a circular outline. The size (line width) of the wire 66a may be smaller than or equal to the size of the underlying plug 64a. The size (line width) of the wire 66b may be greater than, equal to, or smaller than the size (line width) of the underlying plug 64b.

請參照圖3H與圖4H,插塞64a與64b以及多個導線66a與66b例如是金屬層,如鎢或銅。在一些實施例中,插塞64a與64b還包括阻障層,位於金屬層與介電層62a與62b之間。阻障層例如是鈦、氮化鈦、鉭、氮化鉭或其組合。插塞64a與64b以及多個導線66a與66b可以經由單鑲嵌或雙重金屬鑲嵌製程形成,但不限於此。以下以雙重金屬鑲嵌製程為來說明。 Referring to FIG. 3H and FIG. 4H, the plugs 64a and 64b and the plurality of wires 66a and 66b are, for example, metal layers such as tungsten or copper. In some embodiments, the plugs 64a and 64b further include a barrier layer between the metal layer and the dielectric layer 62a and 62b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. The plugs 64a and 64b and the plurality of wires 66a and 66b can be formed through a single damascene or dual damascene process, but is not limited thereto. The following uses the dual damascene process as an example.

參照圖3H與4H,在堆疊結構52堆疊結構SK2上形成介電層62。介電層62包括介電層62a與62b。介電層62a與62b之間可以具有分界面或無分界面。介電層62例如是氧化矽。經由微影與蝕刻製程在介電層62中形成多個溝渠(未示出)與多個插 塞孔(未示出),之後,再回填阻障層以及金屬填充層,然後再經由回蝕刻製程或是化學機械研磨製程移除介電層62上多餘的阻障層以及金屬填充層,以形成插塞64a與64b以及多個導線66a與66b。 Referring to FIGS. 3H and 4H , a dielectric layer 62 is formed on the stack structure 52 and the stack structure SK2 . The dielectric layer 62 includes dielectric layers 62a and 62b. There may be an interface or no interface between the dielectric layers 62a and 62b. The dielectric layer 62 is, for example, silicon oxide. A plurality of trenches (not shown) and a plurality of insertions are formed in the dielectric layer 62 through lithography and etching processes. Plug holes (not shown), and then backfill the barrier layer and the metal filling layer, and then remove the excess barrier layer and metal filling layer on the dielectric layer 62 through an etch-back process or a chemical mechanical polishing process, so as to Plugs 64a and 64b and a plurality of wires 66a and 66b are formed.

請參照圖2I、圖3I與圖3I,在介電層62以及多個導線66a與66b上形成介電層68a以及介層窗70a與70b。介層窗70a與70b埋在介電層68a中。介層窗70a著陸在導線66a上並與其電性連接;介層窗70b著陸在導線66b上並與其電性連接。從上視圖觀之,介層窗70a具有島狀或點狀的輪廓,如圖2I所示。介層窗70b具有環狀的輪廓。介層窗70a的尺寸(徑長)可以小於或等於下方的導線66a的尺寸。介層窗70b的尺寸(線寬)可以大於、等於或小於下方的導線66b的尺寸(線寬)。 Referring to FIG. 2I, FIG. 3I and FIG. 3I, a dielectric layer 68a and vias 70a and 70b are formed on the dielectric layer 62 and a plurality of wires 66a and 66b. Vias 70a and 70b are buried in dielectric layer 68a. Via 70a lands on and is electrically connected to wire 66a; via 70b lands on and is electrically connected to wire 66b. From the top view, the via 70a has an island-like or dot-like outline, as shown in FIG. 2I . The via 70b has a circular profile. The size (path length) of the via 70a may be smaller than or equal to the size of the underlying wire 66a. The size (line width) of via 70b may be greater than, equal to, or smaller than the size (line width) of underlying wire 66b.

請參照圖2J、圖3J與圖4J,在介電層68a上形成介電層68b與第二導體層M2。第二導體層M2埋在介電層68b中。第二導體層M2是指在堆疊結構SK2上方的上內連線結構130的第二導體層。第二導體層M2包括多個導線72a與72b。導線72a與72b各自分別沿著方向Y延伸,且沿著方向X排列。導線72a與72b分別與介層窗70a與70b電性連接。在Z方向上,導線72a與72b分別與導線66a與66b重疊。導線72b又可稱為第二導線。 Referring to FIG. 2J , FIG. 3J and FIG. 4J , a dielectric layer 68 b and a second conductor layer M2 are formed on the dielectric layer 68 a. The second conductor layer M2 is buried in the dielectric layer 68b. The second conductor layer M2 refers to the second conductor layer of the upper interconnect structure 130 above the stack structure SK2. The second conductor layer M2 includes a plurality of wires 72a and 72b. The wires 72 a and 72 b extend along the direction Y and are arranged along the direction X respectively. Wires 72a and 72b are electrically connected to vias 70a and 70b, respectively. In the Z direction, conductors 72a and 72b overlap conductors 66a and 66b, respectively. The wire 72b can also be called a second wire.

請參照圖3J與圖4J,介層窗70a與70b以及多個導線72a與72b例如是金屬填充層,如鎢或銅。在一些實施例中,介層窗70a與70b還包括阻障層,位於金屬填充層與介電層68a與68b之間。阻障層例如是鈦、氮化鈦、鉭、氮化鉭或其組合。介層窗70a與70b 以及多個導線72a與72b可以經由單鑲嵌或雙重金屬鑲嵌製程形成,但不限於此。以下以雙重金屬鑲嵌製程為來說明。 Referring to FIG. 3J and FIG. 4J, the vias 70a and 70b and the plurality of wires 72a and 72b are, for example, metal filling layers such as tungsten or copper. In some embodiments, vias 70a and 70b further include a barrier layer between the metal fill layer and dielectric layers 68a and 68b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. Vias 70a and 70b And the plurality of wires 72a and 72b can be formed through a single damascene or dual damascene process, but is not limited thereto. The following uses the dual damascene process as an example.

請參照圖3J,首先,在介電層62以及第一導體層M1上形成介電層68。介電層68包括介電層68a與68b。介電層68a與68b之間可以具有分界面或無分界面。介電層68例如是氧化矽。在一些實施例中,經由圖案化製程,例如是微影與蝕刻製程,在介電層68中形成多個溝渠與多個插塞孔。在另一些實施例中,可以經由自行對準雙重圖案化(Self-aligned double patterning,SADP)製程來形成多個溝渠(未示出)與多個插塞孔(未示出)。之後,再回填阻障層以及金屬填充層。然後再經由回蝕刻製程或是化學機械研磨製程移除介電層68上多餘的阻障層以及金屬填充層,以形成介層窗70a與70b以及多個導線72a與72b。 Referring to FIG. 3J , firstly, a dielectric layer 68 is formed on the dielectric layer 62 and the first conductive layer M1 . The dielectric layer 68 includes dielectric layers 68a and 68b. Dielectric layers 68a and 68b may have an interface or no interface. The dielectric layer 68 is, for example, silicon oxide. In some embodiments, a plurality of trenches and a plurality of plug holes are formed in the dielectric layer 68 through patterning processes, such as lithography and etching processes. In other embodiments, a plurality of trenches (not shown) and a plurality of plug holes (not shown) may be formed through a self-aligned double patterning (SADP) process. After that, the barrier layer and the metal fill layer are backfilled. Then, the excess barrier layer and the metal filling layer on the dielectric layer 68 are removed through an etch-back process or a chemical mechanical polishing process to form vias 70a and 70b and a plurality of wires 72a and 72b.

圖5示出根據另一些實施例的3D AND快閃記憶體的上視圖。圖6示出為圖5的線V-V’的剖面圖。圖7示出為圖5的線VI-VI’的剖面圖。 FIG. 5 shows a top view of a 3D AND flash memory according to other embodiments. Fig. 6 is a cross-sectional view taken along line V-V' of Fig. 5 . Fig. 7 is a cross-sectional view taken along line VI-VI' of Fig. 5 .

請參照圖5、圖6與圖7,在其他實施例中,在基底99與堆疊結構SK2之間還形成電路結構220以及下內連線結構(或稱為第二內連線結構)230。介電基底100位於導體層103與基底99之間。基底99例如是包括半導體。電路結構220可以包括主動元件或是被動元件。主動元件例如是電晶體、二極體等。被動元件例如是電容器、電感等。電晶體可以是N型金氧半(NMOS)電晶體、P型金氧半(PMOS)電晶體或是互補式金氧半元件(CMOS)。在一些實施例中,電路結構220可以包括平面緩衝器(Plane-Buffer)。 Referring to FIG. 5 , FIG. 6 and FIG. 7 , in other embodiments, a circuit structure 220 and a lower interconnection structure (or called a second interconnection structure) 230 are further formed between the substrate 99 and the stack structure SK2 . The dielectric substrate 100 is located between the conductive layer 103 and the substrate 99 . The substrate 99 includes, for example, a semiconductor. The circuit structure 220 may include active components or passive components. Active elements are, for example, transistors, diodes, and the like. Passive components are, for example, capacitors, inductors, and the like. The transistor can be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor or a complementary metal oxide semiconductor device (CMOS). In some embodiments, the circuit structure 220 may include a plane buffer (Plane-Buffer).

請參照圖5、圖6與圖7,下內連線結構230可以包括多層介電層230以及形成在多層介電層230中的導體內連線233。導體內連線233包括多個插塞234a、234b與多個導線236a與236b等。導線236a可藉由插塞234a連接到電路結構220。導線(或稱為第三導線)236b與插塞(或稱為第二插塞)234b可以共同形成密封環DS的下段DSL,以電性連接下方的密封環DS的中間段DSM。從上視圖觀之,導線236b與插塞234b具有環狀的輪廓。導線236b與插塞234b的尺寸(徑長)可以大於、等於或小於密封環DS的中間段DSM的尺寸(線寬)。 Referring to FIG. 5 , FIG. 6 and FIG. 7 , the lower interconnection structure 230 may include a multilayer dielectric layer 230 and a conductor interconnection 233 formed in the multilayer dielectric layer 230 . The conductor interconnection 233 includes a plurality of plugs 234a, 234b, a plurality of wires 236a, 236b, and the like. The wire 236a can be connected to the circuit structure 220 through the plug 234a. The wire (or called as the third wire) 236b and the plug (or called as the second plug) 234b can jointly form the lower section DSL of the sealing ring DS to electrically connect the middle section DSM of the lower sealing ring DS. Viewed from the top view, the wire 236b and the plug 234b have a circular outline. The size (diameter length) of the wire 236b and the plug 234b may be greater than, equal to or smaller than the size (line width) of the middle section DSM of the sealing ring DS.

基於上述,本發明實施例之三維快閃記憶體的密封環可以從基底的表面向上穿過接地導體層,而連續延伸至上內連線結構的頂面。因此,本發明實施例之三維快閃記憶體可以將相鄰的兩塊元區的堆疊結構有效隔絕,減少或避免基底和接地導體層之間的漏電路徑而增加關閉電流Ioff,降低對於記憶單元操作的影響。 Based on the above, the sealing ring of the 3D flash memory according to the embodiment of the present invention can extend upwards from the surface of the substrate through the ground conductor layer, and continuously extend to the top surface of the upper interconnection structure. Therefore, the three-dimensional flash memory of the embodiment of the present invention can effectively isolate the stack structure of two adjacent cell areas, reduce or avoid the leakage path between the substrate and the ground conductor layer to increase the off-current I off , and reduce the impact on the memory. Effects of unit operations.

本發明實施例之三維快閃記憶體的製造方法可以在形成記憶體元件的同時在塊元區的外圍形成密封環,因此,可以與現有的製程整合,而不會增加製程的步驟。 The manufacturing method of the three-dimensional flash memory of the embodiment of the present invention can form a sealing ring on the periphery of the block region while forming the memory element, so it can be integrated with the existing manufacturing process without increasing the steps of the manufacturing process.

100:介電基底 100: Dielectric substrate

103:導體層 103: conductor layer

104:絕緣層 104: insulation layer

R2:第二區 R2: second area

SK2:堆疊結構 SK2: stacked structure

106:中間層 106: middle layer

138:閘極層 138:Gate layer

P1:第一部分 P1: part one

P2:第二部分 P2: Part Two

142b:襯層 142b: lining

144b:主體部 144b: Main body

DS:密封環 DS: sealing ring

DSM:中間段 DSM: middle section

Claims (17)

一種記憶體元件,包括:介電基底,包括第一區與環繞在所述第一區周圍的第二區;複合堆疊結構,在所述第一區與所述第二區中的所述介電基底上方;多個記憶單元,位於所述複合堆疊結構中;分隔結構,延伸穿過位於所述第一區的所述複合堆疊結構,將所述複合堆疊結構分隔為多個區塊;以及密封環的中間段,延伸穿過位於所述第二區的所述複合堆疊結構,其中所述密封環的所述中間段包括:主體部,延伸穿過位於所述第二區的所述複合堆疊結構;以及襯層,位於所述主體部與所述複合堆疊結構之間,其中所述密封環的所述中間段密閉環繞在所述第一區周圍。 A memory element, comprising: a dielectric substrate including a first area and a second area surrounding the first area; a composite stack structure, the dielectric in the first area and the second area above the electrical substrate; a plurality of memory cells located in the composite stack structure; a separation structure extending through the composite stack structure located in the first region to separate the composite stack structure into a plurality of blocks; and an intermediate section of a seal ring extending through the composite stack in the second region, wherein the intermediate section of the seal ring includes a main body extending through the composite stack in the second region a stack structure; and a liner between the body portion and the composite stack structure, wherein the intermediate section of the seal ring hermetically surrounds the first region. 如請求項1所述的記憶體元件,其中所述密封環的所述主體部與所述複合堆疊結構由所述密封環的所述襯層電性絕緣。 The memory device according to claim 1, wherein the main body portion of the sealing ring and the composite stack structure are electrically insulated by the liner of the sealing ring. 如請求項1所述的記憶體元件,其中所述密封環的所述襯層包括絕緣材料,所述主體部包括導體材料。 The memory device according to claim 1, wherein the lining layer of the sealing ring includes an insulating material, and the main body portion includes a conductive material. 如請求項1所述的記憶體元件,更包括:導體層,位於所述複合堆疊結構與所述介電基底之間,其中所述密封環的所述中間段延伸穿過所述導體層。 The memory device according to claim 1, further comprising: a conductor layer located between the composite stack structure and the dielectric substrate, wherein the middle section of the sealing ring extends through the conductor layer. 如請求項4所述的記憶體元件,其中所述密封環更包括:下段,位於所述中間段下方且與所述中間段連接,其中所述下段為部分的第一內連線,所述第一內連線位於所述介電基底與基底之間;以及上段,位於所述中間段上方且與所述中間段連接,其中所述上段為部分的第二內連線,所述第二內連線位於所述複合堆疊結構上方。 The memory device according to claim 4, wherein the sealing ring further includes: a lower section, located below the middle section and connected to the middle section, wherein the lower section is a part of the first inner line, the The first interconnection line is located between the dielectric base and the base; and the upper section is located above the middle section and connected to the middle section, wherein the upper section is a part of the second interconnection line, and the second Interconnects are located above the composite stack structure. 一種記憶體元件的製造方法,包括:提供介電基底,包括第一區與環繞在所述第一區周圍的第二區;形成堆疊結構,於所述第一區與所述第二區中的所述介電基底上方,其中所述堆疊結構包括交替堆疊的多個絕緣層與多個中間層;以及形成分隔結構與密封環的中間段,其中所述分隔結構位於所述第一區中的所述堆疊結構中,所述密封環的所述中間段位於所述第二區中的所述堆疊結構中,其中所述密封環的所述中間段密閉環繞在所述第一區周圍。 A method of manufacturing a memory element, comprising: providing a dielectric substrate including a first region and a second region surrounding the first region; forming a stack structure in the first region and the second region above the dielectric substrate, wherein the stack structure includes a plurality of insulating layers and a plurality of intermediate layers stacked alternately; and an intermediate segment forming a separation structure and a seal ring, wherein the separation structure is located in the first region In the stacked structure, the middle section of the sealing ring is located in the stacked structure in the second zone, wherein the middle section of the sealing ring is hermetically wrapped around the first zone. 如請求項6所述的記憶體元件的製造方法,其中所述密封環更包括:其中形成所述分隔結構與所述密封環的所述中間段包括: 形成第一溝渠與第二溝渠,其中所述第一溝渠位於所述第一區的所述堆疊結構中,所述第二溝渠位於所述第二區的所述堆疊結構中;形成第一襯層與第二襯層,其中所述第一襯層位於所述第一溝渠的側壁,並所述第二襯層位於所述第二溝渠的側壁;以及形成第一主體部與第二主體部,其中所述第一主體部位於所述第一溝渠的剩餘空間中,所述第二主體部位於所述第二溝渠的剩餘空間中。 The manufacturing method of the memory device according to claim 6, wherein the sealing ring further comprises: wherein the intermediate section forming the separation structure and the sealing ring comprises: forming a first ditch and a second ditch, wherein the first ditch is located in the stacked structure in the first region, and the second ditch is located in the stacked structure in the second region; forming a first liner a layer and a second liner, wherein the first liner is located on a sidewall of the first trench, and the second liner is located on a sidewall of the second trench; and forming a first body portion and a second body portion , wherein the first main body part is located in the remaining space of the first ditch, and the second main body part is located in the remaining space of the second ditch. 如請求項7所述的記憶體元件的製造方法,更包括:在形成所述第一襯層與所述第二襯層前,將所述第一溝渠與所述第二溝渠周圍的所述多個中間層取代為多個閘極導體層。 The manufacturing method of the memory device according to claim 7, further comprising: before forming the first liner and the second liner, forming the first trench and the surrounding area of the second trench The intermediate layers are replaced by gate conductor layers. 如請求項8所述的記憶體元件的製造方法,更包括:形成導體層,位於所述堆疊結構與所述介電基底之間,其中所述第一溝渠與所述第二溝渠還延伸穿過所述導體層。 The method for manufacturing a memory device according to claim 8, further comprising: forming a conductor layer between the stacked structure and the dielectric substrate, wherein the first trench and the second trench also extend through through the conductor layer. 如請求項6所述的記憶體元件的製造方法,更包括:形成第一內連線,於所述所述介電基底與基底之間,其中部分的所述第一內連線形成所述密封環的下段;以及形成第二內連線,於所述堆疊結構上方,其中部分的所述第二內連線形成所述密封環的上段。 The manufacturing method of the memory device according to claim 6, further comprising: forming a first interconnection between the dielectric substrate and the substrate, wherein part of the first interconnection forms the a lower section of the sealing ring; and forming a second interconnection above the stack structure, wherein part of the second interconnection forms an upper section of the sealing ring. 一種半導體元件,包括: 複合堆疊結構,在介電基底上方,其中所述複合堆疊結構包括多個導體層與多個絕緣層交替堆疊而成,其中所述介電基底包括第一區與環繞在所述第一區周圍的第二區,其中所述複合堆疊結構,在所述第一區與所述第二區中的所述介電基底上方;密封環,包括:中間段,延伸穿過所述複合堆疊結構,且與所述多個導體層電性絕緣;上段,位於所述中間段上方且與所述中間段連接;以及下段,位於所述中間段下方且與所述中間段連接,其中所述密封環的所述中間段密閉環繞在所述第一區周圍。 A semiconductor element comprising: A composite stacked structure above a dielectric substrate, wherein the composite stacked structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately, wherein the dielectric substrate includes a first region and a surrounding area around the first region a second region of the composite stack structure, wherein the composite stack structure is over the dielectric substrate in the first region and the second region; a seal ring comprising: a middle section extending through the composite stack structure, and electrically insulated from the plurality of conductor layers; an upper section, located above and connected to the middle section; and a lower section, located below the middle section and connected to the middle section, wherein the sealing ring Said intermediate section of said first region is hermetically wrapped around said first zone. 如請求項11所述的半導體元件,其中所述密封環的所述中間段包括:主體部,延伸穿過位於所述複合堆疊結構;以及襯層,位於所述主體部與所述複合堆疊結構之間。 The semiconductor element as claimed in claim 11, wherein said intermediate section of said seal ring comprises: a main body extending through said composite stack structure; and a liner between said main body and said composite stack structure between. 如請求項12所述的半導體元件,其中所述主體部以及所述襯層具有環狀輪廓。 The semiconductor element according to claim 12, wherein the main body portion and the liner have a ring-shaped profile. 如請求項11所述的半導體元件,其中所述上段包括:第一插塞,位於所述主體部上且與所述主體部電性連接;第一導線,位於所述第一插塞上且與所述第一插塞電性連接;介層窗,位於所述第一導線上且與所述第一導線電性連接;以及第二導線,位於所述介層窗上且與所述介層窗電性連接。 The semiconductor element according to claim 11, wherein the upper section includes: a first plug located on the main body part and electrically connected to the main body part; a first wire located on the first plug and electrically connected to the first plug; a via located on the first wire and electrically connected to the first wire; and a second wire located on the via and connected to the via The layer windows are electrically connected. 如請求項14所述的半導體元件,其中所述第一插塞、所述第一導線、所述介層窗以及所述第二導線具有環狀輪廓。 The semiconductor device of claim 14, wherein the first plug, the first wire, the via, and the second wire have a ring-shaped profile. 如請求項11所述的半導體元件,其中所述下段包括:第三導線,位於所述主體部下且與所述主體部電性連接;以及第二插塞,位於所述第三導線下且與所述第三導線電性連接。 The semiconductor element according to claim 11, wherein the lower section includes: a third wire located under the main body part and electrically connected to the main body part; and a second plug located under the third wire and connected to the main body part The third wire is electrically connected. 如請求項16所述的半導體元件,其中所述第三導線與所述第二插塞具有環狀輪廓。 The semiconductor device as claimed in claim 16, wherein the third lead and the second plug have ring-shaped contours.
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