TWI830112B - 3d and flash memory device - Google Patents

Abstract

A three-dimensional AND flash memory device includes a gate stack structure and a silt. The silt extends along the first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of rows, and each row includes a plurality of channel pillars, a plurality of charge storage structures, and a plurality of pairs of conductive pillars. The plurality of pairs of conductive pillars are arranged in the plurality of channel pillars and penetrate the gate stack structure, and are respectively connected to the plurality of channel pillars. Each pair of conductive pillars includes a first conductive pillar and a second conductive pillar separated from each other along a second direction. There is an acute angle between the second direction and the first direction.

Description

Three-dimensional AND flash memory device

The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a three-dimensional AND flash memory element and a manufacturing method thereof.

Non-volatile memory has the advantage that stored data will not disappear even after a power outage, so it is widely used in personal computers and other electronic devices. Currently, three-dimensional memories commonly used in the industry include NOR (NOR) memory and NAND (NAND) memory. In addition, another type of three-dimensional memory is the AND memory, which can be applied in multi-dimensional memory arrays and has high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become a current trend.

The present invention proposes a three-dimensional AND flash memory element and a manufacturing method thereof that can reduce the chip area or simplify the wiring complexity.

An embodiment of the present invention provides a three-dimensional AND flash memory device, including a gate stack structure disposed on a dielectric substrate and including multiple gate layers and multiple insulating layers stacked alternately with each other. The dividing wall extends along the first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of columns, and each column includes a plurality of channel pillars, a plurality of charge storage structures and a plurality of pairs of conductor pillars. The plurality of channel pillars are disposed on the dielectric substrate and pass through the gate stack structure. The plurality of charge storage structures are disposed between the plurality of gate layers and sidewalls of the plurality of channel pillars. The plurality of pairs of conductor posts are disposed within the plurality of channel posts and pass through the gate stack structure, and are each connected to the plurality of channel posts. Each pair of conductor posts includes a first conductor post and a second conductor post, the first conductor post and the second conductor post being spaced apart from each other along a second direction, wherein the second direction is separated from the first conductor post. The direction is at an acute angle.

An embodiment of the present invention provides a three-dimensional AND flash memory device, including a gate stack structure disposed on a dielectric substrate and including multiple gate layers and multiple insulating layers stacked alternately with each other. The dividing wall extends along the first direction and divides the gate stack structure into a plurality of sub-blocks. Each subblock includes multiple columns. Each column includes: multiple channel pillars, multiple charge storage structures and multiple conductor pillars. A plurality of channel pillars are disposed on the dielectric substrate and pass through the gate stack structure. A plurality of charge storage structures are disposed between the plurality of gate layers and the sidewalls of the plurality of channel pillars. A plurality of conductor pillars are arranged in pairs in each channel pillar and pass through the gate stack structure, and are each connected to the plurality of channel pillars. Each pair of conductor posts is arranged and spaced apart from each other in a second direction, wherein the second direction is at right angles to the first direction. The three-dimensional AND flash memory device also includes a plurality of plugs, a plurality of first conductive lines, a plurality of via windows and a plurality of second conductive lines. A plurality of plugs are located on the plurality of conductor posts, wherein each plug lands and connects to a corresponding conductor post. A plurality of first conductors are located on the plurality of plugs, wherein each of the first conductors includes a first part and a second part. The first part extends along the first direction and is connected to the corresponding plug. A second portion extends along the second direction and connects the first portion. A plurality of vias are located on the plurality of first conductors, wherein each via lands on the second portion. A plurality of second conductive lines connect the plurality of via windows, extend along the second direction, and are arranged along the first direction.

Based on the above, embodiments of the present invention can form source lines and bit lines through multi-layer conductor interconnections, or through source and drain pillars that form an acute angle with the partition wall. Therefore, the occupied chip area can be reduced. Or reduce the complexity of winding.

Figure 1A shows a circuit diagram of a 3D AND flash memory array in accordance with some embodiments. Figure IB shows a top view of a 3D AND flash memory array in accordance with some embodiments. Figure 1C shows a partial three-dimensional view of the memory array of a simplified portion of Figure IB. 1D and 1E show cross-sectional views along line I-I' of FIG. 1C. Figure 1F shows a top view of line II-II' of Figures 1C, 1D and 1E.

FIG. 1A is a schematic diagram of two blocks BLOCK ⁽ⁱ⁾ and BLOCK ⁽ⁱ⁺¹⁾ of the vertical AND memory array 10 configured in columns and rows. Block BLOCK ⁽ⁱ⁾ includes memory array A ⁽ⁱ⁾ . One column (for example, the m+1th column) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common word line (for example, WL ⁽ⁱ⁾ _m+1 ). The AND memory cells 20 in each column (for example, the m+1th column) of the memory array A ⁽ⁱ⁾ correspond to a common word line (for example, WL ⁽ⁱ⁾ _m+1 ) and are coupled to different source columns ( For example, SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain posts (for example, DP ⁽ⁱ⁾ _n and DP ⁽ⁱ⁾ _n+1 ), so that the AND memory cells 20 move along a common word line (such as WL ⁽ⁱ⁾ _m+1 ) are logically arranged into a column.

One row (for example, the n-th row) of the memory array A ^{( i )} is a set of AND memory cells 20 having a common source column (for example, SP ^{( i )} _n ) and a common drain column (for example, DP ^{( i )} _n ). The AND memory cells 20 of each row (for example, the nth row) of the memory array A ⁽ⁱ⁾ correspond to different word lines (for example, WL ^{( i )} _m+1 and WL ^{( i )} _m ), and are coupled to a common Source post (e.g. SP ^{( i )} _n ) and a common drain post (e.g. DP ^{( i )} _n ). Therefore, the AND memory cells 20 of memory array A ⁽ⁱ⁾ are logically arranged in a row along a common source column (eg, SP ^{( i )} _n ) and a common drain column (eg, DP ^{( i )} _n ). In a physical layout, depending on the manufacturing method applied, rows or columns may be twisted, configured in a honeycomb pattern or otherwise for high density or other reasons.

In FIG. 1A , in block BLOCK ⁽ⁱ⁾ , the AND memory cells 20 in the nth row of memory array A ⁽ⁱ⁾ share a common source column (for example, SP ^{( i )} _n ) and a common drain column ( For example DP ^{( i )} _n ). The AND memory cells 20 in the n+1th row share a common source column (for example, SP ⁽ⁱ⁾ _n+1 ) and a common drain column (for example, DP ^{( i )} _n+1 ).

A common source post (for example, SP ^{( i )} _n ) is coupled to a common source line (for example, SL _n ); a common drain post (for example, DP ^{( i )} _n ) is coupled to a common bit line (for example, DP ( i ) n ). BL _n ). A common source column (such as SP ^{( i )} _n+1 ) is coupled to a common source line (such as SL _n+1 ); a common drain column (such as DP ^{( i )} _n+1 ) is coupled to a common bit line (e.g. BL _n+1 ).

Similarly, block BLOCK ⁽ⁱ⁺¹⁾ includes memory array A ⁽ⁱ⁺¹⁾ , which is similar to memory array A ^{( i) in block BLOCK(i)} . One column (for example, the m+1th column ^{) of the memory array A (i} +1) is a set of AND memory cells 20 with a common word line (for example, WL ⁽ⁱ⁺¹⁾ _m+1 ). The AND memory cells 20 of each column (for example, the m+1th column) of the memory array A ⁽ⁱ +1) correspond to a common word line (for example, WL ⁽ⁱ⁺¹⁾ _m+1 ) and are coupled to different Source posts (such as SP ⁽ⁱ⁺¹⁾ _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and drain posts (such as DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (for example, the nth row) of the memory array A ^{( i+1 )} is the AND of a common source column (for example, SP ^{( i+1 )} _n ) and a common drain column ( for example, DP ^{( i+1 )} _n ). Memory units 20 are assembled. The AND memory cells 20 of each row (for example, the n-th row) of the memory array A ⁽ⁱ⁺¹ ) correspond to different word lines (for example, WL ^{( i+1 )} _m+1 and WL ^{( i+1 )} _m ), and coupled to a common source post (eg SP ^{( i+1 )} _n ) and a common drain post (eg DP ^{( i+1 )} _n ). Therefore, the AND memory cells 20 of memory array A ⁽ⁱ⁺¹⁾ are logically arranged in a row along a common source column (for example, SP ^{( i+1 )} _n ) and a common drain column (for example, DP ^{( i+1 )} _n ). .

Block BLOCK ⁽ⁱ⁺¹⁾ and block BLOCK ⁽ⁱ⁾ share source lines (for example, SL _n and SL _n+1 ) and bit lines (for example, BL _n and BL _n+1 ). Therefore, the source line SL _n and the bit line BL _n are coupled to the n-th row AND memory cell 20 in the AND memory array A ^{(i) of} the block BLOCK (i), and are coupled to the block BLOCK ⁽ⁱ⁺ The n-th row AND memory unit 20 in the AND memory array A ⁽ⁱ⁺¹⁾ in ¹⁾ . Similarly, the source line SL _n+1 and the bit line BL _n+1 are coupled to the n+1th row AND memory cell 20 in the AND memory array A ⁽ⁱ⁾ of the block BLOCK ⁽ⁱ ), and are coupled to The n+1th row AND memory unit 20 in the AND memory array A ⁽ⁱ⁺¹⁾ in block BLOCK ⁽ i+1).

Referring to FIGS. 1B to 1D , the memory array 10 may include multiple sub-blocks, such as sub-block B1 and sub-block B2. The partition wall SLT extends along the direction X to separate the gate stack structures 52 of the two adjacent sub-blocks B1 and B2. The dividing wall SLT is an insulating material. Insulating materials may include organic insulating materials, inorganic insulating materials, or combinations thereof. Each of the sub-blocks B1 and B2 may include a gate stack structure 52 disposed on the dielectric substrate 50, a plurality of channel pillars 16, a plurality of first conductor pillars (also called source pillars) 32a and a plurality of second conductor pillars. A conductor pillar (also called a drain pillar) 32b and a plurality of charge storage structures 40.

Referring to FIG. 1D , the memory array 10 may be disposed on an interconnect structure of a semiconductor die, such as one or more active devices (eg, transistors) formed on a semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed over the conductor interconnect structure on the silicon substrate. The dielectric substrate 50 may include an array region AR and a step region SR (as shown in FIG. 1B ).

Referring to FIGS. 1B and 1C , the gate stack structure 52 is formed on the dielectric substrate 50 in the array region AR and the step region SR. The gate stack structure 52 includes a plurality of gate layers (also called word lines) 38 and a multi-layer insulating layer 54 vertically stacked on the surface of the dielectric substrate 50 (as shown in FIGS. 1C to 1E ). In the Z direction, the gate layers 38 are electrically isolated by the insulating layer 54 disposed between them. Gate layer 38 extends in a direction parallel to the surface of dielectric substrate 50 (shown in FIGS. 1C-1E). As shown in FIG. 1B , the gate layer 38 in the step region SR may have a step structure SC. Therefore, the lower gate layer 38 is longer than the upper gate layer 38 , and the end of the lower gate layer 38 laterally extends beyond the end of the upper gate layer 38 . As shown in FIG. 1B , the contact window C1 for connecting the gate layer 38 can land on the end of the gate layer 38 to connect each gate layer 38 to each wire.

Referring to FIGS. 1B to 1E , the memory array 10 further includes a plurality of channel columns 16 . The channel pillar 16 extends continuously through the gate stack structure 52 of the array area AR. In some embodiments, the channel column 16 may have an annular shape when viewed from above (as shown in FIG. 1B ). The material of the channel pillar 16 may be a semiconductor, such as undoped polycrystalline silicon. The channel column 16 may also be called a vertical channel (VC).

Referring to FIGS. 1C to 1E , the memory array 10 further includes an insulating filling layer 24 , an insulating pillar 28 , a plurality of first conductive pillars 32 a and a plurality of second conductive pillars 32 b. In this example, the first conductor post 32a serves as the source post; the second conductor post 32b serves as the drain post. The pair of first conductor pillars 32 a and second conductor pillars 32 b are disposed in the channel pillar 16 , and each extends in a direction perpendicular to the gate layer 38 (ie, the Z direction). The first conductive pillar 32a and the second conductive pillar 32b are separated by the insulating filling layer 24 and the insulating pillar 28. The first conductor post 32a and the second conductor post 32b are electrically connected to the channel post 16. The first conductive pillar 32a and the second conductive pillar 32b include doped polycrystalline silicon or metal material. The insulating pillar 28 is made of silicon nitride, for example. The insulating filling layer 24 is, for example, silicon oxide.

Referring to FIGS. 1D and 1E , at least a portion of the charge storage structure 40 is disposed between the channel pillar 16 and the multi-layer gate layer 38 . The charge storage structure 40 may include a tunneling layer (also known as a bandgap engineered tunneling oxide layer) 14 , a charge storage layer 12 and a blocking layer 36 . The charge storage layer 12 is located between the tunneling layer 14 and the barrier layer 36 . In some embodiments, tunneling layer 14 and barrier layer 36 include silicon oxide. The charge storage layer 12 includes silicon nitride, or other materials that can capture charges. In some embodiments, as shown in FIG. 1D , a portion of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12 ) continuously extends in a direction perpendicular to the gate layer 38 (ie, the Z direction), and the charge storage Another portion of structure 40 (barrier layer 36 ) surrounds gate layer 38 . In other embodiments, as shown in FIG. 1E , the charge storage structure 40 (tunnel layer 14 , charge storage layer 12 and barrier layer 36 ) surrounds the gate layer 38 .

Referring to FIG. 1F , the charge storage structure 40 , the channel pillar 16 , the source pillar 32 a and the drain pillar 32 b are surrounded by the gate layer 38 and define the memory cell 20 . The memory unit 20 can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column 32a and the drain column 32b, since the source column 32a and the drain column 32b are connected to the channel column 16, electrons can be transported along the channel column 16 and stored in the entire charge storage. In the structure 40, in this way, a 1-bit operation can be performed on the memory unit 20. In addition, for operations utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and the drain post 32b . For source side injection, channel-hot-electron injection or band-to-band tunneling hot carrier injection operations, the electrons can be Or the holes are locally trapped in the charge storage structure 40 adjacent to one of the two source pillars 32a and drain pillars 32b, so that the memory cell 20 can be processed into unit cell (SLC, 1 bit) or multiple Bit cell (MLC, greater than or equal to 2 bits) operations.

During operation, a voltage is applied to the selected word line (gate layer) 38 , for example, when a voltage higher than the corresponding starting voltage (V _th ) of the corresponding memory cell 20 is applied, intersecting the selected word line 38 The channel region of the channel column 16 is turned on, allowing current to enter the drain column 32b from the bit line BL _n or BL _n+1 (shown in FIG. 1C ), and flow to the source column 32 a (for example, through the conductive channel region). , in the direction indicated by arrow 60), and finally flows to the source line _SLn or SLn ₊₁ (shown in Figure 1C).

Referring to FIG. 1C , the bit lines BL _n BL _n+1 and the source lines SL _n , SL _n+1 can be formed through conductor interconnects located above the memory cell array. The formation method of the bit lines BL _n , BL _n+1 and the source lines SL _n , SL _n+1 can be as shown in FIGS. 2A to 2E and 3A to 3E , or as shown in FIGS. 4A to 4C and 5A As shown in Figure 5C.

2A-2E illustrate a top view of a manufacturing process of a 3D AND flash memory according to some embodiments. 3A to 3E are cross-sectional views along line III-III' of FIGS. 2A to 2E. Figure 3F shows a partial perspective view of Figure 3E. The cross-sectional views of the memory array 10 in FIGS. 3A to 3E are similar to those in FIG. 1E , but they may also be as shown in FIG. 1D . Additionally, for clarity, dielectric layers 62 and 68 are not shown in FIGS. 2A-2E and 3F.

Referring to FIG. 2A , FIG. 3A and FIG. 3F , the gate stack structure 52 is divided into a plurality of sub-blocks B by the partition wall SLT. For simplicity, only a single sub-block B is shown in the figure. There are multiple columns R in sub-block B, such as R1, R2, R3 and R4. Only 4 columns are shown in the sub-block B in FIGS. 2A to 2E . However, the embodiment of the present invention is not limited thereto, and each sub-block B may include more columns.

The channel columns 16 of each row R are arranged along the direction X. The channel columns 16 of two adjacent columns, such as columns R1 and R2, are staggered to each other. Channel columns 16 in odd-numbered columns, such as columns R1 and R3, are arranged along the direction Y. Channel columns 16 in even-numbered columns, such as columns R2 and R4, are arranged along the direction Y. The direction Y and the direction X are perpendicular to each other.

A pair of conductor posts (i.e., the first conductor post 32a and the second conductor post 32b) in each channel post 16 are arranged along the direction Y, and are separated by an insulating post 28 (not shown in FIG. 2A for the sake of simplicity. out) are separated from each other. The plurality of first conductive pillars 32a and the plurality of second conductive pillars 32b in each column R are respectively arranged along the direction X. The plurality of first conductive pillars 32a and the plurality of second conductive pillars 32b in odd-numbered columns, such as columns R1 and R3, are arranged along the direction Y. The even-numbered columns, for example, columns R2 and R4, include a plurality of first conductive columns 32a and a plurality of second conductive columns 32b arranged along the direction Y.

Please refer to Figure 2B, Figure 3B and Figure 2F3F, the dielectric layer 62a covers the gate stack structure 52. Plugs 64a and 64b are embedded in dielectric layer 62a. The plugs 64a and 64b respectively land on the first conductor post 32a and the second conductor post 32b and are electrically connected thereto. The size of plugs 64a and 64b may be less than or equal to the size of first conductor post 32a and second conductor post 32b.

Referring to FIG. 2C, FIG. 3C and FIG. 3F, the dielectric layer 62b covers the dielectric layer 62a. The dielectric layer 62b has a first conductor layer M1 therein. The first conductor layer M1 refers to the first conductor layer connected within the conductors above the memory array 10 . The first conductor layer M1 includes a plurality of conductive lines 66a and 66b. The wires 66a and 66b are electrically connected to the plugs 64a and 64b respectively. The conductor 66a includes a first part P1a and a second part P2a; the conductor 66b includes a first part P1b and a second part P2b. The first part P1a and the second part P2a or the first part P1b and the second part P2b may be combined into an L-shape, a T-shape, a cross-shape or similar shapes respectively. In some embodiments, wires 66a and 66b have the same shape to simplify the manufacturing process. The following description takes the L-shaped conductor 66a as an example. The first portion P1a extends along the direction X and is connected to the plug 64a. The length of the first portion P1a in the direction X may be less than, equal to, or greater than the diameter of the first conductor post 32a. The second part P2a is connected to one end of the first part P1a and extends along the direction Y to cover above the channel pillar 16 or cover the charge storage structure 40 , and may even extend to the gate layer covering outside the charge storage structure 40 above 38.

The first parts P1a and P1b, which are electrically connected to the first conductor column 32a and the second conductor column 32b in the same channel column 16, are opposite to each other; the second parts P2a and P2b are far away from each other and do not overlap in the X direction (such as rows R1 and R2); or adjacent to each other and partially overlapping in the X direction (such as rows R3 and R4). In the same column R, a plurality of first parts P1a or P1b may be arranged along the direction X respectively. In the same column R, a plurality of second parts P2a or P2b may be arranged along the direction X respectively. In adjacent columns R, such as columns R1 and R2, the plurality of second portions P2a and/or P2b may be offset from each other.

The plugs 64a and 64b and the plurality of conductors 66a and 66b are, for example, metal filling layers, such as tungsten or copper. In some embodiments, plugs 64a and 64b also include barrier layers between the metal fill layer and dielectric layers 62a and 62b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. The plugs 64a and 64b and the plurality of conductors 66a and 66b may be formed through a single damascene or dual damascene process, but are not limited thereto. The following uses the dual metal inlay process as an example.

Referring to FIG. 3C , dielectric layer 62 is formed on gate stack structure 52 . Dielectric layer 62 includes dielectric layers 62a and 62b. There may be an interface or no interface between the dielectric layers 62a and 62b. Dielectric layer 62 is, for example, silicon oxide. A plurality of trenches T1 and a plurality of plug holes H1 are formed in the dielectric layer 62 through a photolithography and etching process. After that, the barrier layer and the metal filling layer are backfilled, and then removed through an etching back process or a chemical mechanical polishing process. The excess barrier layer and metal filling layer on the dielectric layer 62 are removed to form plugs 64a and 64b and a plurality of conductive lines 66a and 66b.

Referring to FIG. 2D, FIG. 3D and FIG. 3F, the dielectric layer 68a covers the dielectric layer 62 and the plurality of conductors 66a and 66b. Buried in dielectric layer 68a are via windows 70a and 70b. Vias 70a and 70b land on conductors 66a and 66b, respectively. In more detail, the via window 70a lands on the second part P2a of the conductor 66a and is electrically connected thereto; the via window 70b lands on the second part P2b of the conductor 66b and is electrically connected thereto. The via windows 70 a and 70 b may cover above the channel pillar 16 or cover the charge storage structure 40 , and may even extend to cover the gate layer 38 . In the same column R, multiple vias 70a and 70b may be arranged along the direction X respectively. In adjacent rows R, the vias 70a and the vias 70a or the vias 70a and the vias 70b may be staggered to each other. In this embodiment, the plurality of vias 70a in row R1, the plurality of vias 70b in row R1, the plurality of vias 70a in row R2, the multiple vias 70b in row R2, the plurality of vias 70b in row R3. A plurality of vias 70a, a plurality of vias 70b in row R3, a plurality of vias 70a in row R4, and a plurality of vias 70b in row R4 are arranged into via rows RV1, RV2, RV3, RV4, and RV5. , RV6, RV7 and RV8.

Referring to FIG. 2E, FIG. 3E and FIG. 3F, the dielectric layer 68b covers the dielectric layer 68a. The dielectric layer 68b has a second conductor layer M2 therein. The second conductor layer M2 refers to the second conductor layer connected within the conductors above the memory array 10 . The second conductor layer M2 includes a plurality of conductive lines 72a and 72b. The conductive wires 72a and 72b respectively extend along the direction Y and are arranged along the direction X. The conductors 72a and 72b are electrically connected to the vias 70a and 70b respectively. In the Z direction, conductors 72a and 72b overlap second portions P2a and P2b of conductors 66a and 66b, respectively. The conductors 72a and 72b electrically connecting the first conductor column 32a and the second conductor column 32b in the same channel column 16 are not adjacent. Adjacent conductors 72a and 72b are connected to two conductor posts in different columns (the first conductor post 32a and the second conductor post 32b). In some embodiments, each channel column 16 is spanned by at least two (eg, six) conductors 72a and 72b.

The vias 70a and 70b and the plurality of conductors 72a and 72b are, for example, metal filling layers, such as tungsten or copper. In some embodiments, vias 70a and 70b also include barrier layers located between the metal fill layer and dielectric layers 68a and 68b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. The vias 70a and 70b and the plurality of conductors 72a and 72b can be formed through a single damascene or dual damascene process, but are not limited thereto. The following uses the dual metal inlay process as an example.

Referring to FIG. 3E , first, the dielectric layer 68 is formed on the dielectric layer 62 and the first conductor layer M1. Dielectric layer 68 includes dielectric layers 68a and 68b. There may or may not be an interface between dielectric layers 68a and 68b. Dielectric layer 68 is, for example, silicon oxide. In some embodiments, a plurality of trenches and a plurality of plug holes are formed in the dielectric layer 68 through a patterning process, such as a lithography and etching process. In other embodiments, multiple trenches and multiple plug holes may be formed through a self-aligned double patterning (SADP) process. After that, the barrier layer and metal filling layer are backfilled. Then, the excess barrier layer and metal filling layer on the dielectric layer 68 are removed through an etch-back process or a chemical mechanical polishing process to form via windows 70a and 70b and a plurality of conductors 72a and 72b.

Please refer to FIG. 3F. The conductive lines 72a and 72b of the second conductor layer M2 can be used as source lines and bit lines respectively. In this embodiment, the spacing between the conductors of the second conductor layer M2 is quite small, so the occupied chip area can be reduced.

In the above embodiment, the first conductor pillars 32a and the second conductor pillars 32b are arranged along the Y direction perpendicular to the direction X in which the partition wall SLT extends. However, the arrangement direction of the first conductive pillars 32a and the second conductive pillars 32b is not limited to this. In some other embodiments, the first conductive pillar 32a and the second conductive pillar 32b are along a direction that forms an acute angle with the X direction in which the partition wall SLT extends, as shown in FIGS. 4A to 4C and 5A to 5C.

4A-4C illustrate a top view of a manufacturing process of a 3D AND flash memory according to some embodiments. 5A to 5C are cross-sectional views along line IV-IV' of FIGS. 4A to 4C. The cross-sectional view of the memory array 10 in FIGS. 5A to 5C is similar to that in FIG. 1E , but may also be as shown in FIG. 1D . Additionally, for clarity, dielectric layer 62 is not shown in FIGS. 4A-4C.

Referring to FIG. 4A and FIG. 5A , the gate stack structure 52 is divided into a plurality of sub-blocks B by the partition wall SLT. For simplicity, only sub-blocks B1 and B2 are shown in the figure. Each sub-block B has multiple columns R, such as R1 and R2. Each sub-block B in FIGS. 4A to 4C only shows two columns. However, it is not limited thereto, and each sub-block B may include more columns.

The channel columns 16 of each row R are arranged along the direction X. The channel columns 16 of two adjacent columns, such as columns R1 and R2, are staggered to each other. The channel columns 16 of the odd-numbered columns of the sub-blocks B1 and B2, such as the column R1, are arranged along the direction Y. The channel columns 16 of the even-numbered columns of the sub-blocks B1 and B2, such as column R2, are arranged along the direction Y. The direction Y and the direction X are perpendicular to each other.

The plurality of first conductive pillars 32a and the plurality of second conductive pillars 32b in each column R are respectively arranged along the direction X. A pair of conductive pillars (ie, the first conductive pillar 32a and the second conductive pillar 32b) in each channel pillar 16 are arranged along the direction S and are separated from each other by an insulating pillar 28 (not shown in FIG. 4A). The angle Θ between the direction S and the X direction extending from the partition wall SLT is an acute angle. The included angle Θ is, for example, 55 degrees.

In the same sub-block B, the plurality of first conductive pillars 32a in column R1 and the plurality of second conductive pillars 32b in adjacent column R2 are staggered in the direction Y.

Referring to FIG. 4B and FIG. 5B , the dielectric layer 62 a covers the gate stack structure 52 . Plugs 64a and 64b are embedded in dielectric layer 62a. The plugs 64a and 64b respectively land on the first conductor post 32a and the second conductor post 32b and are electrically connected thereto. The size of plugs 64a and 64b may be less than or equal to the size of first conductor post 32a and second conductor post 32b.

Referring to FIG. 4C and FIG. 5C, the dielectric layer 62b covers the dielectric layer 62a. The dielectric layer 62b has a first conductor layer M1 therein. The first conductor layer M1 includes a plurality of conductive lines 66a and 66b. The wires 66a and 66b are electrically connected to the plugs 64a and 64b respectively.

The first conductor layer M1 includes a plurality of conductive lines 66a and 66b. The conductive wires 66a and 66b respectively extend along the direction Y, are arranged along the direction X and are arranged alternately with each other. The wires 66a and 66b are electrically connected to the plugs 64a and 64b respectively. The conductors 66a and 66b electrically connecting the first conductor column 32a and the second conductor column 32b in the same channel column 16 are adjacent to each other. In some embodiments, each channel post 16 is spanned by at least two conductors 66a and two conductors 66b.

The wire 66a electrically connected to the first conductive post 32a of the row R1 of the sub-block B1 extends in the direction Y and is electrically connected to the first conductive post 32a of the row R1 of the sub-block B2. The wires 66b electrically connected to the second conductive posts 32b of the row R1 of the sub-block B1 extend in the direction Y and are electrically connected to the second conductive posts 32b of the row R1 of the sub-block B2. The wire 66a electrically connected to the first conductive post 32a of the row R2 of the sub-block B1 extends in the direction Y and is electrically connected to the first conductive post 32a of the row R2 of the sub-block B2. The wires 66b electrically connected to the second conductive posts 32b of the row R2 of the sub-block B1 extend in the direction Y and are electrically connected to the second conductive posts 32b of the row R2 of the sub-block B2.

The plugs 64a and 64b and the plurality of conductors 66a and 66b are, for example, metal filling layers, such as tungsten or copper. In some embodiments, plugs 64a and 64b also include barrier layers between the metal fill layer and dielectric layers 62a and 62b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. The plugs 64a and 64b and the plurality of conductors 66a and 66b may be formed through a single damascene or dual damascene process, but are not limited thereto. The following uses the dual metal inlay process as an example.

Referring to FIG. 5C , dielectric layer 62 is formed on gate stack 52 . Dielectric layer 62 includes dielectric layers 62a and 62b. There may be an interface or no interface between the dielectric layers 62a and 62b. Dielectric layer 62 is, for example, silicon oxide. A plurality of trenches T2 and a plurality of plug holes H2 are formed in the dielectric layer 62 through a photolithography and etching process. After that, the barrier layer and the metal filling layer are backfilled, and then removed through an etching back process or a chemical mechanical polishing process. The excess barrier layer and metal filling layer on the dielectric layer 62 are removed to form plugs 64a and 64b and a plurality of conductive lines 66a and 66b. The conductive lines 66a and 66b of the first conductor layer M1 can be used as source lines and bit lines respectively.

Referring to FIG. 4D , in some embodiments, the radii of the first conductor post 32a and the second conductor post 32b are respectively a’. The distance between the first conductor post 32a and the second conductor post 32b is b'. The distance between the centers of the first conductor post 32a and the second conductor post 32b is 2a'+b'. The distance between the channel columns 16 is c’. The distance d' between the conductor line 66a and the conductor line 66b of the first conductor layer M1 is (2a'+b')cosΘ. The distance d' between the wires 66a and 66b of the first conductor layer M1 may be equal to 1/4c'. The width e' of the wire 66a or the wire 66b of the first conductor layer M1 may be equal to 1/8c'.

Referring to FIG. 4C, in this embodiment, the wires 66a and 66b of the first conductor layer M1 above the memory array can be used as source lines and bit lines, thus reducing the complexity of the wiring.

Based on the above, embodiments of the present invention can form source lines and bit lines through multi-layer conductor interconnects, thus reducing the occupied chip area. Another embodiment of the present invention uses source poles and drain poles that form an acute angle with the partition wall. Therefore, the complexity of the wiring can be reduced.

10. A ⁽ⁱ⁾ , A ⁽ⁱ⁺¹⁾ : memory array 12: charge storage layer 14: tunneling layer 16: channel pillar 20: memory unit 24: insulating filling layer 28: insulating pillar 32a: source pillar/conductor Pillar/first conductor pillar 32b: drain pillar/conductor pillar/second conductor pillar 36: barrier layer 38: gate layer/word line 40: charge storage structure 50: dielectric substrate 52: gate stack structure 54: Insulating layer 60: arrows 62, 62a, 62b, 68, 68a, 68b: dielectric layer 64a, 64b: plugs 66a, 66b, 72a, 72b: wires 70a, 70b: via window AR: array areas B, B1, B2, BLOCK, BLOCK ⁽ⁱ⁾ , BLOCK ⁽ⁱ⁺¹⁾ : sub-block BL _n , BL _n+1 : bit line C1: contact window SP ^{( i )} _n , SP ⁽ⁱ⁾ _n+1 , SP ^{( i+1 )} _n , SP ⁽ⁱ⁺¹⁾ _n+1 : source column DP ⁽ⁱ⁾ _n , DP ⁱ⁾ _n+1 , DP ⁱ⁺¹⁾ _n , DP ⁽ⁱ⁺¹⁾ _n+1 : source Posts WL ⁽ⁱ⁾ _m , WL ⁽ⁱ⁾ _m+1 , WL ⁽ⁱ⁺¹⁾ _m , WL ⁽ⁱ⁺¹⁾ _m+1 : word line M1: first conductor layer M2: second conductor layer P1a , P1b: the first part P2a, P2b: the second part R, R1, R2, R3, R4: columns RV1, RV2, RV3, RV4, RV5, RV6, RV7, RV8: via column SC: ladder structure SLT: separation Wall SR: Step area T1, T2: Trench H1, H2: Hole S, X, Y, Z: Direction I-I', II-II', III-III', IV-IV': Line a', b' , c', d', e': distance Θ: angle

Figure 1A shows a circuit diagram of a 3D AND flash memory array in accordance with some embodiments. Figure IB shows a top view of a 3D AND flash memory array in accordance with some embodiments. Figure 1C shows a partial three-dimensional view of the memory array of a simplified portion of Figure IB. 1D and 1E show cross-sectional views along line I-I' of FIG. 1C. Figure 1F shows a top view of line II-II' of Figures 1C, 1D and 1E. 2A-2E illustrate a top view of a manufacturing process of a 3D AND flash memory according to some embodiments. 3A to 3E are cross-sectional views along line III-III' of FIGS. 2A to 2E. Figure 3F shows the perspective view of Figure 3E. 4A to 4C illustrate a top view of a manufacturing process of a 3D AND flash memory according to other embodiments. Figure 4D shows a partial schematic diagram of Figure 4C. 5A to 5C are cross-sectional views along line IV-IV' of FIGS. 4A to 4C.

16:Channel column

38: Gate layer/word line

32a: Source post/conductor post/first conductor post

32b: Drain post/conductor post/second conductor post

40:Charge storage structure

52: Gate stack structure

64a, 64b: plug

66a, 66b: Wire

SLT: dividing wall

M1: first conductor layer

B, B1, B2: sub-blocks

R, R1, R2: columns

X, Y: direction

IV-IV’: line

Claims (10)

A three-dimensional AND flash memory element includes: a gate stack structure, which is disposed on a dielectric substrate and includes multiple gate layers and multiple insulation layers that are alternately stacked on each other; a partition wall extends along a first direction to connect the The gate stack structure is divided into a plurality of sub-blocks, wherein each sub-block includes: a plurality of columns, and each column includes: a plurality of channel pillars disposed on the dielectric substrate and passing through the gate stack structure; a charge storage structure disposed between the plurality of gate layers and sidewalls of the plurality of channel pillars; and a plurality of pairs of conductor pillars disposed within the plurality of channel pillars and passing through the gate stack structure, And each is connected to the plurality of channel pillars, wherein each pair of conductor pillars includes a first conductor pillar and a second conductor pillar, and the first conductor pillar and the second conductor pillar are separated from each other along the second direction. , wherein the angle between the second direction and the first direction is an acute angle, the first conductor post serves as a source post, and the second conductor post serves as a drain post. The three-dimensional AND flash memory device according to claim 1, further comprising: a plurality of first conductors extending along a third direction, connecting the first conductor pillar, the third direction and the first direction Vertically; a plurality of second conductors extend along the third direction and connect the second conductor columns. The three-dimensional AND flash memory device of claim 2, wherein each channel column is spanned by two first conductive lines and two second conductive lines. The three-dimensional AND flash memory device of claim 2, wherein the plurality of first conductor pillars in the same sub-block and the plurality of second conductor pillars in adjacent columns are staggered in the third direction. The three-dimensional AND flash memory device as claimed in claim 1, wherein the acute angle is 55 degrees. A three-dimensional AND flash memory element includes: a gate stack structure, which is disposed on a dielectric substrate and includes multiple gate layers and multiple insulation layers that are alternately stacked on each other; a partition wall extends along a first direction to connect the The gate stack structure is divided into a plurality of sub-blocks, wherein each sub-block includes: a plurality of columns, and each column includes: a plurality of channel pillars disposed on the dielectric substrate and passing through the gate stack structure; a charge storage structure disposed between the plurality of gate layers and sidewalls of the plurality of channel pillars; a plurality of conductor pillars arranged in pairs within each channel pillar and passing through the gate stack structure, and Each pair is connected to the plurality of channel pillars, wherein each pair of conductor pillars are arranged and spaced apart from each other in a second direction, wherein the second direction forms a right angle with the first direction; A plurality of plugs located on the plurality of conductor posts, wherein each plug lands and connects to a corresponding conductor post; a plurality of first conductors located on the plurality of plugs, wherein each first conductor It includes: a first part extending along the first direction and connecting the corresponding plug; and a second part extending along the second direction and connecting the first part; a plurality of via windows located on the plurality of a first conductor, wherein each via lands on the second portion; and a plurality of second conductors connecting the plurality of vias, extending along the second direction, and along the Arranged in the first direction, each pair of conductor posts includes a first conductor post and a second conductor post, the first conductor post serves as a source post, and the second conductor post serves as a drain post. The three-dimensional AND flash memory device of claim 6, wherein the plurality of plugs connecting the plurality of first conductor posts and the plurality of second conductor posts of each column are connected to the plurality of plugs and the plurality of second conductor posts. The via windows are respectively arranged along the first direction. The three-dimensional AND flash memory device as claimed in claim 6, wherein two adjacent second conductive lines connect two conductive columns in different columns. The three-dimensional AND flash memory device of claim 6, wherein the two second conductive lines connecting each pair of conductive pillars are not adjacent. The three-dimensional AND flash memory device as claimed in claim 6, wherein each channel column is spanned by at least two or more second conductors.

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