TW202329429A - 3d and flash memory device - Google Patents

Abstract

A three-dimensional AND flash memory device includes a gate stack structure and a silt. The silt extends along the first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of rows, and each row includes a plurality of channel pillars, a plurality of charge storage structures, and a plurality of pairs of conductive pillars. The plurality of pairs of conductive pillars are arranged in the plurality of channel pillars and penetrate the gate stack structure, and are respectively connected to the plurality of channel pillars. Each pair of conductive pillars includes a first conductive pillar and a second conductive pillar separated from each other along a second direction. There is an acute angle between the second direction and the first direction.

Description

3D AND Flash Memory Components

The present invention relates to a semiconductor element and its manufacturing method, and in particular to a three-dimensional AND flash memory element and its manufacturing method.

Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it is widely used in personal computers and other electronic devices. The 3D memory commonly used in the industry currently includes Negative OR (NOR) memory and Negative AND (NAND) memory. In addition, another type of three-dimensional memory is AND memory, which can be applied in a multi-dimensional memory array and has high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become a current trend.

The invention proposes a three-dimensional AND flash memory element and its manufacturing method, which can reduce the chip area or simplify the complexity of winding.

An embodiment of the present invention provides a three-dimensional AND flash memory device, comprising: a gate stack structure disposed on a dielectric substrate, and including multiple gate layers and multiple insulating layers stacked alternately. The partition wall extends along the first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes: a plurality of columns, and each column includes: a plurality of channel pillars, a plurality of charge storage structures and a plurality of pairs of conductor pillars. The plurality of channel pillars are disposed on the dielectric substrate and pass through the gate stack structure. The plurality of charge storage structures are disposed between the plurality of gate layers and sidewalls of the plurality of channel pillars. The multiple pairs of conductor columns are disposed in the plurality of channel columns and pass through the gate stack structure, and are respectively connected to the plurality of channel columns. Each pair of conductor columns includes a first conductor column and a second conductor column, and the first conductor column and the second conductor column are separated from each other along a second direction, wherein the second direction is the same as the first conductor column. The direction includes an acute angle.

An embodiment of the present invention provides a three-dimensional AND flash memory device, comprising: a gate stack structure disposed on a dielectric substrate, and including multiple gate layers and multiple insulating layers stacked alternately. The partition wall extends along the first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of columns. Each row includes: a plurality of channel pillars, a plurality of charge storage structures and a plurality of conductor pillars. A plurality of channel pillars are arranged on the dielectric substrate and pass through the gate stack structure. A plurality of charge storage structures are disposed between the plurality of gate layers and sidewalls of the plurality of channel pillars. A plurality of conductor columns are arranged in pairs in each channel column and pass through the gate stack structure, and are respectively connected with the plurality of channel columns. Each pair of conductor columns is arranged in a second direction and separated from each other, wherein the second direction forms a right angle with the first direction. The three-dimensional AND flash memory device further includes a plurality of plugs, a plurality of first wires, a plurality of vias, and a plurality of second wires. A plurality of plugs are located on the plurality of conductor posts, wherein each plug lands and connects to a corresponding conductor post. A plurality of first wires are located on the plurality of plugs, wherein each of the first wires includes a first portion and a second portion. The first part, extending along the first direction, is connected with the corresponding plug. A second portion, extending along the second direction, connects the first portion. A plurality of vias are located on the plurality of first wires, wherein each via lands on the second portion. A plurality of second wires, connected to the plurality of vias, extend along the second direction, and are arranged along the first direction.

Based on the above, the embodiment of the present invention can form the source line and the bit line through the multi-layer conductor interconnection, or through the source column and the drain column at an acute angle with the partition wall, so that the occupied chip area can be reduced Or reduce the complexity of winding.

Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a top view of a 3D AND flash memory array according to some embodiments. FIG. 1C shows a partial three-dimensional view of the simplified portion of the memory array in FIG. 1B. 1D and 1E show cross-sectional views along the line I-I' of FIG. 1C. Fig. 1F shows a top view of line II-II' of Fig. 1C, Fig. 1D and Fig. 1E.

FIG. 1A is a schematic diagram of two blocks BLOCK ⁽ⁱ⁾ and BLOCK ⁽ⁱ⁺¹⁾ including vertical AND memory arrays 10 arranged in columns and rows. Block BLOCK ⁽ⁱ⁾ includes memory array A ⁽ⁱ⁾ . A column (eg column m+1) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common word line (eg WL ⁽ⁱ⁾ _m+1 ). The AND memory cells 20 of each column (eg column m+1) of the memory array A ⁽ⁱ⁾ correspond to a common word line (eg WL ⁽ⁱ⁾ _m+1 ), and are coupled to different source columns ( For example SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain poles (for example DP ⁽ⁱ⁾ _n and DP ⁽ⁱ⁾ _n+1 ), so that the AND memory cell 20 is along a common word line (for example WL ⁽ⁱ⁾ _m+1 ) are logically arranged in a column.

A row (eg row n ⁾ of the memory array A ^{( i} ) is a set of AND memory cells 20 having a common source column (eg SP ^{( i )} _n ) and a common drain column (eg DP ^{( i )} _n ). The AND memory cells 20 of each row (eg row n) of the memory array A ⁽ⁱ⁾ correspond to different word lines (eg WL ^{( i )} _m+1 and WL ^{( i )} _m ), and are coupled to a common Source posts (eg SP ^{( i )} _n ) and common drain posts (eg DP ^{( i )} _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁾ are logically arranged in a row along a common source column (eg, SP ^{( i )} _n ) and a common drain column (eg, DP ^{( i )} _n ). In a physical layout, the rows or columns may be distorted, arranged in a honeycomb pattern or otherwise, for high density or for other reasons, depending on the fabrication method applied.

In FIG. 1A, in the block BLOCK ⁽ⁱ⁾ , the AND memory cells 20 in the nth row of the memory array A ⁽ⁱ⁾ share a common source column (for example, SP ^{( i )} _n ) and a common drain column ( For example DP ^{( i )} _n ). The AND memory cells 20 in row n+1 share a common source column (eg SP ⁽ⁱ⁾ _n+1 ) and a common drain column (eg DP ^{( i )} _n+1 ).

A common source post (eg SP ^{( i )} _n ) is coupled to a common source line (eg SL _n ); a common drain post (eg DP ^{( i )} _n ) is coupled to a common bit line ( eg _BLn ). A common source post (eg SP ^{( i )} _n+1 ) is coupled to a common source line (eg SL _n+1 ); a common drain post (eg DP ^{( i )} _n+1 ) is coupled to a common bit line (eg BL _n+1 ).

Similarly, block BLOCK ⁽ⁱ⁺¹⁾ includes memory array A ⁽ⁱ⁺¹⁾ which is similar to memory array A ^{(i) in block BLOCK (i) .} A column (eg column ^{m+1) of the memory array A (i} +1) is a set of AND memory cells 20 having a common word line (eg WL ⁽ⁱ⁺¹⁾ _m+1 ). The AND memory cells 20 of each column (for example, the m+1th column) of the memory array A ⁽ⁱ +1) correspond to a common word line (for example, WL ⁽ⁱ⁺¹⁾ _m+1 ), and are coupled to different Source posts (eg SP ⁽ⁱ⁺¹⁾ _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and drain posts (eg DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (for example, row n) of memory array A ^{( i+1 )} is an AND of a common source column (for example, SP ^{( i+1 )} _n ) and a common drain column (for example, DP ^{( i+1 )} _n ) A collection of memory units 20 . The AND memory cells 20 of each row (for example, row n) of the memory array A ⁽ⁱ⁺¹ ) correspond to different word lines (for example, WL ^{( i+1 )} _m+1 and WL ^{( i+1 )} _m ), And coupled to a common source pole (eg SP ^{( i+1 )} _n ) and a common drain pole (eg DP ^{( i+1 )} _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁺¹⁾ are logically arranged in a row along a common source column (eg SP ^{( i+1 )} _n ) and a common drain column (eg DP ^{( i+1 )} _n ) .

The block BLOCK ⁽ⁱ⁺¹⁾ and the block BLOCK ⁽ⁱ⁾ share source lines (such as SL _n and SL _n+1 ) and bit lines (such as BL _n and BL _n+1 ). Therefore, the source line SL _n and the bit line BL _n are coupled to the nth row of AND memory cells 20 in the AND memory array A (i) of the block BLOCK ^{( i)} , and are coupled to the block BLOCK ^{(i+ 1)} AND memory cells 20 in the nth row of the AND memory array A ⁽ⁱ⁺¹⁾ . Similarly, the source line SL _n+1 and the bit line BL _n+1 are coupled to the n+1th row of AND memory cells 20 in the AND memory array A ⁽ⁱ⁾ of the block BLOCK ⁽ⁱ ), and are coupled to AND memory cells 20 in the n+1th row of the AND memory array A ^{( i+1) in the block BLOCK (} i+1).

Referring to FIG. 1B to FIG. 1D , the memory array 10 may include a plurality of sub-blocks, such as sub-block B1 and sub-block B2 . The partition wall SLT extends along the direction X, and separates the gate stack structures 52 of two adjacent sub-blocks B1 and B2 . The partition wall SLT is an insulating material. The insulating material may include an organic insulating material, an inorganic insulating material, or a combination thereof. Each sub-block B1 and B2 may include a gate stack structure 52 disposed on a dielectric substrate 50, a plurality of channel pillars 16, a plurality of first conductive pillars (also referred to as source pillars) 32a and a plurality of second conductive pillars. Conductor posts (also called drain posts) 32 b and a plurality of charge storage structures 40 .

Referring to FIG. 1D , the memory array 10 can be disposed on the interconnect structure of the semiconductor die, such as disposed on one or more active devices (eg, transistors) formed on the semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed above the conductor interconnection structure on the silicon substrate. The dielectric substrate 50 may include an array region AR and a stepped region SR (as shown in FIG. 1B ).

Referring to FIG. 1B and FIG. 1C , the gate stack structure 52 is formed on the dielectric substrate 50 in the array region AR and the step region SR. The gate stack structure 52 includes a plurality of gate layers (also referred to as word lines) 38 and multiple layers of insulating layers 54 vertically stacked on the surface of the dielectric substrate 50 (as shown in FIGS. 1C to 1E ). In the Z direction, the gate layers 38 are electrically isolated by an insulating layer 54 disposed between them. The gate layer 38 extends in a direction parallel to the surface of the dielectric substrate 50 (shown in FIGS. 1C-1E ). As shown in FIG. 1B , the gate layer 38 in the stepped region SR may have a stepped structure SC. Therefore, the lower gate layer 38 is longer than the upper gate layer 38 , and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38 . As shown in FIG. 1B , the contact window C1 for connecting the gate layer 38 may land on the end of the gate layer 38 to connect each gate layer 38 to each wire.

Referring to FIG. 1B to FIG. 1E , the memory array 10 further includes a plurality of channel pillars 16 . The channel pillar 16 extends continuously through the gate stack structure 52 of the array region AR. In some embodiments, the channel column 16 may have a ring shape when viewed from above (as shown in FIG. 1B ). The material of the channel pillar 16 can be semiconductor, such as undoped polysilicon. The channel column 16 may also be called a vertical channel (vertical channel, VC).

Referring to FIG. 1C to FIG. 1E , the memory array 10 further includes an insulating filling layer 24 , an insulating pillar 28 , a plurality of first conductor pillars 32 a and a plurality of second conductor pillars 32 b. In this example, the first conductive post 32a is used as a source post; the second conductive post 32b is used as a drain post. The pair of first conductor pillars 32 a and second conductor pillars 32 b are disposed in the channel pillars 16 , and each extends in a direction perpendicular to the gate layer 38 (ie, the Z direction). The first conductive post 32 a and the second conductive post 32 b are separated by the insulating filling layer 24 and the insulating post 28 . The first conductive post 32 a and the second conductive post 32 b are electrically connected to the channel post 16 . The first conductive pillar 32a and the second conductive pillar 32b include doped polysilicon or metal material. The insulating pillar 28 is, for example, silicon nitride. The insulating filling layer 24 is, for example, silicon oxide.

Referring to FIG. 1D and FIG. 1E , at least a part of the charge storage structure 40 is disposed between the channel pillar 16 and the multilayer gate layer 38 . The charge storage structure 40 may include a tunneling layer (or called a bandgap engineered tunnel oxide layer) 14 , a charge storage layer 12 and a blocking layer 36 . The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36 . In some embodiments, the tunneling layer 14 and the barrier layer 36 include silicon oxide. The charge storage layer 12 includes silicon nitride, or other materials that can trap charges. In some embodiments, as shown in FIG. 1D , a part of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12 ) extends continuously in the direction perpendicular to the gate layer 38 (ie, the Z direction), and the charge storage Another portion of structure 40 (barrier layer 36 ) surrounds gate layer 38 . In other embodiments, as shown in FIG. 1E , the charge storage structure 40 (the tunneling layer 14 , the charge storage layer 12 and the blocking layer 36 ) surrounds the gate layer 38 .

Referring to FIG. 1F , the charge storage structure 40 , the channel column 16 , the source column 32 a and the drain column 32 b are surrounded by the gate layer 38 and define the memory cell 20 . The memory unit 20 can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column 32a and the drain column 32b, since the source column 32a and the drain column 32b are connected to the channel column 16, electrons can be transmitted along the channel column 16 and stored in the entire charge storage In the structure 40, a 1-bit operation can be performed on the memory unit 20 in this way. In addition, for the operation utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and the drain post 32b. . For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electrons can be Or the holes are locally trapped in the charge storage structure 40 adjacent to one of the two source posts 32a and drain posts 32b, so that the unit cell (SLC, 1 bit) or multiple Bit cell (MLC, greater than or equal to 2 bits) operations.

In operation, a voltage is applied to a selected word line (gate layer) 38 , such as when a corresponding threshold voltage (V _th ) higher than that of the corresponding memory cell 20 is applied, intersecting the selected word line 38 The channel region of the channel column 16 is turned on, allowing current to enter the drain column 32b from the bit line BL _n or BL _n+1 (shown in FIG. 1C ) and flow to the source column 32a (eg , in the direction indicated by the arrow 60 ), finally flows to the source line SL _n or SL _n+1 (shown in FIG. 1C ).

Referring to FIG. 1C , the bit lines BL _n BL _n+1 and the source lines SL _n , SL _n+1 can be formed through conductor interconnections above the memory cell array. The formation method of bit lines BL _n , BL _n+1 and source lines SL _n , SL _n+1 can refer to FIG. 2A to FIG. 2E and FIG. 3A to FIG. 3E , or refer to FIG. 4A to FIG. 4C and FIG. 5A To Figure 5C.

2A-2E illustrate top views of a fabrication flow of a 3D AND flash memory according to some embodiments. 3A to 3E are cross-sectional views along line III-III' of FIGS. 2A to 2E . Figure 3F shows a partial perspective view of Figure 3E. The cross-sectional views of the memory array 10 in FIGS. 3A to 3E are similar to those in FIG. 1E , but they can also be as shown in FIG. 1D . Additionally, for clarity, dielectric layers 62 and 68 are not shown in FIGS. 2A-2E and 3F.

Referring to FIG. 2A , FIG. 3A and FIG. 3F , the gate stack structure 52 is divided into a plurality of sub-blocks B by a partition wall SLT. For simplicity, only a single sub-block B is shown in the figure. There are a plurality of columns R in the sub-block B, such as R1, R2, R3 and R4. Only 4 columns are shown in the sub-block B in FIG. 2A to FIG. 2E , however, the embodiment of the present invention is not limited thereto, and each sub-block B may include more columns.

The channel pillars 16 of each row R are arranged along the direction X. The channel pillars 16 of two adjacent columns, such as columns R1 and R2, are staggered. Channel columns 16 of odd columns, such as columns R1 , R3 , are arranged along the direction Y. The channel pillars 16 of even columns, such as columns R2, R4, are arranged along the direction Y. The direction Y and the direction X are perpendicular to each other.

A pair of conductor pillars (namely the first conductor pillar 32a and the second conductor pillar 32b) in each channel pillar 16 are arranged along the direction Y, and are separated by insulating pillars 28 (for the sake of simplicity, not shown in FIG. 2A ). out) separated from each other. The plurality of first conductor columns 32 a and the plurality of second conductor columns 32 b of each row R are arranged along the direction X respectively. Odd columns, such as columns R1 and R3 , are arranged along the direction Y with a plurality of first conductor pillars 32 a and a plurality of second conductor pillars 32 b. The even columns, such as columns R2 and R4, are arranged along the direction Y with a plurality of first conductor columns 32a and a plurality of second conductor columns 32b.

Please refer to Figure 2B, Figure 3B and Figure 2F3F, the dielectric layer 62 a covers the gate stack structure 52 . Plugs 64a and 64b are buried in dielectric layer 62a. The plugs 64a and 64b respectively land on the first conductor post 32a and the second conductor post 32b and are electrically connected thereto. The size of the plugs 64a and 64b may be smaller than or equal to the size of the first conductive post 32a and the second conductive post 32b.

Referring to FIG. 2C, FIG. 3C and FIG. 3F, the dielectric layer 62b covers the dielectric layer 62a. The dielectric layer 62b has a first conductor layer M1 therein. The first conductor layer M1 refers to the first conductor layer of the conductor interconnection above the memory array 10 . The first conductive layer M1 includes a plurality of wires 66a and 66b. The wires 66a and 66b are electrically connected to the plugs 64a and 64b respectively. The wire 66a includes a first portion P1a and a second portion P2a; the wire 66b includes a first portion P1b and a second portion P2b. The first part P1a and the second part P2a or the first part P1b and the second part P2b can be combined into L-shape, T-shape, cross-shape or similar shapes respectively. In some embodiments, the wires 66a and 66b have the same shape to simplify the complexity of the manufacturing process. Hereinafter, the L-shaped wire 66a is taken as an example for illustration. The first portion P1a extends along the direction X and is connected to the plug 64a. The length of the first portion P1a in the direction X may be less than, equal to or greater than the diameter of the first conductor post 32a. The second part P2a is connected to one end of the first part P1a, and extends along the direction Y to cover the channel column 16 or the charge storage structure 40 , and even extend to cover the gate layer outside the charge storage structure 40 38 above.

The first parts P1a and P1b that are electrically connected to the first conductor post 32a and the second conductor post 32b in the same channel post 16 are opposite to each other; the second parts P2a and P2b are far away from each other and do not overlap in the X direction (such as columns R1 and R2); or adjacent to each other and partially overlapping in the X direction (such as columns R3 and R4). In the same column R, a plurality of first parts P1a or P1b may be arranged along the direction X, respectively. In the same column R, the plurality of second parts P2a or P2b may be arranged along the direction X, respectively. In adjacent columns R, such as column R1 and column R2, the plurality of second portions P2a and/or P2b may be staggered with each other.

The plugs 64a and 64b and the plurality of wires 66a and 66b are, for example, metal filling layers such as tungsten or copper. In some embodiments, the plugs 64a and 64b further include a barrier layer between the metal fill layer and the dielectric layers 62a and 62b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. The plugs 64a and 64b and the plurality of wires 66a and 66b can be formed through a single damascene or dual damascene process, but is not limited thereto. The following uses the dual damascene process as an example.

Referring to FIG. 3C , a dielectric layer 62 is formed on the gate stack structure 52 . The dielectric layer 62 includes dielectric layers 62a and 62b. There may be an interface or no interface between the dielectric layers 62a and 62b. The dielectric layer 62 is, for example, silicon oxide. A plurality of trenches T1 and a plurality of plug holes H1 are formed in the dielectric layer 62 through a lithography and etching process, and then the barrier layer and the metal filling layer are backfilled, and then removed by an etch-back process or a chemical mechanical polishing process. The excess barrier layer and metal filling layer on the dielectric layer 62 are removed to form plugs 64a and 64b and a plurality of wires 66a and 66b.

Referring to FIG. 2D, FIG. 3D and FIG. 3F, the dielectric layer 68a covers the dielectric layer 62 and the plurality of wires 66a and 66b. Vias 70a and 70b are buried in dielectric layer 68a. Vias 70a and 70b land on leads 66a and 66b, respectively. In more detail, the via 70a lands on and is electrically connected to the second portion P2a of the wire 66a; the via 70b lands on and is electrically connected to the second portion P2b of the wire 66b. The vias 70 a and 70 b can cover the channel pillar 16 or the charge storage structure 40 , and even extend to cover the gate layer 38 . In the same row R, a plurality of vias 70a and 70b may be arranged along the direction X, respectively. In adjacent columns R, the vias 70 a and 70 a or between the vias 70 a and 70 b may be staggered. In this embodiment, the plurality of vias 70a of row R1, the plurality of vias 70b of row R1, the plurality of vias 70a of row R2, the plurality of vias 70b of row R2, and the plurality of vias 70b of row R3 Vias 70a, vias 70b of row R3, vias 70a of row R4, and vias 70b of row R4 are arranged into via rows RV1, RV2, RV3, RV4, RV5. , RV6, RV7 and RV8.

Referring to FIG. 2E, FIG. 3E and FIG. 3F, the dielectric layer 68b covers the dielectric layer 68a. The dielectric layer 68b has a second conductor layer M2 therein. The second conductor layer M2 refers to the second conductor layer of the conductor interconnection above the memory array 10 . The second conductor layer M2 includes a plurality of wires 72a and 72b. The wires 72 a and 72 b extend along the direction Y and are arranged along the direction X respectively. Wires 72a and 72b are electrically connected to vias 70a and 70b, respectively. In the Z direction, the wires 72a and 72b overlap the second portions P2a and P2b of the wires 66a and 66b, respectively. The wires 72 a and 72 b electrically connecting the first conductive post 32 a and the second conductive post 32 b in the same channel post 16 are not adjacent. Adjacent wires 72 a and 72 b are connected to two conductor posts (first conductor post 32 a and second conductor post 32 b ) in different columns. In some embodiments, each channel column 16 is spanned by at least two (for example, six) wires 72a and 72b.

The vias 70a and 70b and the plurality of wires 72a and 72b are, for example, metal fill layers such as tungsten or copper. In some embodiments, vias 70a and 70b further include a barrier layer between the metal fill layer and dielectric layers 68a and 68b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. The vias 70a and 70b and the plurality of wires 72a and 72b can be formed by a single damascene or dual damascene process, but is not limited thereto. The following uses the dual damascene process as an example.

Referring to FIG. 3E , firstly, a dielectric layer 68 is formed on the dielectric layer 62 and the first conductive layer M1 . The dielectric layer 68 includes dielectric layers 68a and 68b. Dielectric layers 68a and 68b may have an interface or no interface. The dielectric layer 68 is, for example, silicon oxide. In some embodiments, a plurality of trenches and a plurality of plug holes are formed in the dielectric layer 68 through patterning processes, such as lithography and etching processes. In other embodiments, the plurality of trenches and the plurality of plug holes may be formed through a self-aligned double patterning (SADP) process. After that, the barrier layer and the metal fill layer are backfilled. Then, the redundant barrier layer and the metal filling layer on the dielectric layer 68 are removed through an etch-back process or a chemical mechanical polishing process, so as to form vias 70a and 70b and a plurality of wires 72a and 72b.

Referring to FIG. 3F , the wires 72 a and 72 b of the second conductor layer M2 can be used as source lines and bit lines, respectively. In this embodiment, the distance between the wires of the second conductor layer M2 is quite small, so the occupied chip area can be reduced.

In the above embodiments, the first conductive posts 32 a and the second conductive posts 32 b are arranged along the Y direction perpendicular to the X direction in which the partition wall SLT extends. However, the arrangement direction of the first conductor pillars 32 a and the second conductor pillars 32 b is not limited thereto. In some other embodiments, the first conductor post 32 a and the second conductor post 32 b form an acute angle with the X direction extending along the partition wall SLT, as shown in FIGS. 4A to 4C and FIGS. 5A to 5C .

4A-4C illustrate top views of a fabrication flow of a 3D AND flash memory according to some embodiments. 5A to 5C are cross-sectional views along line IV-IV' of FIGS. 4A to 4C . The cross-sectional views of the memory array 10 in FIGS. 5A to 5C are similar to those in FIG. 1E , but they can also be as shown in FIG. 1D . Additionally, dielectric layer 62 is not shown in FIGS. 4A-4C for clarity.

Referring to FIG. 4A and FIG. 5A , the gate stack structure 52 is divided into a plurality of sub-blocks B by a partition wall SLT. For simplicity, only sub-blocks B1 and B2 are shown in the figure. There are multiple columns R in each sub-block B, such as R1, R2. Each sub-block B in FIG. 4A to FIG. 4C only shows 2 columns, however, it is not limited thereto, and each sub-block B may include more columns.

The channel pillars 16 of each row R are arranged along the direction X. The channel pillars 16 of two adjacent columns, such as columns R1 and R2, are staggered. The odd-numbered columns of the sub-blocks B1 and B2 , such as the column R1 , are arranged along the direction Y. The channel pillars 16 of the even-numbered columns of the sub-blocks B1 and B2 , such as the column R2 , are arranged along the direction Y. The direction Y and the direction X are perpendicular to each other.

The plurality of first conductor columns 32 a and the plurality of second conductor columns 32 b of each row R are arranged along the direction X respectively. A pair of conductor pillars (ie, the first conductor pillar 32 a and the second conductor pillar 32 b ) in each channel pillar 16 are arranged along the direction S and separated from each other by insulating pillars 28 (not shown in FIG. 4A ). The angle Θ between the direction S and the X direction where the partition wall SLT extends is an acute angle. The included angle Θ is, for example, 55 degrees.

In the same sub-block B, the plurality of first conductor pillars 32a of the row R1 and the plurality of second conductor pillars 32b of the adjacent row R2 are staggered in the direction Y.

Referring to FIG. 4B and FIG. 5B , the dielectric layer 62 a covers the gate stack structure 52 . Plugs 64a and 64b are buried in dielectric layer 62a. The plugs 64a and 64b respectively land on the first conductor post 32a and the second conductor post 32b and are electrically connected thereto. The size of the plugs 64a and 64b may be smaller than or equal to the size of the first conductive post 32a and the second conductive post 32b.

Referring to FIG. 4C and FIG. 5C, the dielectric layer 62b covers the dielectric layer 62a. The dielectric layer 62b has a first conductor layer M1 therein. The first conductive layer M1 includes a plurality of wires 66a and 66b. The wires 66a and 66b are electrically connected to the plugs 64a and 64b respectively.

The first conductive layer M1 includes a plurality of wires 66a and 66b. The conductive wires 66 a and 66 b extend along the direction Y respectively, are arranged along the direction X and are arranged alternately with each other. The wires 66a and 66b are electrically connected to the plugs 64a and 64b respectively. The wires 66 a and 66 b electrically connecting the first conductive post 32 a and the second conductive post 32 b in the same channel post 16 are adjacent to each other. In some embodiments, each channel pillar 16 is spanned by at least two wires 66a and two wires 66b.

The conductive wire 66a electrically connected to the first conductive post 32a of the row R1 of the sub-block B1 extends in the direction Y and electrically connects the first conductive post 32a of the row R1 of the sub-block B2. The conductive wire 66b electrically connected to the second conductive column 32b of the column R1 of the sub-block B1 extends in the direction Y and electrically connects the second conductive column 32b of the column R1 of the sub-block B2. The conductive wire 66a electrically connected to the first conductive pillar 32a of the row R2 of the sub-block B1 extends in the direction Y and electrically connects the first conductive pillar 32a of the row R2 of the sub-block B2. The conductive wire 66b electrically connected to the second conductive pillar 32b of the row R2 of the sub-block B1 extends in the direction Y and electrically connects the second conductive pillar 32b of the row R2 of the sub-block B2.

The plugs 64a and 64b and the plurality of wires 66a and 66b are, for example, metal filling layers such as tungsten or copper. In some embodiments, the plugs 64a and 64b further include a barrier layer between the metal fill layer and the dielectric layers 62a and 62b. The barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or combinations thereof. The plugs 64a and 64b and the plurality of wires 66a and 66b can be formed through a single damascene or dual damascene process, but is not limited thereto. The following uses the dual damascene process as an example.

Referring to FIG. 5C , a dielectric layer 62 is formed on the gate stack structure 52 . The dielectric layer 62 includes dielectric layers 62a and 62b. There may be an interface or no interface between the dielectric layers 62a and 62b. The dielectric layer 62 is, for example, silicon oxide. A plurality of trenches T2 and a plurality of plug holes H2 are formed in the dielectric layer 62 through a lithography and etching process, and then the barrier layer and the metal filling layer are backfilled, and then removed through an etch-back process or a chemical mechanical polishing process. The excess barrier layer and metal filling layer on the dielectric layer 62 are removed to form plugs 64a and 64b and a plurality of wires 66a and 66b. The wires 66 a and 66 b of the first conductor layer M1 can be respectively used as source lines and bit lines.

Referring to FIG. 4D , in some embodiments, the radii of the first conductor post 32a and the second conductor post 32b are respectively a'. The distance between the first conductor column 32a and the second conductor column 32b is b'. The distance between the centers of the first conductor post 32a and the second conductor post 32b is 2a'+b'. The distance between the channel posts 16 is c'. The distance d' between the wire 66a and the wire 66b of the first conductor layer M1 is (2a'+b')cosΘ. The distance d' between the wire 66a and the wire 66b of the first conductor layer M1 may be equal to 1/4c'. The width e' of the wire 66a or the wire 66b of the first conductor layer M1 may be equal to 1/8c'.

Referring to FIG. 4C , in this embodiment, the wires 66 a and 66 b of the first conductor layer M1 above the memory array can be used as source lines and bit lines, thus reducing the complexity of wiring.

Based on the above, the embodiment of the present invention can form the source line and the bit line through the multi-layer conductor interconnection, therefore, the occupied chip area can be reduced. In another embodiment of the present invention, the source post and the drain post form an acute angle with the partition wall, thereby reducing the complexity of the wiring.

10. A ⁽ⁱ⁾ , A ⁽ⁱ⁺¹⁾ : memory array 12: charge storage layer 14: tunneling layer 16: channel column 20: memory unit 24: insulating filling layer 28: insulating column 32a: source column/conductor pillar/first conductor pillar 32b: drain pole/conductor pillar/second conductor pillar 36: barrier layer 38: gate layer/word line 40: charge storage structure 50: dielectric substrate 52: gate stack structure 54: Insulation layer 60: arrows 62, 62a, 62b, 68, 68a, 68b: dielectric layer 64a, 64b: plugs 66a, 66b, 72a, 72b: wires 70a, 70b: via AR: array area B, B1, B2, BLOCK, BLOCK ⁽ⁱ⁾ , BLOCK ⁽ⁱ⁺¹⁾ : sub-block BL _n , BL _n+1 : bit line C1: contact windows SP ^{( i )} _n , SP ⁽ⁱ⁾ _n+1 , SP ^{( i+1 )} _n , SP ⁽ⁱ⁺¹⁾ _n+1 : source post DP ⁽ⁱ⁾ _n , DP ⁱ⁾ _n+1 , DP ⁱ⁺¹⁾ _n , DP ⁽ⁱ⁺¹⁾ _n+1 : source Pole WL ⁽ⁱ⁾ _m , WL ⁽ⁱ⁾ _m+1 , WL ⁽ⁱ⁺¹⁾ _m , WL ⁽ⁱ⁺¹⁾ _m+1 : word line M1 : first conductor layer M2 : second conductor layer P1a , P1b: first part P2a, P2b: second part R, R1, R2, R3, R4: column RV1, RV2, RV3, RV4, RV5, RV6, RV7, RV8: via column SC: ladder structure SLT: separation Wall SR: Step area T1, T2: Ditch H1, H2: Hole S, X, Y, Z: Direction I-I', II-II', III-III', IV-IV': Line a', b' , c', d', e': distance Θ: included angle

Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a top view of a 3D AND flash memory array according to some embodiments. FIG. 1C shows a partial three-dimensional view of the simplified portion of the memory array in FIG. 1B. 1D and 1E show cross-sectional views along the line I-I' of FIG. 1C. Fig. 1F shows a top view of line II-II' of Fig. 1C, Fig. 1D and Fig. 1E. 2A-2E illustrate top views of a fabrication flow of a 3D AND flash memory according to some embodiments. 3A to 3E show cross-sectional views along line III-III' of FIGS. 2A to 2E . Figure 3F shows a perspective view of Figure 3E. 4A to 4C show top views of the manufacturing process of 3D AND flash memory according to other embodiments. FIG. 4D shows a partial schematic view of FIG. 4C. 5A to 5C are sectional views shown as line IV-IV' of FIGS. 4A to 4C .

16: Channel column

38:Gate layer/word line

32a: source post/conductor post/first conductor post

32b: drain pole/conductor column/second conductor column

40:Charge storage structure

52:Gate stack structure

64a, 64b: Plugs

66a, 66b: wires

SLT: partition wall

M1: the first conductor layer

B, B1, B2: sub-blocks

R, R1, R2: columns

X, Y: direction

IV-IV': line

Claims (10)

A three-dimensional AND flash memory element, comprising: The gate stack structure is arranged on the dielectric substrate, and includes multi-layer gate layers and multi-layer insulating layers stacked alternately with each other; a partition wall extending along a first direction to divide the gate stack structure into a plurality of sub-blocks, wherein each sub-block includes: Multiple columns, each column includes: A plurality of channel pillars are arranged on the dielectric substrate and pass through the gate stack structure; a plurality of charge storage structures disposed between the plurality of gate layers and sidewalls of the plurality of channel pillars; and A plurality of pairs of conductor pillars are arranged in the plurality of channel pillars and pass through the gate stack structure, and are respectively connected to the plurality of channel pillars, wherein each pair of conductor pillars includes a first conductor pillar and a second conductor pillar , the first conductor post and the second conductor post are spaced apart from each other along a second direction, wherein the angle included between the second direction and the first direction is an acute angle. The three-dimensional AND flash memory device as described in claim 1, further comprising: a plurality of first wires extending along a third direction and connecting the first conductor posts, the third direction being perpendicular to the first direction; A plurality of second wires extend along the third direction and connect the second conductor posts. The three-dimensional AND flash memory device as claimed in claim 2, wherein each channel column is spanned by two first wires and two second wires. The three-dimensional AND flash memory device according to claim 2, wherein the plurality of first conductive pillars in the same sub-block and the plurality of second conductive pillars in adjacent columns are staggered in the third direction. The three-dimensional AND flash memory device according to claim 1, wherein the acute angle is 55 degrees. A three-dimensional AND flash memory element, comprising: The gate stack structure is arranged on the dielectric substrate, and includes multi-layer gate layers and multi-layer insulating layers stacked alternately with each other; a partition wall extending along a first direction to divide the gate stack structure into a plurality of sub-blocks, wherein each sub-block includes: Multiple columns, each column includes: A plurality of channel pillars are arranged on the dielectric substrate and pass through the gate stack structure; a plurality of charge storage structures disposed between the plurality of gate layers and sidewalls of the plurality of channel pillars; A plurality of conductor columns are arranged in pairs in each channel column and pass through the gate stack structure, and are respectively connected to the plurality of channel columns, wherein each pair of conductor columns is arranged in the second direction and separated from each other open, wherein the second direction forms a right angle with the first direction; a plurality of plugs on the plurality of conductor posts, wherein each plug lands on and connects to a corresponding conductor post; A plurality of first wires on the plurality of plugs, wherein each first wire includes: a first portion, extending along said first direction, connected to a corresponding plug; and a second portion extending along the second direction and connected to the first portion; a plurality of vias on the first plurality of conductive lines, wherein each via lands on the second portion; and A plurality of second wires, connected to the plurality of vias, extend along the second direction, and are arranged along the first direction. The three-dimensional AND flash memory device according to claim 6, wherein the plurality of plugs and the plurality of plugs connecting the plurality of first conductor columns and the plurality of second conductor columns of each column are The vias are respectively arranged along the first direction. The three-dimensional AND flash memory device according to claim 6, wherein two adjacent second wires are connected to two conductor posts in different columns. The three-dimensional AND flash memory device as claimed in claim 6, wherein the two second wires connecting the conductor posts of each pair are not adjacent. The three-dimensional AND flash memory device according to claim 6, wherein each channel column is spanned by at least two second wires.

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