KR100928021B1 - Semiconductor device with three-dimensional array structure - Google Patents

Abstract

A semiconductor device having a three-dimensional structure is provided. The semiconductor device includes a cell array region and a row decoder region adjacent to the cell array region. The cell array region is composed of a first cell block having a first gate line in a first layer, and a second cell block having a second gate line in a second layer on the first layer. The row decoder region includes a first row decoder controlling the first gate line and a second row decoder controlling the second gate line. There is a first wiring connecting the first gate line and the first row decoder, and a second wiring connecting the second gate line and the second row decoder.

Cell Array Area, Row Decoder, Metal Contact

Description

Semiconductor device having a three-dimensional array structure {SEMICONDUCTOR DEVICE WITH THREE-DIMENSIONAL ARRAY STRUCTURE}

1 is a block diagram schematically illustrating a semiconductor device having a three-dimensional structure according to example embodiments of the inventive concepts.

2 illustrates a method of arranging a row decoder of a semiconductor device having a three-dimensional structure according to an embodiment of the present invention.

3A is a layout of a semiconductor device having a three-dimensional structure disposed by the method of FIG. 2, according to embodiments of the present invention, and FIGS. 3B, 3C, and 3D are respectively II ′, II of FIG. 3A. Sections taken along lines II 'and III-III'.

4A and 5A are various modifications of the layout of a semiconductor device having a three-dimensional structure arranged in the method of FIG. 2, according to embodiments of the present invention, and FIGS. 4B and 5B are respectively FIGS. 4A and 5A. These are cross-sectional views taken along the line II '.

6 illustrates a method of arranging a row decoder of a semiconductor device having a three-dimensional structure according to another embodiment of the present invention.

7A through 14A are various modifications of a layout of a semiconductor device having a three-dimensional structure arranged by the method of FIG. 6, according to embodiments of the present disclosure.

7B to 14B are cross-sectional views taken along line II ′ of FIGS. 7A to 14A, respectively.

15A through 17A are layouts of a semiconductor device having a three-dimensional structure according to example embodiments.

15B to 17B are cross-sectional views taken along the line II ′ of FIGS. 15A to 17A, respectively.

18 schematically illustrates an electronic device including a semiconductor device having a three-dimensional structure according to embodiments of the present invention.

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a three-dimensional array structure.

With the development of semiconductor manufacturing technology, the demand for high density memory has continued. Various methods have been proposed to meet these needs. One such method is to provide a semiconductor device having a three-dimensional array structure. Techniques for implementing a three-dimensional structure semiconductor device are described in US Patent No. 5,835,396 (1998.12.7) entitled " THREE- DIMENTIONAL READ-ONLY MEMORY ", and US Patent No. 6034882 (2000.3.7) " VERTICALLY STACKED FIELD NONVOLATILE MEMORY aND PROGRAMMABLE "under the title, and U.S. Patent No. 7,002,825 to (2006.2.21)" METHOD oF FABRICATION are placed respectively entitled WORD LINE ARRANGEMENT HAVING SEGMENTED WORD LINES " , hereby incorporated by reference in this application.

The three-dimensional structure semiconductor device includes memory cell arrays each formed in a plurality of semiconductor layers. The semiconductor layers may include well-known silicon substrates and substrates sequentially stacked on the silicon substrate. The stacked substrates can be formed using, for example, selective epitaxy techniques. A stacked structure semiconductor device is a stacked flash memory device. Since a stacked flash memory device has a plurality of word lines, the row decoder must be able to control them independently.

The present invention provides a semiconductor device having a plurality of word lines and a method of forming the same.

The present invention provides a semiconductor device having a three-dimensional structure. The semiconductor device may include a cell array region including a first cell block having a first gate line in a first layer and a second cell block having a second gate line in a second layer on the first layer; A row decoder region adjacent the cell array region and including a first row decoder controlling the first gate line and a second row decoder controlling the second gate line; A first wiring connecting the first gate line and the first row decoder; And a second wiring connecting the second gate line and the second row decoder.

In one embodiment. The first row decoder may include an odd first row decoder that controls an odd first gate line, and an even first row decoder that controls an even first gate line. The second row decoder may include an odd second row decoder controlling an odd second gate line, and an even second row decoder controlling an even second gate line. The odd first row decoder and the even first row decoder are provided on opposite sides of the cell array region to face each other, and the odd second row decoder and the even second row decoder are opposite sides of the cell array region to face each other. Can be provided.

The even first row decoder and the odd second row decoder may be provided at one side of the cell array region, and the odd first row decoder and the even second row decoder may be provided at the other side of the cell array region. The even first row decoder and the even second row decoder may be provided at one side of the cell array region, and the odd first row decoder and the odd second row decoder may be provided at the other side of the cell array region.

In the present invention, the semiconductor device includes a cell array including a first cell block having a first gate line in a first layer and a second cell block having a second gate line in a second layer on the first layer. domain; Wirings commonly connected to the first gate line and the second gate line; And a row decoder adjacent to the cell array region and simultaneously selecting and controlling the first gate line and the second gate line through the wiring.

Hereinafter, a semiconductor device according to example embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings. The invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

Although terms such as first, second, third, etc. are used to describe various parts, materials, etc. in various embodiments of the present specification, these parts should not be limited by the same terms. Also, these terms are only used to distinguish one part from another part. Thus, what is referred to as the first part in one embodiment may be referred to as the second part in other embodiments.

The semiconductor device having a three-dimensional structure according to the present invention may be a flash memory array, a read only memory array, a static random access memory array, or the like. A flash memory array having a floating gate is described, for example. The semiconductor device having a three-dimensional structure according to the present invention may be a NAND flash memory array or the like.

The flash memory array according to the present invention has a plurality of stacked semiconductor layers used as substrates for forming memory cells. Although three semiconductor layers (ie, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer) are shown for convenience of description, the number of the semiconductor layers may be two or four or more.

1 is a block diagram schematically illustrating a semiconductor device having a three-dimensional structure according to example embodiments of the inventive concepts.

Strings 100S, 200S, 300S of memory cells are provided on the semiconductor layers, respectively. There are a plurality of strings in each semiconductor layer, and only one string is shown in each semiconductor layer in FIG. The strings of each semiconductor layer may be arranged vertically. The string will include a string select transistor, a ground select transistor, and a plurality of memory cells connected in series therebetween. For example, the string 100S on the first semiconductor layer includes a first string select transistor SSTL1, a first ground select transistor GSTL1, and a plurality of memory cells connected in series between the second semiconductor layer. The string 200S on the top may include a second string select transistor SSTL2, a second ground select transistor GSTL2, and a plurality of memory cells connected in series therebetween, and the string 300S on the third semiconductor layer may include a third string. The string select transistor SSTL3, the third ground select transistor GSTL3, and a plurality of memory cells connected in series therebetween may be included.

The memory cells MCi_j and the string select transistors SSTLj of each layer are individually controlled by the select signals WLi and LSSLj of the row decoder X-DEC corresponding thereto, while the ground select transistors GSTLj may be commonly controlled by one selection signal GSL. A structure in which three semiconductor layers are arranged and sixteen main cells are arranged in one string is described, for example. That is, 0 ≦ i ≦ 15 and 1 ≦ j ≦ 3.

Drains of the string select transistors SSTL1, SSTL2, and SSTL3 are connected in common. The drains are electrically connected to the source of the main string select transistor SSTM, and the drain of the main string select transistor SSTM is electrically connected to the bit line BL. The sources of the ground select transistors GSTL1, GSTL2, GSTL3 are commonly connected. The sources are electrically connected to the drain of the main ground select transistor GSTM, and the source of the main ground select transistor GSTM is electrically connected to a common source line CSL. The main string select transistor SSTM and the main ground select transistor GSTM are controlled by the select signals SSLM and GSLM, respectively. The main string select transistor SSTM and the main ground select transistor GSTM may be disposed in the first semiconductor layer 102, the second semiconductor layer, or the third semiconductor layer.

In general, the semiconductor device includes a memory cell array area MC and a row decoder area X-DEC adjacent thereto. 2 illustrates a method of arranging a row decoder of a semiconductor device having a three-dimensional structure according to an embodiment of the present invention. Referring to FIG. 2, the memory cell array region may include a pair of cell array regions adjacent to each other, and the row decoder region may be disposed on one side of the cell array region. That is, it can be understood that the region A including one cell array region and one row decoder disposed on one side adjacent thereto, and the region B having an arrangement structure symmetric with the region A are repeatedly connected.

3A is a layout of a semiconductor device having the three-dimensional structure of FIG. 1 arranged in the method of FIG. 2, in accordance with embodiments of the present invention. Only area A of FIG. 2 is shown. 3B, 3C, and 3D are cross-sectional views taken along lines II ′, II-II ′, and III-III ′ of FIG. 3A, respectively. 3 illustrates, for example, the cell array region B of FIG. 2 and a row decoder adjacent thereto.

According to embodiments of the present invention, the first semiconductor layer 102 may be a single crystal silicon wafer. The second and third semiconductor layers 202 and 302 may be single crystal silicon epitaxy layers formed by a well-known epitaxy process using the first semiconductor layer as a seed. 3A through 3D, the semiconductor layers 102, 202, and 302 may include active regions 103, 203, and 303 (ACT) extending along one direction, and a device isolation pattern defining the active regions. (104, 204, 304). The device isolation pattern may be formed by a well-known device isolation process, for example, shallow trench device isolation (STI).

Gate lines extend over the semiconductor layers 102, 202, and 302 in one direction across the active regions. The gate lines may include a string select line LSSL_j, a ground select line LGSL_j, and word lines WLi_j therebetween. LSSL_j represents a string select line of the j th semiconductor layer. WLi_j represents the i-th word line of the j-th semiconductor layer. LGSL_j represents the ground select line of the j th semiconductor layer. For convenience of discussion, the string select line, ground select line and word lines of the j th semiconductor layer are referred to as the j th gate line. For example, the string selection line LSSL_1 and the ground selection line LGSL_1 and the word lines WLi_1 therebetween of the first semiconductor layer 102 are referred to as first gate lines. Each of the word lines may include charge storage layers 108, 208, and 308, dielectric layers 109, 209, and 309, and gate electrodes 110, 210, and 310. Each of the selection lines may include charge storage layers 108, 208, and 308 and gate electrodes 110, 210, and 310. The charge storage layer may be a floating gate or a charge trap layer. A tunnel insulating layer 106, 206, 306 is interposed between each of the word lines and the semiconductor layers 102, 202, and 302. Source / drain impurity regions 105, 205, and 305 are formed in an active region between the selection lines and the word lines.

An interlayer insulating film 401 is formed on the semiconductor layers 102, 202, and 302. The interlayer insulating layer 401 may be interposed between the semiconductor layers. Bit lines BL may extend across the gate lines WLi_j on the interlayer insulating layer of the third semiconductor layer 302. The bit lines BL may extend over the active regions 103, 203, and 303 (ACT).

Drains of the string select transistors controlled by the string select lines LSSL_j may be commonly connected to the drain plug 454. The drain plug 454 may be connected to a source of the main string select transistor SSTM, and the drain of the main string select transistor SSTM may be electrically connected to the bit line BL through the contact plug 452. Sources of the ground select transistors controlled by the ground select lines LGSL_j may be commonly connected to the source plug 456. The source plug 456 may be connected to the drain of the main ground select transistor GSTM, and the source of the main ground select transistor may be electrically connected to the common source line CSL. In the drawing, although the common source line CSL, the main string select transistor GSTM and the main ground select transistor GSTM are formed in the first semiconductor layer 102, the present disclosure is not limited thereto. It may be formed on the second semiconductor layer 202 or the third semiconductor layer 302. The drain plug 452 and the source plug 454 may be formed of a barrier metal layer and a metallic material on the barrier metal layer. The barrier metal film may be at least one of titanium, tantalum, titanium nitride tantalum nitride, and tungsten nitride, and the metallic material may be formed of at least one of copper, aluminum, and tungsten.

Referring again to FIGS. 3A and 3B, the memory cell array region of the semiconductor device having the three-dimensional structure may include the first cell block 100 and the second semiconductor layer 202 of the first semiconductor layer 102. The second cell block 200 and the third cell block 300 of the third semiconductor layer 302 may be included. The first cell block 100, the second cell block 200, and the third cell block 300 may include the first gate line, the second gate line, and the third gate line, respectively. Can be. The row decoder region may include a first row decoder DEC1 for controlling the first gate line, a second row decoder DEC2 for controlling the second gate line, and a third row for controlling the third gate line. It may include a decoder DEC3.

Referring to FIG. 3B, the first gate line including the word line WLi_1 and the string select line LSSL_1 of the first semiconductor layer and the first row decoder DEC1 may be connected by a first wiring. The first wiring may include a first gate line contact 412 contacting the first gate line, a first metal pattern 414 connected to the first gate line contact 412, and the first metal pattern 414. ) And a first decoder contact 416 connecting the first row decoder DEC1. The second gate line including the word line WLi_2 and the string select line LSSL_2 of the second semiconductor layer and the second row decoder may be connected by a second wiring. The second wiring may include a second gate line contact 422 contacting the second gate line, a second metal pattern 424 connected to the second gate line contact 422, and the second metal pattern 424. ) And a second decoder contact 426 connecting the second row decoder DEC2. The third gate line including the word line WLi_3 and the string select line LSSL_3 of the third semiconductor layer and the third row decoder may be connected by a third wiring. The third wiring may include a third gate line contact 432 contacting the third gate line, a third metal pattern 434 connected to the third gate line contact 432, and the third metal pattern 434. ) And a third decoder contact 436 connecting the third row decoder DEC3. The gate line contacts 412, 422, and 432 may be disposed at one side of the cell array region adjacent to the row decoder region. The contacts 412, 422, 432, 416, 426, and 436 may be formed of a barrier metal layer and a metallic material on the barrier metal layer. The barrier metal film may be at least one of titanium, tantalum, titanium nitride tantalum nitride, and tungsten nitride, and the metallic material may be formed of at least one of copper, aluminum, and tungsten.

In order to facilitate wiring, the first metal pattern 414, the second metal pattern 424, and the third metal pattern 434 may be sequentially stacked on the third semiconductor layer 302. . The bit lines BL may be formed simultaneously with at least one of the first metal pattern, the second metal pattern, and the third metal pattern, and may be substantially disposed on the same layer. The bit lines BL may be formed of the same material as the first metal pattern, the second metal pattern, and the third metal pattern.

Meanwhile, referring to FIG. 3C, since the ground select transistors GSTLj may be commonly controlled by one select signal GSL, the ground select lines LGSL_j may be formed through the first and second ground lines. It can be commonly connected to the second and third row decoders. The ground line may include a ground line contact 442 and a ground line contact 442 contacting the first ground select line LGSL_1, the second ground select line LGSL_2, and the third ground select line LGSL_3. Ground metal pattern 444, and ground decoder contacts 446, 447, and 448. The ground line contact 442 may contact the third ground selection line through the first ground selection line and the second ground selection line. The ground metal pattern 444 may be formed of the same material on the same layer as the bit lines BL.

The first row decoder DEC1 is closest to the cell array region, the third row decoder DEC3 is farthest, and the second row decoder DEC2 is connected to the first row decoder DEC1 and the first row decoder DEC1. It may be arranged between the three row decoder DEC3.

The number of the first gate lines, the number of first row decoder outputs controlling the second gate line, the number of second gate lines controlling the number of second row decoder outputs, and the number of third gate lines controlling the first gate line; The number of third row decoder outputs controlling the same may be the same.

According to FIGS. 3B and 3C, the first row decoder DEC1, the second row decoder DEC2, and the third row decoder DEC3 are all disposed on the first semiconductor layer 102, but the present invention is not limited thereto. According to embodiments of the present invention, other modified arrangements may be possible. For example, referring to FIG. 3E, the second row decoder DEC2 may be disposed in the second semiconductor layer 202, and the third row decoder DEC3 may be disposed in the third semiconductor layer 302, respectively. Can be. Therefore, since the total area of the row decoder region is reduced, the degree of integration can be further improved.

In the semiconductor device having a three-dimensional structure according to embodiments of the present disclosure, various modifications of the method of connecting the row decoder region and the memory cell array region are described. In the same three-dimensional structure as in FIG. 3A, arrangement methods for connecting word lines of each semiconductor layer to a row decoder are provided in various modifications. For ease of discussion, only the word lines are selectively shown and described except for the selection lines of FIG. 3A. 4A-14A are various layouts, and FIGS. 4B-14B are cross-sectional views taken along the line II ′ of FIGS. 4A-14A, respectively.

4A and 4B, the first word line WLi_1 is connected to the first row decoder DEC1 by the first wiring, and the second word line WLi_2 and the third word line WLi_3 are formed by the first wiring. The second row decoder DEC2 may be commonly connected to each other by two wires. The first wiring may include a first word line contact 412 contacting the first word line WLi_1, a first metal pattern 414 connected to the first word line contact 412, and the first metal. It may include a first decoder contact 416 connecting the pattern and the first row decoder. The second wiring may include a second word line contact 422 contacting the second word line WLi_2 and a third word line WLi_3 and a second metal pattern connected to the second word line contact 422. 424) and a second decoder contact 426 connecting the second metal pattern to the second row decoder. The second word line contact 422 may contact the second word line WLi_2 through the third word line WLi_3. The second row decoder DEC2 may control the second word line WLi_2 and the third word line WLi_3 in common. The first wordline contact 412 and the second wordline contact 422 may be disposed at one side of the cell array region adjacent to the row decoder region. For easy wiring, the first metal pattern 414 and the second metal pattern 424 may be sequentially stacked on the third semiconductor layer 302.

5A and 5B, the first word line WLi_1 and the second word line WLi_2 are commonly connected to the first row decoder DEC1 by the first wiring and the third word line WLi_3. May be connected to the second row decoder DEC2 by a second wiring. The first wiring includes a first word line contact 412 that contacts the first word line WLi_1 and the second word line WLi_2, and a first metal pattern connected to the first word line contact 412. 414, and a first decoder contact 416 connecting the first metal pattern to the first row decoder. The first word line contact 412 may contact the first word line WLi_1 through the second word line WLi_2. The second wiring may include a third word line contact 432 contacting the third word line WLi_3, a third metal pattern 434 connected to the third word line contact 432, and the third metal. It may include a third decoder contact 436 connecting the pattern and the second row decoder DEC2. The first row decoder DEC1 may control the first word line WLi_1 and the second word line WLi_2 in common. The first word line line contact 412 and the second word line contact 422 may be disposed at one side of the cell array region adjacent to the row decoder region. In order to facilitate wiring, the first metal pattern 414 and the third metal pattern 434 may be sequentially stacked on the third semiconductor layer 302.

Meanwhile, referring to FIG. 6, the memory cell array region may include cell array regions separated from each other, and row decoder regions disposed between the cell array regions. The row decoder regions may be understood to be disposed at both sides of the memory cell array regions. At least one row decoder of the row decoder regions may be disposed on an opposite side of the cell array region to face another row decoder. That is, it can be understood that the region C including one cell array region and one row decoder disposed on one side adjacent thereto, and the region D having a symmetrical arrangement structure with the region C are repeatedly connected. Alternatively, it may be understood that the region C including one cell array region and one row decoder disposed on one side adjacent thereto is repeatedly connected. The layouts and cross-sectional views of the semiconductor device having the three-dimensional structure of FIG. 1 arranged in the manner of FIG. 6 are shown below. Only area C of FIG. 6 is shown.

7A and 7B, the third row decoder DEC3 is disposed on opposite sides of the first row decoder DEC1 and the second row decoder DEC2. The first word line WLi_1 is connected to the first row decoder DEC1 by a first wiring, the second word line WLi_2 is connected to the second row decoder DEC2 by a second wiring, and the third The word line WLi_3 may be connected to the third row decoder DEC3 by a third wiring. The first wiring may include a first word line contact 412 contacting the first word line WLi_1, a first metal pattern 414 connected to the first word line contact 412, and the first metal. It may include a first decoder contact 416 connecting the pattern and the first row decoder. The second wiring may include a second word line contact 422 contacting the second word line WLi_2, a second metal pattern 424 connected to the second word line contact 422, and the second metal. A second decoder contact 426 connecting the pattern and the second row decoder may be included. The third wiring may include a third word line contact 432 contacting the third word line WLi_3, a third metal pattern 434 connected to the third word line contact 432, and the third metal. It may include a third decoder contact 436 connecting the pattern and the third row decoder. The first wordline line contact 412 and the second wordline contact 422 may be disposed at one side of the cell array region adjacent to the first and second row decoder regions. The third word line line contact 432 may be disposed on the other side of the cell array region adjacent to the third row decoder region. In order to facilitate wiring, the first metal pattern 414 and the second metal pattern 424 may be sequentially stacked on the third semiconductor layer 302. The third metal pattern constituting the third wiring may be positioned on a plane substantially the same as the first metal pattern or the second metal pattern constituting the first wiring or the second wiring.

8A and 8B, the first row decoder DEC1 and the second row decoder DEC2 may be disposed on the other side of the memory cell array area to face each other. The first row decoder DEC1 controls the first word line WLi_1 and the second word line WLi_2 in common, and the second row decoder DEC2 controls the third word line WLi_3.

The first word line WLi_1 and the second word line WLi_2 are commonly connected to the first row decoder DEC1 by the first wiring, and the third word line WLi_3 is connected to the second row by the second wiring. It may be connected to the decoder DEC2. The first wiring includes a first word line contact 412 that contacts the first word line WLi_1 and the second word line WLi_2, and a first metal pattern connected to the first word line contact 412. 414, and a first decoder contact 416 connecting the first metal pattern to the first row decoder. The first word line contact 412 may contact the first word line WLi_1 through the second word line WLi_2. The second wiring may include a third word line contact 432 contacting the third word line WLi_3, a third metal pattern 434 connected to the third word line contact 432, and the third metal. It may include a third decoder contact 436 connecting the pattern and the second row decoder DEC2. The first row decoder DEC1 may control the first word line WLi_1 and the second word line WLi_2 in common. The first word line line contact 412 may be disposed at one side of the cell array region adjacent to the first row decoder region. The third word line line contact 432 may be disposed on the other side of the cell array region adjacent to the second row decoder region. In order to facilitate wiring, the first metal pattern 414 and the third metal pattern 434 may be disposed on substantially the same plane in the third semiconductor layer 302.

9A and 9B, the first row decoder DEC1 and the second row decoder DEC2 may be disposed on the other side of the memory cell array area to face each other. The first row decoder DEC1 controls the first word line WLi_1, and the second row decoder DEC2 controls the second word line WLi_2 and the third word line WLi_3 in common.

The first word line WLi_1 is connected to the first row decoder DEC1 by the first wiring, and the second word line WLi_2 and the third word line WLi_3 are connected to the second row decoder DE by the second wiring. May be commonly connected to DEC2). The first wiring may include a first word line contact 412 contacting the first word line WLi_1, a first metal pattern 414 connected to the word line contact 412, and the first metal pattern. And a first decoder contact 416 connecting the first row decoder. The second wiring may include a second word line contact 422 contacting the second word line WLi_2 and a third word line WLi_3 and a second metal pattern connected to the second word line contact 422. 424) and a second decoder contact 426 connecting the second metal pattern to the second row decoder. The second word line contact 422 may contact the second word line WLi_2 through the third word line WLi_3. The second row decoder DEC2 may control the second word line WLi_2 and the third word line WLi_3 in common. The first word line line contact 412 may be disposed at one side of the cell array region adjacent to the first row decoder region. The second word line line contact 422 may be disposed on the other side of the cell array region adjacent to the second row decoder region. In order to facilitate wiring, the first metal pattern 414 and the second metal pattern 424 may be disposed on substantially the same plane on the third semiconductor layer 302.

In the following, modifications of the method of connecting the word lines of each semiconductor layer to the row decoder, for example, in the case where the number of the semiconductor layers is 2 are described.

For convenience of discussion, the first row decoder DEC1 may be an odd first row decoder DEC1_odd that controls an odd first word line WLodd_1, and an even first word line. It can be understood to include an even first row decoder DEC1_even for controlling WLeven_1, and the second row decoder DEC2 is an odd number for controlling an odd-numbered second word line WLodd_2. It may be understood that a second row decoder DEC2_odd and an even second row decoder DEC2_even that control the even-numbered second word line WLeven_2 are provided. The odd first word line WLodd_1 may be WLi_1 (i = 0, 2, 4,..., 15), and the even-numbered first word line WLeven_1 may be WLi_1 (i = 1, 3). , 5, ...., 14). The odd first row decoder and the even first row decoder are provided on opposite sides of the cell array region to face each other, and the odd second row decoder and the even second row decoder of the cell array region face each other. It may be provided on the opposite side.

10A and 10B, the even first row decoder DEC1_even and the even second row decoder DEC2_even are disposed on one side of the cell array region, and the odd first row decoder DEC1_odd and the odd number agent are formed on one side of the cell array region. The second row decoder DEC2_odd may be provided on the other side of the cell array region.

The even first word line WLeven_1 is connected to the even first row decoder DEC1_even by an even first wiring, and the even second word line WLeven_2 is even even second wiring. It may be connected to the even second row decoder DEC2_even. The odd first word line WLodd_1 is connected to the odd first row decoder DEC1_odd by an odd first wiring, and the odd second word line WLodd_2 is an odd second wiring. May be connected to the odd second row decoder DEC2_odd.

The even first wiring may include an even first word line contact 412e contacting the even first word line WLeven_1, an even first metal pattern 414e connected to the even first word line contact 412e, And an even first decoder contact 416e connecting the even first metal pattern 414e and the even first row decoder DEC1_even. The even second wiring may include an even second word line contact 422e in contact with the even second word line WLeven_2, an even second metal pattern 424e connected to the even second word line contact 422e, And an even second decoder contact 426e connecting the even second metal pattern 424e and the even second low decoder DEC2_even. The odd first wire may include an odd first word line contact 412o contacting the odd first word line WLodd_1, an odd first metal pattern 414o connected to the odd first word line contact 412o, And an odd first decoder contact 416o connecting the odd first metal pattern 414o and the odd first row decoder DEC1_odd. The odd second wiring may include an odd second word line contact 422o contacting the odd second word line WLodd_2, an odd second metal pattern 424o connected to the odd second word line contact 422o, And an odd second decoder contact 426o connecting the odd second metal pattern 424o and the odd second row decoder DEC2_odd. The even first word line line contact 412e and the even second word line line contact 422e may be disposed at one side of the cell array region. The odd first word line line contact 412o and the odd second word line line contact 422o may be disposed at the other side of the cell array region.

11A and 11B, similar to FIGS. 10A and 10B, the even first row decoder and the even second row decoder may include the odd first row decoder and the odd agent on one side of the cell array region. A two row decoder may be provided on the other side of the cell array region. However, both the first word line and the second word line are commonly controlled by one row decoder.

The even first word line WLeven_1 and the even second word line WLeven_2 may be commonly connected to the even row decoder DEC_even by an even wiring. The odd first word line WLodd_1 and the odd second word line WLodd_2 may be commonly connected to the odd row decoder DEC_odd by odd wiring.

The even wiring is an even word line contact 412e contacting the even first word line WLeven_1 and the even second word line WLeven_2 and an even metal pattern 414e connected to the even word line contact 412e. And an even decoder contact 416e connecting the even metal pattern 414e and the even row decoder DEC_even. The odd-numbered wiring may include an odd word line contact 412o contacting the odd first word line WLodd_1 and the odd second word line WLodd_2, and an odd metal pattern 414o connected to the odd word line contact 412o. And an odd decoder contact 416o connecting the odd metal pattern 414o and the even odd row decoder DEC_odd. The even word line line contact 412e may be disposed at one side of the cell array region. The odd word line line contact 412o may be disposed on the other side of the cell array region.

12A and 12B, the even first row decoder and the odd second row decoder are located at one side of the cell array region, and the odd first row decoder and the even second row decoder are arranged in the cell array region. It may be provided on the other side.

The even first word line WLeven_1 is connected to the even first row decoder DEC1_even by an even first wiring, and the even second word line WLeven_2 is even even second wiring. It may be connected to the even second row decoder DEC2_even. The odd first word line WLodd_1 is connected to the odd first row decoder DEC1_odd by an odd first odd wiring, and the odd second word line WLodd_2 is an odd second wiring. ) May be connected to the odd second row decoder DEC2_odd.

The even first wiring may include an even first word line contact 412e contacting the even first word line WLeven_1, an even first metal pattern 414e connected to the even first word line contact 412e, And an even first decoder contact 416e connecting the even first metal pattern 414e and the even first row decoder DEC1_even. The even second wiring may include an even second word line contact 422e in contact with the even second word line WLeven_2, an even second metal pattern 424e connected to the even second word line contact 422e, And an even second decoder contact 426e connecting the even second metal pattern 424e and the even second row decoder DEC2_even. The odd first wire may include an odd first word line contact 412o contacting the odd first word line WLodd_1, an odd first metal pattern 414o connected to the odd first word line contact 412o, And an odd first decoder contact 416o connecting the odd first metal pattern 414o and the odd first row decoder DEC1_odd. The odd second wiring may include an odd second word line contact 422o contacting the odd second word line WLodd_2, an odd second metal pattern 424o connected to the odd second word line contact 422o, And an odd second decoder contact 426o connecting the odd second metal pattern 424o and the odd second row decoder DEC2_odd. The even first word line line contact 412e and the odd second word line line contact 422o may be disposed at one side of the cell array region. The odd first word line line contact 412o and the even second word line line contact 422e may be disposed on the other side of the cell array region.

13A and 13B, the odd first row decoder DEC1_odd and the even first row decoder DEC1_even are provided on opposite sides of the cell array region to face each other, and the odd second row decoder DEC2_odd ) And the even second row decoder DEC2_even may be provided on the same side of the cell array region.

The even first word line WLeven_1 is connected to the even first row decoder DEC1_even by an even first wiring, and the odd first word line WLodd_1 is an odd first wiring. Is connected to the odd first row decoder DEC1_odd. The second word line WLi_2 may be connected to the second row decoder DEC2 by a second wiring.

The even first wiring may include an even first word line contact 412e contacting the even first word line WLeven_1, an even first metal pattern 414e connected to the even first word line contact 412e, And an even first decoder contact 416e connecting the even first metal pattern 414e and the even first row decoder DEC1_even. The odd first wire may include an odd first word line contact 412o contacting the odd first word line WLodd_1, an odd first metal pattern 414o connected to the odd first word line contact 412o, And an odd first decoder contact 416o connecting the odd first metal pattern 414o and the odd first row decoder DEC1_odd. The second wiring may include a second word line contact 422 contacting the second word line WLi_2, a second metal pattern 424 connected to the second word line contact 422, and the second metal. A second decoder contact 426 connecting the pattern 424 and the second row decoder DEC2 may be included. The even first word line line contact 412e may be disposed at one side of the cell array region. The odd first word line line contact 412o may be disposed on the other side of the cell array region. The second word line line contact 422 may be disposed on any one of the one side or the other side of the cell array region.

14A and 14B, the odd first row decoder DEC1_odd and the even first row decoder DEC1_even are provided on the same side of the cell array area, and the odd second row decoder DEC2_odd The even second row decoder DEC2_even may be provided on an opposite side of the cell array region to face each other.

The first word line WLi_1 may be connected to the first row decoder DEC1 by a first wiring. The even second word line WLeven_2 is connected to the even second row decoder DEC2_even by an even second wiring, and the odd second word line WLodd_2 is an odd second wiring. Is connected to the odd second row decoder DEC2_odd.

The first wiring may include a first word line contact 412 contacting the first word line WLi_1, a first metal pattern 414 connected to the first word line contact 412, and the first metal. A first decoder contact 416 connecting the pattern 414 and the first row decoder DEC1 may be included. The even second wiring may include an even first word line contact 422e contacting the even second word line WLeven_2, an even second metal pattern 424e connected to the even second wordline contact 422e, And an even second decoder contact 426e connecting the even second metal pattern 424e and the even second row decoder DEC2_even. The odd second wiring may include an odd second word line contact 422o contacting the odd second word line WLodd_2, an odd second metal pattern 424o connected to the odd second word line contact 422o, And an odd second decoder contact 426o connecting the odd second metal pattern 424o and the odd second row decoder DEC2_odd. The even second word line line contact 422e may be disposed at one side of the cell array region. The odd second word line line contact 422o may be disposed on the other side of the cell array region. The first word line line contact 412 may be disposed on one side or the other side of the cell array region.

In the case where the number of semiconductor layers is two, examples of applying the embodiment of the present invention are shown with reference to FIGS. 15, 16, and 17.

FIG. 15 illustrates that the region A and the region B of FIG. 2 are arranged side by side adjacent to each other. Referring to FIG. 15, the region A includes a cell array region A and a row decoder region A adjacent thereto. The cell array region A includes a first cell block 100 having a first gate line WLi_1 in the first layer, and a second gate line WLi_2 in the second layer on the first layer. A second cell block 200 is included, and the row decoder region A includes a first row decoder DEC1 for controlling a first gate line and a second row decoder DEC2 for controlling a second gate line. The region B includes a cell array region B and a row decoder region B adjacent thereto. The cell array region B includes a third cell block 300 having a third gate line WLi_1 in the first layer, and a fourth gate line WLi_2 in the second layer on the first layer. A fourth cell block 400 is included, and the row decoder region B includes a third row decoder DEC1 for controlling a third gate line and a fourth row decoder DEC2 for controlling a fourth gate line. The cell array region B may be spaced apart from the cell array region A by the row decoder region A and the row decoder region B. FIG.

FIG. 16 illustrates that the region C of FIG. 6 and the region D having a structure symmetric with the region C are arranged adjacent to each other side by side. Referring to FIG. 16, the area C includes a cell array area C and row decoder C1 and row decoder C2 at both sides thereof. The cell array region C includes a first cell block 100 having a first gate line WLi_1 in the first layer, and a second gate line WLi_2 in the second layer on the first layer. The second cell block 200 is included. The row decoder C1 includes a first row decoder DEC1 for controlling the first gate line, and the row decoder C2 includes a second row decoder DEC2 for controlling the second gate line. The area D includes a cell array area D and row decoder D1 and row decoder D2 at both sides thereof. The cell array region D includes a third cell block 300 having a third gate line WLi_1 in the first layer, and a fourth gate line WLi_2 in the second layer on the first layer. Fourth cell block 400 is included. The row decoder D1 includes a second row decoder DEC2 for controlling the second gate line, and the row decoder D2 includes a first row decoder DEC1 for controlling the first gate line.

It may be understood that the row decoder C2 and the row decoder D1 are adjacent to each other, and the row decoder C1 and the row decoder D2 are disposed adjacent to each other. The cell array region D may be spaced apart from the cell array region C by the row decoder C1 and the row decoder D2. Other cell array regions not shown may be understood to be spaced apart from the cell array region C or the cell array region D by the row decoder C2 and the row decoder D1.

FIG. 17 shows that region C of FIG. 6 is repeatedly arranged. Referring to FIG. 17, the region C includes a cell array region C and the row decoder C1 and the row decoder C2 at both sides thereof.

The embodiments described above with reference to the drawings may be capable of their own construction as well as their combined construction.

Referring to FIG. 18, an electronic device 500 including a semiconductor device according to embodiments of the present disclosure is described. The electronic device 500 may be a wireless communication device such as a PDA, a laptop computer, a portable computer, a web tablet, a cordless phone, a mobile phone, a digital music player, or wireless information. It can be used for any device that can transmit and / or receive in the environment.

The electronic device 500 may include a controller 510, an input / output device 520, a memory 530, and a wireless interface 540 coupled to each other through a bus 550. The controller 510 may include, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. The input / output device 520 may include, for example, a keypad, a keyboard, and a display. The memory 530 may be used, for example, to store instructions executed by the controller 510. The memory 530 may be used to store user data. The memory 530 may include a semiconductor device having a three-dimensional array structure according to embodiments of the present invention. The memory 530 may further include other types of memory, volatile memory that can be accessed at any time, and various other types of memory.

The electronic device 500 may use the wireless interface 540 to transmit data to or receive data from a wireless communication network that communicates with an RF signal. For example, the wireless interface 540 may include an antenna, a wireless transceiver, and the like.

The electronic device 500 according to embodiments of the present invention may be used in a communication interface protocol such as a third generation communication system such as CDMA, GSM, NADC, E-TDMA, WCDAM, and CDMA2000.

According to an embodiment of the present invention, word lines of a plurality of layers may be easily processed according to the arrangement of the row decoders. By the row decoders disposed at both sides of the cell array region, the margins of the metal contact and the metal wiring can be sufficiently secured, and the metal contact or / and the metal wiring can be simultaneously formed. In addition, since one row decoder shares several word lines, the chip area can be reduced.

Accordingly, the nonvolatile memory device can be formed in a stacked structure and the limitation of scale down can be overcome.

Claims (39)

A cell array region comprising a first cell block having a first gate line in a first layer and a second cell block having a second gate line in a second layer on the first layer; A row decoder region adjacent the cell array region and including a first row decoder controlling the first gate line and a second row decoder controlling the second gate line; A first wiring connecting the first gate line and the first row decoder; And And a second wiring connecting the second gate line and the second row decoder. The method according to claim 1, And the first row decoder and the second row decoder are provided at one side of the cell array region. The method according to claim 2, The first wiring is: A first gate line contact in contact with the first gate line; And A first metal pattern on the second layer, the first metal pattern being connected to the first gate line contact; The second wiring is: A second gate line contact in contact with the second gate line; And And a second metal pattern on the second layer, the second metal pattern being connected to the second gate line contact. The method according to claim 3, And a bit line provided on the second layer at the same height as the first metal pattern or the second metal pattern. The method according to claim 3, And the first gate line contact and the second gate line contact are disposed on the one side of the cell array region. The method according to claim 3, The second metal pattern is provided on the first metal pattern. The method according to claim 3, The cell array region further comprises a third cell block having a third gate line in a third layer on the second layer, And the third gate line is connected to the second decoder through the second gate line contact. The method according to claim 3, The cell array region further includes a third cell block having a third gate line at a third layer on the second layer, and the row decoder region further includes a third row decoder to control the third gate line. and, And the third row decoder is provided on the other side of the cell array region to face the first row decoder and the second row decoder. The method according to claim 8, Further comprising a third wiring connecting the third gate line and the third row decoder, The third wiring is: A third gate line contact in contact with the third gate line; And And a third metal pattern on the third layer, the third metal pattern being connected to the third gate line contact. The method according to claim 9, And the third gate line contact is disposed on the other side of the cell array region. The method according to claim 2, A third cell block spaced from the cell array region by the row decoder region, the third cell block having a third gate line in the first layer and a fourth gate line in the second layer on the first layer And a further cell array region comprising four cell blocks. The method according to claim 11, The row decoder region may further include a third row decoder for controlling the third gate line, and a fourth row decoder for controlling the fourth gate line, wherein the third row decoder and the fourth row decoder are configured as the third row decoder. And a semiconductor device arranged at one side of the cell array region. The method according to claim 1, And the first row decoder and the second row decoder are provided on opposite sides of the cell array region to face each other. The method according to claim 13, The first wiring is: A first gate line contact in direct contact with the first gate line; And A first metal pattern on the second layer, the first metal pattern being connected to the first gate line contact; The second wiring is: A second gate line contact in direct contact with the second gate line; And And a second metal pattern on the second layer, the second metal pattern being connected to the second gate line contact. The method according to claim 14, And the first gate line contact and the second gate line contact are disposed on opposite sides of the cell array region to face each other. The method according to claim 14, The first metal pattern and the second metal pattern are provided at the same height. The method according to claim 16, And a bit line provided on the second layer at the same height as the first metal pattern and the second metal pattern. The method according to claim 14, The cell array region further comprises a third cell block having a third gate line in a third layer on the second layer, And the third gate line is connected to the second row decoder through the second gate line contact. The method according to claim 13, A third cell block spaced apart from the cell array region by the first row decoder and the second row decoder, each having a third gate line in the first layer, and the second layer on the first layer And other cell array regions including a fourth cell block having a fourth gate line in the semiconductor device. The method according to claim 19, The row decoder region further includes a third row decoder adjacent to the first row decoder and a fourth row decoder adjacent to the second row decoder, wherein the third row decoder is another cell array adjacent to the third row decoder. And control the third gate line of a region, and wherein the fourth row decoder controls the fourth gate line of another cell array region adjacent to the fourth row decoder. The method according to claim 1, The first row decoder includes an odd first row decoder controlling an odd first gate line, and an even first row decoder controlling an even first gate line, The second row decoder includes an odd second row decoder controlling an odd second gate line, and an even second row decoder controlling an even second gate line. The method according to claim 21, The odd first row decoder and the even first row decoder are provided at both sides of the cell array region to face each other, and the odd second row decoder and the even second row decoder are at both sides of the cell array region facing each other. A semiconductor device provided in the. The method according to claim 22, And the even first row decoder and the odd second row decoder are provided at one side of the cell array region, and the odd first row decoder and the even second row decoder are provided at the other side of the cell array region. The method according to claim 22, And the even first row decoder and the even second row decoder are provided at one side of the cell array region, and the odd first row decoder and the odd second row decoder are provided at the other side of the cell array region. The method according to claim 21, The odd first row decoder and the even first row decoder are provided on both sides of the cell array region to face each other, and the odd second row decoder and the even second row decoder are provided on the same side of the cell array region. Semiconductor device. The method according to claim 21, The odd first row decoder and the even first row decoder are provided on the same side of the cell array region, and the odd second row decoder and the even second row decoder are provided on both sides of the cell array region facing each other. Semiconductor device. The method according to claim 1, And the first row decoder and the second row decoder are provided in the first layer. The method according to claim 1, And the first row decoder is provided to the first layer, and the second row decoder is provided to the second layer. The method according to claim 1, And the number of the first gate lines and the number of the second gate lines are the same as the number of the first row decoder outputs and the number of the second row decoder outputs, respectively. The method according to claim 1, And the first gate line and the second gate line are select lines or word lines of a NAND flash device. The method according to claim 1, Wherein said first layer is a silicon substrate and said second layer is a semiconductor layer formed by selective epitaxy techniques. A cell array region including a cell block having a gate line; A row decoder adjacent to the cell array region and controlling the gate line; A wiring connecting the gate line and the row decoder, The row decoder includes an odd row decoder controlling an odd gate line, and an even row decoder controlling an even gate line, And the odd row decoder and the even row decoder are provided on opposite sides of the cell array region to face each other. A cell array region comprising a first cell block having a first gate line in a first layer and a second cell block having a second gate line in a second layer on the first layer; Wirings commonly connected to the first gate line and the second gate line; And And a row decoder adjacent to the cell array region and simultaneously selecting and controlling the first gate line and the second gate line through the wiring. The method according to claim 33, The wiring is: A gate line contact in contact with the first gate line and the second gate line; And A metal pattern connected to the gate line contact on the second layer, And the gate line contact penetrates through the second gate line. The method according to claim 33, The row decoder is provided on one side of the cell array region. The method according to claim 33, The cell array region further comprises a third cell block having a third gate line in a third layer on the second layer, The semiconductor device further includes another row decoder controlling the third gate line, and a third wiring connecting the third gate line and the other row decoder. The method of claim 36, And the row decoder and the other row decoder are provided on opposite sides of the cell array region to face each other. The method of claim 36, And the row decoder and the other row decoder are provided on the same side of the cell array region. The method according to claim 33, The row decoder includes an odd row decoder that controls odd first gate lines and an odd second gate line, and an even row decoder that controls even first gate lines and even second gate lines. and, And the odd row decoder is provided at one side of the cell array region, and the even row decoder is provided at the other side of the cell array region.

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