KR20090127007A - Non-volatile memory device comprising shared bit line and method of fabricating the same memory device - Google Patents

Abstract

PURPOSE: A nonvolatile memory device comprising a shared bit line and a method for fabricating the memory device are provided to minimize interference between bit lines, by forming the shared bit line. CONSTITUTION: A field region(110) is formed on a substrate along a first direction, and comprises a first field formed in a body and a second field separated into two small areas by a bridge. An active area(101) is formed on the substrate, and is confined to a string structure by the field region. The active region has at least two string structures connected by the bridge. A shared bit line(190) is formed on the top of the field region along a first direction, and is connected to the bridge through a bit line contact(direct contact:DC).

Description

Non-volatile memory device comprising shared bit line and method of fabricating the same memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a nonvolatile memory device and a method for manufacturing the same, which are advantageous for high integration.

A flash memory device, which is a nonvolatile memory device, is a memory device that has excellent portability and impact resistance, and is electrically programmable and erased, and has recently been used in portable information devices such as portable PCs and mobile phones. The demand for memory devices is increasing rapidly. On the other hand, in order to develop a large-capacity memory device capable of storing a large amount of data, research on high integration technology of the memory device has been actively conducted. Accordingly, a flash memory device has been proposed in which 16 or 32 memory cells are connected in series to form one string for high integration of the memory device.

On the other hand, as the pitch of the device is reduced in the flash memory device due to the high integration, it is difficult to form a contact between the string active and the bit line. That is, within a small device pitch, a very precise alignment process is required in order to form a contact between the string active and the bit line, and defects such as adjacent bit lines and shorts often occur after formation.

In addition, when forming 1string / 1bit-line at a very small device pitch, a double patterning technology (DPT) process is performed to form a bitline aligned with string active, which is also one of the very difficult processes.

Furthermore, as the bit line spacing narrows as the device pitch decreases, parasitic capacitances C _{BL - to - BL} generated between the bit lines increase, leading to a problem of deterioration in performance of the device. For example, since the read time t _read of the memory increases in proportion to the resistance and the capacitance, the read time may be shortened by reducing the resistance and the capacitance. If only capacitance is considered here, the capacitance is proportional to the surface area of the bit lines and inversely proportional to the distance between the bit lines. Therefore, as the distance between the bit lines decreases, the capacitance increases. Therefore, it is necessary to solve the parasitic capacitance increase problem caused by narrowing the bit line spacing due to the device pitch reduction. In addition, a method of reducing the resistance between the bit line contact and the active should be studied.

Accordingly, an object of the present invention is to solve the problem of increasing the parasitic capacitance while facilitating the bit line and contact process, thereby reducing the process cost and improving the performance of the device, and a manufacturing method thereof. To provide.

In order to achieve the above object, the present invention is a substrate; A field region formed in the first direction on the substrate, the field region having a first field formed integrally with the second field divided into two small regions by a bridge; An active region formed on the substrate and defined by the field region in a string structure, wherein at least two of the string structures are connected to each other through the bridge; And a shared bit line formed on the field region in the first direction and connected to the bridge through a bit line direct contact (DC). Provided is a memory device.

In the present invention, a word line is formed in a second direction perpendicular to the first direction across the active area and the field area, and the bridge is disposed along the second direction. It may be arranged in a straight line form or zigzag form.

The bit line contact may be formed to contact at least one small region of two adjacent small regions. Furthermore, the active portion of the bridge portion may have a convex structure in at least one of two adjacent first fields and two small regions.

Typically, in the nonvolatile memory device of the present invention, the first field and the second field are alternately arranged, and the active region may allow the two string structures to be connected to each other through the bridge.

In order to achieve the above object, the present invention also provides a field region having a second field formed in a first direction on a substrate, and divided into two small regions by an integrally formed first field and a bridge region. Forming a; Growing a tunnel oxide film on an active region defined by the field region and concatenated by the bridge region, wherein at least two string structures are connected to each other; Forming a bitline contact over the bridge region; And forming a shared bit line connected to the bit line contact on the field region in the first direction.

In the present invention, the forming of the field region may include stacking different first, second, and third insulating layers on a substrate, and etching the second and third insulating layers through a double patterning technology (DPT) process. Making; Depositing a first oxide film over the entire surface of the resultant on the substrate and planarizing the second insulating film through a CMP process; A photo mask pattern is formed on the first oxide layer, and a trench is formed by etching a predetermined portion of the substrate using the second insulating layer and the photo mask pattern, and the photo mask pattern is removed to remove the photo mask pattern. Forming a bridge region under the first oxide film; Depositing a second oxide film over the entire surface of the resultant on the substrate and planarizing the second insulating film to expose the second insulating film through a CMP process, thereby forming a field region in the first direction. The first oxide layer and the second insulating layer may be removed using a second oxide layer as a mask to expose an active region on the substrate, and a tunnel oxide layer may be grown on the active region.

The method of claim 1, further comprising: forming a word line in a second direction perpendicular to the first direction crossing the active area and the field area, before the forming of the bit line contact, wherein the photo mask pattern comprises: Arranged along the second direction, it may be arranged in a straight line form or zigzag form.

The bit line contact may be formed to contact at least one small region of two adjacent small regions. Furthermore, the active of the bridge region may have a convex structure in at least one of two adjacent first fields and two small regions.

On the other hand, the shared bit line can be easily formed through the Cu damascene process.

Furthermore, the present invention provides a memory card including the nonvolatile memory device; and a controller for controlling the nonvolatile memory device and exchanging data with the nonvolatile memory device.

On the other hand, the present invention to achieve the above object, the non-volatile memory device; and a processor for communicating with the non-volatile memory device via a bus; And an input / output device communicating with the bus.

The nonvolatile memory device and the method of manufacturing the same according to the present invention form a shared bit line, thereby minimizing interference between bit lines, and do not need to perform a complicated DPT process on the bit lines.

In addition, by forming a bit line contact on the shared bit line through the bridge region, the contact process may be performed very easily. For example, tungsten gap fill may be easily performed when forming a contact through securing a pitch between relatively wide bit lines.

Furthermore, due to the wide beach between the shared bit line, the copper (Cu) damascene process can be easily applied when forming the shared bit line.

Due to the above advantages, the nonvolatile memory device of the present invention and its manufacturing method can reduce the process cost and can significantly improve the performance of the device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, when a component is described as being on top of another component, it may be directly on top of another component, and a third component may be interposed therebetween. In addition, in the drawings, the thickness or size of each component is exaggerated for convenience and clarity of description, and parts irrelevant to the description are omitted. Like numbers refer to like elements in the figures. On the other hand, the terms used are used only for the purpose of illustrating the present invention and are not used to limit the scope of the invention described in the meaning or claims.

1 is a block diagram of a nonvolatile memory according to an embodiment of the present invention.

Referring to FIG. 1, a nonvolatile memory includes a memory cell array 10, a page buffer 20, a Y-gating circuitry 30, and a control and decoder circuit. Decoder Circuitry 40 may be provided.

The memory cell array 10 may include a plurality of memory blocks, and each of the memory blocks may include a plurality of nonvolatile memory cells. The nonvolatile memory cells may be flash memory cells, and may further be NAND flash memory cells or NOR flash memory cells. The page buffer 20 may temporarily store data to be written to the memory cell array 10 or data read from the memory cell array 10. The Y-gating circuit 30 may transmit data stored in the page buffer 20.

The control and decoder circuit 40 receives a command (CMD) and an address from the outside, and writes data to or reads data from the memory cell array 10. May be output and the address may be decoded. The control and decoder circuit 40 may output a control signal for data input / output to the page buffer 20 and provide address information to the Y-gating circuit 30.

FIG. 2 is a layout diagram illustrating a portion of a memory cell array of a nonvolatile memory according to an embodiment of the present invention, and may represent a portion of the memory cell array 10 described with reference to FIG. 1. 3A-3D are cross-sectional views taken along cut lines I-I ', II-II', III-III 'and IV-IV' of FIG. 2, respectively.

2 and 3A through 3D, the memory cell array 10 may include a plurality of active regions Act defined by the field regions 110 formed in the semiconductor layer 100. The semiconductor layer 100 may include a substrate and / or an epitaxial layer, a silicon on insulator (SOI) layer, or the like. The active regions Act may be parallel to each other in a line shape, and are generally referred to as string actives or strings.

A string selection line SSL and a ground selection line GSL crossing the active regions Act may be positioned above the active regions Act. A plurality of word lines WL ₁ , WL ₂ ,..., WL _{n −1} crossing the upper portion of the active regions Act between the string select line SSL and the ground select line GSL. , WL _n ) may be disposed. The string select line SSL, the ground select line GSL, and the word lines WL ₁ , WL ₂ ,..., WL _{n −1} , WL _n may be parallel to each other. Impurity regions are formed in active regions adjacent to both sides of the word lines WL ₁ , WL ₂ ,..., WL _{n −1} , WL _n , the string select line SSL, and the ground select line GSL. 101 may be formed respectively.

As a result, string select transistors, cell transistors, and ground select transistors connected in series are formed. The string select transistor, the ground select transistor, and cell transistors disposed therebetween may constitute one unit memory block. Impurity regions 101 adjacent to the string select line SSL and opposite to the ground select line GSL may be defined as drain regions of respective string select transistors. In addition, the impurity regions 101 adjacent to the ground select line GSL and opposite to the string select line SSL may be defined as source regions of the ground select transistor.

Each of the word lines WL ₁ , WL ₂ ,..., WL _{n −1} , WL _n is a tunneling insulating layer 131 and a charge storage layer sequentially stacked on the semiconductor layer 100. A layer 133, a blocking insulating layer 135, and a cell gate conductive layer 141 may be included. In addition, although not shown, each of the word lines WL ₁ , WL ₂ ,..., WL _{n −1} , WL _n may be formed on the cell gate conductive layer 141 and / or a cell barrier conductive layer. Alternatively, a word line conductive film may be further provided.

The tunneling insulating layer 131 and the charge storage layer 133 may be separated for each cell transistor adjacent in the direction of the word lines WL ₁ , WL ₂ ,..., WL _{n −1} , WL _n . In this case, the top surface of the field region 110 and the top surface of the charge storage layer 133 may have substantially the same level. The tunneling insulating layer 131 may be a silicon oxide layer. The charge storage layer 133 may be a charge trap layer or a floating gate conductive layer. The blocking insulating layer 135 may be shared by cell transistors adjacent in the direction of the word lines WL ₁ , WL ₂ ,..., WL _n-1 , and WL _n . Spacers 150 may be disposed on sidewalls of the tunneling insulating layer 131 and the charge storage layer 133, the blocking insulating layer 135, and the cell gate conductive layer 141. The spacer 150 may be composed of multiple layers.

Spacers 150 may be disposed on sidewalls of the tunneling insulating layer 131 and the charge storage layer 133, the blocking insulating layer 135, and the cell gate conductive layer 141. The spacer 150 may be composed of multiple layers.

As described above, the string select line SSL and the ground select line GSL may have the same stacked structure as the word lines WL ₁ , WL ₂ ,..., WL _{n −1} , WL _n . In general, the widths of the string select line SSL and the ground select line GSL may be larger than the widths of the word lines WL ₁ , WL ₂ ,..., WL _{n −1} , WL _n . However, this is exemplary and the present invention is not necessarily limited thereto.

A first interlayer insulating layer 160 is provided to cover word lines WL ₁ , WL ₂ ,..., WL _{n −1} , WL _n , a string select line SSL, and a ground select line GSL. A common source line CSL is provided to penetrate the first interlayer insulating layer 160 and to be connected to the source region of the ground select line GSL. The common source line CSL may be formed in parallel with the ground select line GSL. The second interlayer insulating layer 170 may be provided on the first interlayer insulating layer 160.

A shared bit line contact (SBC) that penetrates the second interlayer insulating layer 170 and the first interlayer insulating layer 160 and connects to the drain region of the string select line SSL may be provided. Shared bit lines across the top of the word lines WL ₁ , WL ₂ ,..., WL _{n −1} , WL _n while connecting to the shared bit line contact SBC on the second interlayer insulating layer 170. (BL ₁ , ..., BL _{2n -1} ) may be arranged. The shared bit lines BL ₁ ,..., BL _2n-1 may not be disposed above the active regions Act, but may be disposed in parallel to the field region 110, and the number thereof may be parallel to the number of the active regions Act. It corresponds to 1/2 of the word line. More detailed descriptions of the shared bit lines BL ₁ ,..., BL _{2n- 1} and the shared bit line contacts SBC are provided below with reference to FIG. 4A.

4A to 4H are layout views of various bridge regions and SBCs according to an embodiment of the present invention, and schematically illustrate only portions where shared bit lines and shared bit line contacts are disposed in a cell region.

Referring to FIG. 4A, the active region 101 and the field region 110 in the form of lines are also shown on the present substrate, and the field region 110 is divided into two types, one of which is the first field 110a integrally formed. And the other is the second field 110b divided into two small regions by the bridge region A. FIG.

Meanwhile, the shared bit line 190 passes through the second field region 110b of the field region 110. Therefore, the number of bit lines is reduced by half than when one bit line per string of the conventional active region 101 passes. On the other hand, since the pitch between the fields on which the shared bit line 190 is formed is three times higher than in the related art, even if the width of the shared bit line 190 is significantly increased, the interference problem between the shared bit lines 190 does not occur.

The bridge region A may be formed anywhere in the second field, and the shared bitline contact 180 may be formed in this portion. The shared bit line contact 180 is also very easy to form because the active region including the bridge region A is wide. In addition, the shape can also be formed in a variety of course. In addition, the arrangement of the shared bit line contact 180 may be located in another position, that is, in a zigzag form, as shown in this figure, but may also be located in a straight line. However, it is advantageous to arrange the margin between the shared bit line contacts 180 in a zigzag form rather than being disposed in a straight line. The location of the shared bit line contact 180 depends on where the bridge region A is formed, which will be described below with reference to FIG. 5A.

Meanwhile, the second field 110b is divided into two small regions by the bridge region A. The bridge region A may be configured in two forms. One of the structures may be a structure in which a tunnel oxide layer is grown as an active phase by exposing active during a process. The other may have a structure in which an oxide film such as an oxide film in a field region is thinly formed on the active phase without the active being exposed. The first structure is preferable because the patterning process is required once more to expose the active area of the bridge.

On the other hand, 200 denoted by a dotted line is SSL, which is formed on both the upper and lower sides where the shared bit line contact is formed. That is, in the nonvolatile memory device of this embodiment, the structure of the cell region has a symmetrical structure with respect to the shared bit line contact, and substantial memory cells are formed in which word lines are formed under the lower SSL and the upper SSL.

FIG. 4B is identical to FIG. 4A except that the bridge region and the shared bitline contacts 180 are formed in a straight line along the SSL 200.

4C shows that the shared bitline contact 180a may be formed longer to span both small regions of the peripheral second field 110b instead of being formed only in the bridge region. Of course, it can be formed to cover either one.

FIG. 4D is the same as FIG. 4C except that the bridge region and shared bitline contact 180a are formed in a straight line along the SSL 200.

FIG. 4E extends in the direction of four adjacent fields of the bridge area B, namely, two small areas of the second field 110b positioned up and down, and two first fields 110a on both the left and right sides, and in the field direction. It has a convex form. The active form of the bridge region B may be formed through intentional patterning during the bridge region B forming process, or may be formed by the degree of etching during the etching process. As such, when the bridge region B is formed to be wide, a wider space for forming the shared bit line contact 180 can be secured, thereby providing an advantage of making the contact process easier.

Unlike FIG. 4E, FIG. 4F is formed to have a convex shape only in the direction of the second field 110b in which the active portion of the bridge region C is positioned up and down.

4G is the same as FIG. 4F except that the bridge region C and the shared bitline contact 180 are formed in a straight line along the SSL 200.

4H has a structure in which the bridge region D is formed similarly to FIG. 4E, but the shared bit line contact 180b is formed left to right and not up and down.

Although the forms of shared bitline contacts formed of various types of bridge regions have been illustrated so far, the bridge regions and shared bitline contacts are not limited to such structures or arrangements. For example, the active of the bridge region may be formed convexly in at least one direction of four adjacent fields. In addition, the convexly formed bridge region may be formed to have a long length so that the shared bit line contact may cover the field as shown in FIG. 4C or 4D. On the other hand, when the active of the bridge region is formed convexly to the left and right field regions, it is preferable to form the zigzag rather than forming the bridge region in a straight line.

Forming a wider bridge area to broaden the active can form a large shared bitline contact, which facilitates the contact process, but also reduces resistance by widening the contact area with the active contacting the lower side or the shared bitline touching the upper side. There are also advantages of the side. On the other hand, the shared bit line and the shared bit line contact of the present embodiment can be applied to all kinds of nonvolatile memory devices, such as NAND flash and NOR flash.

5A through 5N are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a shared bit line according to an embodiment of the present invention, and FIGS. 6A through 6E illustrate FIGS. 5I, 5J, 5K, 5M, and Each plan view corresponds to FIG. 5N.

First, referring to FIG. 5A, the first insulating film 210, the second insulating film 220, the third insulating film 230, and the polysilicon film 240 are sequentially stacked on the substrate 100, and the polysilicon film ( A photo mask pattern 250 for forming a pattern on the 240 is formed through a photolithography process. The first insulating layer 210 may be a pad oxide layer, the second insulating layer may be a silicon nitride (SiN) layer, and the third insulating layer may be a medium temperature deposition of oxide (MTO) layer. Of course, the first, second, and third insulating films are not limited to the above-described insulating films, of course.

On the other hand, the narrow spaced patterned part on the left becomes the cell region, and the large pattern on the right is for forming an isolation layer that separates the cell region from other peripheral circuit regions.

Referring to FIG. 5B, an etching process may be performed using the photomask pattern 250 as a mask to etch a portion of the third insulating film 230, that is, the MTO layer, and may be processed through an ashing or strip process. Remove 250. The polysilicon layer 240a and the third insulating layer 230a patterned through the etching process are formed.

Referring to FIG. 5C, the fourth insulating layer is thinly deposited on the entire surface of the substrate on which the polysilicon layer 240a and the third insulating layer 230a patterns are formed through an ALD (Atomic Layer Deposition) process. The fourth insulating film 235 is preferably formed of the same material as the third insulating film 230a, for example, an MTO film. On the other hand, the thickness of the fourth insulating film 235 is preferably formed in a thickness and interval of about one to one. The thickness of the insulating layer 235 may be an active string or field spacing in the memory device finally formed.

Referring to FIG. 5D, a polysilicon film 245 is formed on the fourth insulating film 235.

Referring to FIG. 5E, most of the polysilicon layer 245 on the fourth insulating layer is removed through an etch-back process. That is, most of the polysilicon film 245 on the upper surface of the substrate is removed through the etch back process, but the polysilicon film 245a between the fourth insulating films 235 of the narrow pattern is not removed.

Referring to FIG. 5F, an etching process is performed using the polysilicon layers 240 and 245a as a mask through an etching process to form a pattern to the second insulating layer 220, that is, the SiN layer, and the polysilicon layers 240 and 245a. ). The process so far is called a DPT process.

Referring to FIG. 5G, an oxide film 215 gap fill process may be performed on the entire surface of the substrate 100 on which the pattern is formed. That is, the oxide film 215 is deposited to fill the gap between the MTO film of the third insulating film and the fourth insulating film 230b and 235a on the substrate 100 and the patterns of the second insulating film 220a.

Referring to FIG. 5H, the second insulating film 220a is planarized through the CMP process. After the planarization process is completed as described above, a process for forming the bridge region, which is the core of the present invention, is performed, which will be described with reference to the plan view.

5I and 6A, a photo mask pattern 260 for forming a bridge region is formed on the second insulating film 220a and the oxide film 215a exposed through the planarization process. Of course, the photo mask pattern 260 is formed only in the cell region, and is also formed in the portion where the shared bit line contact is to be formed. That is, the shared bit line contact is formed in the SSL outer portion as in the prior art.

As shown in FIG. 6A, the photo mask pattern 260 may be formed in a straight line along the word line. However, as shown by a dotted line, the photo mask pattern 260a may be zigzag along the word line.

5J and 6B, the oxide film 215a and the first insulating film 210 are etched and removed using the photomask pattern 260 and the second insulating film 220a as a mask. The photo mask pattern 260 is removed through an ashing / strip process.

5K and 6C, trenches are formed to a predetermined depth of the substrate 100 through an etching process using the patterns formed on the substrate as masks to form the field region and the device isolation layer.

Referring to FIG. 5L, an oxide film 115 gap fill process is performed on the entire surface of a substrate to form a field region and an isolation layer.

5M and 6D, the planarization process is performed until the second insulating film 220a is exposed through the CMP process. The field region 110 and the device isolation layer 115a are formed through the planarization process. Although the same is illustrated in FIG. 6D, the field region 110 is divided into a first field 110a integrally formed with a second field 110b divided into two small regions by a bridge region. That is, in the case of the second field, an oxide film is thinly formed on the bridge region and the upper surface of the substrate is positioned below.

Meanwhile, hereinafter, the upper region of the substrate will be referred to as an active region so as to be consistent with FIGS. 1 to 4H. In other words, after the ion implant process or the like is performed on the upper region of the substrate, the substrate becomes an active region. However, the upper region of the substrate is referred to as the active region from the viewpoint of sharing of the active region.

Referring to FIGS. 5N and 6E, the active layer is removed by removing the second insulating layer 220a and the lower first insulating layer 210a using the oxide layer, that is, the oxide layer of the field region 110 and the device isolation layer 115a as a mask. The tunnel oxide film 131 is grown on the exposed and exposed active region. Meanwhile, in the plan view of FIG. 6, the shared bit line 190 and the shared bit line contact 180 are shown together for the sake of understanding. That is, the shared bit line 190 is disposed on the second field 100b in which the bridge area exists among the field area 110, and the shared bit line contact 180 is connected to the bridge area of the second field 110b. Is formed. On the other hand, the portion of the second field 110b is indicated by a dotted line on the substrate, which means that the second field is formed like the first field in the bit line direction except for the bridge portion.

Here, although the shared bitline contact 180 is disposed in a straight line, as described above, by adjusting the arrangement of the photo mask pattern during the photo mask pattern process of FIG. 6A, the arrangement of the bridge region can be adjusted and thus shared. The arrangement of the bit line contacts 180 may also be adjusted. Meanwhile, the structure of the field regions adjacent to the bridge region may also be formed in various forms as shown in FIGS. 4A to 4H.

Since the process of the nonvolatile memory device is the same as the conventional one, a description thereof will be omitted.

However, when forming a shared bit line contact, a contact process may be performed very easily according to securing a large space of a contact region. The shared bit line contact includes a barrier metal and a conductive material, and as the barrier metal, SiN spacer / Ti / TiN or Ti / TiN may be used. But it is not limited thereto.

On the other hand, by increasing the spacing between the shared bit line, the bit line process can also be performed very easily. For example, when copper (Cu), which is excellent in terms of cost and conductivity, is used as a material of a bit line, a damascene process is used, and it is difficult to perform a narrow gap bit line using a copper damascene process. there was. However, in the case of the present invention, by adopting a shared bit line, the copper damascene process can be performed very easily due to the spacing between the bit lines that are about three times wider than in the related art.

7A and 7B are a plan view and a cross-sectional view of a nonvolatile memory device according to another embodiment of the present invention.

7A and 7B, the structure of the shared bitline or the shared bitline contact of this embodiment is almost the same as that of Figs. 5N and 6E, but the structure of the bridge region portion is slightly different. That is, in FIGS. 5N and 6E, the first insulating film and the oxide film were thinly formed on the active portion of the bridge region. However, in the present embodiment, the first insulating film and the oxide film do not exist and the tunnel oxide film 131 is present on the active film. do.

The structure of the bridge region of the present embodiment is a bridge region by performing a process of removing the first insulating film and the oxide film 115a on the bridge region after the removing of the first and second insulating films 210a and 220a after the FIG. 6D process. It can also be achieved by exposing the active onto the phase and growing the tunnel oxide along with other active portions.

As described above, the nonvolatile memory device having the shared bit line and the method of manufacturing the same of the present invention form a shared bit line, thereby minimizing interference between the bit lines, and eliminating the complicated DPT process for the bit lines. It offers the benefits of doing so. In addition, by forming a contact on the shared bit line through the bridge region, the bit line contact process and the copper (Cu) damascene process of the bit line can be easily performed. Thus, the cost in the process can be significantly reduced. In addition, due to the increased spacing between the bitlines and the large contact contact area, the parasitic capacitance and resistance can be reduced, thereby significantly improving the performance of the device.

8 is a schematic diagram illustrating a memory card 5000 according to an embodiment of the present invention.

Referring to FIG. 8, the controller 510 and the memory 520 may be arranged to exchange electrical signals. For example, when the controller 510 issues a command, the memory 520 may transmit data. The memory 520 may include a nonvolatile memory device according to any one of embodiments of the present invention. Nonvolatile memory devices according to various embodiments of the present disclosure may be disposed in “NAND” and “NOR” architecture memory arrays (not shown) corresponding to the logic gate design as is well known in the art. Memory arrays arranged in a plurality of rows and columns may constitute one or more memory array banks (not shown). The memory 520 may include such a memory array (not shown) or a memory array bank (not shown). In addition, the memory card 5000 may be a conventional row decoder (not shown), column decoder (not shown), I / O buffers (not shown), and / or to drive the above-described memory array bank (not shown). A control register may be further included. The memory card 5000 may include various types of cards, for example, a memory stick card, a smart media card (SM), a secure digital (SD), and a mini secure digital card ( It can be used in a memory device such as a mini secure digital card (mini SD), or a multi media card (MMC).

9 is a schematic diagram illustrating an electrical and electronic system 6000 according to an embodiment of the present invention.

Referring to FIG. 9, the electrical and electronic system 6000 may include a controller 610, an input / output device 620, a memory 630, and an interface 640. The electrical and electronic system 6000 may be a mobile system or a system for transmitting or receiving information. The mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player or a memory card. Can be. The controller 610 may execute a program and control the electric and electronic system 6000. The controller 610 may be, for example, a microprocessor, a digital signal processor, a microcontroller, or a similar device. The input / output device 620 may be used to input or output data of the electrical and electronic system 6000. The electrical and electronic system 6000 may be connected to an external device, such as a personal computer or a network, by using the input / output device 630 to exchange data with the external device. The input / output device 620 may be, for example, a keypad, a keyboard, or a display. The memory 630 may store code and / or data for the operation of the controller 610 and / or store data processed by the controller 610. The memory 630 may include a nonvolatile memory according to any one of embodiments of the present invention. The interface 640 may be a data transmission path between the electrical and electronic system 6000 and another external device. The controller 610, the input / output device 620, the memory 630, and the interface 640 may communicate with each other via the bus 650. For example, such an electrical and electronic system 6000 may be a mobile phone, MP3 player, navigation, portable multimedia player (PMP), solid state disk (SSD) or consumer electronics. (household appliances) can be used.

So far, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a block diagram of a nonvolatile memory according to an embodiment of the present invention.

2 is a layout diagram illustrating a portion of a memory cell array of a nonvolatile memory according to an embodiment of the present invention.

3A-3D are cross-sectional views taken along cut lines I-I ', II-II', III-III 'and IV-IV' of FIG. 2, respectively.

4A-4H are layout views for various bridge regions and SBCs in accordance with one embodiment of the present invention.

5A through 5N are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a shared bit line according to an embodiment of the present invention.

6A through 6E are respective plan views corresponding to FIGS. 5I, 5J, 5K, 5M, and 5N.

7A and 7B are a plan view and a cross-sectional view of a nonvolatile memory device according to another embodiment of the present invention.

8 is a schematic diagram illustrating a memory card 5000 according to an embodiment of the present invention.

9 is a schematic diagram illustrating a system 6000 according to an embodiment of the present invention.

<Description of main parts of drawing>

100: substrate 101: active

110: field area 110a: first field

110b: second field 115 and 115a: device isolation film

131: tunnel oxide film 133: charge storage layer

135: blocking insulating film 141: gate conductive film

160: first interlayer insulating film 170: second interlayer insulating film

180, 180a, 180b: SBC 190: Shared Bitline

200: SSL 210, 210a: first insulating film (pad oxide)

220, 220a: second insulating film SiN

230, 230a, 230b, and 235: third or fourth insulating film MTO

240, 240a, 245, 245a: polysilicon film

250, 260, 260a: photo mask pattern

235: second MTO insulating film 215, 215a: oxide film

510, 610: controller 520, 630: memory

620: input / output device 640: interface

650: bus 5000: memory card

6000: electrical and electronic systems

Claims (23)

Board; A field region formed in the first direction on the substrate, the field region having a first field formed integrally with the second field divided into two small regions by a bridge; An active region formed on the substrate and defined by the field region in a string structure, wherein at least two of the string structures are connected to each other through the bridge; And A non-volatile memory having a shared bit line formed on the field region in the first direction, the shared bit line being connected to the bridge through a bit line contact (DC); device. According to claim 1, A word line is formed in a second direction perpendicular to the first direction across the active area and the field area. The bridge is disposed along the second direction, Non-volatile memory device, characterized in that arranged in a straight line or zigzag form. The method of claim 2, And the bit line contact is in contact with at least one small region of two adjacent small regions. The method of claim 3, wherein And the active portion of the bridge portion has a convex structure in at least one of two adjacent first fields and two small regions. The method of claim 2, And the active portion of the bridge portion has a convex structure in at least one of two adjacent first fields and two small regions. According to claim 1, A tunnel oxide film is formed on the active region. According to claim 1, And an oxide film forming the field region is formed on the active film of the bridge portion. According to claim 1, The bit line contact includes a barrier metal and a conductive material, And the bit line is formed of copper (Cu) using a damascene process. The method of claim 8, The barrier metal is SiN spacer / Ti / TiN or Ti / TiN, And the conductive material is tungsten (W) or polysilicon. According to claim 1, The first field and the second field are alternately arranged, The active region is a nonvolatile memory device, characterized in that the two string structure is connected to each other through the bridge. Forming a field region on the substrate in a first direction, the field region having a second field divided into two small regions by an integrally formed first field and a bridge region; Growing a tunnel oxide film on an active region defined by the field region and confined to a string structure and at least two string structures connected to each other by the bridge region; Forming a bitline contact over the bridge region; And And forming a shared bit line connected to the bit line contact on the field region in the first direction. The method of claim 11, wherein The field region forming step, Stacking different first, second, and third insulating films on a substrate, and etching the second and third insulating films through a double patterning technology (DPT) process; Depositing a first oxide film over the entire surface of the resultant on the substrate and planarizing the second insulating film through a CMP process; A photo mask pattern is formed on the first oxide layer, and a trench is formed by etching a predetermined portion of the substrate using the second insulating layer and the photo mask pattern, and the photo mask pattern is removed to remove the photo mask pattern. Forming a bridge region under the first oxide film; And depositing a second oxide film over the entire surface of the resultant on the substrate and planarizing the second insulating film to expose the second insulating film through a CMP process, thereby forming a field region in the first direction. In the tunnel oxide film growing step, the first oxide film and the second insulating film are removed using the second oxide film as a mask to expose the active region on the substrate, and the tunnel oxide film is grown on the active region. Device manufacturing method. The method of claim 12, The DPT process Stacking a first polysilicon film on the third insulating film; Forming a photo mask pattern on the first polysilicon layer, etching a portion of the third insulating layer using the photo mask pattern, and removing the photo mask pattern; Forming an MTO film and a second polysilicon film over the entire surface of the resultant on the substrate and removing a predetermined portion of the second polysilicon film through an etch-back; And etching the first insulating film to expose the second polysilicon layer and removing the second polysilicon layer using the second polysilicon layer as a mask. The method of claim 12, Before the bit line contact forming step, Forming a word line in a second direction perpendicular to the first direction across the active area and the field area; The photo mask pattern is disposed along the second direction, A method of manufacturing a nonvolatile memory device, characterized in that arranged in a straight line or zigzag form. The method of claim 14, And forming the bit line contact so as to contact at least one small region of two adjacent small regions. The method of claim 15, And wherein the active portion of the bridge region has a convex structure in at least one direction between two adjacent first fields and two small regions. The method of claim 14, And wherein the active portion of the bridge region has a convex structure in at least one direction between two adjacent first fields and two small regions. The method of claim 12, In the exposing the active region, removing the first insulating film and the second oxide film on the bridge region, thereby growing the tunnel oxide film on the active phase on the bridge region. The method of claim 12, Wherein the first insulating film is a pad oxide film, the second insulating film is a silicon nitride (SiN) film, and the third insulating film is a metal tungsten oxide (MTO) film. The method of claim 12, Forming the bit line contact Etching the insulating layers deposited over the bridge region to form a contact hole for exposing the active portion of the bridge region; Performing an ion implantation process to reduce contact resistance at the bottom of the contact hole; Depositing a barrier metal into the hole; And filling a conductive material on the barrier metal. The method of claim 12, The shared bit line is a non-volatile memory device manufacturing method characterized in that formed through the Cu damascene (Damascene) process. A nonvolatile memory device according to any one of claims 1 to 10; and And a controller controlling the nonvolatile memory device and exchanging data with the nonvolatile memory device. A nonvolatile memory device according to any one of claims 1 to 10; and A processor in communication with the nonvolatile memory device via a bus; And And an input / output device in communication with the bus.

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