TWI836313B - 3d flash memory module chip and method of fabricating the same - Google Patents

Abstract

A 3D flash memory module chip includes a memory chip and a control chip. The memory chip includes a plurality of tiles and a plurality of heaters. The tiles each include a plurality of 3D flash memory structures. The heaters are disposed around the 3D flash memory structures of each of the tiles. The control chip is bonded with the memory chip to drive at least one of the heaters.

Description

Three-dimensional flash memory module chip and manufacturing method thereof

The present invention relates to a memory module and a manufacturing method thereof, and in particular, to a three-dimensional flash memory module and a manufacturing method thereof.

Non-volatile memory has the advantage that stored data will not disappear even after a power outage, so it is widely used in personal computers and other electronic devices. Currently, three-dimensional memories commonly used in the industry include NOR (NOR) memory and NAND (NAND) memory. In addition, another type of three-dimensional memory is the AND memory, which can be applied in multi-dimensional memory arrays and has high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become a current trend.

The present invention provides a three-dimensional flash memory module chip and a manufacturing method thereof, which can perform a healing process on a part of the flash memory.

In one embodiment of the present invention, a three-dimensional flash memory module chip includes: a memory chip and a control chip. The memory chip includes: a plurality of blocks, each block including a plurality of three-dimensional flash memory structures; and a plurality of heaters, which are arranged around the plurality of three-dimensional flash memory structures of each block. The control chip is coupled to the memory chip to drive at least one of the plurality of heaters.

In one embodiment of the present invention, a method for manufacturing a three-dimensional flash memory module chip includes: forming a memory chip, including: forming a plurality of blocks on a first substrate, each block including a plurality of three-dimensional flash memory structures; and forming a plurality of heaters around the plurality of three-dimensional flash memory structures of each block; forming a control chip; and bonding the control chip to the memory chip, wherein the control chip is used to drive the plurality of heaters.

Based on the above, the three-dimensional flash memory module chip and its manufacturing method of the present invention use an additional control chip to drive the heater to perform partial repair processing on each block of the flash memory. The control chip can be fabricated separately to avoid the heater controller occupying the area of the memory chip, and the control chip can be fabricated with a lower-level process to reduce the cost of the process.

After multiple operations, the performance of flash memory will be significantly reduced, so the flash memory needs to be repaired (healing). The repair process can use a heater to heat the flash memory to repair the charge storage structure (such as the nitride layer) of the flash memory. In current technology, word lines are mostly used as heaters. However, due to the large number of word lines and the complex configuration relationship with other components (such as word line decoders), the layout design of the flash memory structure is more difficult.

Embodiments of the present invention provide several types of three-dimensional flash memory module chips. The heater is arranged above the three-dimensional flash memory structure of the memory chip or around the side wall, and the memory chip is bonded to the control chip to control the The chip drives the heater to repair local areas of the memory chip.

1A and 1B are respectively a three-dimensional schematic diagram of a three-dimensional flash memory module chip according to an embodiment of the present invention. 2A is a partial top view of a three-dimensional flash memory structure of a memory chip according to an embodiment of the present invention. Fig. 2B is a cross-sectional view along line I-I' of Fig. 2A. 3A is a partial top view of a memory chip with a heater according to another embodiment of the present invention. Fig. 3B is a cross-sectional view along line I-I' of Fig. 3A.

1A and 1B , a three-dimensional flash memory module chip (also referred to as a three-dimensional integrated circuit, 3DIC) 5000 according to an embodiment of the present invention includes: a memory chip 1000 and a control chip 2000. The memory chip 1000 includes a plurality of three-dimensional flash memory structures 1100 and a plurality of heaters 1200. The plurality of heaters 1200 are disposed around the plurality of three-dimensional flash memory structures 1100. In some embodiments, the plurality of heaters 1200 are disposed above the plurality of three-dimensional flash memory structures 1100, as shown in FIG. 1A . In other embodiments, the plurality of heaters 1200 are disposed in a separation trench 1110 between the plurality of three-dimensional flash memory structures 1100, as shown in FIG. 1B . The control chip 2000 is disposed above the memory chip 1000 to drive the heater 1200 in the memory chip 1000. The control chip 2000 and the memory chip 1000 may be bonded to each other via a bonding structure 3000.

1A and 1B , the three-dimensional flash memory structure 1100 of the memory chip 1000 may be a three-dimensional AND flash memory structure (as shown in FIGS. 2A and 2B ), a three-dimensional NAND flash memory structure (not shown), or a three-dimensional NOR flash memory structure (not shown). The three-dimensional AND flash memory structure is used as an example to illustrate the three-dimensional flash memory structure 1100 of the present invention, however, the embodiments of the present invention are not limited thereto.

Referring to FIGS. 2A and 2B , the memory chip 1000 may include a plurality of blocks T. The blocks T may be arranged into an array including multiple rows and multiple columns. In this embodiment, four block elements T (for example, T1 to T4) are used for illustration. Among the four block elements T, the block elements T1 and T2 are arranged in one row; the block elements T3 and T4 are arranged in another row. The block elements T1 and T3 are arranged in one row; the block elements T2 and T4 are arranged in another row. Each block T may include multiple blocks B (for example, B1~B4). Each block B includes a three-dimensional flash memory structure 1100. Multiple three-dimensional flash memory structures 1100 extend in the X direction and are arranged in the Y direction. Two adjacent three-dimensional flash memory structures 1100 are separated from each other by separation trenches 1110 .

Referring to FIG. 2B , each three-dimensional flash memory structure 1100 may include at least one memory array formed by a plurality of memory cells. In more detail, the three-dimensional flash memory structure 1100 may be disposed over one or more active devices (eg, the first transistor 1020 ) on the first substrate (eg, the semiconductor substrate) 1010 . The first transistor 1020 is, for example, a complementary metal oxide semiconductor field effect transistor (CMOS). Therefore, this architecture can also be called a complementary metal oxide semiconductor field effect transistor under the array (CMOS under Array, CUA) architecture.

2B , the three-dimensional flash memory structure 1100 may be disposed in the back end of line (BEOL) of a semiconductor die. For example, the three-dimensional flash memory structure 1100 may be buried in a first internal connection structure 1030. The first internal connection structure 1030, for example, includes a lower internal connection structure 1032 and an upper internal connection structure 1034. The lower internal connection structure 1032 is disposed above one or more active elements (e.g., the first transistor 1020) on a first substrate (e.g., a semiconductor substrate) 1010 and below the memory array of the three-dimensional flash memory structure 1100. The upper internal connection structure 1034 is disposed above the memory array of the three-dimensional flash memory structure 1100. The lower interconnect structure 1032 includes, for example, a lower first metal layer BM1, a lower second metal layer BM2, and a lower third metal layer BM3, and vias BV1 and BV2 therebetween. The upper interconnect structure 1034 includes, for example, an upper first metal layer TM1 and an upper second metal layer TM2, and a via TV1 therebetween. The number of metal layers and vias of the lower interconnect structure 1032 and the upper interconnect structure 1034 are not limited to the above.

Referring to FIG. 2B , the three-dimensional flash memory structure 1100 includes a plurality of gate stack structures 52 . Each gate stack structure 52 is formed on the lower interconnect structure 1032 . Each gate stack structure 52 extends in the X direction from the array area AR of the first substrate 1010 to the step area SR. The gate stack structure 52 includes a plurality of gate layers (also called word lines) 38 and a multi-layer insulating layer 54 vertically stacked on the surface of the first substrate 1010 . In the Z direction, the gate layers 38 are electrically isolated by the insulating layer 54 disposed between them. Gate layer 38 includes a metal layer such as tungsten. In some embodiments, the gate layer 38 further includes a barrier layer 37, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. The insulating layer 54 is, for example, silicon oxide.

Gate layer 38 extends in a direction parallel to the surface of first substrate 1010 (shown in Figure 2D). The gate layer 38 in the stepped region SR may have a stepped structure SC (shown in FIG. 2B ), so that the lower gate layer 38 is longer than the upper gate layer 38 , and the end of the lower gate layer 38 laterally extends out of the upper part. end of gate layer 38 . The contact window C1 used to connect the gate layer 38 can land on the end of the gate layer 38 located in the step region SR, thereby connecting each gate layer 38 to the lower interconnect structure 1034 through the contact window C1 Each conductor of the structure 1032 is, for example, the conductor of the lower third metal layer BM3.

Referring to FIG. 2B , the three-dimensional flash memory structure 1100 also includes a plurality of channel pillars 16 . The channel pillar 16 extends continuously through the gate stack structure 52 of the array area AR. In some embodiments, channel post 16 may have an annular profile when viewed from above. The material of the channel pillar 16 may be a semiconductor, such as undoped polycrystalline silicon.

Referring to FIG. 2B, the three-dimensional flash memory structure 1100 also includes an insulating filling layer 24, an insulating pillar 28, a plurality of conductive pillars (for example, as source pillars) 32a and a plurality of conductor pillars (for example, as drain pillars). )32b. The conductive pillars 32 a and 32 b and the insulating pillar 28 are disposed in the channel pillar 16 and each extend in a direction perpendicular to the gate layer 38 (ie, the Z direction). The conductive pillars 32 a and 32 b are separated from the insulating pillar 28 by the insulating filling layer 24 and are electrically coupled to the channel pillar 16 . Conductor pillars 32a and 32b are, for example, doped polycrystalline silicon. The insulating filling layer 24 is, for example, silicon oxide; the insulating pillar 28 is, for example, silicon nitride.

2B , the charge storage structure 40 is disposed between the channel pillar 16 and the multi-layer gate layer 38. The charge storage structure 40 may include a tunneling layer (or a gap-engineered tunneling oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36. In some embodiments, the tunneling layer 14, the charge storage layer 12, and the blocking layer 36 are, for example, silicon oxide, silicon nitride, and silicon oxide. In some embodiments, a portion of the charge storage structure 40 (e.g., the tunneling layer 14) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), and another portion of the charge storage structure 40 (e.g., the charge storage layer 12 and the blocking layer 36) surrounds the gate layer 38, as shown in FIG2B. In other embodiments, the charge storage structure 40 (e.g., the tunneling layer 14, the charge storage layer 12, and the blocking layer 36) surrounds the gate layer 38 (not shown). Each gate layer 38 and the surrounding charge storage structure 40, the channel pillar 16, the source pillar 32a and the drain pillar 32b define a memory cell 20. Therefore, each three-dimensional flash memory structure 1100 includes at least one memory array composed of a plurality of memory cells 20.

The three-dimensional flash memory structure 1100 further includes a local bit line LBL _n and a local source line LSL _n and a global bit line GBL _n and a global source line GSL _n . The local bit line LBL _n and the local source line LSL _n are located in the upper first metal layer TM1 of the upper interconnect structure 1034, and are electrically connected to the source pillar 32 a and the drain pillar 32 b through the contact window C2, respectively. The global bit line GBL _n and the global source line GSL _n are electrically connected to the local bit line LBL _n and the local source line LSL _n through the upper via (not shown) in the upper interconnect structure 1034, respectively.

The memory unit 20 can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column 32a and the drain column 32b, since the source column 32a and the drain column 32b are connected to the channel column 16, electrons can be transported along the channel column 16 and stored in the entire charge storage. In the structure 40, in this way, a 1-bit operation can be performed on the memory unit 20. In addition, for operations utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and the drain post 32b . For source side injection, channel-hot-electron injection or band-to-band tunneling hot carrier injection operations, the electrons can be Or the holes are locally trapped in the charge storage structure 40 adjacent to one of the two source pillars 32a and drain pillars 32b, so that the memory cell 20 can be processed into unit cell (SLC, 1 bit) or multiple Bit cell (MLC, greater than or equal to 2 bits) operations.

During operation, a voltage is applied to the selected word line (gate layer) 38 , for example, when a voltage higher than the corresponding starting voltage (V _th ) of the corresponding memory cell 20 is applied, intersecting the selected word line 38 The channel region of the channel column 16 is turned on, allowing current to enter the drain column 32b from the bit line BL _n , and flow to the source column 32a through the conductive channel region, and finally flow to the source line SL _n .

3A and 3B , the memory chip 1000 further includes a plurality of heaters 1200. The heaters 1200 may be disposed in a dielectric layer 1040 above the three-dimensional flash memory structure 1100. The material of the dielectric layer 1040 is, for example, silicon oxide. The heater 1200 includes a metal layer 1202, such as copper or tungsten. In some embodiments, the heater 1200 further includes a barrier layer 1204, such as titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof.

Referring to FIG. 3A , in some embodiments, a single heater 1200 is disposed on each block B, and the two heaters 1200 of any two adjacent blocks B are separated from each other. The heater 1200 may extend in the X direction. In one embodiment, the heater 1200 is disposed in the array region AR and extends to the step region SR (as shown in FIGS. 3A and 3B ). In one embodiment, the heater 1200 may be disposed in the array region AR, but not in the step region SR (not shown). That is, the length of the heater 1200 may be greater than, equal to, or less than the length of the three-dimensional flash memory structure 1100 in the X direction.

In addition, multiple heaters 1200 may be provided on each block B, for example, each of the array region AR and the step region SR has a heater 1200, and each of the heaters 1200 may be heated (not shown). However, the present invention is not limited thereto. In another embodiment, multiple heaters 1200 of two, three or more adjacent blocks B may be combined into a single heater (not shown) to heat the three-dimensional flash memory structure 1100 of multiple blocks B at the same time.

Referring to FIG. 3A , the top view shape of the heater 1200 is, for example, a rectangle or other shapes. The multiple heaters 1200 on multiple blocks B may have the same width or different widths. The width W1 of the heater 1200 in the array area AR is the same as the width W2 of the heater 1200 in the step area SR. However, the present invention is not limited thereto. The shape of the heater 1200 can be changed according to actual needs or designs. The width W1 of the heater 1200 in the array area AR may be greater than, equal to, or smaller than the width W2 of the heater 1200 in the step area SR.

1A, 1B and 3B, the memory chip 1000 further includes a bonding layer 1300. The bonding layer 1300 includes a pad 1302 and an insulating layer 1304. The insulating layer 1304 is disposed on the heater 1200. The material of the insulating layer 1304 is, for example, silicon oxide. The pad 1302 is disposed in the insulating layer 1304 on the surface of each heater 1200. The material of the pad 1302 is, for example, copper. The pad 1302 includes pads 1302a and 1302b. The pads 1302a and 1302b are respectively connected to the first end E1 and the second end E2 of the heater 1200.

In the above embodiments, the plurality of three-dimensional flash memory structures 1100 are three-dimensional AND flash memory structures, and the plurality of heaters 1200 are disposed above the three-dimensional AND flash memory structures (as shown in Figures 3A, 3B and shown in Figure 6A). In other embodiments, the plurality of three-dimensional flash memory structures 1100 are three-dimensional AND flash memory structures, and the plurality of heaters 1200 are disposed in the separation trenches 1110 between the three-dimensional AND flash memory structures (such as As shown in Figure 4A to Figure 4C).

Fig. 4A is a partial top view of a memory chip with a heater according to another embodiment of the present invention. Fig. 4B is a partial top view of a heater and a pad of a memory chip according to another embodiment of the present invention. Fig. 4C is a cross-sectional view taken along line II-II' of Fig. 4B.

Referring to FIGS. 4A and 4C , a plurality of heaters 1200 are disposed in the separation trenches 1110 between the three-dimensional flash memory structures 1100 . The heater 1200 is disposed around the multiple gate layers 38 and the multiple insulation layers 54 of the gate stack structure 52 . The heater 1200 is separated from the plurality of gate layers 38 and the multi-layer insulating layers 54 by an insulating liner 1112 (as shown in FIG. 4C ). The insulating liner 1112 includes an insulating material such as silicon oxide or silicon nitride. Heater 1200 includes a metal layer 1202 (shown in Figure 4C), such as copper or tungsten. In some embodiments, heater 1200 also includes barrier layer 1204 (shown in Figure 4C). Barrier layer 1204 is located between insulating liner 1112 and metal layer 1202 . The barrier layer 1204 is, for example, titanium, tantalum, titanium nitride, tantalum nitride, or combinations thereof.

In some embodiments, a single heater 1200 is disposed in each separation trench 1110. For example, the heater 1200 may extend in the X direction. In one embodiment, the heater 1200 is disposed in the array region AR and extends to the step region SR (as shown in FIGS. 4A and 4B ). In one embodiment, the heater 1200 may be disposed in the array region AR but not in the step region SR (not shown). That is, the length of the heater 1200 may be greater than, equal to, or less than the length of the three-dimensional flash memory structure 1100 in the X direction.

Alternatively, a plurality of heaters 1200 may be disposed in each separation trench 1110, for example, each of the array region AR and the step region SR has a heater 1200, and heating can be performed separately (not shown). However, the present invention is not limited thereto.

Please refer to FIG. 4A. In addition, the top view shape of the heater 1200 is, for example, a rectangle or other shapes. The plurality of heaters 1200 in the plurality of separation trenches 1110 may have the same width or different widths. However, the present invention is not limited thereto. The shape of the heater 1200 can be changed according to actual needs or designs.

4B and 4C , contact windows C3 are provided on the surfaces of the two ends (i.e., E1 and E2) of each heater 1200. The contact windows C3 can be connected to the upper pads 1302a and 1302b via the upper internal connection structure 1034, so that the heater 1200 of the memory chip 1000 can be electrically connected to the control chip 2000 via the upper internal connection structure 1034 and the pads 1302a and 1302b. The material of the pads 1302a and 1302b is, for example, copper.

Figures 5A to 5E are various three-dimensional schematic diagrams of a control chip according to an embodiment of the present invention. Figure 6A is a three-dimensional schematic diagram of a memory chip and a control chip according to an embodiment of the present invention. Figure 6B is a circuit schematic diagram of Figure 6A.

Referring to FIG. 5A , the control chip 2000 may include a plurality of cells T’. These cells T’ may be arranged in an array. In this embodiment, four cells T’ (e.g., T1’ to T4’) are used as an example for explanation. Among the four cells T’, cell T1’ and cell T2’ are arranged in one row; cell T3’ and cell T4’ are arranged in another row. Cell T1’ and cell T3’ are arranged in one row; cell T2’ and cell T4’ are arranged in another row.

Please refer to FIG. 5A and FIG. 5E. Each block T' includes a plurality of driving columns 2000R and rows 2000C. Each driving column 2000R includes a second transistor 2020, a second interconnect structure 2030 and a pad 2052, as shown in FIG. 5E. The second transistor 2020 is disposed on the active region 2012 of the second substrate 2010. The second substrate 2010 may be a semiconductor substrate, such as a silicon substrate. The second transistor 2020 may be a complementary metal-oxide-semiconductor (CMOS) transistor. The second transistor 2020 may be a planar transistor (as shown in FIGS. 5A to 5E ) or a fin-shaped transistor (as shown in FIG. 8 ).

5B, 5E and 8, the second transistor 2020 includes a gate dielectric layer 2024, a gate layer 2028, a source region 2022a and a drain region 2022b. The gate dielectric layer 2024 is, for example, silicon oxide or a high dielectric constant material. The gate layer 2028 is, for example, doped polysilicon or tungsten. The gate layer 2028 is located on the gate dielectric layer 2024. The gate layer 2028 is in the shape of a long strip, and its extension direction is, for example, the same as the extension direction of the heater 1200, for example, extending in the X direction, as shown in FIG6A. In some examples, the gate layers 2028 of the second transistors 2020 in two adjacent columns (e.g., cells T1′ and T2′, or cells T3′ and T4′) may be electrically connected, as shown in FIG. 5A .

Referring to FIG. 5E , the source region 2022a and the drain region 2022b of the second transistor 2020 are disposed in the active region 2012 on both sides of the gate layer 2028. The source region 2022a and the drain region 2022b have dopants, such as N-type or P-type dopants. In some embodiments, two adjacent second transistors 2020 share the source region 2022a.

Please refer to FIG. 5B and FIG. 5C. The second interconnect structure 2030 is located on the plurality of second transistors 2020. The second interconnect structure 2030 includes a dielectric layer 2031 (as shown in FIG. 5C ) and a plurality of contact windows 2032 and 2034 located in the dielectric layer 2031 , a plurality of wires 2036 and 2040 and a plurality of via windows 2038 . 2042. A plurality of contact windows 2032 respectively land on the source region 2022a and the drain region 2022b, and are electrically connected to the source region 2022a and the drain region 2022b. The contact window 2034 lands on the gate layer 2028 and is electrically connected to the gate layer 2028 . The contact window 2032 is in the shape of a long strip, which extends along the X direction and is substantially parallel to the gate layer 2028, as shown in FIG. 5B and FIG. 5D. The shape of the contact window 2034 is different from the shape of the contact window 2032, and its shape is, for example, columnar, as shown in FIG. 5B. Wires 2036 and 2040 (as shown in Figure 5C) are respectively provided on a plurality of contact windows 2032 and 2034. The wires 2036 and 2040 are electrically insulated by vias 2038 . The via window 2042 is disposed on the wire 2040 and electrically connects the wire 2040 to the bonding layer 2050 above. The dielectric layer 2031 is, for example, silicon oxide. The plurality of contacts 2032 and 2034, the plurality of wires 2036 and 2040 and the plurality of vias 2038 and 2042 include metal layers such as tungsten or copper. The plurality of contacts 2032, 2034, the plurality of wires 2036, 2040, and the plurality of vias 2038, 2042 may further include a barrier layer (not shown) such as titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof. .

5C , the pad 2052 of each driver row 2000R is a part of the bonding layer 2050 of the control chip 2000. The bonding layer 2050 includes the pad 2052 and the insulating layer 2054. The insulating layer 2054 is located on the second inner connection structure 2030. The pad 2052 is located in the insulating layer 2054 and is electrically connected to the via 2042 of the second inner connection structure 2030. The material of the pad 2052 is, for example, copper. The material of the insulating layer 2054 is, for example, silicon oxide.

5A and 5E , the pad 2052 includes a pad 2052a and a pad 2052b. More specifically, each driver row 2000R includes a pair of pads 2052a and 2052b arranged along the X direction. The pad 2052a will be electrically connected to the first end E1 of the heater 1200; the pad 2052b will be electrically connected to the second end E2 of the heater 1200 to the ground, as shown in FIGS. 1A , 1B and 6A . Referring to FIGS. 5C and 5D , each pad 2052a is electrically connected to the wire 2040a thereunder via the via 2042a. The wires 2040a in the same cell T' are separated and electrically isolated from each other, so as to be electrically connected to the drain region 2022b of the second transistor 2020, as shown in FIG5A and FIG5C. Each pad 2052b is electrically connected to the wire 2040b below it through the via 2042b, as shown in FIG5D. Multiple pads 2052b in the same row of cells T' (e.g., cells T1' and T3', or cells T2' and T4') are electrically connected to the ground through the same wire 2040b, as shown in FIG5A and FIG5D.

Referring to FIG. 5C , FIG. 1A and FIG. 1B , the bonding layer 2050 of the control chip 2000 and the bonding layer 1300 of the memory chip 1000 are bonded to each other to form a bonding structure 3000 . More specifically, the position of the insulating layer 2054 of the control chip 2000 corresponds to the position of the insulating layer 1304 of the memory chip 1000, and are bonded to each other. The positions of the pads 2052a and 2052b of the control chip 2000 correspond to the positions of the pads 1302a and 1302b of the memory chip 1000, and are bonded to each other.

5A, 5C and 5D, the row 2000C of the control chip 2000 connects multiple block elements T' (for example, block elements T1' and T3', or block elements T2' and T4') of the same row via wires 2040c. The plurality of common source regions 2022a of the second transistor 2020 are electrically coupled to the global power supply 2100.

Referring to FIG. 5E , the drain region 2022b of the second transistor 2020 of the control chip 2000 is connected to the second inner connection structure 2030 and the pad 2052a of the bonding layer 2050, as shown in FIG. 5C . The pad 2052a is electrically connected to the pad 1302a of the first end E1 of the heater 1200 connected to the memory chip 1000, as shown in FIG. 6A . In one embodiment, each driver row 2000R of the control chip 2000 can control a heater 1200 of a corresponding block B of the memory chip 1000, as shown in FIG. 6A and FIG. 6B .

Please refer to FIG. 5E . In some embodiments, the control chip 2000 further includes a row decoder 2300 and a column decoder 2200. The row decoder 2300 is electrically connected to the global power supply 2100. After receiving the row address signals A3 and A4, the row decoder 2300 selects a plurality of blocks (two in this example, such as blocks T1' and T3' in FIG. 5A ) in one row (e.g., row 2000C ₁ in FIG. 5A ). The global power supply 2100 is thereby provided to a plurality of common source regions 2022a of a plurality of second transistors 2020 of each block (e.g., blocks T1' and T3' in FIG. 5A ) in the selected row (e.g., row 2000C ₁ in FIG. 5A ) via the wire 2040c (shown in FIG. 5A ) of the second internal connection structure 2030 . The row decoder 2200 is electrically connected to the gate layers 2028 of the second transistors 2020 of the driving rows 2000R. After receiving the row address signals A0-A2 (or control signals), the row decoder 2200 decodes the input row address signals to select one (e.g., the second transistor 2020 ₁ in FIG. 5A ) or more of the second transistors 2020 and turn them on.

Generally speaking, the memory chip 1000 includes a control logic unit for controlling the memory array, and the register in the control logic unit stores the state signal of the erase times of the memory array of each block B. When the erase times reaches a predetermined number, the state signal is sent to the control chip 2000.

6A and 6B , when performing the repair process, the control chip 2000 can generate a row address signal and a column address signal corresponding to the block T and block B (e.g., block B1 of block T1 in FIG. 6A ) that need to be repaired based on the received status signal, and transmit the row address signal and the column address signal to the row decoder 2200 and the row decoder 2300 respectively. The row decoder 2300 selects one of the rows (e.g., row 2000C ₁ in FIG. 6A ) according to the received row address signal, thereby providing the global power 2100 to the wire 2040c of the blocks (e.g., blocks T1′ and T3′ in FIG. 5A ) located in the row (e.g., row 2000C ₁ in FIG. 6A ). The row decoder 2200 selects a second transistor 2020 ₁ of a driving row 2000R ₁ according to the received row address signal and turns it on. Therefore, the current can flow from the global power supply 2100 into the source region 2022a of the second transistor 2020 ₁ through the wire 2040c, and through the channel and drain region 2022b of the second transistor 2020 ₁ , through the second internal connection structure 2030 and the pad 2052a, into the pad 1302a of the memory chip 1000, and enter the first end E1 of the heater 1200 (for example, 1200 ₁ ). Afterwards, the current flows through the heater 1200 ₁ , flows out from the second end E2 of the heater 1200 ₁ , and enters the pad 2052b of the control chip 2000 through the pad 1302b of the memory chip 1000 , and then is electrically connected to the ground through the wire 2040b. The embodiment of the present invention can provide a high drive current to a specific heater 1200 (e.g., 1200 1 ) by the second transistor (driver) 2020 (e.g., 2020 ₁ ) of the control chip 2000 , so that the conductor of the heater 1200 (e.g., 1200 ₁ ) is heated, thereby repairing the charge storage layer in the three-dimensional flash memory structure 1100 of a specific block B (e.g., B1) in a specific block T ₍ e.g., T1).

1A and 1B , in some embodiments, during the repair process, a single heater 1200 (e.g., 1200 ₁ ) can be driven by the control chip 2000 to repair the charge storage layer in the three-dimensional flash memory structure 1100 (e.g., 1100 1 ) of a single block B (e.g., _B1 ). Referring to FIG. 1B , in other embodiments, during the repair process, two heaters 1200 (e.g., 1200 ₂ and 1200 ₃ ) can also be driven by the control chip 2000 at the same time to repair the charge storage layer in the three-dimensional flash memory structure 1100 (e.g., 1100 ₂ ) of a single block B (e.g., B2 ).

7A to 7C are schematic cross-sectional views of the manufacturing process of the three-dimensional flash memory module chip of the present invention.

Referring to FIG. 7A , a wafer 1010W is provided, and a plurality of memory chips 1000 are formed on the wafer 1010W. The plurality of memory chips 1000 have scribe lines SL between each other. The method for forming the memory chips 1000 is described as follows. Referring to FIG. 3B , one or more active components (e.g., a first transistor) 1020 are first formed on the wafer 1010W. Next, a lower internal connection structure 1032 is formed on the active component 1020. The lower internal connection structure 1032 can be formed by any known method, such as inlay, dual inlay, etc. Afterwards, an insulating stack structure (not shown) formed by alternately stacking an insulating layer (e.g., silicon oxide) 54 and another insulating layer (not shown, e.g., silicon nitride) is formed on the lower interconnect structure 1032. Afterwards, the tunneling layer 14, channel pillar 16, and conductive pillars 32a and 32b of the charge storage structure 40 can be formed in the insulating stack structure by any known method. The material of the tunneling layer 14 can be a dielectric material, such as silicon oxide. The material of the channel pillar 16 can be a semiconductor, such as undoped polysilicon. The conductive pillars 32a and 32b are, for example, doped polysilicon.

Then, lithography and etching processes are performed to form separation trenches 1110 in the insulating stack structure and to separate the insulating stack structure into a plurality of blocks B.

Afterwards, a gate replacement process is performed to form the gate stack structure 52. First, an etching process is performed to inject an etching solution into the separation trench 1110 to remove another insulating layer in the insulating stack structure to form a plurality of horizontal openings 34, and then a gate layer 38 is formed in the horizontal openings 34. In some embodiments, before forming the gate layer 38, a charge storage layer 12 and a blocking layer 36 are also formed in the horizontal openings 34. The charge storage layer 12 is, for example, silicon nitride. The barrier layer 36 is, for example, a material with a high dielectric constant greater than or equal to 7, such as aluminum oxide (Al ₁ O ₃ ), ferrous oxide (HfO ₂ ), tantalum oxide (La ₂ O ₅ ), transition metal oxide, tungsten oxide, or a combination thereof. The gate layer 38 is, for example, tungsten. In some embodiments, before forming the multi-layer gate layer 38, a barrier layer 37 is further formed. The material of the barrier layer 37 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

Next, a separation slit SLT is formed in the separation trench 1110. The method for forming the separation slit SLT includes filling an insulating filling material on the gate stack structure 52 and in the separation trench 1110, and then removing excess insulating filling material on the gate stack structure 52 by an etching back process or a planarization process. The insulating filling material is, for example, silicon oxide.

Afterwards, an upper interconnection structure 1034 (including local bit lines LBL _n , local source lines LSL _n , and global bit lines GBL _n and global source lines GSL _n ) is formed on the gate stack structure 52 . The upper interconnect structure 1034 can be formed by any known method, such as damascene, dual damascene, etc., which will not be described in detail here.

3A and 3B , in the present embodiment, after the upper interconnect structure 1034 (including the local bit line LBL _n , the local source line LSL _n , and the global bit line GBL _n and the global source line GSL _n ) is formed, a heater 1200 is further formed above the upper interconnect structure 1034. The heater 1200 is formed by, for example, first forming a dielectric layer 1040 above the upper interconnect structure 1034. The material of the dielectric layer 1040 is, for example, silicon oxide. In some embodiments, a planarization process, such as a chemical mechanical planarization process, is further performed to make the dielectric layer 1040 have a flat surface. Thereafter, a lithography and etching process is performed to form a plurality of trenches OP1 in the dielectric layer 1040. Then, a barrier material layer and a metal material layer are sequentially formed on the dielectric layer 1040 and in the trench. Then, a planarization process, such as a chemical mechanical planarization process, is performed to remove the barrier material layer and the metal material layer on the surface of the dielectric layer 1040, and form a barrier layer 1204 and a metal layer 1202 in the trench. The metal material layer is, for example, copper or tungsten. The barrier material layer is, for example, titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof.

Please refer to FIG. 3B , after the heater 1200 is formed, the bonding layer 1300 is formed. The method for forming the bonding layer 1300 is described as follows. An insulating layer 1304 is first formed on the heater 1200 and the dielectric layer 1040, and then a lithography and etching process is performed to form a plurality of pad openings OP2 in the insulating layer 1304. The bottom of the pad opening OP2 exposes the heater 1200. Thereafter, a conductive layer is formed on the insulating layer 1304 and in the pad opening OP2. Then, a planarization process, such as a chemical mechanical planarization process, is performed to remove the conductive layer on the insulating layer 1304 and form a pad 1302 in the pad opening OP2.

In the above embodiments, the heater 1200 of the memory chip 1000 is formed after the upper interconnect structure 1034 is formed. In other embodiments, the heater 1200 of the memory chip 1000 may be formed before the upper interconnect structure 1034 is formed.

Please refer to FIG. 4C. The heater 1200 of the memory chip 1000 is formed after the gate stack structure 52 of the three-dimensional flash memory 1100 is formed. The upper interconnection structure 1034 (including the local bit line LBL _n and the local source line LSL _n and the separation trench 1110 formed between the gate stack structure 52 before the formation of the global bit line GBL _n and the global source line GSL _n ).

Referring to FIGS. 4A and 4C , the heater 1200 is formed by, for example, first forming a lining material layer in the separation trench 1110 . The lining material layer is, for example, silicon oxide or silicon nitride. Then, a barrier material layer and a metal material layer are sequentially formed on the gate stack structure 52 and in the separation trench 1110 . Then a planarization process, such as a chemical mechanical planarization process, is performed to remove the barrier material layer and the metal material layer on the surface of the gate stack structure 52, and form an insulating liner 1112 and a barrier in the separation trench 1110. layer 1204 and metal layer 1202. The metal material layer is, for example, copper or tungsten. The barrier material layer is, for example, titanium, tantalum, titanium nitride, tantalum nitride or combinations thereof.

4B and 4C , after the heater 1200 is formed, the upper interconnect structure 1034 (including local bit lines LBL _n , local source lines LSL _{n ,} and global bit lines GBL _n and global source lines GSL _n ) is formed. Then, a bonding layer 1300 is formed on the upper interconnect structure 1034 according to the above method.

Referring to FIG. 7A, multiple control chips 2000 are provided. The control wafer 2000 is formed as follows. Referring to FIG. 5C , a second transistor 2020 is formed on the second substrate (wafer) 2010 . Next, a second interconnect structure 2030 is formed on the second transistor 2020. The second interconnect structure 2030 can be formed by any known method, such as damascene, dual damascene, etc. Thereafter, the bonding layer 2050 is formed on the second interconnect structure 2030 according to the above method. After that, cutting is performed to form a plurality of control wafers 2000.

7B , the bonding layer 2050 of the plurality of control chips 2000 is bonded to the bonding layer 1300 of the memory chip 1000 to form a bonding structure 3000. The bonding method is, for example, a hybrid bonding process. In some embodiments, after the plurality of control chips 2000 are bonded to the memory chip 1000 on the wafer 1010W, an encapsulation layer (not shown) is formed around the sidewalls of the plurality of control chips 2000.

Please refer to FIG. 7C , a cutting process is performed to form a plurality of independent three-dimensional flash memory module chips 5000 .

In summary, the present invention combines a memory chip with a control chip to form a three-dimensional flash memory module chip. By providing a high drive current through the driver of the control chip to heat the heater in the memory chip, the charge storage structure of the flash memory can be repaired to achieve a faster erase speed and improve the durability of the flash memory. Furthermore, the control chip can locally heat the corresponding block according to the state signal of the control logic unit of the memory chip. In addition, for this three-dimensional flash memory module chip formed by bonding, the control chip can be manufactured separately without forming a large-area heater controller in the memory chip. Therefore, the heater controller can be prevented from occupying the area of the memory chip, and the control chip can be manufactured with a lower-level process to reduce the cost of the process.

14: tunneling layer 16: channel column 20: memory cell 24: insulating filling layer 28: insulating column 32a: conductor column/source column 32b: conductor column/drain column 34: horizontal opening 36: blocking layer 37, 1204: barrier layer 38, 2028: gate layer 40: charge storage structure 52: gate stack structure 54, 13 04, 2054: insulating layer 1000: memory chip 1010: first substrate 1010W: wafer 1020: first transistor 1020: active element 1030: first internal connection structure 1032: lower internal connection structure 1034: upper internal connection structure 1040, 2031: dielectric layer 1100, 1100 ₁ , 1100 ₂ : 3D flash memory structure 1110 : separation trench 1112 : insulation liner 1200 , 1200 ₁ , 1200 ₂ , 1200 ₃ : heater 1202 : metal layer 1300 , 2050 : bonding layer 3000 : bonding structure 1302 , 1302 a , 1302 b , 2052 , 2052 a , 2052 b : pad 2000 : control chip 2000C , 2000C ₁ , 2000C ₂ : Row 2000R: Driving row 2010: Second substrate 2012: Active region 2020, 20201: Second transistor 2022a: Source region 2022b: Drain region 2024: Gate dielectric layer 2030: Second internal connection structure 2032, 2034, C1, C2, C3: Contact window 2036, 2040, 2040a, 2040b, 2040c: Conductor 2038, 2042, 2042a, 2042b: Interlayer window 2100: Global power supply 2200: Row decoder 2300: Row decoder 5000: Three-dimensional flash memory module chip A0, A1, A2: Row address signal A 3. A4: row address signal AR: array area B, B1, B2, B3, B4: block BM1: lower first metal layer BM2: lower second metal layer BM3: lower third metal layer BV1, BV2, TV1: via TM1: upper first metal layer TM2: upper second metal layer E1: first end E2: second end OP1: trench OP2: pad opening SC: step structure SL: cutting line SLT: separation slit SR: step area T, T', T1, T1', T2, T2', T3, T3', T4, T4': block W1, W2: width I-I', II-II': line X, Y, Z: direction

FIG. 1A and FIG. 1B are three-dimensional schematic diagrams of a three-dimensional flash memory module chip according to an embodiment of the present invention. FIG. 2A is a partial top view of a three-dimensional flash memory structure of a memory chip according to an embodiment of the present invention. FIG. 2B is a cross-sectional view of line I-I’ of FIG. 2A. FIG. 3A is a partial top view of a memory chip with a heater according to another embodiment of the present invention. FIG. 3B is a cross-sectional view of line I-I’ of FIG. 3A. FIG. 4A is a partial top view of a memory chip with a heater according to another embodiment of the present invention. FIG. 4B is a partial top view of a heater and a pad of a memory chip according to another embodiment of the present invention. FIG. 4C is a cross-sectional view of line II-II’ of FIG. 4B. Figures 5A to 5E are various three-dimensional schematic diagrams of a control chip according to an embodiment of the present invention. Figure 6A is a three-dimensional schematic diagram of a memory chip and a control chip according to an embodiment of the present invention. Figure 6B is a partial circuit schematic diagram of Figure 6A. Figures 7A to 7C show cross-sectional schematic diagrams of the manufacturing process of the three-dimensional flash memory module chip of the present invention. Figure 8 is a three-dimensional schematic diagram of another control chip according to an embodiment of the present invention.

1000:Memory chip

1100, 1100 ₁ : Three-dimensional flash memory structure

1200, 1200 ₁ : heater

1300, 2050: Joint layer

1302, 1302a, 1302b, 2052, 2052a, 2052b: pads

1304, 2054: Insulation layer

2000:Control chip

3000:Joint structure

5000: 3D flash memory module chip

B1, B2, B3, B4: Blocks

E1: first end

E2: Second end

X, Y, Z: direction

Claims (14)

A three-dimensional flash memory module chip comprises: a memory chip, comprising: a plurality of blocks, each block comprising a plurality of three-dimensional flash memory structures; and a plurality of heaters; a control chip, coupled to the memory chip, for driving at least one of the plurality of heaters, wherein the plurality of heaters are arranged above the plurality of three-dimensional flash memory structures and adjacent to the control chip. A three-dimensional flash memory module chip as described in claim 1, wherein the memory chip further comprises: a plurality of first transistors located on a first substrate; a plurality of three-dimensional flash memory structures located above the plurality of first transistors; and a first internal connection structure, wherein the plurality of three-dimensional flash memory structures are buried in the first internal connection structure. The three-dimensional flash memory module chip as described in claim 2, wherein the first internal connection structure includes: a lower internal connection structure, located between the multiple three-dimensional flash memory structures and the multiple first transistors, and electrically connecting the multiple three-dimensional flash memory structures and the multiple first transistors; and an upper internal connection structure, located on the multiple three-dimensional flash memory structures, and electrically connecting the multiple three-dimensional flash memory structures. A three-dimensional flash memory module chip as described in claim 2, wherein the control chip comprises: a plurality of drive columns, wherein each drive column comprises: a second transistor, located on a second substrate, wherein the source region of the second transistor is electrically connected to a global power source; a first pad, electrically connected to the drain region of the second transistor, and electrically connected to a first end of one of the plurality of heaters; and a second pad, wherein the second pad is grounded and electrically connected to a second end of the one of the plurality of heaters. The three-dimensional flash memory module chip as described in claim 4, wherein the control chip further includes: a column decoder electrically coupled to the multiple gate layers of the multiple second transistors of the multiple drive columns; and a row decoder electrically coupled to the multiple source regions of the multiple second transistors and the global power supply. The three-dimensional flash memory module chip according to claim 4, wherein the control chip includes a plurality of block cells arranged in an array, wherein the plurality of sources of the plurality of second transistors of the plurality of block cells in the same row The polar regions are electrically connected to each other. A three-dimensional flash memory module chip as described in claim 4, wherein the control chip and the memory chip are bonded via a bonding structure. The three-dimensional flash memory module chip of claim 1, wherein the plurality of three-dimensional flash memory structures include a plurality of three-dimensional AND flash memory structures, a three-dimensional NAND flash memory structure or a plurality of three-dimensional NOR Flash memory structure. A method of manufacturing a three-dimensional flash memory module chip, including: forming a memory chip, including: forming a plurality of blocks on a first substrate, each block including a plurality of three-dimensional flash memory structures; and forming a plurality of heating forming a control chip; and bonding the control chip and the memory chip, wherein the control chip is used to drive the plurality of heaters, wherein the plurality of heaters are formed in the plurality of three-dimensional flash memories above the body structure. The manufacturing method of the three-dimensional flash memory module chip as described in claim 9, wherein forming the memory chip further includes: forming a plurality of first transistors on the first substrate; and forming the plurality of three-dimensional flash memory structures on the plurality of first transistors. The manufacturing method of a three-dimensional flash memory module chip according to claim 10, wherein forming the control chip includes: forming a plurality of driving columns, wherein forming each driving column includes: forming a second transistor, and forming a second transistor on the second transistor. on the substrate; Forming a second interconnect structure on the second transistor, wherein the source region of the second transistor is electrically coupled to the global power supply through the second interconnect structure; forming a first pad, On the second interconnect structure, the first pad is electrically connected to the drain region of the second transistor through the second interconnect structure; and a second pad is formed on the second interconnect structure. On the second interconnect structure, the second pad is electrically connected to ground via the second interconnect structure. The manufacturing method of the three-dimensional flash memory module chip as described in claim 11 further includes: electrically connecting the first pad to the first end of one of the multiple heaters; and electrically connecting the second pad to the second end of the one of the multiple heaters. The manufacturing method of the three-dimensional flash memory module chip as described in claim 9, wherein the control chip and the memory chip are hybrid-bonded via a bonding structure. The manufacturing method of a three-dimensional flash memory module chip as claimed in claim 9, wherein the plurality of three-dimensional flash memory structures include a plurality of three-dimensional AND flash memory structures, three-dimensional NAND flash memory structures or multiple A three-dimensional NOR flash memory structure.

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