TW202318645A - 3d flash memory module chip and method of fabricating the same - Google Patents

Abstract

A 3D flash memory module chip includes a memory chip and a control chip. The memory chip includes a plurality of tiles and a plurality of heaters. The tiles each include a plurality of 3D flash memory structures. The heaters are disposed around the 3D flash memory structures of each of the tiles. The control chip is bonded with the memory chip to drive at least one of the heaters.

Description

Three-dimensional flash memory module chip and its manufacturing method

The present invention relates to a memory module and its manufacturing method, and in particular to a three-dimensional flash memory module and its manufacturing method.

Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it is widely used in personal computers and other electronic devices. The 3D memory commonly used in the industry currently includes Negative OR (NOR) memory and Negative AND (NAND) memory. In addition, another type of three-dimensional memory is AND memory, which can be applied in a multi-dimensional memory array and has high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become a current trend.

The invention provides a three-dimensional flash memory module chip and a manufacturing method thereof, which can perform healing on a part of the flash memory.

In an embodiment of the present invention, a three-dimensional flash memory module chip includes: a memory chip and a control chip. The memory chip includes: a plurality of blocks, each of which includes a plurality of three-dimensional flash memory structures; and a plurality of heaters, arranged on the plurality of three-dimensional flash memory structures of each block around. The control chip is bonded to the memory chip to drive at least one of the plurality of heaters.

In one embodiment of the present invention, a method for manufacturing a three-dimensional flash memory module chip includes: forming a memory chip, including: forming a plurality of blocks on a first substrate, each block including a plurality of three-dimensional a flash memory structure; and forming a plurality of heaters around the plurality of three-dimensional flash memory structures of each block; forming a control chip; and bonding the control chip and the memory chip, wherein the The control chip is used to drive the plurality of heaters.

Based on the above, in the three-dimensional flash memory module chip and its manufacturing method of the present invention, an additional control chip is used to drive the heater to perform local repair processing on each block of the flash memory. The control chip can be manufactured separately to avoid the area of the memory chip occupied by the heater controller, and the control chip can be manufactured with a lower process to reduce the cost of the process.

The performance of the flash memory will obviously decrease after being operated many times, so the flash memory needs to be repaired (healing). The repair process may use a heater to heat the flash memory to repair the charge storage structure (eg nitride layer) of the flash memory. In current technologies, word lines are mostly used as heaters. However, due to the large number of word lines and the complex configuration relationship with other components (such as word line decoders), the layout design of the flash memory structure is relatively difficult.

Embodiments of the present invention provide several types of three-dimensional flash memory module chips. The heater is arranged above or around the sidewall of the three-dimensional flash memory structure of the memory chip, and the memory chip is bonded to the control chip to control the The wafer drives the heater to repair the local area of the memory wafer.

FIG. 1A and FIG. 1B are three-dimensional schematic diagrams of a three-dimensional flash memory module chip according to an embodiment of the present invention. FIG. 2A is a partial top view of a three-dimensional flash memory structure of a memory chip according to an embodiment of the present invention. Fig. 2B is a cross-sectional view along line I-I' of Fig. 2A. 3A is a partial top view of a memory chip with a heater according to another embodiment of the present invention. Fig. 3B is a cross-sectional view along line I-I' of Fig. 3A.

Referring to FIG. 1A and FIG. 1B , a three-dimensional flash memory module chip (also called a three-dimensional integrated circuit, 3DIC) 5000 according to an embodiment of the present invention includes: a memory chip 1000 and a control chip 2000 . The memory chip 1000 includes a plurality of three-dimensional flash memory structures 1100 and a plurality of heaters 1200 . A plurality of heaters 1200 are disposed around the plurality of three-dimensional flash memory structures 1100 . In some embodiments, multiple heaters 1200 are disposed above multiple three-dimensional flash memory structures 1100, as shown in FIG. 1A. In some other embodiments, a plurality of heaters 1200 are disposed in the separation trenches 1110 between the plurality of three-dimensional flash memory structures 1100, as shown in FIG. 1B . The control chip 2000 is disposed above the memory chip 1000 for driving the heater 1200 in the memory chip 1000 . The control chip 2000 and the memory chip 1000 can be bonded to each other through the bonding structure 3000 .

Please refer to FIG. 1A and FIG. 1B, the three-dimensional flash memory structure 1100 of the memory chip 1000 may be a three-dimensional AND flash memory structure (as shown in FIG. 2A and FIG. 2B ), a three-dimensional NAND flash memory structure (not shown ) or a three-dimensional NOR flash memory structure (not shown). The following uses a three-dimensional AND flash memory structure as an example to illustrate the three-dimensional flash memory structure 1100 of the present invention, however, the embodiment of the present invention is not limited thereto.

Referring to FIG. 2A and FIG. 2B , the memory chip 1000 may include a plurality of blocks T. Referring to FIG. These block elements T can be arranged into an array including a plurality of rows and a plurality of columns. In this embodiment, four block elements T (for example, T1 - T4 ) are used for illustration. Among the four blocks T, block T1 and block T2 are arranged in one row; block T3 and block T4 are arranged in another row. Block T1 and block T3 are arranged in one row; block T2 and block T4 are arranged in another row. Each block T may include a plurality of blocks B (for example, B1 - B4 ). Each block B includes a 3D flash memory structure 1100 . A plurality of three-dimensional flash memory structures 1100 extend in the X direction and are arranged in the Y direction. Two adjacent three-dimensional flash memory structures 1100 are separated from each other by a separation trench 1110 .

Referring to FIG. 2B , each three-dimensional flash memory structure 1100 may include at least one memory array formed by a plurality of memory cells. In more detail, the three-dimensional flash memory structure 1100 can be disposed above one or more active devices (eg, the first transistor 1020 ) on the first substrate (eg, a semiconductor substrate) 1010 . The first transistor 1020 is, for example, a complementary metal oxide semiconductor field effect transistor (CMOS). Therefore, this structure can also be called a CMOS under Array (CUA) structure.

Referring to FIG. 2B , the three-dimensional flash memory structure 1100 can be disposed in the back end of line (BEOL) of the semiconductor die. For example, the 3D flash memory structure 1100 can be embedded in the first interconnection structure 1030 . The first interconnection structure 1030 includes, for example, a lower interconnection structure 1032 and an upper interconnection structure 1034 . The lower interconnection structure 1032 is disposed above one or more active devices (eg, first transistors 1020 ) on the first substrate (eg, semiconductor substrate) 1010 and below the memory array of the 3D flash memory structure 1100 . The upper interconnect structure 1034 is disposed above the memory array of the 3D flash memory structure 1100 . The lower interconnection structure 1032 , for example, includes a lower first metal layer BM1 , a lower second metal layer BM2 , and a lower third metal layer BM3 , and vias BV1 and BV2 between them. The upper interconnection structure 1034 includes, for example, the upper first metal layer TM1 and the upper second metal layer TM2 , and a via TV1 between them. The number of metal layers and vias of the lower interconnection structure 1032 and the upper interconnection structure 1034 are not limited to the above.

Referring to FIG. 2B , the three-dimensional flash memory structure 1100 includes a plurality of gate stack structures 52 . Each gate stack structure 52 is formed on the lower interconnect structure 1032 . Each gate stack structure 52 extends in the X direction from the array region AR of the first substrate 1010 to the step region SR. The gate stack structure 52 includes a plurality of gate layers (also referred to as word lines) 38 and multiple layers of insulating layers 54 vertically stacked on the surface of the first substrate 1010 . In the Z direction, the gate layers 38 are electrically isolated by an insulating layer 54 disposed between them. The gate layer 38 includes a metal layer such as tungsten. In some embodiments, the gate layer 38 further includes a barrier layer 37 , such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The insulating layer 54 is, for example, silicon oxide.

The gate layer 38 extends in a direction parallel to the surface of the first substrate 1010 (shown in FIG. 2D ). The gate layer 38 in the stepped region SR may have a stepped structure SC (shown in FIG. 2B ), so that the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally out of the upper portion. end of gate layer 38 . The contact window C1 for connecting the gate layer 38 can be landed on the end of the gate layer 38 located in the step region SR, so as to connect each gate layer 38 to the lower interconnection through the contact window C1 and the upper interconnection structure 1034 Each wire of the structure 1032 is, for example, a wire of the lower third metal layer BM3.

Please refer to FIG. 2B , the three-dimensional flash memory structure 1100 further includes a plurality of channel pillars 16 . The channel pillar 16 extends continuously through the gate stack structure 52 of the array region AR. In some embodiments, the channel post 16 may have a ring-shaped profile when viewed from above. The material of the channel pillar 16 can be semiconductor, such as undoped polysilicon.

Please refer to FIG. 2B, the three-dimensional flash memory structure 1100 also includes an insulating filling layer 24, an insulating column 28, a plurality of conductor columns (for example, as a source column) 32a, and a plurality of conductor columns (for example, as a drain column) ) 32b. The conductive columns 32 a and 32 b and the insulating column 28 are disposed in the channel column 16 and each extends in a direction perpendicular to the gate layer 38 (ie, the Z direction). The conductive pillars 32 a and 32 b are separated from the insulating pillar 28 by the insulating filling layer 24 , and are electrically coupled to the channel pillar 16 . The conductor pillars 32a and 32b are, for example, doped polysilicon. The insulating filling layer 24 is, for example, silicon oxide; the insulating pillar 28 is, for example, silicon nitride.

Referring to FIG. 2B , the charge storage structure 40 is disposed between the channel pillar 16 and the multilayer gate layer 38 . The charge storage structure 40 may include a tunneling layer (or called a bandgap engineered tunnel oxide layer) 14 , a charge storage layer 12 and a blocking layer 36 . The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36 . In some embodiments, the tunneling layer 14 , the charge storage layer 12 and the blocking layer 36 are, for example, silicon oxide, silicon nitride, and silicon oxide. In some embodiments, a part of the charge storage structure 40 (for example, the tunneling layer 14 ) extends continuously in a direction perpendicular to the gate layer 38 (ie, the Z direction), while another part of the charge storage structure 40 (for example, the charge The storage layer 12 and the barrier layer 36) surround the gate layer 38, as shown in FIG. 2B. In other embodiments, the charge storage structure 40 (such as the tunneling layer 14 , the charge storage layer 12 and the blocking layer 36 ) surrounds the gate layer 38 (not shown). Each gate layer 38 and its surrounding charge storage structure 40 , channel pillar 16 , and source pillar 32 a and drain pillar 32 b define a memory cell 20 . Therefore, each three-dimensional flash memory structure 1100 includes at least one memory array composed of a plurality of memory units 20 .

The 3D flash memory structure 1100 further includes local bit lines LBL _n and local source lines LSL _n and global bit lines GBL _n and global source lines GSL _n . The local bit line _LBLn and the local source line _LSLn are located on the upper first metal layer TM1 of the upper interconnection structure 1034, and are electrically connected to the source column 32a and the drain column 32b through the contact window C2, respectively. The global bit line GBL _n and the global source line GSL _n are electrically connected to the local bit line LBL _n and the local source line LSL _n respectively via an upper via (not shown) in the upper interconnection structure 1034 .

The memory unit 20 can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column 32a and the drain column 32b, since the source column 32a and the drain column 32b are connected to the channel column 16, electrons can be transmitted along the channel column 16 and stored in the entire charge storage In the structure 40, a 1-bit operation can be performed on the memory unit 20 in this way. In addition, for the operation utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and the drain post 32b. . For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electrons can be Or the holes are locally trapped in the charge storage structure 40 adjacent to one of the two source posts 32a and drain posts 32b, so that the unit cell (SLC, 1 bit) or multiple Bit cell (MLC, greater than or equal to 2 bits) operations.

In operation, a voltage is applied to a selected word line (gate layer) 38 , such as when a corresponding threshold voltage (V _th ) higher than that of the corresponding memory cell 20 is applied, intersecting the selected word line 38 The channel region of the channel pillar 16 is turned on, allowing current to enter the drain pillar 32b from the bit line _BLn , flow through the turned on channel region to the source pillar 32a, and finally flow to the source line _SLn .

Please refer to FIG. 3A and FIG. 3B , the memory chip 1000 further includes a plurality of heaters 1200 . The heater 1200 may be disposed in the dielectric layer 1040 above the three-dimensional flash memory structure 1100 . The material of the dielectric layer 1040 is, for example, silicon oxide. The heater 1200 includes a metal layer 1202, such as copper or tungsten. In some embodiments, the heater 1200 further includes a barrier layer 1204, such as titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof.

Referring to FIG. 3A , in some embodiments, a single heater 1200 is disposed on each block B, and the two heaters 1200 of any two adjacent blocks B are separated from each other. The heater 1200 may extend in the X direction. In one embodiment, the heater 1200 is disposed in the array region AR and extends to the stepped region SR (as shown in FIGS. 3A and 3B ). In an embodiment, the heater 1200 may be located in the array area AR, but not in the stepped area SR (not shown). That is, the length of the heater 1200 may be greater than, equal to, or less than the length of the three-dimensional flash memory structure 1100 in the X direction.

In addition, a plurality of heaters 1200 may be disposed on each block B, for example, there is one heater 1200 in the array area AR and the step area SR respectively, and may be heated separately (not shown). However, the embodiments of the present invention are not limited thereto. In another embodiment, multiple heaters 1200 adjacent to two, three or more blocks B can also be combined into a single heater (not shown) to heat multiple blocks B at the same time 1100 of three-dimensional flash memory structures.

Referring to FIG. 3A , the top view shape of the heater 1200 is, for example, a rectangle or other shapes. The plurality of heaters 1200 on the plurality of blocks B may have the same width or different widths. The width W1 of the heater 1200 in the array area AR is the same as the width W2 of the heater 1200 in the stepped area SR. However, the present invention is not limited thereto. The shape of the heater 1200 can be changed according to actual needs or designs. The width W1 of the heater 1200 in the array region AR may be greater than, equal to, or smaller than the width W2 of the heater 1200 in the step region SR.

Referring to FIG. 1A , FIG. 1B and FIG. 3B , the memory chip 1000 further includes a bonding layer 1300 . The bonding layer 1300 includes a pad 1302 and an insulating layer 1304 . An insulating layer 1304 is provided on the heater 1200 . The material of the insulating layer 1304 is, for example, silicon oxide. The pads 1302 are disposed in the insulating layer 1304 on the surface of each heater 1200 . The material of the pad 1302 is copper, for example. The pads 1302 include pads 1302a and 1302b. The pads 1302a and 1302b are respectively connected to the first end E1 and the second end E2 of the heater 1200 .

In the above embodiments, the plurality of three-dimensional flash memory structures 1100 are three-dimensional AND flash memory structures, and the plurality of heaters 1200 are arranged above the three-dimensional AND flash memory structures (as shown in Fig. 3A, Fig. 3B and Figure 6A). In some other embodiments, the plurality of three-dimensional flash memory structures 1100 are three-dimensional AND flash memory structures, and the plurality of heaters 1200 are disposed in the separation trenches 1110 between the three-dimensional AND flash memory structures (such as Figures 4A to 4C).

FIG. 4A is a partial top view of a memory chip with a heater according to another embodiment of the present invention. 4B is a partial top view of a heater and pads of a memory chip according to another embodiment of the present invention. Fig. 4C is a sectional view taken along line II-II' of Fig. 4B.

Referring to FIG. 4A and FIG. 4C , a plurality of heaters 1200 are disposed in the separation trenches 1110 between the three-dimensional flash memory structures 1100 . The heater 1200 is disposed around the plurality of gate layers 38 and the multi-layer insulating layer 54 of the gate stack structure 52 . The heater 1200 is separated from the plurality of gate layers 38 and the multilayer insulating layer 54 by an insulating liner 1112 (as shown in FIG. 4C ). The insulating liner 1112 includes insulating materials such as silicon oxide or silicon nitride. The heater 1200 includes a metal layer 1202 (as shown in FIG. 4C ), such as copper or tungsten. In some embodiments, the heater 1200 also includes a barrier layer 1204 (as shown in FIG. 4C ). The barrier layer 1204 is located between the insulating liner 1112 and the metal layer 1202 . The barrier layer 1204 is, for example, titanium, tantalum, titanium nitride, tantalum nitride or combinations thereof.

In some embodiments, a single heater 1200 is disposed in each separation trench 1110 . For example, the heater 1200 may extend in the X direction. In one embodiment, the heater 1200 is disposed in the array region AR and extends to the stepped region SR (as shown in FIGS. 4A and 4B ). In an embodiment, the heater 1200 may be located in the array area AR, but not in the stepped area SR (not shown). That is, the length of the heater 1200 may be greater than, equal to, or less than the length of the three-dimensional flash memory structure 1100 in the X direction.

Alternatively, a plurality of heaters 1200 may be disposed in each separation trench 1110 , for example, there is one heater 1200 in the array area AR and the step area SR respectively, and may be heated separately (not shown). However, the embodiments of the present invention are not limited thereto.

Please refer to FIG. 4A , in addition, the top view shape of the heater 1200 is, for example, a rectangle or other shapes. The plurality of heaters 1200 in the plurality of separation trenches 1110 may have the same width or different widths. However, the present invention is not limited thereto. The shape of the heater 1200 can be changed according to actual needs or designs.

Referring to FIG. 4B and FIG. 4C , contact windows C3 are respectively provided on the surfaces of the two ends (ie E1 and E2 ) of each heater 1200 . The contact window C3 can be connected to the upper pads 1302a and 1302b via the upper interconnection structure 1034, so that the heater 1200 of the memory chip 1000 can be electrically connected to the control chip 2000 through the upper interconnection structure 1034 and the pads 1302a, 1302b. connect. The material of the pads 1302a and 1302b is copper, for example.

5A to 5E are various perspective views of a control chip according to an embodiment of the present invention. FIG. 6A is a schematic perspective view of a memory chip and a control chip according to an embodiment of the present invention. FIG. 6B is a schematic circuit diagram of FIG. 6A.

Referring to FIG. 5A, the control chip 2000 may include a plurality of blocks T'. These block elements T' may be arranged in an array. In this embodiment, four block elements T' (such as T1'~T4') are taken as an example for illustration. Among the four block elements T', block element T1' and block element T2' are arranged in one column; block element T3' and block element T4' are arranged in another column. Block T1' and block T3' are arranged in one row; block T2' and block T4' are arranged in another row.

Referring to FIG. 5A and FIG. 5E, each block T' includes a plurality of driving columns 2000R and rows 2000C. Each driving column 2000R includes a second transistor 2020 , a second interconnection structure 2030 and a pad 2052 , as shown in FIG. 5E . The second transistor 2020 is disposed on the active region 2012 of the second substrate 2010 . The second substrate 2010 may be a semiconductor substrate, such as a silicon substrate. The second transistor 2020 may be a complementary metal oxide semiconductor (CMOS) transistor. The second transistor 2020 can be a planar transistor (as shown in FIGS. 5A to 5E ) or a fin transistor (as shown in FIG. 8 ).

Referring to FIG. 5B and FIG. 5E and FIG. 8 , the second transistor 2020 includes a gate dielectric layer 2024 , a gate layer 2028 , a source region 2022 a and a drain region 2022 b. The gate dielectric layer 2024 is, for example, silicon oxide or high dielectric constant material. The gate layer 2028 is, for example, doped polysilicon or tungsten. The gate layer 2028 is located on the gate dielectric layer 2024 . The gate layer 2028 is strip-shaped, and its extending direction is, for example, the same as that of the heater 1200 , such as extending in the X direction, as shown in FIG. 6A . In some examples, the gate layers 2028 of the second transistors 2020 in two adjacent columns (such as blocks T1 ′ and T2 ′, or blocks T3 ′ and T4 ′) can be electrically connected, as shown in FIG. 5A .

Referring to FIG. 5E , the source region 2022 a and the drain region 2022 b of the second transistor 2020 are disposed in the active region 2012 on both sides of the gate layer 2028 . The source region 2022a and the drain region 2022b have dopants, such as N-type or P-type dopants. In some embodiments, two adjacent second transistors 2020 share the source region 2022a.

Referring to FIG. 5B and FIG. 5C , the second interconnection structure 2030 is located on the plurality of second transistors 2020 . The second interconnect structure 2030 includes a dielectric layer 2031 (as shown in FIG. 5C ), and a plurality of contact windows 2032, 2034, a plurality of wires 2036, 2040 and a plurality of via windows 2038, located in the dielectric layer 2031. 2042. A plurality of contact windows 2032 respectively land on the source region 2022a and the drain region 2022b, and are electrically connected to the source region 2022a and the drain region 2022b. The contact 2034 lands on the gate layer 2028 and is electrically connected to the gate layer 2028 . The contact window 2032 is strip-shaped, which extends along the X direction and is roughly parallel to the gate layer 2028 , as shown in FIG. 5B and FIG. 5D . The shape of the contact window 2034 is different from that of the contact window 2032 , and its shape is, for example, columnar, as shown in FIG. 5B . The conductive wires 2036 and 2040 (as shown in FIG. 5C ) are disposed on the contact windows 2032 and 2034 respectively. The wire 2036 is electrically insulated from the wire 2040 by a via 2038 . The via window 2042 is disposed on the wire 2040 and electrically connects the wire 2040 to the upper bonding layer 2050 . The dielectric layer 2031 is, for example, silicon oxide. The plurality of contacts 2032, 2034, the plurality of wires 2036, 2040 and the plurality of vias 2038, 2042 include metal layers such as tungsten or copper. The plurality of contacts 2032, 2034, the plurality of wires 2036, 2040 and the plurality of vias 2038, 2042 may further include a barrier layer (not shown) such as titanium, tantalum, titanium nitride, tantalum nitride or a combination thereof .

Referring to FIG. 5C , the pads 2052 of each driving column 2000R are part of the bonding layer 2050 of the control chip 2000 . The bonding layer 2050 includes a pad 2052 and an insulating layer 2054 . The insulating layer 2054 is located on the second interconnection structure 2030 . The pad 2052 is located in the insulating layer 2054 and is electrically connected to the via 2042 of the second interconnection structure 2030 . The material of the pad 2052 is copper, for example. The material of the insulating layer 2054 is, for example, silicon oxide.

Referring to FIG. 5A and FIG. 5E , the pad 2052 includes a pad 2052 a and a pad 2052 b. More specifically, each driving column 2000R includes a pair of pads 2052 a and 2052 b disposed along the X direction. The pad 2052a is electrically connected to the first end E1 of the heater 1200; the pad 2052b is electrically connected to the second end E2 of the heater 1200 to ground, as shown in FIGS. 1A, 1B and 6A. Referring to FIG. 5C and FIG. 5D , each pad 2052 a is electrically connected to the wire 2040 a below it via the via 2042 a. The wires 2040a in the same block T' are separated and electrically isolated from each other, so as to be electrically connected to the drain region 2022b of the second transistor 2020, as shown in FIG. 5A and FIG. 5C . Each pad 2052b is electrically connected to the wire 2040b below it via the via 2042b, as shown in FIG. 5D. The plurality of pads 2052b of the block T' in the same row (such as block T1' and T3', or block T2' and T4') are electrically connected to the ground through the same wire 2040b, as shown in FIG. 5A and FIG. 5D Show.

Referring to FIG. 5C , FIG. 1A and FIG. 1B , the bonding layer 2050 of the control chip 2000 and the bonding layer 1300 of the memory chip 1000 are bonded to form a bonding structure 3000 . More specifically, the position of the insulating layer 2054 of the control chip 2000 corresponds to the position of the insulating layer 1304 of the memory chip 1000 and is bonded to each other. The positions of the pads 2052 a and 2052 b of the control chip 2000 correspond to the positions of the pads 1302 a and 1302 b of the memory chip 1000 , and are bonded to each other.

Please refer to FIG. 5A, FIG. 5C and FIG. 5D, the row 2000C of the control chip 2000 connects multiple blocks T' (for example, T1' and T3', or T2' and T4') of the same row via wires 2040c. The multiple common source regions 2022 a of the second transistor 2020 are electrically coupled to the global power supply 2100 .

Referring to FIG. 5E , the drain region 2022 b of the second transistor 2020 of the control chip 2000 is connected to the second interconnect structure 2030 and the pad 2052 a of the bonding layer 2050 , as shown in FIG. 5C . The pad 2052 a is electrically connected to the pad 1302 a connected to the first end E1 of the heater 1200 of the memory chip 1000 , as shown in FIG. 6A . In one embodiment, each driving row 2000R of the control chip 2000 can control a heater 1200 of a corresponding block B of the memory chip 1000 , as shown in FIGS. 6A and 6B .

Referring to FIG. 5E , in some embodiments, the control chip 2000 further includes a row decoder 2300 and a column decoder 2200 . The row decoder 2300 is electrically connected to the global power supply 2100 . After receiving the row address signals A3 and A4, the row decoder 2300 selects multiple blocks (two in this example, such as block T1' and T3' of FIG. 5A ) in one row (for example, row 2000C ₁ in FIG. 5A ). ). In this way, the global power supply 2100 is provided to each block (such as block T1 of FIG. 5A ) of the selected row (such as row 2000C ₁ of FIG. 5A ) via the wire 2040c (shown in FIG. 5A ) of the second interconnection structure 2030 'and T3') the multiple common source regions 2022a of the multiple second transistors 2020 . The column decoder 2200 is electrically connected to the gate layers 2028 of the second transistors 2020 driving the columns 2000R. After receiving the column address signals A0~A2 (or control signals), the column decoder 2200 decodes the input column address signals to select one of the plurality of second transistors 2020 (such as the second transistor 2020 in FIG. 5A ). Transistor 2020 ₁ ) or more and turn it on.

Generally speaking, the memory chip 1000 includes a control logic unit for controlling the memory array, and the register in the control logic unit stores the state signal of the erasing times of the memory array of each block B. When the number of times of erasing reaches a predetermined number of times, the status signal will be sent to the control chip 2000 .

Please refer to FIG. 6A and FIG. 6B. During the repair process, the control chip 2000 can generate the block T and block B that need to be repaired based on the received status signal (for example, block B1 of block T1 in FIG. 6A ). The corresponding column address signal and row address signal, and the column address signal and row address signal are sent to the column decoder 2200 and the row decoder 2300 respectively. The row decoder 2300 selects one of the rows (such as the row 2000C ₁ in FIG. 6A ) according to _the received row address signal, thereby providing the global power supply 2100 to the block element (such as The conductor 2040c of block elements T1' and T3' of FIG. 5A. The column decoder 2200 selects a second transistor 2020 ₁ driving the column 2000R ₁ and turns it on according to the received column address signal. Therefore, current can flow from the global power supply 2100 into the source region 2022a of the second transistor ₂₀₂₀₁ through the wire 2040c, and pass through the channel and drain region 2022b of the second transistor ₂₀₂₀₁ , and through the second interconnection structure 2030 and the connection. The pad 2052a flows into the pad 1302a of the memory chip 1000 and enters the first end E1 of the heater 1200 (eg, 1200 ₁ ). Afterwards, the current passes through the heater 1200 ₁ , flows out from the second end E2 of the heater 1200 ₁ , passes through the pad 1302b of the memory chip 1000, and then enters the pad 2052b of the control chip 2000, and then is electrically connected through the wire 2040b to ground. In the embodiment of the present invention, by controlling the second transistor (driver) 2020 (for example, 2020 ₁ ) of the chip 2000, a high driving current can be provided to a specific heater 1200 (for example, 1200 ₁ ), so that the heater 1200 ( Conductors such as 1200 ₁ ) are heated to repair the charge storage layer in the 3D flash memory structure 1100 of a specific block B (eg, B1 ) in a specific block T (eg, T1 ).

Please refer to FIG. 1A and FIG. 1B. In some embodiments, during the repair process, a single heater 1200 (for example, 1200 ₁ ) can be driven by the control chip 2000 to repair a single block B (for example, B1). The charge storage layer in the three-dimensional flash memory structure 1100 (eg, 1100 ₁ ). Please refer to FIG. 1B. In some other embodiments, when repairing, two heaters 1200 (for example, 1200 ₂ and 1200 ₃ ) can be simultaneously driven by the control chip 2000 to repair a single block B (for example, B2) The charge storage layer in the three-dimensional flash memory structure 1100 (for example, 1100 ₂ ).

7A to 7C are schematic cross-sectional views showing the manufacturing process of the three-dimensional flash memory module chip of the present invention.

Referring to FIG. 7A , a wafer 1010W is provided, and a plurality of memory chips 1000 are formed on the wafer 1010W. The plurality of memory chips 1000 have scribe lines SL between each other. The method of forming the memory chip 1000 is as follows. Referring to FIG. 3B , one or more active devices (such as first transistors) 1020 are first formed on the wafer 1010W. Next, a lower interconnection structure 1032 is formed on the active device 1020 . The lower interconnection structure 1032 can be formed by any known method, such as damascene, dual damascene and other methods. Afterwards, an insulating stack structure (not shown) formed by alternately stacking insulating layers (such as silicon oxide) 54 and another insulating layer (not shown, such as silicon nitride) is formed on the lower interconnection structure 1032 . Thereafter, the tunneling layer 14, the channel pillar 16, and the conductive pillars 32a and 32b of the charge storage structure 40 can be formed in the insulating stack structure by any known method. The material of the tunneling layer 14 can be a dielectric material, such as silicon oxide. The material of the channel pillar 16 can be a semiconductor, such as undoped polysilicon. The conductor pillars 32a and 32b are, for example, doped polysilicon.

Next, a lithography and etching process is performed to form a separation trench 1110 in the insulating stack structure and divide the insulating stack structure into a plurality of blocks B.

Afterwards, a gate replacement process is performed to form a gate stack structure 52 . First, an etching process is performed to inject an etching solution into the separation trench 1110 to remove another insulating layer in the insulating stack structure to form a plurality of horizontal openings 34 , and then form a gate layer 38 in the horizontal openings 34 . In some embodiments, the charge storage layer 12 and the blocking layer 36 are also formed in the horizontal opening 34 before forming the gate layer 38 . The charge storage layer 12 is, for example, silicon nitride. The barrier layer 36 is, for example, a material with a high dielectric constant greater than or equal to 7, such as aluminum oxide (Al ₁ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxide , lanthanide oxides, or combinations thereof. The gate layer 38 is, for example, tungsten. In some embodiments, barrier layer 37 is also formed before forming multilayer gate layer 38 . The material of the barrier layer 37 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

Next, a separation slit SLT is formed in the separation trench 1110 . The method for forming the separation slit SLT includes filling the insulating filling material on the gate stack structure 52 and the separation trench 1110, and then removing the excess insulating filling material on the gate stack structure 52 through an etch-back process or a planarization process. . The insulating filling material is, for example, silicon oxide.

After that, an upper interconnection structure 1034 (including local bit line LBL _n , local source line LSL _n and global bit line GBL _n and global source line GSL _n ) is formed on the gate stack structure 52 . The upper interconnect structure 1034 can be formed by any known method, such as damascene, dual damascene, etc., which will not be described in detail here.

Please refer to FIG. 3A and FIG. 3B , in this embodiment, in the upper interconnection structure 1034 (including local bit line LBL _n , local source line LSL _n and global bit line GBL _n and global source line GSL _n ) is formed, a heater 1200 is also formed over the upper interconnect structure 1034 . The heater 1200 is formed by, for example, firstly forming the dielectric layer 1040 above the upper interconnection structure 1034 . The material of the dielectric layer 1040 is, for example, silicon oxide. In some embodiments, a planarization process, such as a chemical mechanical planarization process, is also performed to make the dielectric layer 1040 have a flat surface. After that, lithography and etching processes are performed to form a plurality of trenches OP1 in the dielectric layer 1040 . Next, a barrier material layer and a metal material layer are sequentially formed on the dielectric layer 1040 and in the trench. Then a planarization process, such as a chemical mechanical planarization process, is performed to remove the barrier material layer and the metal material layer on the surface of the dielectric layer 1040 to form the barrier layer 1204 and the metal layer 1202 in the trench. The metal material layer is copper or tungsten, for example. The barrier material layer is, for example, titanium, tantalum, titanium nitride, tantalum nitride or combinations thereof.

Referring to FIG. 3B , after the heater 1200 is formed, a bonding layer 1300 is formed. The method of forming the bonding layer 1300 is as follows. An insulating layer 1304 is first formed on the heater 1200 and the dielectric layer 1040 , and then lithography and etching processes are performed to form a plurality of pad openings OP2 in the insulating layer 1304 . The bottom of the pad opening OP2 exposes the heater 1200 . Afterwards, a conductive layer is formed on the insulating layer 1304 and in the pad opening OP2. Then, a planarization process, such as a chemical mechanical planarization process, is performed to remove the conductive layer on the insulating layer 1304 to form the pad 1302 in the pad opening OP2.

In the above embodiments, the heater 1200 of the memory chip 1000 is formed after the upper interconnection structure 1034 is formed. In other embodiments, the heater 1200 of the memory chip 1000 may be formed before the upper interconnection structure 1034 is formed.

Please refer to FIG. 4C, the heater 1200 of the memory chip 1000 is formed after the gate stack structure 52 of the three-dimensional flash memory 1100 is formed, and the upper interconnection structure 1034 (including the local bit line LBL _n , the local source line LSL _n and the global bit line GBL _n and the global source line GSL _n ) are formed in the separation trench 1110 between the gate stack structures 52 .

Please refer to FIG. 4A and FIG. 4C , the formation method of the heater 1200 is, for example, to form a lining material layer in the separation trench 1110 first. The lining material layer is, for example, silicon oxide or silicon nitride. Next, a barrier material layer and a metal material layer are sequentially formed on the gate stack structure 52 and in the separation trench 1110 . Then, a planarization process, such as a chemical mechanical planarization process, is performed to remove the barrier material layer and the metal material layer on the surface of the gate stack structure 52, so as to form an insulating liner 1112 and a barrier layer in the separation trench 1110. layer 1204 and metal layer 1202 . The metal material layer is copper or tungsten, for example. The barrier material layer is, for example, titanium, tantalum, titanium nitride, tantalum nitride or combinations thereof.

4B and 4C, after the heater 1200 is formed, the upper interconnection structure 1034 (including the local bit line LBL _n , the local source line LSL _n , the global bit line GBL _n and the global source line GSL is formed. _n ). Thereafter, the bonding layer 1300 is formed on the upper interconnection structure 1034 according to the method described above.

Referring to FIG. 7A , multiple control chips 2000 are provided. The method of forming the control wafer 2000 is as follows. Referring to FIG. 5C , a second transistor 2020 is formed on a second substrate (wafer) 2010 . Next, a second interconnection structure 2030 is formed on the second transistor 2020 . The second interconnection structure 2030 can be formed by any known method, such as damascene, dual damascene and other methods. Thereafter, a bonding layer 2050 is formed on the second interconnection structure 2030 according to the method described above. After that, dicing is performed to form a plurality of control wafers 2000 .

Referring to FIG. 7B , bonding layers 2050 of a plurality of control chips 2000 and bonding layers 1300 of a memory chip 1000 are bonded to form a bonding structure 3000 . The bonding method is, for example, a hybrid bonding process. In some embodiments, after the plurality of control wafers 2000 are bonded to the memory wafer 1000 on the wafer 1010W, an encapsulation layer (not shown) is also formed around the sidewalls of the plurality of control wafers 2000 .

Referring to FIG. 7C , a dicing process is performed to form a plurality of independent three-dimensional flash memory module chips 5000 .

To sum up, the present invention bonds the memory chip and the control chip to form a three-dimensional flash memory module chip. By controlling the driver of the chip to provide a high driving current to heat the heater in the memory chip, the charge storage structure of the flash memory can be repaired to achieve faster erasing speed and the durability of the flash memory can be improved. Furthermore, the control chip can locally heat the corresponding block according to the state signal of the control logic unit of the memory chip. In addition, the control chip of the three-dimensional flash memory module chip formed by bonding can be fabricated separately without forming a large-area heater controller in the memory chip, so the heater controller can avoid occupying the area of the memory chip , and the control chip can be manufactured with a lower-level process to reduce the cost of the process.

14: Tunneling layer 16: Channel column 20: Memory unit 24: Insulation filling layer 28: Insulation column 32a: Conductor column/source column 32b: Conductor column/drain column 34: Horizontal opening 36: Barrier layer 37, 1204: Barrier layer 38, 2028: gate layer 40: charge storage structure 52: gate stack structure 54, 1304, 2054: insulating layer 1000: memory chip 1010: first substrate 1010W: wafer 1020: first transistor 1020: Active component 1030: first interconnect structure 1032: lower interconnect structure 1034: upper interconnect structure 1040, 2031: dielectric layer 1100, 1100 ₁ , 1100 ₂ : three-dimensional flash memory structure 1110: separation trench 1112: insulating liner 1200, 1200 ₁ , 1200 ₂ , 1200 ₃ : heater 1202: metal layer 1300, 2050: bonding layer 3000: bonding structure 1302, 1302a, 1302b, 2052, 2052a, 2052b: pad 2000: control wafer 2000C, 2000C ₁ , 2000C ₂ : row 2000R: drive column 2010: second substrate 2012: active region 2020, 20201: second transistor 2022a: source region 2022b: drain region 2024: gate dielectric layer 2030: second Interconnect structure 2032, 2034, C1, C2, C3: contact window 2036, 2040, 2040a, 2040b, 2040c: wire 2038, 2042, 2042a, 2042b: via window 2100: global power supply 2200: column decoder 2300: row Decoder 5000: three-dimensional flash memory module chip A0, A1, A2: column address signal A3, A4: row address signal AR: array area B, B1, B2, B3, B4: block BM1: lower part One metal layer BM2: lower second metal layer BM3: lower third metal layer BV1, BV2, TV1: via window TM1: upper first metal layer TM2: upper second metal layer E1: first end E2: second end OP1: Trench OP2: Pad opening SC: Ladder structure SL: Cutting line SLT: Separation slit SR: Ladder area T, T', T1, T1', T2, T2', T3, T3', T4, T4': Block element W1, W2: width I-I', II-II': line X, Y, Z: direction

FIG. 1A and FIG. 1B are three-dimensional schematic diagrams of a three-dimensional flash memory module chip according to an embodiment of the present invention. FIG. 2A is a partial top view of a three-dimensional flash memory structure of a memory chip according to an embodiment of the present invention. Fig. 2B is a cross-sectional view along line I-I' of Fig. 2A. 3A is a partial top view of a memory chip with a heater according to another embodiment of the present invention. Fig. 3B is a cross-sectional view along line I-I' of Fig. 3A. FIG. 4A is a partial top view of a memory chip with a heater according to another embodiment of the present invention. 4B is a partial top view of a heater and pads of a memory chip according to another embodiment of the present invention. Fig. 4C is a sectional view taken along line II-II' of Fig. 4B. 5A to 5E are various perspective views of a control chip according to an embodiment of the present invention. FIG. 6A is a schematic perspective view of a memory chip and a control chip according to an embodiment of the present invention. FIG. 6B is a partial circuit diagram of FIG. 6A. 7A to 7C are schematic cross-sectional views showing the manufacturing process of the three-dimensional flash memory module chip of the present invention. FIG. 8 is a schematic perspective view of another control chip according to an embodiment of the present invention.

1000:memory chip

1100, 1100 ₁ : three-dimensional flash memory structure

1200, 1200 ₁ : heater

1300, 2050: bonding layer

1302, 1302a, 1302b, 2052, 2052a, 2052b: Pads

1304, 2054: insulating layer

2000: Control chip

3000: joint structure

5000: 3D flash memory module chip

B1, B2, B3, B4: blocks

E1: first end

E2: second end

X, Y, Z: direction

Claims (18)

A three-dimensional flash memory module chip, comprising: Memory chips, including: a plurality of blocks, each block comprising a plurality of three-dimensional flash memory structures; and a plurality of heaters disposed around the plurality of three-dimensional flash memory structures of each block; A control chip is bonded to the memory chip and used to drive at least one of the plurality of heaters. The three-dimensional flash memory module chip as claimed in claim 1, wherein the plurality of heaters are disposed above the plurality of three-dimensional flash memory structures and adjacent to the control chip. The three-dimensional flash memory module chip as claimed in claim 1, wherein the plurality of heaters are disposed in the plurality of separation trenches between the plurality of three-dimensional flash memory structures. The three-dimensional flash memory module chip as described in claim 1, wherein the memory chip also includes: a plurality of first transistors located on the first substrate; The plurality of three-dimensional flash memory structures are located above the plurality of first transistors; and The first interconnection structure, wherein the plurality of three-dimensional flash memory structures are buried in the first interconnection structure. The three-dimensional flash memory module chip as described in claim 4, wherein the first interconnection structure comprises: The lower interconnection structure is located between the plurality of three-dimensional flash memory structures and the plurality of first transistors, and is electrically connected to the plurality of three-dimensional flash memory structures and the plurality of first transistors. transistors; and The upper interconnect structure is located on the plurality of 3D flash memory structures and is electrically connected to the plurality of 3D flash memory structures. The three-dimensional flash memory module chip as described in claim 4, wherein the control chip includes: a plurality of drive columns, each of which includes: The second transistor is located on the second substrate, and the source region of the second transistor is electrically connected to the global power supply; a first pad electrically connected to the drain region of the second transistor, and electrically connected to a first end of one of the plurality of heaters; and The second pad is grounded and electrically connected to the second end of the one of the plurality of heaters. The three-dimensional flash memory module chip as described in claim 6, wherein the control chip further includes: a column decoder electrically coupled to the plurality of gate layers of the plurality of second transistors driving the columns; and The row decoder is electrically coupled to the multiple source regions of the multiple second transistors and the global power supply. The three-dimensional flash memory module chip as claimed in item 6, wherein the control chip includes multiple blocks arranged in an array, wherein multiple sources of multiple second transistors of multiple blocks in the same row The polar regions are electrically connected to each other. The three-dimensional flash memory module chip as claimed in claim 6, wherein the control chip and the memory chip are bonded via a bonding structure. The three-dimensional flash memory module chip as claimed in claim 1, wherein the plurality of three-dimensional flash memory structures include a plurality of three-dimensional AND flash memory structures, three-dimensional NAND flash memory structures or multiple three-dimensional NOR Flash memory structure. A method for manufacturing a three-dimensional flash memory module chip, comprising: Form memory chips, including: forming a plurality of blocks on the first substrate, each block including a plurality of three-dimensional flash memory structures; and forming a plurality of heaters around the plurality of three-dimensional flash memory structures of each block; forming a control wafer; and bonding the control chip and the memory chip, wherein the control chip is used to drive the plurality of heaters. The method for manufacturing a three-dimensional flash memory module wafer as claimed in claim 11, wherein the plurality of heaters are formed above the plurality of three-dimensional flash memory structures. The method for manufacturing a three-dimensional flash memory module wafer as claimed in claim 12, wherein the plurality of heaters are formed in a plurality of separation trenches around the plurality of three-dimensional flash memory structures. The manufacturing method of the three-dimensional flash memory module wafer as described in claim 11, wherein forming the memory wafer further includes: forming a plurality of first transistors on the first substrate; and The plurality of three-dimensional flash memory structures are formed above the plurality of first transistors. The manufacturing method of the three-dimensional flash memory module wafer as described in claim 14, wherein forming the control wafer includes: forming a plurality of drive columns, wherein forming each drive column includes: forming a second transistor on the second substrate; forming a second interconnection structure on the second transistor, wherein the source region of the second transistor is electrically coupled to a global power supply through the second interconnection structure; forming a first pad on the second interconnection structure, the first pad is electrically connected to the drain region of the second transistor through the second interconnection structure; and A second pad is formed on the second interconnection structure, and the second pad is electrically connected to ground through the second interconnection structure. The method for manufacturing a three-dimensional flash memory module chip as described in claim 15, further comprising: electrically connecting the first pad to a first end of one of the plurality of heaters; and The second pad is electrically connected to the second end of the one of the plurality of heaters. The method for manufacturing a three-dimensional flash memory module chip as claimed in claim 11, wherein the control chip and the memory chip are hybrid bonded via a bonding structure. The manufacturing method of the three-dimensional flash memory module wafer as described in claim 11, wherein the plurality of three-dimensional flash memory structures include a plurality of three-dimensional AND flash memory structures, three-dimensional NAND flash memory structures or multiple A three-dimensional NOR flash memory structure.

Images