TWI812153B - 製造封裝的方法和封裝 - Google Patents

製造封裝的方法和封裝 Download PDF

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TWI812153B
TWI812153B TW111113599A TW111113599A TWI812153B TW I812153 B TWI812153 B TW I812153B TW 111113599 A TW111113599 A TW 111113599A TW 111113599 A TW111113599 A TW 111113599A TW I812153 B TWI812153 B TW I812153B
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Taiwan
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die
iii
type transistor
semiconductor substrate
package
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TW111113599A
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TW202322408A (zh
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陳建宏
賴昱安
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台灣積體電路製造股份有限公司
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Abstract

一種製造封裝的方法包括將III-V族晶粒直接地接合到互補式金屬氧化物半導體(CMOS)晶粒，以形成晶粒堆疊。III-V族晶粒包括(111)半導體基板和第一電路，第一電路包括形成在(111)半導體基板的表面處的基於III-V族的n型電晶體。CMOS晶粒包括(100)半導體基板，以及在(100)半導體基板上包括n型電晶體和p型電晶體的第二電路。第一電路電性連接到第二電路。

Description

製造封裝的方法和封裝
本揭示內容係關於包含III-V族/矽和矽互補式金屬氧化物半導體積體電路的封裝和其製造方法。
與矽基的電晶體相比，氮化鎵(GaN)n型(N通道)電晶體在實現高性能、高功率效率(例如功率附加效率(Power Added Efficiency,PAE))應用方面具有顯著優越的性能，高性能、高功率效率應用包括射頻(RF)功率放大器、開關、低噪聲放大器，這些裝置的應用包括5G/6G射頻網路和行動裝置。GaN n型電晶體也具有小的形狀因子。
然而，部分由於電洞帶結構，p型GaN電晶體具有比n型GaN電晶體低得多的p型遷移率。因此，製造高電壓GaN互補式裝置電路是不切實際的。
矽互補式金屬氧化物半導體(Complementarity Metal-oxide-semiconductor,CMOS)電路(包括NMOS和PMOS裝置)具有用於較低的功耗和高密度邏輯和計算電路的優異的電晶體特性，並且適用於複雜的類比/混合信號電路。然而，經由矽CMOS 技術所構建的功率放大器具有非常低的功率效率，例如功率附加效率(PAE)。
本揭示內容的一些實施方式提供了一種製造封裝的方法，包含：將III-V族晶粒直接地接合到互補式金屬氧化物半導體(CMOS)晶粒以形成晶粒堆疊。其中III-V族晶粒包含：(111)半導體基板、和第一電路。第一電路包含：基於III-V族的n型電晶體，形成在(111)半導體基板的表面處。並且其中互補式金屬氧化物半導體晶粒包含：(100)半導體基板、第二電路。第二電路包含：n型電晶體和p型電晶體。n型電晶體在(100)半導體基板上。p型電晶體在(100)半導體基板上，其中第一電路電性連接到第二電路。
本揭示內容的另一些實施方式提供了一種封裝，包含：III-V族晶粒、以及互補式金屬氧化物半導體(CMOS)晶粒。III-V族晶粒包含：(111)半導體基板、和基於III-V族的n型電晶體。基於III-V族的n型電晶體在(111)半導體基板的表面處。互補式金屬氧化物半導體(CMOS)晶粒物理性地接合到III-V族晶粒，互補式金屬氧化物半導體晶粒包含：(100)半導體基板、n型電晶體、和p型電晶體。n型電晶體在(100)半導體基板上。p型電晶體在(100)半導體基板上。
本揭示內容的又另一些實施方式提供了一種封裝， 包含：III-V族晶粒、以及互補式金屬氧化物半導體(CMOS)晶粒。III-V族晶粒包含：(111)半導體基板、基於III-V族的n型電晶體、和第一電性連接器。基於III-V族的n型電晶體形成在(111)半導體基板的表面處。第一電性連接器連接到基於III-V族的n型電晶體。互補式金屬氧化物半導體晶粒直接地接合到III-V族晶粒，互補式金屬氧化物半導體包含：(100)半導體基板、p型電晶體、和第二電性連接器。p型電晶體在(100)半導體基板的表面處。第二電性連接器連接到p型電晶體，其中第一電性連接器和第二電性連接器將基於III-V族的n型電晶體和p型電晶體互相連接。
10:互連件(電性連接件)
101:電路
102:電晶體
104:被動裝置
120:晶圓
120’:III-V族晶粒(裝置晶粒)
122:基板
124:III-V族化合物層(緩衝層)
126:III-V族化合物層
128:III-V族化合物層
129:開口
130:GaN貫穿導孔
131:載流子通道
132:p型GaN層
133:閘極介電層
134:鈍化層
136:源極區域
138:汲極區域
140:開口
142:遮罩層
143:金屬性材料
144:金屬閘極
146:層間介電質
148:接觸插塞
151:矽貫穿導孔
152:互連結構
154:膠帶
156:電性連接器
160:開口
160B:底部
2:封裝
201:電路
202:電路
203:p型電晶體
205:被動裝置
206:電晶體
220:晶圓
220’:CMOS晶粒
222:基板
220’:CMOS晶粒(裝置晶粒、晶粒)
220”:附加的CMOS晶粒
222:基板
251:矽貫穿導孔
252:互連結構
256:電性連接器(接合墊)
32:底部填料
34:電性連接器
36:晶粒堆疊
38:封裝組件
300:製程
302:製程
304:製程
306:製程
308:製程
310:製程
312:製程
314:製程
316:製程
318:製程
320:製程
322:製程
324:製程
40:散熱器
42:熱界面材料
44:封裝
400:製程
402:製程
404:製程
406:製程
408:製程
410:製程
412:製程
414:製程
416:製程
418:製程
420:製程
422:製程
424:製程
426:製程
500:製程(製程流程)
502:製程
504:製程
506:製程
508:製程
510:製程
512:製程
600:製程(製程流程)
602:製程
604:製程
606:製程
608:製程
610:製程
612:製程
614:製程
616:製程
700:製程(製程流程)
702:製程
704:製程
706:製程
708:製程
710:製程
712:製程
714:製程
800:製程(製程流程)
802:製程
804:製程
806:製程
808:製程
810:製程
本揭示內容的多個態樣可由以下的詳細描述並且與所附圖式一起閱讀，得到最佳的理解。注意的是，根據產業中的標準做法，各個特徵並未按比例繪製。事實上，為了討論的清楚起見，可任意地增加或減少各個特徵的尺寸。
第1圖繪示了根據一些實施方式在包括III-V族晶粒和CMOS晶粒的封裝中的多個電路的示意性框圖。
第2圖繪示了根據一些實施方式在包括III-V族晶粒和CMOS晶粒的封裝中的多個電路和對應的p型和n型電晶體的示意性框圖。
第3圖至第14圖繪示了根據一些實施方式在III-V 族裝置晶粒/晶圓的形成中的多個中間階段的多個截面視圖。
第15圖繪示了根據一些實施方式在第3圖至第14圖中的多個製程的製程流程。
第16圖至第28圖繪示了根據一些實施方式在III-V族裝置晶粒/晶圓的形成中的多個中間階段的多個截面視圖。
第29圖繪示了根據一些實施方式在第16圖至第28圖中的多個製程的製程流程。
第30圖至第35圖繪示了根據一些實施方式在用於III-V族裝置晶粒/晶圓的多個互連結構的形成中的多個中間階段的多個截面視圖。
第36圖繪示了根據一些實施方式在第30圖至第35圖的多個製程的製程流程。
第37圖至第44圖繪示了根據一些實施方式在III-V族裝置晶粒/晶圓的多個互連結構的形成中的多個中間階段的多個截面視圖。
第45圖繪示根據一些實施方式在第37圖至第44圖中的多個製程的製程流程。
第46圖至第52圖繪示了根據一些實施方式在CMOS裝置晶粒/晶圓的形成中的多個中間階段的多個截面視圖。
第53圖繪示了根據一些實施方式在接合製程中的製程流程。
第54圖至第57圖繪示了根據一些實施方式在接合製程中的多個中間階段的多個截面視圖。
第58圖繪示了根據一些實施方式經由混合接合製程所形成的封裝的截面視圖。
第59圖繪示了根據一些實施方式在第54圖至第57圖中所示的多個製程的製程流程。
第60圖至第63圖繪示了根據一些實施方式的一些封裝的多個截面視圖。
之後的揭示內容提供了許多不同的實施方式或實施例，以實現本揭示內容的不同的特徵。以下描述組件和排列的具體實施例，以簡化本揭示內容。當然，這些僅僅是實施例而不是限制性的。例如，在隨後的描述中，形成第一特徵其在第二特徵上方或之上，可包括第一特徵和第二特徵以直接接觸而形成的實施方式，且也可包括附加的特徵可形成在介於第一特徵和第二特徵之間，因此第一特徵和第二特徵可不是直接接觸的實施方式。另外，本揭示內容可在各個實施例中重複參考標號和/或字母。此重複是為了簡化和清楚性的目的，重複本身不意指所論述的各個實施方式和/或配置之間的關係。
此外，為了便於描述一個元件或特徵與另一個元件或特徵之間，如圖式中所繪示的關係，在此可能使用空間相對性用語，諸如「在下方」、「低於」、「較下」、「在 上方的」、「較上」、和類似的用語。除了在圖式中繪示的方向之外，空間相對性用語旨在涵蓋裝置在使用中或操作中的不同方向。設備可經其它方式定向(旋轉90度或處於其它定向)，並且由此可同樣地解讀本文所使用的空間相對性描述詞。
提供了多個封裝及其形成方法，這些封裝包含基於互補式金屬氧化物半導體(CMOS)的裝置晶粒(以下稱為CMOS晶粒)和基於III-V族的裝置晶粒(以下稱為III-V族晶粒)。根據本揭示內容的一些實施方式，III-V族n型電晶體形成在包括(111)基板的第一裝置晶粒上。III-V族晶粒可以沒有p型裝置。III-V n型電晶體適用於高電壓。p型電晶體和n型電晶體都形成在包括(100)基板的CMOS晶粒中，並且p型電晶體和n型電晶體適用於低電壓。將III-V族晶粒和CMOS晶粒堆疊，以減小從III-V族晶粒到CMOS晶粒的互連件的長度。這裡所討論的多個實施方式是為了提供多個實施例來實現製造或使用本揭示內容的主題，並且本領域一般技術人員將容易地理解多種修改，可以進行這些修改而保持在不同的多個實施方式的設想範圍之內。在各個視圖和說明性實施方式中，相似的參考標號用於表示相似的元件。儘管討論了方法實施方式為以特定的順序來執行，但是其它的方法實施方式可以用任何邏輯的順序執行。
第1圖繪示了根據一些實施方式在封裝2中的多個電路的示意性框圖。多個電路包括形成在第一裝置晶粒 120’中的多個部分、和形成在第二裝置晶粒220’中的多個部分。第一裝置晶粒120’包括基於III-V族半導體材料所形成的多個裝置，因此在下文中替代性地稱為III-V族晶粒120’。第二裝置晶粒220’包括多個基於CMOS的裝置，例如p型電晶體和n型電晶體二者，p型電晶體和n型電晶體可具有由矽、矽鍺、或類似者所形成的通道。根據一些實施方式，裝置晶粒220’沒有基於III-V族半導體的裝置。裝置晶粒220’在下文中替代性地稱為CMOS晶粒220’。
根據一些實施方式，III-V族晶粒120’可包括射頻(Radio Frequency,RF)前段模組(Front End Module,FEM)101。對應的電路可包括前端電路，例如功率放大器(Power Amplifiers,PAs)、開關、低噪聲放大器(Low-Noise Amplifier,LNAs)、或類似者，或其組合。III-V族晶粒120’也可包括一些控制電路的多個部分(例如n型電晶體)，其可用於控制前端電路。在III-V族晶粒120’中的電路是基於III-V族的裝置，如將在隨後的段落中所討論的，基於III-V族的裝置可承受中等的和高的電源供應電壓，並且可在高的電源供應電壓下運作，例如，高於約3.5伏特、12伏特、或類似者。
CMOS晶粒220’可包括邏輯/核心電路201，其可包括控制器其用於控制在III-V族晶粒120’中的前端電路。在CMOS晶粒220’中的實施例電路201可包括但不限於鎖相環(Phase Lock Loop,PLL)、混頻器 (mixer)、可變的增益放大器(Variable Gain Amplifier,VGA)、移相器、類比至數位轉換器/數位至類比轉換器(ADC/DAC)、帶隙參考(Bandgap Reference,BG)電路、電壓調節器(Voltage Regulator,VR)、包絡跟踪器(envelope tracker)、應用處理器(Application Processor,AP)、或類似者、或其組合。在CMOS晶粒220’中的多個電路可包括非III-V族包含的電路，例如，具有矽、矽鍺、鍺、或類似者作為對應的電晶體的通道。在CMOS晶粒220’中的裝置和電路在比III-V族晶粒120’的電源供應電壓低的低電源供應電壓(例如，低於約1.5伏特)下運作，因此是低電壓裝置和電路。
形成複數個互連件10，以將在III-V族晶粒120’中的電路和在CMOS晶粒220’中的電路互相連接以形成一系統，互連件10可包括微凸塊(mircro bump,U-bumps)、焊料區域、接合墊(例如在混合接合結構中)、或類似者。例如，互連件10可包括互連件，互連件用於將在III-V族晶粒120’中的功率放大器的輸入耦合到在CMOS晶粒220’中的輸出。在III-V族晶粒120’中的開關可連接到CMOS晶粒220’(通過電性連接件10)並由來自CMOS晶粒220’的控制信號所控制，並且此開關可用於將功率放大器或低噪聲放大器電性耦合和信號耦合到天線(未示出)。低噪聲放大器的輸出也可通過電性連接件10而耦合到CMOS晶粒220’的輸入。
第2圖從電路和對應的p型和n型電晶體的觀點繪示了封裝2的框圖。根據一些實施方式，裝置晶粒120’包括(111)基板，並且裝置晶粒220’包括(100)基板。基於III-V族的n型電晶體102形成在III-V族晶粒120’中，使得電晶體102具有高的遷移率和低的寄生電容。在III-V族晶粒120’而不是CMOS晶粒220’中形成高電壓n型電晶體是有利的。例如，由於高遷移率，CMOS電晶體更偏好(100)基板。相反地，n型III-V電晶體偏好(111)基板，並且當在(100)電晶體上形成時將具有大量的缺陷。
既然p型III-V電晶體具有非常低的效率，所以III-V族晶粒120’可以沒有p型裝置。根據一些實施方式，在III-V族晶粒120’中的電路中的p型裝置的一些功能可經由在III-V族晶粒120’中形成的多個被動裝置104(其可包括電容器、電阻器、電感器、或類似者)以代替p型電晶體而實現。例如，使用被動裝置104的電路可包括及(AND)閘、或(OR)閘、互斥或(XOR)閘、或類似者。根據一些實施方式，一些p型電晶體203形成在CMOS晶粒220’中，並且直接地連接到在III-V族晶粒120’中的n型電晶體102(在其之間沒有主動裝置和被動裝置)，以形成功能性電路202。功能性電路202可以是低電壓電路，例如一些控制器，並且可包括反相器、及(AND)閘、或(OR)閘、互斥或(XOR)閘、或類似者、或更複雜的電路。例如，反相器可包括作為下拉裝置的n型電晶體、和 作為上拉裝置的p型電晶體，其中n型電晶體102在III-V族晶粒120’中，而p型電晶體203在CMOS晶粒220’中。本揭示內容的多個實施方式使得這種類型的連接方案成為可能。
CMOS晶粒220’還包括n型電晶體和p型電晶體206二者，n型電晶體和p型電晶體206可用於形成參考第1圖所討論的多個電路。III-V族晶粒120’和CMOS晶粒220’的連接(通過互連件10)在第57圖、第58圖、和第60圖至第63圖中的多個示例實施方式中示出。
用於形成在第1圖和第2圖中所示的電路和對應的裝置的多個形成製程在隨後的圖式中示出。第3圖至第45圖繪示了實施例III-V族晶圓和晶粒120'的形成。第46圖至第53圖繪示了實施例CMOS晶圓和晶粒220’的形成。第54圖至第59圖繪示了多個製程，用於接合III-V族晶粒120’和CMOS晶粒220’以形成封裝。
第3圖至第14圖繪示了根據一些實施方式在III-V族晶粒和對應的n型電晶體的形成中的多個中間階段的多個截面視圖。根據這些實施方式，n型電晶體沒有閘極介電質。參考第3圖，提供了晶圓120，晶圓120包括基板122作為一部分。在如第15圖中所示的製程300中，相應的製程繪示為製程302。根據一些實施方式，基板122是半導體基板，其可包括例如矽基板。基板122可以是由塊體材料所形成的塊體基板，或者可以是包括由不同的材料所形成的複數個層的複合基板。基板122的表面在矽的 (111)表面平面上，因此將基板122稱為(111)基板。
參考第4圖，在基板122上方形成緩衝層124，緩衝層124充當用於隨後形成的多個上覆的層的緩衝和/或過渡層。在第15圖中所示的製程300中，相應的製程繪示為製程304。外延地成長緩衝層124可使用金屬有機氣相外延(Metal Organic Vapor Phase Epitaxy,MOVPE)、或類似的方法。緩衝層124功能上可用作緩衝層，以減少介於基板122和隨後形成的III-V族化合物層126之間的晶格失配。緩衝層124可包括單個層或複數個層。根據一些實施方式，緩衝層124包括AlN-GaN超晶格層、AlN-AlGaN超晶格層、或GaN-AlGaN超晶格層。
參考第5圖，在緩衝層124上方外延地成長III-V族化合物層126。在第15圖中所示的製程300中，相應的製程繪示為製程306。根據一些實施方式，III-V族化合物層126是氮化鎵(GaN)層。外延地成長GaN層26可經由使用例如金屬有機氣相外延，在此期間使用含鎵的前驅物和含氮的前驅物。III-V族化合物層126也可包括GaAs或InP而不是GaN，或者可包括GaAs層或InP層。
參考第6圖，III-V族化合物層128形成在III-V族化合物層126上方並且可接觸III-V族化合物層126。在第15圖中所示的製程300中，相應的製程繪示為製程308。III-V族化合物層128的實施例材料可包括AlGaN、 AlInN、InGaN、或類似者、或其組合。外延地成長III-V族化合物層128可經由使用例如金屬有機氣相外延。載流子通道131(也稱為二維電子氣(Two-Dimensional Electron,2DEG))形成並位在介於III-V族化合物層126和128之間的界面附近，並且可在III-V族化合物層126中。
根據一些實施方式，如在第7圖中所示，形成GaN貫穿導孔(Through-GaN Via，TGV)130。形成GaN貫穿導孔130可使用金屬性材料，此金屬性材料可由鎢、鈷、鎳、或類似者、或其合金所形成、或者包含鎢、鈷、鎳、或類似者、或其合金。此形成製程可包括蝕刻III-V族化合物層124、126、和128，以形成開口並暴露基板122。然後用金屬性材料填充開口，接著進行平坦化製程，例如化學機械研磨(CMP)製程或機械研磨製程，以移除過量的金屬性材料，留下GaN貫穿導孔130。GaN貫穿導孔130可具有兩種功能。一些GaN貫穿導孔130可形成在III-V族晶圓120中相應的晶粒的邊緣附近，並且圍繞晶粒的內部區域。這些GaN貫穿導孔具有阻止III-V族化合物層的破裂和分層的功能，III-V族化合物層破裂和分層可能發生在晶圓120的晶粒鋸切期間。一些其它的GaN貫穿導孔130可形成為電性連接件，以將基板122連接到上覆的連接件(如在第14圖中所示)。這些GaN貫穿導孔可以被氧化物佈植區域(未示出)包圍，形成氧化物佈植區域是經由將氧佈植到圍繞對應的GaN貫穿導孔的 III-V族化合物層124、126、和128的多個部分中，並經由退火而氧化這些佈植的區域，使得這些GaN貫穿導孔130與III-V族化合物層124、126和、128的這些鄰近的部分電性隔離。根據替代性實施方式，不形成GaN貫穿導孔130。據此，GaN貫穿導孔130顯示為虛線，以表示其可以形成或不形成。
進一步參考第7圖，p型GaN層132形成在III-V族化合物層128上方並接觸III-V族化合物層128。在如第15圖中所示的製程300中，相應的製程繪示為製程310。根據一些實施方式，形成p型GaN層132經由沉積並隨後圖案化p型GaN層，p型GaN層可用鎂摻雜成為p型。
接下來，將鈍化層134沉積在p型GaN層132和III-V族化合物層128的頂表面上方，並且可以接觸此頂表面。在如第15圖中所示的製程300中，相應的製程示出為製程312。實施例鈍化層134包括介電材料，例如矽氧化物和/或矽氮化物。鈍化層134保護在下方的III-V族化合物層128免受電漿的損害，此電漿在隨後的沉積製程中產生。
第9圖繪示了在形成源極區域136和汲極區域138之後的晶圓120的截面視圖。在第15圖中所示的製程300中，相應的製程繪示為製程314。為了形成源極區域136和汲極區域138，首先在鈍化層134上方形成遮罩層(未示出)。經由蝕刻遮罩層、鈍化層134、和III-V族 化合物層128而形成兩個開口。因此暴露了在p型GaN層132的相對的多個側上的III-V族化合物層126的多個部分。根據一些實施方式，經由沉積而形成金屬層以填充開口，隨後經由平坦化製程以移除在遮罩層上方的金屬層的過量部分。金屬層的剩餘部分是源極區域136和汲極區域138。然後移除遮罩層，留下源極區域136和汲極區域138，源極區域136和汲極區域138通過歐姆接觸而經由載流子通道131而互相連接。
根據一些實施方式，源極區域136和汲極區域138包括一或多種導電材料。例如，源極區域136和汲極區域138可包含Ti、Co、Ni、W、Pt、Ta、Pd、Mo、TiN、AlCu合金、或其合金。
參考第10圖，形成遮罩層142，其可以是諸如SiN、TiN、或類似者的硬遮罩。在遮罩層142和鈍化層134中形成開口140，以暴露p型GaN層132。在如第15圖中所示的製程300中，相應的製程繪示為製程316。接下來，如在第11圖中所示，形成金屬閘極144以填充開口140。在第15圖中所示的製程300中，相應的製程繪示為製程318。形成製程可包括沉積製程，隨後是平坦化製程。金屬閘極144可由鎢、銅、鈷、鎳、或類似者、或其合金所形成、或包含鎢、銅、鈷、鎳、或類似者、或其合金。然後移除遮罩層142，並且在第12圖中示出所得的結構。在如第15圖中所示的製程300中，相應的製程繪示為製程320。
參考參考第13圖，沉積層間介電質(ILD)146。在第15圖中所示的製程300中，相應的製程繪示為製程322。在層間介電質146的沉積之前，也可沉積接觸蝕刻停止層(CESL，未示出)作為保形層。
第14圖繪示了多個接觸插塞148的形成，多個接觸插塞148連接到源極區域136和汲極區域138以及金屬閘極144。在第15圖中所示的製程300中，相應的製程繪示為製程324。當形成GaN貫穿導孔130時，多個接觸插塞148中的一者形成在GaN貫穿導孔130上方並且連接到GaN貫穿導孔130。
在上述的實施方式中，p型GaN層132、源極區域136和汲極區域138、以及載流子通道131共同地形成n型電晶體102，其在第2圖中示意性地示出。晶圓120可以沒有p型電晶體。如在第14圖中所示的n型電晶體102沒有閘極介電質。當將電壓施加到p型GaN層132時，可調整流動通過載流子通道131以及介於源極區域136和汲極區域138之間的裝置電流。例如，當無電壓、負電壓、或低的正電壓施加在p型GaN層132上時，在p型GaN層132的直接下方的載流子通道131的部分被耗盡，並且將相應的電晶體102關斷。當在p型GaN層132上施加足夠高的正電壓時，耗盡的載流子通道131被恢復並增強，對應的源極區域136和汲極區域138通過恢復的載流子通道131而連接，並且將相應的電晶體102導通。
第16圖至第28圖繪示了根據本揭示內容的多個 替代性實施方式在n型電晶體的形成中的多個中間階段的多個截面視圖。這些實施方式類似於在第3圖至第14圖中所示的實施方式，除了對應的電晶體現在包括閘極介電質。據此，如在第28圖中所示的n型電晶體可物理性地切斷載流子通道。除非另有說明，否則在這些實施方式中的組件的材料和形成製程與在先前的實施方式中由相似的參考標號所表示的相似的組件基本上相同。因此，關於在第16圖至第28圖中所示的組件的形成製程和材料的細節可在先前的實施方式的討論中找到。
參考第16圖，提供了包括基板122的晶圓120。在如第29圖中所示的製程400中，相應的製程繪示為製程402。基板122可以是(111)基板，基板122的頂表面在基板122的(111)平面上。第17圖繪示了III-V族化合物層124的外延的成長，III-V族化合物層124是緩衝層。在如第29圖中所示的製程400中，相應的製程繪示為製程404。III-V族化合物層124可以是超晶格層。第18圖繪示了根據一些實施方式的III-V族化合物層126的外延成長，III-V族化合物層126可以是GaN層。在如第29圖中所示的製程400中，相應的製程繪示為製程406。第19圖繪示了根據一些實施方式的III-V族化合物層128的外延成長，其可以是AlGaN層或AlInN層。在如第29圖中所示的製程400中，相應的製程繪示為製程408。第20圖繪示了GaN貫穿導孔130的形成。在如第29圖中所示的製程400中，相應的製程繪示為製程 410。根據多個替代性實施方式，也可略過GaN貫穿導孔130的形成。
第21圖繪示了用於定義金屬閘極開口的蝕刻製程。在如第29圖所示的製程400中，相應的製程繪示為製程412。在蝕刻製程中，將III-V族化合物層128蝕刻以形成開口129，通過開口129而暴露在下方的III-V族化合物層126。
參考第22圖，沉積閘極介電層133至延伸到開口129中。在如第29圖中所示的製程400中，相應的製程繪示為製程414。閘極介電層133也包括與III-V族化合物層126重疊並接觸的部分。閘極介電層133可增加所得的電晶體102的閾值電壓(第28圖)。閘極介電層133的實施例材料可選自矽氧化物、矽氮化物、鎵氧化物、鋁氧化物、鈧氧化物、鋯氧化物、鑭氧化物、鉿氧化物、或其組合。根據一些實施方式，形成閘極介電層133使用原子層沉積(Atomic Layer Deposition,ALD)。根據其它的實施方式，形成閘極介電層133使用電漿增強化學氣相沉積(PECVD)或低壓化學氣相沉積(LPCVD)。
參考第23圖，沉積金屬性材料143。在如第29圖中所示的製程400中，相應的製程繪示為製程416。根據一些實施方式，金屬性材料143包括導電材料，此導電材料包括難熔金屬或相應的化合物，包括Ti、TiN、W、TiW、Ni、Au、Cu、或類似者，或其合金。第24圖繪示了平坦化製程(例如CMP製程)，以移除金屬性材料143 的過量部分，形成金屬閘極144。在如第29圖中所示的製程400中，相應的製程繪示為製程418。
第25圖繪示了鈍化層134的沉積。在如第29圖中所示的製程400中，相應的製程繪示為製程420。第26圖繪示了源極區域136和汲極區域138的形成。在如第29圖中所示的製程400中，相應的製程繪示為製程422。第27圖繪示了層間介電質146的沉積。在如第29圖中所示的製程400中，相應的製程繪示為製程424。第28圖繪示了接觸插塞148的形成。在如第29圖中所示的製程400中，相應的製程繪示為製程426。由此形成基於III-V族的n型電晶體102。
第30圖至第35圖繪示了用於III-V族晶圓120的互連結構和電性連接器的形成。在第36圖中示出了相應的製程流程500。參考第30圖，電路101形成在基板122的頂表面處。根據一些實施方式，電路101包括功率放大器、開關、低噪聲放大器、或類似者、或其組合，這些已經參考第1圖進行了討論。在如第36圖中所示的製程500中，相應的製程繪示為製程502。此外，電路101的形成包括基於III-V族的n型電晶體102的形成，此形成製程如在第3圖至第29圖中所示，並且也在第2圖中示出。據此，第30圖至第35圖繪示了在第3圖至第15圖、或在第16圖至第29圖中所示的製程之後的製程。
參考第31圖，形成基板貫穿導孔(或矽貫穿導孔)151。在如第36圖中所示的製程500中，相應的製程 繪示為製程504。此形成製程可包括蝕刻基板122以形成開口，用隔離層襯在開口的側壁，用金屬性材料填充開口，以及執行平坦化製程以移除過量的金屬性材料。儘管示出了一個矽貫穿導孔151，但是可形成複數個矽貫穿導孔151，其可用於散熱或電性連接。用於散熱的矽貫穿導孔151可形成得比用於電性連接的矽貫穿導孔151寬，從而提高散熱效率。
參考第32圖，形成互連結構152。互連結構152也稱為後段製程(Back-End of Line,BEOL)互連結構。如在第36圖中所示的製程500中，相應的製程繪示為製程506。互連結構152也可包括形成在其中的多個被動裝置，這些裝置在第2圖中也示出為被動裝置104。互連結構152可包括介電層，此介電質層可以包括金屬間介電質(IMD)層和上覆的鈍化層。互連結構152還可包括導電特徵，包括金屬線、導孔、重分佈線(redistribution lines,RDLs)、接觸插塞、金屬墊、凸塊下金屬(Bump Metallurgies，UBMs)、和/或類似者，這些在第32圖中示意性地示出。導電特徵連接到電路101，並將在電路101中的裝置互相連接。
第33圖繪示了晶圓120的翻轉和膠帶154層壓到晶圓120。膠帶154用於支撐晶圓120的背側研磨。根據一些實施方式，膠帶154可以是紫外線(Ultra-Violet,UV)可固化膠帶，其可在紫外光下分解。如在第36圖中所示的製程500中，相應的製程繪示為製程508。
第34圖繪示了對薄基板122的背側研磨製程，直到暴露出矽貫穿導孔151。如在第36圖中所示的製程500中，相應的製程繪示為製程510。在背側研磨製程之後，基板122可具有在約300微米(μm)和約400微米之間的範圍內的厚度。在背側研磨製程之後，移除膠帶154。在第34圖中示出所得的結構。
接下來，如在第35圖中所示，形成電性連接器156，以電性連接到互連結構152。如在第36圖中所示的製程500中，相應的製程繪示為製程512。根據一些實施方式，電性連接器156是焊料區域。根據替代性實施方式，電性連接器156是微凸塊，例如微銅凸塊。根據另外的替代性實施方式，電性連接器156用於混合接合。根據一些實施方式，III-V族晶圓120可以被鋸切成分立的多個III-V族晶粒120’，並且分立的多個晶粒120’用於後續的接合和封裝製程。根據替代性實施方式，III-V族晶圓120未被鋸切，並且以晶圓級別與CMOS晶圓或晶粒接合，這將在後續的製程中討論。
第37圖至第44圖繪示了根據多個替代性實施方式的用於III-V族晶圓120的互連結構和電性連接器的形成。這些實施方式類似於在第30圖至第36圖中所示的實施方式，除了矽貫穿導孔151是從基板122的背側形成。在第45圖中示出了製程流程600。簡要地討論了這些製程。
第37圖繪示了包括電路101的晶圓120的形成， 此形成製程包括在第3圖至第15圖、或在第16圖至第29圖中所示的製程。在第45圖中所示的製程600中，相應的製程繪示為製程602。第38圖繪示互連結構152的形成。在第45圖所示的製程600中，相應的製程繪示為製程604。第39圖繪示膠帶154附著到晶圓120的前側。在第45圖所示的製程600中，相應的製程繪示為製程606。第40圖繪示了晶圓120的背側研磨。在第45圖所示的製程600中，相應的製程繪示為製程608。在背側研磨製程之後，基板122可為足夠厚，使得晶圓120不會發生翹曲和斷裂。例如，厚度可在約300微米和約400微米之間的範圍內。
第41圖繪示了基板122的蝕刻，從而形成矽貫穿導孔開口160。在第45圖中所示的製程600中，相應的製程繪示為製程610。根據一些實施方式，開口160具有一端(如第41圖中的頂端，當將晶圓120上下翻轉時，此頂端實際上是開口160的底部160B)。根據一些實施方式，底部160B在(半導體)基板122的介於頂表面和底表面之間的中間層級處。根據替代性實施方式，在互連結構152中的多個金屬墊中的一者暴露於矽貫穿導孔開口160，並且在互連結構152中的對應的金屬墊用來為作蝕刻停止層。第42圖繪示了經由填充金屬性材料，接著進行化學機械研磨製程，在矽貫穿導孔開口160中形成矽貫穿導孔151。在第45圖所示的製程600中，相應的製程繪示為製程612。
第43圖繪示了電性連接器156的形成。在第45圖中所示的製程600中，相應的製程繪示為製程614。第44圖繪示了晶圓120的翻轉和晶粒鋸切製程(如果在此時執行)。在第45圖所示的製程600中，相應的製程繪示為製程616。當鋸切時，分立的多個III-V族晶粒120’彼此分離。根據替代性實施方式，在此時不鋸切晶圓120。
第46圖至第52圖繪示了根據一些實施方式的CMOS晶圓220的形成。相應的製程在第53圖中繪示為製程700。參考第46圖，將基板222提供作為晶圓220的一部分。在第53圖中所示的製程700中，相應的製程繪示為製程702。根據一些實施方式，基板222是半導體基板，其可包括矽基板、矽鍺基板、或類似者。基板122可以是由諸如矽的塊體材料所形成的塊體基板，或者可以是包括由不同的材料所形成的複數個層的複合基板。基板222的頂表面在相應的晶格結構的(100)表面平面上，因此將基板222稱為(100)基板。
參考第47圖，電路201形成在基板222的頂表面處。在第53圖中所示的製程700中，相應的製程繪示為製程704。相應的電路201可包括參考第1圖所討論的電路。此外，電路201包括邏輯/核心電路，邏輯/核心電路包括CMOS裝置，CMOS裝置包括p型(PMOS)電晶體和n型(NMOS)電晶體、二極體等，如在第2圖中示意性示出的電晶體206。電路201也可包括類比電路、數位電路、或類似者、或其組合。如在第2圖中所示，電路201 也可包括在電路202中的p型電晶體203，其中電路202擴展到III-V族晶粒120’和CMOS晶粒220’二者，並且可以是諸如控制器的低電壓電路。實施例電路202可包括功能裝置，例如反相器、閘極、或類似者。
參考第48圖，將矽貫穿導孔251形成為從基板222的前表面延伸到基板222內。矽貫穿導孔251可用於連接到電源或電性接地，和/或可用於傳導低頻電性信號。矽貫穿導孔251的形成製程類似於在第31圖中所示的矽貫穿導孔151的形成。在第53圖中所示的製程700中，相應的製程繪示為製程706。
參考第49圖，互連結構252形成在基板222的頂表面處。在第53圖中所示的製程700中，相應的製程繪示為製程708。參考第50圖，形成被動裝置205。被動裝置205可包括電容器、電阻器、電感器、二極體、或類似者。在第53圖中所示的製程700中，相應的製程繪示為製程710。應當理解，儘管在製程流程700中順序地示出了互連結構252和被動裝置205，但是它們可在共同的製程中形成。被動裝置205和電路201互相連接，以形成功能性電路，功能性電路可包括類比電路和/或數位電路。
參考第51圖，電性連接器256形成在基板222的頂表面處。在第53圖中所示的製程700中，相應的製程繪示為製程712。電性連接器256可以是焊料區域、微凸塊(例如微銅凸塊)、金屬墊、或類似者。在隨後的製程 中，膠帶(未示出)(可以是UV膠帶)可黏附到晶圓220的頂表面。然後對薄的基板222執行背側研磨製程，直到暴露矽貫穿導孔251。在第53圖中所示的製程700中，相應的製程繪示為製程714。在第52圖中示出所得的晶圓220。晶圓220可被鋸切成多個CMOS晶粒220’，或者保持為一晶圓，以執行與III-V族晶圓或III-V族晶粒的後續接合。
第54圖至第57圖繪示了III-V族晶圓/晶粒與CMOS晶圓/晶粒的接合以及對應的封裝製程。在第59圖中示出了相應的製程流程800。參考第54圖，準備III-V族晶粒120’和CMOS晶粒220’，其包括從電性連接器156和256移除氧化物的清潔製程。在第59圖中所示的製程800中，相應的製程繪示為製程802。應當理解，接合製程可在晶粒級別或晶圓級別執行。如果在晶圓級別，所繪示的晶粒是未鋸切的晶圓的多個部分。
接下來，如在第55圖中所示，將III-V族晶粒120’接合到CMOS晶粒220’。此接合可包括焊料接合、直接金屬對金屬接合、或類似者。然後，底部填料32可填充到介於III-V族晶粒120’和CMOS晶粒220’之間的間隙中。在第59圖中所示的製程800中，相應的製程繪示為製程804。第56圖繪示了電性連接器34的形成，電性連接器34電性連接到矽貫穿導孔251，並且可物理性連接或者不物理性連接矽貫穿導孔251。在第59圖中所示的製程800中，相應的製程繪示為製程806。電性連接 器34可以是焊料區域、金屬柱、金屬墊、或類似者。因此形成了晶粒堆疊36。
如果接合的晶粒堆疊在未鋸切的晶圓內部，則可執行鋸切製程以分離多個III-V族晶粒120’和多個CMOS晶粒220’，以形成分立的多個晶粒堆疊36。然後將晶粒堆疊36接合到封裝組件38，並且在第57圖中示出所得的結構。在第59圖中所示的製程800中，相應的製程繪示為製程808。根據一些實施方式，封裝組件38是或包含封裝基板、中介板(interposer)、印刷電路板、包括裝置晶粒的封裝、或類似者。
進一步參考第57圖，散熱器40黏附到晶粒堆疊36，例如通過熱界面材料(Thermal Interface Material,TIM)42。熱界面材料42是具有高導熱性的黏合劑，例如，高於約1瓦/(k*m)、5瓦/(k*m)、或更高。散熱器40可由諸如銅、不銹鋼、或類似者的金屬所形成、或包含諸如銅、不銹鋼、或類似者的金屬。據此，在晶粒堆疊36運作期間在晶粒堆疊36中所產生的熱量可通過矽貫穿導孔251經由熱界面材料42而傳導到散熱器40。矽貫穿導孔151可用於連接到電源、電性接地、或信號。這樣就形成了封裝44。在第59圖中所示的製程800中，相應的製程繪示為製程810。
第58圖繪示了根據多個替代性實施方式的封裝44。這些實施方式類似於在第57圖中的實施方式，除了在第57圖中，III-V族晶粒120’與CMOS晶粒220’ 的接合是通過微凸塊或焊料區域，而在第58圖中，III-V族晶粒120’與CMOS晶粒220’的接合是通過混合接合。在混合接合中，在III-V族晶粒120’中的表面介電層通過熔融接合(利用形成的Si-O-Si鍵)而接合到在CMOS晶粒220’中的表面介電層。此外，在III-V族晶粒120’中的接合墊156通過直接金屬對金屬接合而接合到在CMOS晶粒220’中的接合墊256，其中發生金屬相互擴散，以將接合墊156連接到接合墊256。
第60圖繪示了根據多個替代性實施方式所形成的封裝44。這些實施方式類似於在第57圖中所示的實施方式，除了CMOS晶粒220’不是在上方，而是在III-V族晶粒120’的下方。
第61圖繪示了根據多個替代性實施方式所形成的封裝44。這些實施方式類似於在第60圖中所示的實施方式，除了執行混合接合，而不是焊料接合或微凸塊接合。
第62圖繪示了根據多個替代性實施方式所形成的封裝44。這些實施方式類似於在第58圖中所示的實施方式，除了在III-V族晶粒120’中，III-V族材料可包括除了在第3圖至第29圖中所示的實施方式中所揭示的材料之外的其它材料。
第63圖繪示了根據多個替代性實施方式所形成的封裝44。這些實施方式類似於在第58圖中所示的實施方式，除了有複數個晶粒覆蓋並接合到CMOS晶粒220’。複數個晶粒可包括III-V族晶粒120’和附加的CMOS晶 粒220”。
在上述所繪示的多個實施方式中，根據本揭示內容的一些實施方式討論了一些製程和特徵，以形成三維的(three-dimensional,3D)封裝。也可包括其它多個特徵和多個製程。例如，可以包括測試結構來幫助三維的封裝或三維的積體電路裝置的驗證測試。測試結構可包括，例如，形成在重分佈層中或在基板上的多個測試墊，測試墊允許三維的封裝或三維的積體電路的測試，使用探針和/或探針卡、或類似者。驗證測試可對多個中間結構以及最終結構執行。此外，本文所揭示的結構和方法可與測試方法學結合使用，此測試方法學結合了已知良好的晶粒的中間驗證，以增加良率並降低成本。
本揭示內容的多個實施方式具有一些有利的特徵。經由在(111)基板上形成作為基於III-V族的裝置的高電壓裝置和高功率裝置，提高了高電壓/功率裝置的性能。經由在(100)基板上形成低電壓核心/邏輯裝置，低電壓核心/邏輯裝置的性能也得到了改善。經由堆疊III-V族晶粒和CMOS晶粒，減小了用於在III-V族晶粒和CMOS晶粒中的多個裝置互相連接的電性路徑的長度，並且減少了延遲。這提高了用於一些應用(例如功率放大器)的高功率效應，同時保持了CMOS電路的低寄生電容和高密度。這些實施方式具有優於習知結構的性能，在習知結構中，III-V族晶粒和CMOS晶粒可並排接合到在下方的封裝基板，並且通過封裝基板而相互通信。在這種情況下，信號路徑很 長。
根據本揭示內容的一些實施方式，一種製造封裝的方法包括將III-V族晶粒直接地接合到CMOS晶粒以形成晶粒堆疊，其中III-V族晶粒包括(111)半導體基板；和第一電路包含形成在(111)半導體基板表面處的基於III-V族的n型電晶體，並且其中CMOS晶粒包含(100)半導體基板；第二電路包含在(100)半導體基板上的n型電晶體；和在(100)半導體基板上的p型電晶體，其中第一電路電性連接到第二電路。
在一實施方式中，III-V族晶粒在CMOS晶粒上方，並且此方法還包含在III-V族晶粒中形成貫穿導孔；研磨(111)半導體基板以顯現出貫穿導孔；以及通過熱界面材料將散熱器黏附到III-V族晶粒，其中熱界面材料物理性接觸貫穿導孔。在一實施方式中，CMOS晶粒在III-V族晶粒上方，並且此方法還包含在CMOS晶粒中形成貫穿導孔；研磨(100)半導體基板以顯現出貫穿導孔；以及通過熱界面材料將散熱器黏附到CMOS晶粒，其中熱界面材料物理性接觸貫穿導孔。
在一實施方式中，將III-V族晶粒接合到CMOS晶粒通過焊料接合或微凸塊接合，並且其中此方法還包含將底部填料分配到介於III-V族晶粒和CMOS晶粒之間的間隙中。在一實施方式中，接合III-V族晶粒和CMOS晶粒通過混合接合。在一實施方式中，III-V族晶粒沒有p型電晶體。在一實施方式中，基於III-V族的n型電晶體 直接地連接到在CMOS晶粒中的附加的p型電晶體，以形成功能性電路。在一實施方式中，在III-V族晶粒中的基於III-V族的n型電晶體直接地連接到在CMOS晶粒中的附加的p型電晶體，以形成反相器。在一實施方式中，基於III-V族的n型電晶體使用二維電子氣(2DEG)作為通道。
根據本揭示內容的一些實施方式，一種封裝包括III-V族晶粒，III-V族晶粒包含(111)半導體基板；和在(111)半導體基板表面處的基於III-V族的n型電晶體；以及與III-V族晶粒物理性接合的CMOS晶粒，CMOS晶粒包含(100)半導體基板；在(100)半導體基板上的n型電晶體；和在(100)半導體基板上的p型電晶體。在一實施方式中，III-V族晶粒在CMOS晶粒上方，並且封裝還包含在III-V族晶粒中的貫穿導孔；熱界面材料，其位於貫穿導孔上方並與貫穿導孔物理性接觸；以及散熱器，其在熱界面材料上方並連接到熱界面材料。在一實施方式中，CMOS晶粒在III-V族晶粒上方，並且封裝還包含在CMOS晶粒中的貫穿導孔；熱界面材料，位於貫穿導孔上方並物理性接觸貫穿導孔；以及散熱器，其在熱界面材料上方並在連接到熱界面材料。
在一實施方式中，封裝還包含底部填料，底部填料在介於III-V族晶粒和CMOS晶粒之間並且與III-V族晶粒和CMOS晶粒物理性接觸。在一實施方式中，接合III-V族晶粒和CMOS晶粒通過混合接合。在一實施方式 中，III-V族晶粒沒有p型電晶體。在一實施方式中，CMOS晶粒包含附加的p型電晶體，並且其中基於III-V族的n型電晶體直接地連接到附加的p型電晶體。在一實施方式中，在III-V族晶粒中的基於III-V族的n型電晶體直接地連接到在CMOS晶粒中的附加的p型電晶體，以形成一反相器。
根據本揭示內容的一些實施方式，一種封裝包括III-V族晶粒，III-V族晶粒包含(111)半導體基板；形成在(111)半導體基板表面處的基於III-V族的n型電晶體；和連接到基於III-V族的n型電晶體的第一電性連接器；以及直接地接合到III-V族晶粒的CMOS晶粒，此CMOS晶粒包含(100)半導體基板；在(100)半導體基板表面處的p型電晶體；和連接到p型電晶體的第二電性連接器，其中第一電性連接器和第二電性連接器將基於III-V族的n型電晶體和p型電晶體互相連接。在一實施方式中，基於III-V族的n型電晶體和p型電晶體直接地互相連接以形成一功能性電路。在一實施方式中，基於III-V族的n型電晶體和p型電晶體形成一反相器。
以上概述了數個實施方式的多個特徵，以便本領域技術人員可較佳地理解本揭示內容的多個態樣。本領域的技術人員應理解，他們可能容易地使用本揭示內容，作為其它製程和結構之設計或修改的基礎，以實現與在此介紹的實施方式的相同的目的，和/或達到相同的優點。本領域技術人員亦應理解，與這些均等的建構不脫離本揭示內容 的精神和範圍，並且他們可進行各種改變、替換、和變更，而不脫離本揭示內容的精神和範圍。
120’:III-V族晶粒(裝置晶粒)
151:矽貫穿導孔
152:互連結構
156:電性連接器
252:互連結構
220’:CMOS晶粒(裝置晶粒、晶粒)
251:矽貫穿導孔
256:電性連接器(接合墊)
34:電性連接器
36:晶粒堆疊
38:封裝組件
40:散熱器
42:熱界面材料
44:封裝

Claims (10)

  1. 一種製造封裝的方法，包含：將一III-V族晶粒直接地接合到一互補式金屬氧化物半導體(CMOS)晶粒以形成一晶粒堆疊，其中該III-V族晶粒包含：一(111)半導體基板；和一第一電路其包含：一基於III-V族的n型電晶體，形成在該(111)半導體基板的一表面處；並且其中該互補式金屬氧化物半導體晶粒包含：一(100)半導體基板；一第二電路其包含：一n型電晶體，在該(100)半導體基板上；和一p型電晶體，在該(100)半導體基板上，其中該第一電路電性連接到該第二電路。
  2. 如請求項1所述之製造封裝的方法，其中該III-V族晶粒在該互補式金屬氧化物半導體晶粒上方，並且該方法還包含：在該III-V族晶粒中形成一貫穿導孔；研磨該(111)半導體基板，以顯現出該貫穿導孔；以及通過一熱界面材料將一散熱器黏附至該III-V族晶粒，其中該熱界面材料物理性接觸該貫穿導孔。
  3. 如請求項1所述之製造封裝的方法，其中該互補式金屬氧化物半導體晶粒在該III-V族晶粒上方，並且該方法還包含：在該互補式金屬氧化物半導體晶粒中形成一貫穿導孔；研磨該(100)半導體基板，以顯現出該貫穿導孔；以及通過一熱界面材料將一散熱器黏附至該互補式金屬氧化物半導體晶粒，其中該熱界面材料物理性接觸該貫穿導孔。
  4. 如請求項1所述之製造封裝的方法，其中將該III-V族晶粒接合到該互補式金屬氧化物半導體晶粒，通過焊料接合或微凸塊接合，並且其中該方法還包含將一底部填料分配到介於該III-V族晶粒和該互補式金屬氧化物半導體晶粒之間的間隙中。
  5. 一種封裝，包含：一III-V族晶粒其包含：一(111)半導體基板；和一基於III-V族的n型電晶體，在該(111)半導體基板的一表面處；以及一互補式金屬氧化物半導體(CMOS)晶粒，物理性地接合到該III-V族晶粒，該互補式金屬氧化物半導體晶粒包含： 一(100)半導體基板；一n型電晶體，在該(100)半導體基板上；和一p型電晶體，在該(100)半導體基板上。
  6. 如請求項5所述之封裝，其中該III-V族晶粒在該互補式金屬氧化物半導體晶粒上方，並且該封裝還包含：一貫穿導孔，在該III-V族晶粒中；一熱界面材料，在該貫穿導孔上方並且物理性接觸該貫穿導孔；以及一散熱器，在該熱界面材料上方並且連接到該熱界面材料。
  7. 如請求項5所述之封裝，其中該互補式金屬氧化物半導體晶粒在該III-V族晶粒上方，並且該封裝還包含：一貫穿導孔，在該互補式金屬氧化物半導體晶粒中；一熱界面材料，在該穿貫穿導孔上方並且物理性接觸該貫穿導孔；和一散熱器，在該熱界面材料上方並且連接該熱界面材料。
  8. 如請求項5所述之封裝，其中該互補式金屬氧化物半導體晶粒包含一附加的p型電晶體，並且其中該 基於III-V族的n型電晶體直接地連接到該附加的p型電晶體。
  9. 一種封裝，包含：一III-V族晶粒其包含：一(111)半導體基板；一基於III-V族的n型電晶體，形成在該(111)半導體基板的一表面處；和一第一電性連接器，連接到該基於III-V族的n型電晶體；以及一互補式金屬氧化物半導體(CMOS)晶粒，直接地接合到該III-V族晶粒，該互補式金屬氧化物半導體包含：一(100)半導體基板；一p型電晶體，在該(100)半導體基板的一表面處；和一第二電性連接器，連接到該p型電晶體，其中該第一電性連接器和該第二電性連接器將該基於III-V族的n型電晶體和該p型電晶體互相連接。
  10. 如請求項9所述之封裝，其中該基於III-V族的n型電晶體和該p型電晶體直接地互相連接，以形成一功能性電路。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201721807A (zh) * 2015-09-24 2017-06-16 英特爾股份有限公司 多層矽／鎵氮化物半導體
TW201729388A (zh) * 2015-12-26 2017-08-16 英特爾公司 晶片上之整合式被動裝置
US20210175136A1 (en) * 2018-12-28 2021-06-10 3D Glass Solutions, Inc. Heterogenous Integration for RF, Microwave and MM Wave Systems in Photoactive Glass Substrates

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858483B2 (en) * 2002-12-20 2005-02-22 Intel Corporation Integrating n-type and p-type metal gate transistors
US8044464B2 (en) * 2007-09-21 2011-10-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4696152B2 (ja) * 2008-11-10 2011-06-08 株式会社日立製作所 半導体装置の製造方法および半導体装置
JP5617835B2 (ja) * 2009-02-24 2014-11-05 日本電気株式会社 半導体装置およびその製造方法
US8212294B2 (en) * 2010-01-28 2012-07-03 Raytheon Company Structure having silicon CMOS transistors with column III-V transistors on a common substrate
US10049947B2 (en) * 2014-07-08 2018-08-14 Massachusetts Institute Of Technology Method of manufacturing a substrate
US10032750B2 (en) * 2016-06-29 2018-07-24 International Business Machines Corporation Integrated DC-DC power converters through face-to-face bonding
US10157885B2 (en) * 2016-07-29 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having magnetic bonding between substrates
US10629512B2 (en) * 2018-06-29 2020-04-21 Xilinx, Inc. Integrated circuit die with in-chip heat sink
US11393789B2 (en) 2019-05-31 2022-07-19 Qualcomm Incorporated Stacked circuits of III-V devices over silicon with high quality integrated passives with hybrid bonding

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201721807A (zh) * 2015-09-24 2017-06-16 英特爾股份有限公司 多層矽／鎵氮化物半導體
TW201729388A (zh) * 2015-12-26 2017-08-16 英特爾公司 晶片上之整合式被動裝置
US20210175136A1 (en) * 2018-12-28 2021-06-10 3D Glass Solutions, Inc. Heterogenous Integration for RF, Microwave and MM Wave Systems in Photoactive Glass Substrates

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