TWI809775B - Method for manufacturing and measuring semiconductor structures - Google Patents

Abstract

A method for manufacturing semiconductor device structure includes providing a substrate having a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; forming a first well region in the substrate and between the first gate structure and the second gate structure; forming a conductive contact within a trench between the first gate structure and the second gate structure; forming a first structure in the first well region, wherein the first structure tapers away from a bottom portion of the conductive contact.

Description

Fabrication and measurement methods of semiconductor structures

This application claims priority to U.S. Patent Application Nos. 17/508,961 and 17/510,786 (i.e., priority dates are "October 22, 2021" and "October 26, 2021"), the content of which is It is incorporated herein by reference in its entirety.

The present disclosure relates to a method of manufacturing and measuring a plurality of semiconductor structures. More particularly, it relates to a method of fabricating and measuring multiple semiconductor structures on a wafer.

According to Moore's law, the density of elements in a semiconductor structure increases sharply, and the size of these elements shrinks rapidly. Therefore, alignment issues caused by such reduced elements become more and more important. In some conventional methods, alignment is checked offline. Furthermore, the accuracy of conventional measurements cannot accommodate the size of these shrinking components. As a result, the wafer may not function properly when the components are fabricated at the intended locations, which may not be known until after fabrication is complete. Thus, manufacturing resources and time costs of the wafer are wasted when the wafer has misaligned components that prevent the wafer from being manufactured as a product. Furthermore, the throughput of these wafers is reduced.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the disclosure provides a method for manufacturing and measuring a plurality of semiconductor structures. The method includes the steps of: receiving a wafer having a plurality of dies; respectively forming the plurality of semiconductor structures in a plurality of blocks of each die, wherein each semiconductor structure has a first fin array and a second array of fins, the second array of fins located above the first array of fins; performing a patterned wafer geometry measurement on the wafer to obtain a first array of fins on the first fin array a displacement between a fin and a first fin of the second fin array; and determining a state of the wafer according to the displacement.

In some embodiments, the step of forming the plurality of semiconductor structures in the plurality of blocks of each die includes: forming the first fin array in each block; and forming the second fin array on the first fin array.

In some embodiments, both the first fin array and the second fin array have N fins, where N is a positive integer. The first fins of the first fin array correspond to the first fins of the second fin array. The displacement between the first fin of the first fin array and the first fin of the second fin array is defined from a top view of the semiconductor structure.

In some embodiments, the step of forming the first fin array in each block includes: forming a first layer; etching the first layer to form the first fin array; and planarizing the first layer to expose an upper surface of the first fin array.

In some embodiments, the step of forming the second fin array on the first fin array includes: forming a second layer on the first fin array; etching the second layer to form the second fin array fin array; and planarizing the second layer to expose an upper surface of the second fin array.

In some embodiments, a patterned wafer geometry measurement is performed on the wafer to obtain a distance between a first fin of the first fin array and a first fin of the second fin array. The step of displacing includes: obtaining a first overlapping ratio of the first fin of the first fin array and the first fin of the second fin array; obtaining an Nth fin array of the first fin array A second overlapping ratio of fins and an Nth fin of the second fin array; obtaining an Ath fin of the first fin array and an Ath fin of the second fin array a center overlap ratio of the fin; and obtaining the displacement according to the first overlap ratio, the second overlap ratio and the center overlap ratio. When N is an odd number, then A is equal to (N+1)2, and when N is an even number, then A is equal to N/2.

In some embodiments, the step of obtaining the displacement according to the first overlap ratio, the second overlap ratio and the center overlap ratio includes: subtracting the first overlap ratio from the center overlap ratio to obtain a first magnification; The center overlap ratio subtracts the second overlap ratio to obtain a second magnification; and the displacement is obtained according to the first magnification and the second magnification.

In some embodiments, the first magnification is substantially equal to the second magnification.

In some embodiments, the step of obtaining the displacement according to the first magnification and the second magnification includes: obtaining an average magnification by averaging the first magnification and the second magnification; The displacement is obtained in a lookup table, wherein the lookup table is configured to store a correspondence between the displacement and the average magnification.

In some embodiments, when the displacement is greater than a threshold, the state of the wafer is determined to be a fail state, and when the displacement is not greater than the threshold, the state of the wafer is determined to be A pass state. In some embodiments, the threshold is approximately 1.5 nm.

In some embodiments, the method further includes: when the state of the wafer is the fail state, removing the wafer from a batch of wafers; and when the state of the wafer is the pass state , the wafer remains in the batch of wafers.

In some embodiments, the threshold is approximately 1.5 nm.

Another embodiment of the present disclosure provides a manufacturing and measurement system. The system includes a processing chamber; and a measurement element. The processing chamber is configured to perform operations including: forming a first array of fins in a block of a die of a wafer; and forming a second array of fins in the first array of fins superior. The measurement element is configured to perform a patterned wafer geometry measurement on the wafer to obtain a distance between a first fin of the first fin array and a first fin of the second fin array A displacement, and also configured to determine a state of the wafer based on the displacement.

In some embodiments, the displacement is defined from a top view of the wafer.

In some embodiments, the first fin array and the second fin array have N fins, wherein N is a positive integer. The measurement element is also configured to: measure a first overlap ratio of the first fin of the first fin array and the first fin of the second fin array; measure one of the first fin array A second overlap ratio of the Nth fin and the Nth fin of the second fin array; and measuring the Ath fin of the first fin array and one of the second fin array A center overlap ratio of the Ath fin. When N is an odd number, A is equal to (N+1)/2, and when N is an even number, A is equal to N/2.

In some embodiments, the measurement element is further configured to: subtract the first overlap ratio from the center overlap ratio to obtain a first magnification; subtract the second overlap ratio from the center overlap ratio to obtain a second magnification; and obtaining the displacement according to the first magnification and the second magnification.

In some embodiments, the measuring element is further configured to obtain an average magnification by averaging the first magnification and the second magnification. The measuring element includes a lookup table configured to store a corresponding relationship between the displacement and the average magnification, and the measuring element is also configured to obtain the displacement according to the lookup table.

In some embodiments, when the displacement is greater than a threshold, the state of the die is determined to be a fail state. When the displacement is not greater than the critical value, the state of the grain is determined to be a pass state.

In some embodiments, the processing chamber is configured to remove the wafer from a batch of wafers when the state of the wafer is a fail state.

In some embodiments, the processing chamber is configured to retain the wafer in a wafer batch when the state of the wafer is a pass-through state.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

The various embodiments (or examples) of the disclosure depicted in the drawings are now described using specific language. It should be understood that no limitation of the scope of the present disclosure is meant here. Any changes or modifications of the described embodiments, and any further application of the principles described in this document, are considered to be within the ordinary skill of the art to which this disclosure pertains. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another, even if they share the same element number.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not constrained by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the presently advanced concepts.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. Presence, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a structural schematic diagram illustrating a manufacturing system 10 according to some embodiments of the present disclosure. Manufacturing system 10 is configured to process a batch of wafers B and also inspect each wafer W in the batch B to determine a status of each wafer W. For example, the manufacturing system 10 performs multiple semiconductor processes on the batch of wafers B, and measures a physical characteristic (such as a dimension of a specific structure) on each wafer W to determine the wafer W based on the measurement result. The state of circle W.

The manufacturing system 10 includes a processing chamber 100 and a measuring element 200 , and the measuring element 200 is coupled to the processing chamber 100 . The processing chamber 100 is configured to perform a plurality of semiconductor processes on the wafers W to form a semiconductor structure SS on each wafer W. The measurement unit 200 is configured to perform a measurement on each wafer W to determine the state of the wafer W.

In some embodiments, the processing chamber 100 fabricates a plurality of fin arrays on the wafer W in two layers. The measuring element 200 measures an overlap ratio between the fin arrays in two layers of the top view of the wafer W, thereby generating a magnification representing the displacement between the fin arrays in the two layers.

In some embodiments, the measurement performed by the measurement element 200 is a patterned wafer geometry (PWG) measurement. In some embodiments, the measurement device 200 includes a memory storing a look-up table 210 . The lookup table 210 stores a correspondence between the magnification and the displacement. In some embodiments, each correspondence stored in the lookup table 210 records a displacement and a magnification. For example, the measuring element 200 finds a corresponding relationship including the generated magnification, and then the measuring element 200 can know the displacement associated with the magnification according to the corresponding relationship in the look-up table 210 . Therefore, when the measuring element 200 obtains the magnification according to the overlapping ratio, the displacement can be obtained according to the look-up table 210 .

In some embodiments, the manufacturing system 10 determines the next manufacturing process of the wafer W according to the state of the wafer W. For example, the wafer W may be determined to be removed from the batch of wafers B, or may be determined to be processed by the next process.

Please refer to Figure 2. FIG. 2 is a schematic structural diagram illustrating a wafer W according to some embodiments of the present disclosure. In some embodiments, the wafer batch B includes more than one wafer W, and each wafer W undergoes the same semiconductor process and the same measurements.

In FIG. 2 , wafer W is a top view of wafer W drawn. An X-axis and a Y-axis are shown to represent the orientation of the wafer W. Referring to FIG. In some embodiments, the wafer W is a semiconductor wafer, for example, a silicon wafer. Wafer W includes a plurality of die D. In some embodiments, those grains D are the same. The number and location of the dies D in the wafer W shown in FIG. 2 are provided for descriptive purposes. Various numbers and positions of the dies D in the wafer W are within the scope of the present invention. Wafer W may have other dies D disposed around the edge of wafer W, for example.

Please refer to Figure 3. FIG. 3 is a structural block diagram illustrating a die D of some embodiments of the present disclosure. Die D is divided into a plurality of blocks (banks) BA. In some embodiments, those blocks BA have the same semiconductor structure SS after the processing chamber 100 performs the semiconductor processes. In FIG. 3 , there are 9 blocks shown in die D, however, the present disclosure is not limited thereto.

In some embodiments, the semiconductor structure SS on the die D includes a plurality of fins configured as a plurality of fin arrays. In some embodiments, the edges of the blocks BA are bounded by fin arrays in the semiconductor structure SS. In other words, the fins on die D are grouped into many arrays, and each array represents a block BA in crystal D. In other words, each block BA has a fin array that is separated from a fin array in other blocks BA.

Please refer to Figure 4 and Figure 5. FIG. 4 is a structural diagram illustrating a block BA viewed from the top view of the wafer W according to some embodiments of the present disclosure. FIG. 5 is a structural diagram illustrating a block BA viewed from a cross-section of the wafer W according to some embodiments of the present disclosure. In FIG. 4, the block BA is shown on the X-Y plane. In FIG. 5, the block BA is shown on the X-Z plane.

As shown in FIG. 5 , the cross-sectional view of the wafer W shows that the semiconductor structure SS has a first layer L1 and a second layer L2, the first layer L1 is disposed on the wafer W, and the second layer L2 is disposed on the first layer L1 . The semiconductor structure SS further includes a first fin array A1 in the first layer L1 and a second fin array A2 in the second layer L2. The first fin array A1 includes a plurality of fins, which are marked as F11, F12˜F1N, and the second fin array A2 includes a plurality of fins, which are marked as F21, F22˜F2N. In some embodiments, the number of the fins in the first fin array A1 is N, and the number of the fins in the second fin array A2 is N. N is an integer. In other words, the first fin array A1 and the second fin array A2 include the same number of fins.

In some embodiments, a first fin F11 of the first fin array A1 corresponds to a first fin F21 of the second fin array A2 . Similarly, a second fin F12 to an Nth fin F1N of the first fin array A1 correspond to a second fin F12 to an Nth fin F2N of the second fin array A2 respectively. In FIG. 5 , the first fins F21 of the second fin array A2 are disposed on the first fins F11 of the first fin array A1 and contact the first fins F11 of the first fin array A1 . Similarly, the second fins F22 to Nth fins F2N of the second fin array A2 are respectively disposed on the second fins F12 to the Nth fins of the first fin array A1 and contact the first fins respectively. The second fin F12 to the Nth fin of the fin array A1.

In some embodiments, the first to Nth fins F11 to F1N of the first fin array A1 are respectively the same as the first to Nth fins F11 to F2N of the second fin array A2 . The first to Nth fins F11 to F1N of the first fin array A1 overlap with the first to Nth fins F11 to F2N of the second fin array A2 respectively. Therefore, only the second fin array A2 can be seen from the top view of the wafer W as shown in FIG. 4 .

The first layer L1 and the second layer L2 are sequentially formed on the wafer W. In some embodiments, the first layer L1 is formed to have a flat upper surface, and the second layer L2 is formed on the flat upper surface of the first layer L1. However, in other embodiments, when the first fin array A1 is formed, the first layer L1 and the wafer W experience the stress caused by these processes. For example, a heat treatment may cause stress in the first layer L1 and the first fin array A1, and the stress may deform the first fin array A1 and the first layer L1. Since the materials of the first layer L1 and the first fin array A1 are different from the wafer W, a heterojunction is formed between the first layer L1 and the wafer W. Stress causes different strains in different materials. Therefore, due to the heterojunction, the first fin array A1 in the first layer L1 is deformed, and as shown in FIGS. 6 and 7 , the first layer L1 cannot have a flat upper surface. Therefore, the second layer L2 cannot be formed on the flat upper surface of the first layer L1.

Please refer to Figure 6. FIG. 6 is a structural schematic diagram illustrating a block BA viewed from the cross-section of the wafer W according to some other embodiments of the present disclosure. As shown in FIG. 6, the first fin array A1 in the first layer L1 is deformed. In some embodiments, compared with the first fin array A1 shown in FIG. 5 , the first fin F11 , the second fin F12 , the (N-1)th fin F1(N−1) and the Nth fin F1N are deformed.

In some embodiments, the first fin array A1 is symmetrical. The first fin F11 is symmetrical to the Nth fin F1N, and the second fin F12 is symmetrical to the (N−1)th fin F1 (N−1). Therefore, the following description will take the first fin F11 and the second fin F12 as an example, and the description of the (N−1)th fin and the Nth fin will not be repeated.

The fins of the first fin array A1 extend from the wafer W substantially along the Z-axis direction. Due to the deformation, the stress deforms the edge of the first fin array A1. Parts of the first fins F11 and the second fins F12 are inclined away from the first fin array A1 (for example, toward the negative Z-axis direction), and the first fins F11 are more deformed than the second fins F12 . As shown in FIG. 6 , only the deformation of the first fin F11 and the second fin F12 is shown, but the present disclosure is not limited thereto. In other embodiments, the stress deforms more than two fins on one element of the first fin array A1.

The first fin F21 and the second fin F22 correspond to the first fin F11 and the second fin F12 . In FIG. 6, the stress deforms the first fins F11 and the second fins F12, so that the upper surfaces of the first fins F11 and the second fins F12 are lower than the rest of the first fin array A1 on the Z axis. fins. Therefore, when the second layer L2 and the second fin array A2 are formed on the deformed first fin array A1, the first fins F21 and the second fins F22 extend deeper than other fins of the second fin array. (towards the negative X-axis direction). Furthermore, due to the deformation, the positions of the first fins F11 and the first fins F21 are not aligned. Similarly, the positions of the second fins F12 and F22 are not aligned due to deformation. Therefore, a displacement d1, a displacement d2, a displacement s(N-1), and a displacement dN representing the deformation are shown in FIG. 6 .

Please refer to Figure 7. FIG. 7 is a structural diagram illustrating a block BA viewed from a cross-section of the wafer W according to some alternative embodiments of the present disclosure. As shown in FIG. 7, the first fin array A1 in a first layer L1 is deformed. In some embodiments, compared with the first fins F11 and the second fins F12 shown in FIG. 5 , the first fins F11 and the second fins F12 of the first fin array A1 are deformed.

The fins of the first fin array A1 extend from the wafer W substantially along the Z-axis. Due to the deformation, the stress deforms the edge of the first fin array A1. The upper portions of the first fins F11 and the second fins F12 are inclined toward the first fin array A1 (for example, toward the X-axis direction), and the first fins F11 are more deformed than the second fins F12 . As shown in FIG. 7 , only the deformed first fins F11 and second fins F12 are shown, but the present disclosure is not limited thereto. In another embodiment, the stress deforms more than two fins on the edge of the first fin array A1.

Similar to the embodiments in FIG. 6 , in FIG. 7 , the upper surfaces of the first fins F11 and the second fins F12 are lower than other fins of the first fin array A1 on the Z axis. When the second layer L2 and the second fin array A2 are formed on the deformed first fin array A1, the first fins F21 and the second fins F22 extend deeper than other fins of the second fin array A2 (direction toward the negative Z axis). Furthermore, due to the deformation, the positions of the first fins F11 and the first fins F21 are not aligned. Similarly, the positions of the second fins F12 and F22 are not aligned due to deformation. Therefore, displacement d1, displacement d2, displacement d(N-1), and displacement dN representing deformation are shown in FIG. 7 .

Please refer to Figure 8. FIG. 8 is a structural diagram illustrating the block BA shown in FIG. 6 viewed from the cross-section of the wafer W according to some embodiments of the present disclosure. As shown in FIG. 6 , the positions of the first fins F11 and the first fins F21 are not aligned, and the positions of the second fins F21 and the second fins F22 are not aligned. Compared with the block BA shown in FIG. 4 , one side of the first fin F11 and one side of the second fin F12 do not overlap with the first fin F21 and the second fin F22 respectively. Therefore, the sides of the first fins F11 and the second fins F12 can be seen from the top view of the wafer W as shown in FIG. 8 .

The displacement d1 represents a length of the side of the first fin F11 that does not overlap the first fin F21 along the X-axis, and the displacement d2 represents that the second fin F12 does not overlap the second fin F22 along the X-axis A length of the side of . Similarly, displacement dN represents a length of the side of the Nth fin F1N that does not overlap the first fin F2N along the X-axis, and displacement d(N-1) represents the (N-1)th fin F2(N-1) A length of the side that does not overlap with the (N-1)th fin F2(N-1) along the X-axis. In addition, a width d represents the width of the fins in the first fin array A1 and the second fin array A2 . In some embodiments, the displacement d1 is greater than the displacement d2, and the displacement dN is greater than the displacement D(N−1).

In some embodiments, the displacement d1, the displacement d2, the displacement d(N−1), and the displacement dN are approximately several nanometers. However, in conventional methods, the measurement equipment cannot have a measurement resolution down to the nanometer level. Therefore, the displacements d1 -dN cannot be directly measured by the measuring element 200 . Compared with the conventional method, the present application uses the measurement element 200 to perform the PWG measurement, and the displacements d1-dN can be obtained by converting the measurement results of the PWG measurement. The details of the steps for obtaining the displacements d1-dN are described below.

The measuring element 200 is configured to measure the overlapping ratio of the first fin array A1 and the second fin array A2 by performing PWG measurement. In some embodiments, the measuring element 200 measures the overlapping ratio R1 of the first fin F11 and the first fin F21, the overlapping ratio RN of the Nth fin F1N and the Nth fin F2N, and the Ath fin Center overlap ratio RA of F1A and A-th fin F2A. When N is an odd number, A is equal to (N+1)/2. When N is an even number, A is equal to N/2. The overlap ratio R1 can be expressed as (d-d1)/d. Similarly, the overlap ratio RN can be expressed as (d-dN)d. In some embodiments, the Ath fin F1A completely overlaps the Ath fin F2A. Therefore, the center overlap ratio RA is approximately equal to zero. In some embodiments, the overlap ratio R1 is equal to the overlap ratio RN.

After obtaining the overlapping ratios R1, RN and RA, the measuring element 200 obtains a magnification M1 associated with the displacement d1 and a magnification MN associated with dN. The magnification M1 can be obtained by subtracting the overlap ratio R1 from the center overlap ratio RA, and the magnification MN can be obtained by subtracting the overlap ratio RN from the center overlap ratio RA. In some embodiments, the magnification M1 is approximately equal to the magnification MN.

After obtaining the magnification M1 and the magnification MN, the measurement device 200 can obtain the displacement d1 and the displacement dN by finding the corresponding relationship associated with the magnification M1 and the magnification MN in the look-up table 210 . In some embodiments, the measuring element 200 is also configured to obtain an average magnification Mavg by averaging the magnification M1 and the magnification MN. The measuring element 200 finds a corresponding relationship associated with the average magnification Mavg in the look-up table 210, and also obtains an average displacement davg according to the corresponding relationship.

The measuring unit 200 determines the state of the wafer W according to the displacement d1, the displacement dN and/or the average displacement davg. When the displacement d1, the displacement dN and/or the average displacement davg is greater than a threshold value, the measurement unit 200 determines that the state of the wafer W is a fail state FAIL. In this case, the fail status FAIL indicates that the deformation of the first fin array A1 in the first layer L1 of the wafer W exceeds manufacturing tolerances such that the displacement d1, the displacement dN and/or the average displacement davg greater than the critical value. Therefore, the wafer W will be removed from the batch of wafers B, and the wafer W will not be processed in the subsequent process.

On the contrary, when the displacement d1, the displacement dN and the average displacement davg are not greater than the critical value, then the measurement unit 200 determines that the state of the wafer W is a passing state PASS. In this case, the deformation of the first fin array A1 in the first layer L1 of the wafer W is within manufacturing tolerances, indicated by the state PASS, so that the displacement d1, the displacement dN and the average displacement davg are not greater than a critical value . Therefore, the wafer W will remain in the batch of wafers B, and the wafer W will be processed in the next process.

Compared with the embodiments shown in FIG. 4, in FIG. 6 and FIG. 8, the position of the first fin F11 in the first layer L1 deviates from the original position toward the negative X-axis direction, and The position of the Nth fin F1N in L1 deviates from the original position toward the X-axis direction. In this embodiment, the first fin array A1 in the first layer L1 may experience a tensile stress, and the edges of the first fin array A1 (for example, the first fin F11 and the N-th fin F1N) extending outward from the first fin array A1.

Please refer to Figure 9. FIG. 9 is a structural diagram illustrating the block BA shown in FIG. 7 viewed from the cross-section of the wafer W according to some embodiments of the present disclosure. As shown in FIG. 7 , the positions of the first fins F11 and the first fins F21 are not aligned, and the positions of the second fins F12 and the second fins F22 are not aligned. Compared with the block BA shown in FIG. 4 , one side of the first fin F11 and one side of the second fin F12 do not overlap with the first fin F21 and the second fin F22 respectively. Therefore, the side portions of the first fin F11 and the second fin F12 can be seen from the top view of the wafer W as shown in FIG. 9 .

Similar to those embodiments shown in FIG. 8, the displacement d1 represents the length by which the sides of the first fin F11 do not overlap with the first fin F21 along the X-axis, and the displacement d2 represents the length of the second fin F12. The length by which the sides do not overlap the second fin F22 along the X-axis. Similarly, the displacement dN represents the length of the side of the Nth fin F1N that does not overlap the second fin F2N along the X axis, and the displacement d(N-1) represents the length of the (N-1)th fin F1 The side portion of (N-1) does not overlap the length of the second fin F2(N-1) along the X-axis. In addition, a width d represents the width of the fins in the first fin array A1 and the second fin array A2. In some embodiments, the displacement d1 is greater than the displacement d2, and the displacement dN is greater than the displacement d(N−1).

In some embodiments, the displacement d1, the displacement d2, the displacement d(N−1), and the displacement dN are approximately several nanometers.

Compared with the embodiments shown in FIG. 4, in FIG. 7 and FIG. 9, the position of the first fin F11 in the first layer L1 deviates from the original position toward the X-axis direction, and in the first layer L1 The position of the Nth fin F1N deviates from the original position toward the negative X-axis direction. In this embodiment, the first fin array A1 in the first layer L1 may experience a compressive stress, and the edges of the first fin array A1 (for example, the first fin F11 and the N-th fin F1N) Compress inwards to the center of the first fin array A1.

The measuring element 200 is configured to measure the overlapping ratios R1, RN and RA of the first fin array A1 and the second fin array A2 by performing PWG measurement. The measuring element 200 is also configured to obtain the magnifications M1, MN and/or the average magnification Mavg according to the overlapping ratios R1, RN and RA in order to obtain the displacements associated with the magnifications M1, MN and Mavg according to the look-up table 210 d1, displacement dN and/or average displacement davg. The above-mentioned steps are similar to the steps described in FIG. 6 and FIG. 8 . Therefore, the details of the steps of displacement d1, displacement dN and average displacement davg will not be repeated herein.

Please refer to Figure 10. 10 is a flow diagram illustrating a method M10 of fabricating a semiconductor structure SS on a wafer W and performing patterned wafer geometry (PWG) measurements according to some embodiments of the present disclosure. The method M10 includes steps S101, S102, S103, S104, S105, S106, S107.

In step S101 , a wafer W is received, and the wafer W has a plurality of dies D . In step S102 , a plurality of semiconductor structures SS are formed in each die D. As shown in FIG. Each semiconductor structure SS includes a first fin array A1 and a second fin array A2, and the second fin array A2 is disposed above the first fin array A1. In step S103 , PWG measurement is performed on the wafer W to obtain the displacement d1 between the first fins F11 of the first fin array A1 and the first fins F21 of the second fin array A2 . In step S104, the state of the wafer W is determined according to the displacement d1. In step S105, when the status of the wafer W is FAIL, the wafer W is removed from the batch of wafers B. In step S106, when the status of the wafer W is PASS, the wafer W remains in the batch of wafers B. In step S107 , the next process is performed on the wafer W having the passing status of the batch of wafers B as PASS. In some embodiments, the subsequent process is a lithography process. In other embodiments, the subsequent process is an etch process.

Please refer to Figure 11. FIG. 11 is a schematic flowchart illustrating some embodiments of the present disclosure such as step S102 shown in FIG. 10 . Step S102 includes steps S111 and S112.

In step S111 , a first fin array A1 is formed in each block BA. In step S112 , the second fin array A2 is formed on the first fin array A1 .

Please refer to Figure 12. FIG. 12 is a schematic flowchart illustrating some embodiments of the present disclosure such as step S111 shown in FIG. 11 . Step S111 includes steps S121, S122 and S123. Please refer to Figure 17, Figure 18 and Figure 19. FIG. 17 to FIG. 19 are structural diagrams illustrating the semiconductor structure SS in different manufacturing steps according to some embodiments of the present disclosure.

In step S121 , a first layer L1 is formed on the wafer W as shown in FIG. 17 . The first layer L1 may be deposited on the wafer W by performing chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition. In step S122 , as shown in FIG. 18 , the first layer L1 is etched to form a first fin array A1 . In some embodiments, the fabrication technique of the first fin array A1 may include depositing the material of the first fin array A1 into etched vacancies in the first layer L1. In step S123 , as shown in FIG. 19 , the first layer L1 is planarized to expose the upper surface of the first fin array A1 .

Please refer to Figure 13. FIG. 13 is a schematic flowchart illustrating some embodiments of the present disclosure such as step S112 shown in FIG. 11 . Step S112 includes steps S131, S132 and S133. Please also refer to FIG. 20 , FIG. 21 and FIG. 5 . 20 and 21 are structural schematic diagrams illustrating the semiconductor structure SS in different manufacturing steps according to some embodiments of the present disclosure.

In step S131 , as shown in FIG. 20 , a second layer L2 is formed on the first fin array A1 . The second layer L2 may be deposited on the wafer W by performing chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition. In step S132 , as shown in FIG. 21 , the second layer L2 is etched to form a second fin array A2 . In some embodiments, the fabrication technique of the second fin array A2 may include depositing the material of the second fin array A2 into a plurality of etch openings in the second layer L2. In step S133 , as shown in FIG. 5 , the second layer L2 is planarized to expose the upper surface of the second fin array A2 .

Please refer to Figure 14. FIG. 14 is a schematic flowchart illustrating some embodiments of the present disclosure such as step S103 shown in FIG. 11 . Step S103 includes steps S141, S142, S143 and S144.

In step S141 , the overlapping ratio R1 of the first fin F11 of the first fin array A1 and the Nth fin F21 of the second fin array A2 is obtained. In step S142 , the overlapping ratio RN of the Nth fin F1N of the first fin array A1 and the Nth fin F2N of the second fin array A2 is obtained. In step S143 , the center overlap ratio RA of the fins F1A of the first fin array A1 and the fins F2A of the second fin array A2 is obtained. In step S144, the displacement d1 is obtained according to the overlapping ratios R1, RN and RA.

Please refer to Figure 15. FIG. 15 is a schematic flowchart illustrating some embodiments of the present disclosure such as step S144 shown in FIG. 14 . Step S144 includes steps S151, S152 and S153.

In step S151 , the magnification M1 is obtained by subtracting the overlap ratio R1 from the center overlap ratio RA. In step S152, the magnification MN is obtained by subtracting the overlap ratio RN from the center overlap ratio RA. In some embodiments, the displacement d1 is obtained according to the magnifications M1 and MN.

Please refer to Figure 16. FIG. 16 is a schematic flowchart illustrating some embodiments of the present disclosure such as step S153 shown in FIG. 15 . Step S153 includes steps S161 and S162.

In step S161 , the average magnification Mavg is obtained by the average magnification M1 and the magnification MN. In step S162 , the displacement d1 and/or the displacement davg are obtained from the lookup table 210 .

In some embodiments, step S161 is omitted from method M10. The displacement davg is obtained by finding the correspondence in the look-up table 210 using the magnification M1. In some embodiments, the magnification M1 is approximately equal to the average magnification Mavg, and the displacement d1 is approximately equal to the average displacement davg.

An embodiment of the disclosure provides a method for manufacturing and measuring a plurality of semiconductor structures. The method includes the steps of: receiving a wafer having a plurality of dies; respectively forming the plurality of semiconductor structures in a plurality of blocks of each die, wherein each semiconductor structure has a first fin array and a second array of fins, the second array of fins located above the first array of fins; performing a patterned wafer geometry measurement on the wafer to obtain a first array of fins on the first fin array a displacement between a fin and a first fin of the second fin array; and determining a state of the wafer according to the displacement.

Another embodiment of the present disclosure provides a manufacturing and measurement system. The system includes a processing chamber; and a measurement element. The processing chamber is configured to perform operations including: forming a first array of fins in a block of a die of a wafer; and forming a second array of fins in the first array of fins superior. The measurement element is configured to perform a patterned wafer geometry measurement on the wafer to obtain a distance between a first fin of the first fin array and a first fin of the second fin array A displacement, and also configured to determine a state of the wafer based on the displacement.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such process, machinery, manufacture, material composition, means, method, or steps are included in the patent scope of this application.

10: Manufacturing system 100: processing chamber 200: Measuring element 210: lookup table A1: The first fin array A2: Second fin array B: A batch of wafers BA: block d(N-1): displacement D: grain d: width d1: displacement d2: displacement dN: displacement F11, F12~F1N: fins F21, F22~F2N: fins FAIL: failed status L1: first floor L2: second floor M10: Method PASS: pass status S101: step S102: step S103: step S104: step S105: step S106: step S107: step S111: step S112: step S121: step S122: step S123: step S131: step S132: step S133: step S141: step S142: step S143: step S144: step S151: step S152: step S153: step S161: step S162: step SS: Semiconductor Structure W: Wafer X: direction axis Y: direction axis Z: direction axis

The disclosure content of the present application can be understood more fully when the drawings are considered together with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components. FIG. 1 is a structural schematic diagram illustrating a manufacturing system of some embodiments of the present disclosure. FIG. 2 is a schematic structural diagram illustrating a wafer according to some embodiments of the present disclosure. FIG. 3 is a structural block diagram illustrating a die of some embodiments of the present disclosure. FIG. 4 is a structural schematic diagram illustrating blocks of some embodiments of the present disclosure viewed from the top view of the wafer. FIG. 5 is a structural diagram illustrating blocks of some embodiments of the present disclosure viewed from a cross-sectional view of the wafer. FIG. 6 is a structural diagram illustrating blocks viewed from a cross-section of the wafer according to other embodiments of the present disclosure. FIG. 7 is a schematic structural diagram illustrating blocks viewed from a cross-section of the wafer of some alternative embodiments of the present disclosure. FIG. 8 is a schematic structural diagram illustrating the blocks shown in FIG. 6 viewed from the cross-section of the wafer according to some embodiments of the present disclosure. FIG. 9 is a structural schematic diagram illustrating the blocks shown in FIG. 7 viewed from the cross-section of the wafer according to some embodiments of the present disclosure. 10 is a flow diagram illustrating a method of fabricating semiconductor structures on a wafer and performing patterned wafer geometry (PWG) measurements according to some embodiments of the present disclosure. FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 , and FIG. 16 are detailed flowcharts illustrating the method shown in FIG. 10 in some embodiments of the present disclosure. FIG. 17 , FIG. 18 , and FIG. 19 are structural schematic diagrams illustrating the semiconductor structure described in FIG. 12 according to some embodiments of the present disclosure. 20 and 21 are structural schematic diagrams illustrating the semiconductor structure described in FIG. 13 according to some embodiments of the present disclosure.

10: Manufacturing system 100: processing chamber 200: Measuring element 210: lookup table B: A batch of wafers FAIL: failed status PASS: pass status W: Wafer

Claims (11)

A method of manufacturing and measuring a plurality of semiconductor structures, comprising: receiving a wafer having a plurality of dies; forming the plurality of semiconductor structures respectively in a plurality of blocks of each die, wherein each semiconductor The structure has a first fin array and a second fin array, the second fin array is located above the first fin array, including forming the first fin array in each block, including: forming a first layer; etching the first layer to form the first fin array; and planarizing the first layer to expose an upper surface of the first fin array; performing a patterned wafer geometry on the wafer measuring to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array; and determining a state of the wafer based on the displacement. The method as claimed in claim 1, wherein respectively forming the plurality of semiconductor structures in the plurality of blocks of each die comprises: forming the second fin array on the first fin array. The method of claim 2, wherein both the first fin array and the second fin array have N fins, where N is a positive integer, wherein the first fin array of the first fin array fins corresponding to the first fins of the second fin array, wherein the displacement between the first fins of the first fin array and the first fins of the second fin array is from the A top view of a semiconductor structure defined. The method according to claim 3, wherein forming the second fin array on the first fin array comprises: forming a second layer on the first fin array; etching the second layer to form the first fin array two fin arrays; and planarizing the second layer to expose an upper surface of the second fin array. The method of claim 4, wherein a patterned wafer geometry measurement is performed on the wafer to obtain a first fin between a first fin array and a first fin of the second fin array The displacement between fins includes: obtaining a first overlap ratio of the first fins of the first fin array and the first fins of the second fin array; obtaining a first overlap ratio of the first fin array A second overlap ratio of the Nth fin and an Nth fin of the second fin array; obtaining an Ath fin of the first fin array and a first overlap ratio of the second fin array A center overlap ratio of A fins; and obtaining the displacement according to the first overlap ratio, the second overlap ratio and the center overlap ratio; wherein when N is an odd number, A is equal to (N+1)2 , and when N is an even number, then A is equal to N/2. The method according to claim 5, wherein according to the first overlap ratio, the second overlap ratio And the center overlap ratio to obtain the displacement includes: subtracting the first overlap ratio from the center overlap ratio to obtain a first magnification; subtracting the second overlap ratio from the center overlap ratio to obtain a second magnification; and The displacement is obtained according to the first magnification and the second magnification. The method of claim 6, wherein the first magnification is substantially equal to the second magnification. The method as claimed in claim 6, wherein obtaining the displacement according to the first magnification and the second magnification comprises: obtaining an average magnification by averaging the first magnification and the second magnification; and The displacement is obtained in a lookup table configured to store a correspondence between the displacement and the average magnification. The method as claimed in claim 1, wherein when the displacement is greater than a critical value, it is determined that the state of the wafer is a failed state, and when the displacement is not greater than the critical value, it is determined that the wafer This state is a pass state. The method according to claim 9, further comprising: when the state of the wafer is the failed state, removing the wafer from a batch of wafers; and when the state of the wafer is the pass status, the wafer remains in the lot. The method of claim 9, wherein the critical value is about 1.5nm.

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