TWI809741B - Multichip system having command transfer mechanism and address generating method - Google Patents

Abstract

A multichip system includes a transmitter-end chip and a receiver-end chip. The transmitter-end chip includes a first port. The receiver-end chip includes a second port. The first port is coupled to the second port, and a work mode of the first port is different from that of the second port. When the transmitter-end chip is coupled to the receiver-end chip without through another chip, the transmitter-end chip determines a first target address of the receiver-end chip with respect to the transmitter-end chip, and transfers a command to the receiver-end chip according to the first target address.

Description

Multi-chip system with command forwarding mechanism and address generation method

This case is about a multi-chip system, especially about a multi-chip system with a command forwarding mechanism applicable to multi-level chips and an address generation method.

In existing multi-chip systems, the function of the master chip is usually different from that of the slave chips. When the master chip and the slave chip need to work together to complete a specific function, the developer of the multi-chip system needs to design a set of codes for controlling the master chip and a set of codes for the slave chip according to the application scenario of the multi-chip system . If the application scenario of the multi-chip system or the specific function needs to be adjusted, the multi-chips need to be able to send, receive and forward commands. At present, chips usually have an interface that can communicate with each other. In the prior art, the mechanism for sending, receiving and forwarding commands between multiple chips is not perfect.

In some implementation aspects, one of the purposes of the present invention is to provide a multi-chip system with a command forwarding mechanism and an address generation method to improve the deficiencies of the prior art.

In some embodiments, the multi-chip system includes a transmitting chip and a receiving chip. The sender chip includes a first connection port. The receiver chip includes a second connection port, the first connection port is coupled to the second connection port, and the operation mode of the first connection port is different from that of the second connection port. When the sending end chip is not connected to the receiving end chip through other chips, the sending end chip determines a first target address of the receiving end chip relative to the sending end chip according to the working mode of the first connection port, And forward a command to the receiver chip according to the first target address.

In some implementations, this case proposes an address generation method applied to a multi-chip system. The multi-chip system includes a sending-end chip and a receiving-end chip. The sending-end chip includes a first connection port, and the receiving-end chip includes a first Two connection ports, the first connection port is coupled to the second connection port, the address generation method includes: the sending chip determines a first address of the receiving chip relative to the sending chip according to the working mode of the first connecting port target address; and, the transmitting chip forwards a command to the receiving chip according to the first target address.

In some implementations, the multi-chip system can use the working mode of the connection port of the chip itself and the identification code of the bus to set the relative target address of each chip. In this way, dies in a multi-die system can forward commands to other dies. The above-mentioned command forwarding mechanism only involves the identification code between hardware and the target address of the script. Therefore, the command forwarding mechanism does not involve control code modification, so it can have high versatility.

About the feature, implementation and effect of this case, hereby cooperate with drawing as preferred embodiment and describe in detail as follows.

100:Multi-chip system

110: switch

200: chip

210: Digital circuit

220: interface circuit

230: port

A~E: Wafer

B1, B1_1, B3~B5: busbar

chip_id: chip identification code

P0~P5: Connecting port

port 0, port 1: the identification code of the connection port

S1~S5: Operation

[Fig. 1] is a schematic diagram of a multi-chip system drawn according to some embodiments of this case; [Fig. 2A] is a schematic diagram of a chip drawn according to some embodiments of this case; and [Fig. 2B] is a schematic diagram of drawing command forwarding according to some embodiments of this case flow chart.

All terms used herein have their ordinary meanings. The definitions of the above-mentioned terms in commonly used dictionaries, and the use examples of any terms discussed here in the content of this case are only examples and should not limit the scope and meaning of this case. Likewise, this case is not limited to the various embodiments shown in this specification.

As used herein, "coupling" or "connection" can refer to two or more elements in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and can also refer to two or more components. Components operate or act on each other. As used herein, the term "circuit" can be a device that is connected in a certain way to process signals by at least one transistor and/or at least one active and passive element.

In some implementations, the multi-chip system provided by some embodiments of the present application can implement a message/command synchronization mechanism between chips, so that these chips can use forwarding in an environment connected through a default connection interface. The way of command drives itself or another chip to perform the corresponding operation, so as to realize the logic application environment with high versatility. In different applications, the multi-chip system provided in some embodiments of this application may use C++ codes/or software frameworks in Linux systems to define functions, commands and/or parameter types, but this application is not limited thereto.

FIG. 1 is a schematic diagram of a multi-chip system 100 according to some embodiments of the present invention. The multi-chip system 100 includes a plurality of chips A˜E and a switch 110 . Chip A includes port P0, chip B includes port P1, chip C includes port P2 and port P3, chip D includes port P4, and chip E includes port P5. In some embodiments, the switch 110 is a switch with a fast peripheral component interconnection (Peripheral Component Interconnect Express, PCI-E) interface, and the connection port P0 of these chips A can be coupled to the chip through the PCI-E interface The connection port P1 of B, the connection port P2 of chip C, and the connection port P4 of chip D. The connection port P3 of the chip C is coupled to the connection port P5 of the chip E.

The arrangement between die A and each of the other dies B, C, and D connected thereto belongs to the first-order connection. In this example, chip A can be operated as a master chip, and the remaining chips B-E can be operated as slave chips. Under this condition, based on the relevant standards of the PCI-E bus, the working mode of the connection port P0 is different from the working modes of the other connection ports P1 , P2 and P4 . For example, the working mode of the port P0 is the root complex (RC) mode, and the working modes of the other ports P1, P2 and P4 are the endpoint (EP) mode. The RC mode is the working mode of the main chip in the PCI-E system, and it can only be connected to the connection port working in the EP mode. The EP mode is a working mode in which the chip operates as a slave chip in the PCI-E system. In addition, the chip A is connected to the chip E through the chip C, so the chip A and the chip E belong to the secondary connection, wherein the connection port P3 and the connection port P5 operate in different modes. For example, port P3 operates in RC mode, and port P5 operates in EP mode.

In some embodiments, a corresponding chip in the plurality of chips A~E (hereinafter referred to as the sending end chip) can use the related operations discussed in the following paragraphs to identify another chip in the plurality of chips A~E (hereinafter referred to as the receiving end chip). Chip) relative target address in the multi-chip system 100, and use the target address to forward the command to the receiving end chip, so as to control the receiving end chip to execute subsequent commands. To understand the operation of command forwarding Operation, the following paragraphs will sequentially explain the various ways of determining the target address and the operation examples of command forwarding. In different embodiments, the transmitting chip can be a master chip or a slave chip, and the receiving chip can also be a slave chip or a master chip.

(1) When the sending end chip is connected to the receiving end chip at the first level, and the connection port of the sending end chip is operating in EP mode, the method of determining the target address of the receiving end chip is as follows:

In some embodiments, when the connection mode between the sending end chip and the receiving end chip is a first-level connection (that is, the sending end chip is connected to the receiving end chip without passing through other chips), the sending end chip can be connected according to the sending end chip. The working mode of the connection port determines the target address of the receiving chip relative to the sending chip, and forwards the command to the receiving chip according to the target address of the receiving chip, so that the receiving chip executes the command.

For example, the transmitting die is die C and the receiving die is die A. Since the port P2 of chip C operates in EP mode (that is, chip C operates as a slave chip relative to chip A), chip C can determine the target address of chip A relative to chip C according to the identifier of the port P2. In some embodiments, in a corresponding chip among the plurality of chips A˜E, the corresponding connection port has an identification code. For example, the chip A includes a connection port P0, so the identification code of the connection port P0 is the first value (for example, it can be 0x10000; marked as port 0). Alternatively, the chip C includes two connection ports P2 and P3, wherein the identification code of the connection port P2 is a first value (such as 0x10000), and the identification code of the connection port P3 is a second value (such as 0x10001; noted as port 1). By analogy, it should be possible to understand the corresponding relationship between the multiple connection ports P0-P5 and their identification codes in FIG. 1 . Since the chip C is connected to the chip A through the connection port P2, the chip C can determine the target address of the chip A as 0x10000 according to the identification code of the connection port P2.

Accordingly, when the sending end chip and the receiving end chip are connected at the first level and the working mode of the connection port of the sending end chip (which is connected to the receiving end chip) is EP mode, the sending end chip can determine the receiving end chip according to the identification code of the connecting port. end chip destination address. The above relationship can be organized into the following table 1:

(2) When the sending end chip is connected to the receiving end chip at the first level, and the connection port of the sending end chip is operated in RC mode, the method of determining the target address of the receiving end chip is as follows:

Compared with the above example, in some embodiments, if the transmitting chip is operated as the main chip, the transmitting chip can further be based on the identification code of the connection port of the transmitting chip and the connecting port of the transmitting chip and the connecting port of the receiving chip The identification code of the bus bar between determines the target address. For example, the transmitting die is die A and the receiving die is die B. Since port P0 of chip A operates in RC mode (i.e., chip A is operating as the master chip relative to chip B), chip A can The identification code determines the destination address of wafer B relative to wafer A.

In some embodiments, the port P0 is connected to any one of the other ports P1 , P2 and P4 via a bus (ie, a PCI-E bus) in the switch 110 . For example, port P0 is connected to port P1 via bus B3, port P0 is connected to port P2 via bus B4, port P0 is connected to port P4 via bus B5, and port P3 is connected via bus B1_1. to port P5. Similar to the port ID, each bus has a corresponding ID. Chip A can be The target address of the chip B is determined according to the identification code of the port P0 and the identification code of the bus B3. For example, if the identification code of the connection port P0 is the first value (ie port 0), the chip A can determine that the target address of the chip B is the identification code of the bus B3. Alternatively, if the identification code of the connection port P0 is the second value (port 1), the chip A can add a preset value (such as, but not limited to, 128) to the identification code of the bus bar B3 to determine the chip B target address. In the example shown in FIG. 1 , the identification code of the port P0 is port 0, so the chip A uses the first method to determine the target address of the chip B.

According to this, when the sending chip and the receiving chip are configured as a first-level connection and the working mode of the connection port of the sending chip (which is connected to the receiving chip) is RC mode, the sending chip can use the identification code of the connecting port and The identification code (denoted as bus_id) of the bus between the sending chip and the receiving chip determines the target address of the receiving chip. The above relationship can be organized into the following table 2:

(3) When the sending end chip and the receiving end chip are two-level connections, and the connection port of the sending end chip operates in RC mode and the connection port connected to the receiving end chip on the bridge chip operates in RC mode, the target of the receiving end chip How the address is determined:

Compared with the above examples, in some embodiments, if the transmitting chip is connected to the receiving chip through a bridge chip, the transmitting chip can use the bridge chip to forward commands to the receiving chip. The transmitter chip determines the bridge chip relative The target address on the sender chip, and the receiver chip is determined from the ID of the bridge chip's bus (which connects to the receiver chip) and the bus bar between the ports of the bridge chip and the receiver chip Target address relative to the bridge chip. In this way, the transmitting chip can determine the target address of the receiving chip relative to the transmitting chip according to the target address of the bridge chip relative to the transmitting chip and the target address of the receiving chip relative to the bridge chip.

For example, in the example of FIG. 1 , chip A and chip E are two-level connections, wherein the transmitting chip can be chip A, the bridge chip can be chip C, and the receiving chip can be chip E. The chip A can determine the target address of the chip C relative to the chip A according to the identification code of the connection port P0 and the identification code of the bus B4 between the connection port P0 and the connection port P2. Referring to the above Table 2, it should be understood that since the identification code of the port P0 is port 0, the chip A can set the identification code of the bus B4 as the target address of the chip C relative to the chip A. Similarly, the chip C can determine the target address of the chip E relative to the chip C according to the identification code of the connection port P3 and the identification code of the bus B1_1 between the connection port P3 and the connection port P5. Referring to the above Table 2, it should be understood that since the identification code of the connection port P3 is port 0, the chip C can set the identification code of the bus B1_1 as the target address of the chip E relative to the chip C. In this way, chip A can determine the target address of chip E relative to chip A according to the target address of chip C relative to chip A and the target address of chip E relative to chip C. In some embodiments, chip A can combine some bits of the target address of chip C with respect to chip A and some bits of the target address of chip E with respect to chip C to form the target address of chip E with respect to chip A . For example, the first 8 bits of the target address of chip E relative to chip A may be at least a part of the target address of chip C relative to chip A, and the last 8 bits of the target address of chip E relative to chip A The element may be at least a portion of the bits in the target address of die E relative to die C.

上表3中的(T1<<8)｜T0代表接收端晶片相對於發送端晶片的目標地址的前置位元可由接收端晶片相對於橋接晶片的目標地址T1中的至少一部分位元決定，且接收端晶片相對於發送端晶片的目標地址的後置位元可由橋接晶片相對於發送端晶片的目標地址T0中的至少一部分位元決定。 In other words, in the configuration of the two-level connection, the sender chip can sequentially determine the target address of the bridge chip relative to the sender chip (marked as T0) and the target address of the receiver chip relative to the bridge chip (marked as T1), The information of the above two target addresses is used to generate the target address of the receiver chip relative to the sender chip. Accordingly, when the sending end chip and the receiving end chip are configured as a secondary connection and the working mode of the connection port of the sending end chip (which is connected to the receiving end chip) is RC mode, the destination address of the receiving end chip relative to the sending end chip The decision methods can be summarized in Table 3 below:

(T1<<8)|T0 in Table 3 above represents that the pre-bits of the target address of the receiving end chip relative to the sending end chip can be determined by at least a part of the bits in the target address T1 of the receiving end chip relative to the bridge chip, In addition, the last bits of the target address of the receiving chip relative to the transmitting chip can be determined by at least a part of the bits of the target address T0 of the bridge chip relative to the transmitting chip.

(4) The process and concept of command forwarding:

FIG. 2A is a schematic drawing of a wafer 200 according to some embodiments of the present invention. The wafer 200 can be any one of the wafers A˜E shown in FIG. 1 . The chip 200 includes a digital circuit 210 , an interface circuit 220 and a connection port 230 . The digital circuit 210 can be the main signal processing circuit in the chip 200 , and it can perform corresponding operations according to the application of the chip 200 . The digital circuit 210 may be, but not limited to, a processor circuit, an ASIC, and the like. The interface circuit 220 can be a controller circuit of the PCI-E interface to control the transmission of data and/or commands of the connection port 230 . The connecting port 230 can be at least one of the connecting ports P0˜P5 in FIG. 1 . For example, If chip 200 is chip A, connection port 230 may be connection port P0. Alternatively, if the chip 200 is the chip C, the connection port 230 can be the connection port P2 and the connection port P3.

The interface circuit 220 can adjust the chip identification code chip_id stored in the interface circuit 220 according to various preset commands, and the chip_id is the target address of the chip receiving the command relative to the sending chip 200 . For example, when the received default command indicates the target address of the chip 200 , the interface circuit 220 can set the chip identification code chip_id to a default value (for example, 0). Alternatively, when the received default command is a command for disconnecting the command forwarding connection, the interface circuit 220 may set the chip identification code chip_id to another value (for example, 1). The digital circuit 210 can confirm whether to execute the received command according to the chip identification code chip_id. For example, when the chip identification code chip_id is 0, the digital circuit 210 can execute the received command. Alternatively, when the chip identification code chip_id is not 0, the digital circuit 210 does not execute the received command, but extracts the identification word of the bus according to the chip identification code chip_id and the working mode of the connection port 230, and forwards the command To another chip (not shown in FIG. 2A ) where the bus bar is connected to the digital circuit 210 .

FIG. 2B is a flowchart illustrating command forwarding according to some embodiments of the present invention. Generally speaking, the input and output of commands can be divided into user input and output layer, transmission layer and execution layer in order from top to bottom. For easy understanding, FIG. 2B only shows the operation flow of the execution layer related to wafer A, wafer C, and wafer E of FIG. 1 .

After chip A receives the command (operation S1), chip A may decide whether to execute the command according to the chip identification code chip_id (operation S2). For example, if the command has a target address indicating chip A, chip A can set the chip identification code chip_id to a default value (default is 0), and if it is the default value, then execute the command on chip A (operation S3) . If the chip identification code chip_id set by chip A is not 0, then communicate through the remote processor in the PCI-E interface (remote processor messaging, The RPMSG) mechanism forwards the command to other chips (operation S4), and waits for the other chip to return the command execution result. After the chip A receives the command execution result generated by itself or the command execution result of other chips, the chip A can return the command execution result to the transport layer and the user input and output layer (operation S5). In some embodiments, the command execution result can be the actual processing result of the command to be executed, or each chip reports that the command execution failed (for example, the command is specified to be executed by chip A, but chip A does not store the command).

By analogy, chip C and chip E can perform similar operations to complete command forwarding and/or command execution. In addition, chip E can return the command execution result to chip C through the RPMSG mechanism, and chip C can return the original command execution result or the command execution result received from chip E to chip A through the RPMSG mechanism. The related operations of the chip C and the chip E are similar to the above-mentioned operations S1 - S5 , so the details will not be repeated here.

(5) Examples of preset commands:

First example: as mentioned above, the default command can be used to set the chip identification code chip_id in each chip A~E, so as to select a chip in the multi-chip system 100 as the current receiving end chip to execute the forwarded command. In some embodiments, the default command may include "select_chip[target address of chip]". In this example, the command select_chip can be used to indicate the target address of the receiving chip. After the multi-chip system 100 successfully executes the command select_chip, the subsequent commands will be executed by the receiving chip.

For example, if chip A wants to forward a command to chip E, chip A can execute the command select_chip 0x104, where 0x104 is the target address of chip E relative to chip A (refer to Table 3). In this way, chip E can set its own chip identification code chip_id as a default value according to the above command, and chip A Subsequent commands can be forwarded to chip E, so that chip E executes subsequent commands according to its own chip identification code chip_id. Or, in another example, if chip A wants to forward the command to chip E, chip A can execute the command select_chip 0x4, and then execute the command select_chip 0x1 through chip C, where 0x4 is the target address of chip C relative to chip A ( Refer to Table 2), and 0x1 is the target address of chip E relative to chip C (refer to Table 2). By continuously executing the commands select_chip 0x4 and select_chip 0x1, the chip E can set its own chip identification code chip_id as a default value to execute subsequent commands. In other words, in the setting mode of two-level connection, chip A can execute the command select_chip once through the target address in Table 3 to forward the command to chip E, or can execute the command select_chip twice consecutively through the target address in Table 2 and chip C To forward the command to chip E.

If chip E wants to forward the command to chip A, chip E can forward the command to chip A via chip C. Since the working mode of the connection port P5 of the chip E is EP mode and the identification code of the connection port P5 is port 0, the target address of the chip C relative to the chip E is 0x10000 (refer to Table 1 above). Since the working mode of the connection port P2 of the chip C is EP mode and the identification code of the connection port P2 is port 1, the target address of the chip A relative to the chip C is 0x10001 (refer to Table 1 above). Accordingly, chip E can execute the command select_chip 0x10000 (switch the subject of command execution to chip C), and execute the command select_chip 0x10001 (switch the subject of command execution to chip A) via chip C to forward the command to chip A. The above-mentioned examples are only described in the use scenario of the two-level connection, and it should be understood that the above-mentioned command forwarding mechanism can be applied to the use scenario of the multi-level connection.

Second example: In some embodiments, the default command may include "route_call[b_transfer] "sub_command"". In this example, the command route_call can be used to control whether the chip should disconnect the previous command forwarding connection, the parameter b_transfer is used to indicate whether to perform command forwarding, and the command Let sub_command be the actual command to be executed by the specified chip. For example, when the parameter b_transfer is 1, the chip can forward the command sub_command to other chips with which it has established a connection, and execute the command sub_command through these chips. Conversely, if the parameter b_transfer is 0, the chip does not forward the command sub_command to other chips with which it has established a connection, and only executes the command sub_command in this chip.

For example, if the current command forwarding link of the multi-chip system 100 is chip A→chip C→chip E. When the chip A executes the command route_call, if the parameter b_transfer is 1, the chip A will forward the command sub_command to the chip C and the chip E, and both the chip C and the chip E will execute the command sub_command. Alternatively, if the parameter b_transfer is 0, chip A does not forward the command sub_command to chip C and chip E, and executes the command sub_command itself.

In some embodiments, the command route_call can be used to cut off the current command forwarding connection. For example, the chip can execute the command route_call 1 "select_chip 0", that is, the command sub_command can be set as the command select_chip 0. In this way, all chips in the current command forwarding connection will execute the command select_chip 0, and then set their respective chip identification codes chip_id to a value of 0, without executing subsequent commands. The above-mentioned examples of advance orders are for illustration only, and this case is not limited to the above-mentioned examples.

(6) Application examples of actual deployment:

Taking the example in FIG. 1 as an example, a possible deployment example is: chip A is the master chip, chip B, chip D, and chip E are slave chips, and chip C is a bridge chip, wherein the connection port P2 connected to chip A The working mode is EP mode, and the working mode of the port P3 connected to the chip E is RC model. In general system applications, chip A can operate as the main sender of commands, which can initialize the multi-chip system 100 by executing the following script: init_soc select_chip [destination address of chip B relative to chip A] init_soc route_call 0" select_chip[destination address of die C relative to die A]" init_soc route_call 0 "select_chip[destination address of die D relative to die A]" init_soc route_call 0 "select_chip[destination address of die E relative to die A]" init_soc

In the above script, the command init_soc is an instruction to control the initialization of the chip, and chip A executes the first line of command init_soc and then performs initialization. After the initialization is completed, chip A executes the second line of command select_chip to transfer the command to chip B. In this way, chip B will execute the command init_soc in the third line to initialize. Next, Chip A executes the fourth command route_call. Since the parameter b_transfer is 0, chip A does not forward the command to chip B, and executes the command select_chip to forward the command to chip D. In this way, the chip D will execute the command init_soc in the fifth line to initialize. By analogy, chip A can use multiple commands of the above script to sequentially forward the command init_soc to other chips B~E, so as to complete the initialization of other chips.

The above script is only used to illustrate a possible example of application deployment, and this case is not limited thereto. It should be understood from the above examples that a convenient and highly versatile command forwarding mechanism can be implemented in the multi-chip system 100 through the method of determining the target address and the use of various preset commands provided by the embodiment of the present case, so as to facilitate management and control each wafer in the multi-wafer system 100 .

The above examples are only described using the PCI-E interface, but this case is not limited thereto. Various signal interfaces applicable to chip connection (such as, but not limited to, USB, SPI, I2C and other interfaces) are all within the scope of this application. The above examples are described by using C++ codes and/or functions or commands used in the software framework of the Linux system as examples, but this case is not limited thereto. In addition, the number and connection method of the plurality of chips A˜E shown in FIG. 1 are only examples, and the number of various chips or different chip connection methods are all within the scope of this application.

To sum up, the multi-chip system in some embodiments of this application can use the working mode of the connection port of the chip itself and the identification code of the bus to set the relative target address of each chip. In this way, dies in a multi-die system can forward commands to other dies. The above-mentioned command forwarding mechanism only involves the identification code between hardware and the target address of the script. Therefore, the command forwarding mechanism does not involve code modification at the software layer, so it can have high versatility.

Although the embodiments of this case are as described above, these embodiments are not intended to limit this case. Those with ordinary knowledge in the technical field can make changes to the technical characteristics of this case according to the explicit or implied content of this case. All these changes All may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be subject to the definition of the scope of patent application in this specification.

100:Multi-chip system

110: switch

A~E: Wafer

B1, B1_1, B3~B5: busbar

P0~P5: Connecting port

port 0, port 1: the identification code of the connection port

Claims (14)

A multi-chip system, comprising: a sending end chip including a first connection port; and a receiving end chip including a second connection port, the first connection port is coupled to the second connection port, and the first The working mode of the connecting port is different from the working mode of the second connecting port, wherein when the sending chip is not connected to the receiving chip through other chips, the sending chip is determined according to the working mode of the first connecting port The receiving end chip is relative to a first target address of the sending end chip, and forwards a command to the receiving end chip according to the first target address. The multi-chip system according to claim 1, wherein the first connection port and the second connection port are connected via a Peripheral Component Interconnect Express (PCI-E) interface. The multi-chip system of claim 1, wherein one of the working mode of the first connecting port and the working mode of the second connecting port is an endpoint mode, and the working mode of the first connecting port is the same as the working mode of the second connecting port The other of the working modes of the second connection port is a root complex mode. The multi-chip system according to claim 1, wherein when the sending chip operates as a slave chip, the sending chip determines the first target address according to the identification code of the first connection port. The multi-chip system as claimed in claim 1, wherein when the sending chip operates as a master (master) chip, the sending chip is based on the identification code of the first connection port and the connection between the second connection port and the first connection port The identification code of the bus bar between determines the first target address. The multi-chip system of claim 1 further includes: a bridge chip, including a third connection port and a fourth connection port, the third connection port is coupled to the first connection port, and the fourth connection port is coupled to To the second connection port, the working mode of the third connection port is different from the working mode of the fourth connection port, wherein the sending end chip is further based on the identification code of the first connection port and the first connection port and the second connection port The identification code of the bus bar between the three connection ports determines a second target address of the bridge chip relative to the sending end chip, and according to the identification code of the fourth connection port and the fourth connection port and the second connection port The identification code of the bus bar between determines a third target address of the receiver chip relative to the bridge chip, and determines the first target address according to the second target address and the third target address. The multi-chip system according to claim 6, wherein the first target address includes some bits of the second target address and some bits of the third target address. The multi-chip system of claim 1 further includes: a bridge chip, including a third connection port and a fourth connection port, the third connection port is coupled to the first connection port, and the fourth connection port is coupled to To the second connection port, the working mode of the third connection port is different from the working mode of the fourth connection port, wherein the sending end chip is further based on the identification code of the first connection port and the first connection port and the second connection port The identification code of the bus between the three ports determines a second target address of the bridge chip relative to the sender chip and forwards the command to the bridge chip according to the second target address, and the bridge chip according to the fourth The identification code of the connection port and the confluence between the fourth connection port and the second connection port The row identification code determines a third target address of the receiver chip relative to the bridge chip, and forwards the command to the receiver chip according to the third target address. The multi-chip system according to claim 1, wherein the receiver chip stores a chip identification code and executes the command when the chip identification code is a default value. The multi-chip system according to claim 9, wherein when the receiver chip receives a default command indicating the first target address, the receiver chip sets the chip identification code to the default value. A method for generating an address, applied to a multi-chip system, the multi-chip system includes a sending chip and a receiving chip, the sending chip includes a first connection port, the receiving chip includes a second connecting port, the The first connection port is coupled to the second connection port and the working mode of the first connection port is different from the working mode of the second connection port. The address generation method includes: the sending end chip according to the work of the first connection port The mode determines a first target address of the receiver chip relative to the transmitter chip; and the transmitter chip forwards a command to the receiver chip according to the first target address. The address generation method of claim 11, wherein the first connection port and the second connection port are connected through a Peripheral Component Interconnect Express (PCI-E) interface. The address generating method of claim 11, wherein when the sending chip operates as a slave chip, the sending chip further determines the first target address according to the identification code of the first connection port. The address generating method of claim 11, wherein, when the sending chip operates as a master (master) chip, the sending chip is further connected to the first connecting port with the second connecting port according to the identification code of the first connecting port The ID of the bus between the ports determines the first target address.

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