CN201397503Y

CN201397503Y - Interrupt expander circuit

Info

Publication number: CN201397503Y
Application number: CN 200820124025
Authority: CN
Inventors: 任荣文; 王金锋; 房庆海; 石志学
Original assignee: Automation Research and Design Institute of Metallurgical Industry
Current assignee: Automation Research and Design Institute of Metallurgical Industry
Priority date: 2008-11-21
Filing date: 2008-11-21
Publication date: 2010-02-03
Anticipated expiration: 2018-11-21

Abstract

The utility model relates to an interrupt expander circuit which pertains to the technical field of computer application of electronic circuit design. The interrupt expander circuit comprises an interrupt input terminal, a photo coupler separation circuit, a slave interrupt control chip set, a master interrupt control chip, a logic circuit, an interrupt selection dial switch and an ISA connector,wherein multiple interrupt sources are connected by the terminal and input into the interrupt control chip set after undergoing photo coupler separation; a computer interacts with the interrupt control chip set by an ISA bus to obtain the interrupt sources, number and process in real time, thereby realizing the expansion control of multiple interrupt; and the interrupt expander circuit has the advantages that a photo coupler controls the interference of the interrupt expander circuit caused by the interrupt source; the circuit is simple, occupies less system resources and is convenient to expansion and migration.

Description

A kind of interruption expanded circuit

Technical field

The utility model relates to computer utility and electronic circuit design field, is specifically related to a kind of interruption expanded circuit.

Background technology

The interrupt resources of industrial computer is limited, and partly interrupts being taken by hard disk, keyboard, serial ports etc., can be limited for the number of interruptions that the user uses, and therefore in a lot of engineerings application, need expansion to interrupt.

Summary of the invention

The purpose of the utility model patent is to provide a kind of interruption expanded circuit, overcomes few this shortcoming of active computer external interrupt quantity, and has characteristics simply efficient, that be convenient to use.

The utility model is by interrupting input end, optical coupling isolation circuit, select toggle switch and ISA joint to form from interrupting control chip group, main Interrupt Control Chip, logical circuit, interruption; Multichannel interrupt source inserts through interrupting input end, by being input to after the light-coupled isolation from interrupting control chip group, receive main Interrupt Control Chip and delivered to by main Interrupt Control Chip on the isa bus of computing machine from interrupting control chip group, wherein logical circuit is used for isa bus, main Interrupt Control Chip and from interrupting the logic control between the control chip group three.Computing machine is mutual by isa bus and Interrupt Control Chip group, obtains to interrupt source and numbering and real-time the processing.

Described interrupting input end can be for 64 tunnel terminals that interrupt input for having; Independently 64 tunnel photoelectric coupled circuit that optical coupling isolation circuit is made up of a plurality of optocouplers; Interrupt Control Chip is become from interrupting control chip group with eight by a slice master Interrupt Control Chip; Logical circuit is made up of several logic chips.

64 tunnel look-at-mes are input to the optocoupler input end through interrupting input end, the output terminal of optocoupler is received eight interruption input pin IR0～IR7 from Interrupt Control Chip respectively, eight interruption output pin INT from Interrupt Control Chip receive the interruption input pin IR0～IR7 of main Interrupt Control Chip successively, and the interruption output pin INT of main Interrupt Control Chip directly is connected on a certain external interrupt on the Computer I SA bus by interrupting selector switch; Eight cascade pin CAS0 from control chip and main Interrupt Control Chip, CAS1, the CAS2 correspondence links together; Eight eight bit data spool pin D0～D7 from Interrupt Control Chip and main Interrupt Control Chip receive on the eight bit data line of isa bus by logic chip two; BIOR signal and interruption input signal INT produce the interrupt acknowledge signal INTA that Interrupt Control Chip need by logic chip three on the isa bus; The BIOR of all Interrupt Control Chip, the lowest order A0 of IOW and address wire is connected on the isa bus by logic chip one; Address wire A1 on the isa bus～A9 obtains the chip selection signal CS0～CS8 of all Interrupt Control Chip by comparable chip and coding chip; Described Interrupt Control Chip comprises that a main Interrupt Control Chip and eight are from Interrupt Control Chip.

Connection terminal described in the utility model is 64 road interrupting input end; Describedly be meant the light-coupled isolation chip to the light-coupled isolation unit; Described Interrupt Control Chip cascade unit is nine Interrupt Control Chip, the wherein direct and ISA communication of a slice master Interrupt Control Chip, other eight Interrupt Control Chip are from Interrupt Control Chip, directly output is connected with optocoupler from Interrupt Control Chip, delivers to main Interrupt Control Chip interrupting the result simultaneously; Logical circuit is meant logic chip one, two, three and comparable chip and coding chip, and isa bus is meant industrial standard architecture bus, is used to interrupt being connected of expander board and computing machine.

The utility model principle of work: the utility model is by isa bus and nine Interrupt Control Chip communications, and eight of a slice master's Interrupt Control Chip cascades are managed 64 the tunnel from Interrupt Control Chip for eight and interrupted from Interrupt Control Chip, thereby realize that 64 the tunnel interrupt expansion.

It is simple to the utlity model has circuit, and occupying system resources is few, is convenient to advantages such as expansion and transplanting.

Description of drawings

Fig. 1 is the utility model structured flowchart.

Fig. 2 is interrupting input end and the optocoupler part of the utility model circuit structure diagram.

Fig. 3 is the Interrupt Control Chip cascade part of the utility model circuit structure diagram.

Fig. 4 is that the chip selection signal of the utility model circuit structure diagram produces part.

Fig. 5 is the logical circuit part of the utility model circuit structure diagram.

Fig. 6 is that the interruption of the utility model circuit structure diagram is selected and the ISA shank.

Embodiment

Below in conjunction with accompanying drawing the utility model is described in further detail.

Fig. 1 is that structured flowchart of the present utility model is mainly by interrupting input end, photoelectric coupled circuit, form from interrupting control chip group, main Interrupt Control Chip, logical circuit and ISA joint; Fig. 2 is interrupting input end and the optocoupler part of the utility model circuit structure diagram, and the look-at-me before the optocoupler is powered by interrupt source, and the circuit after the optocoupler is by power taking on the isa bus.Fig. 3 is the Interrupt Control Chip cascade part of the utility model circuit structure diagram, and interrupt source (64 tunnel or be less than 64 tunnel) is received from the interruption input pin IR0～IR7 of Interrupt Control Chip through after the light-coupled isolation; Eight interruption output pin INT from control chip receive the interruption input pin IR0～IR7 of main Interrupt Control Chip successively, and the interruption output pin INT of main Interrupt Control Chip directly is connected on a certain external interrupt of computing machine on the isa bus by interrupting selector switch; Eight cascade pin CAS0 from Interrupt Control Chip and main Interrupt Control Chip, CAS1, the CAS2 correspondence links together.Fig. 4 is that the chip selection signal of the utility model circuit structure diagram produces part, under the control of ale signal, address wire A1 on the isa bus～A9 relatively obtains chip selection signal CS by comparable chip and address switch, obtains the chip selection signal CS0～CS8 of all Interrupt Control Chip (comprise a main Interrupt Control Chip and eight from Interrupt Control Chip) again through coding chip; Fig. 5 is the logical circuit part of the utility model circuit structure diagram, and eight eight bit data spool pin DATA0～DATA7 from control chip and main Interrupt Control Chip receive on the eight bit data line D0～D7 of isa bus by logic chip two; BIOR signal and interrupt the interrupt acknowledge signal INTA of input signal INT on the isa bus by logic chip three generation Interrupt Control Chip (comprise a main Interrupt Control Chip and eight from Interrupt Control Chip) needs; The BIOR of all Interrupt Control Chip (comprise a main Interrupt Control Chip and eight from Interrupt Control Chip), the lowest order A0 of IOW and address wire is connected on the isa bus by logic chip one.Fig. 6 is that the interruption of the utility model circuit structure diagram is selected and the ISA shank, by interrupting selecting circuit, IRQ10 on can assigned I SA bus, IRQ11, IRQ12, a certain road external hardware among the IRQ15 interrupts being connected with the INT of main Interrupt Control Chip, and the ISA shank is used for this interruption expanded circuit and is connected with isa bus on the equipment.

The processing procedure of interrupting is as follows:

(1) all principal and subordinate's Interrupt Control Chip enter the duty of setting through after the initialization programming, are ready to accept the interrupt request of IR0～IR7;

(2) (IRQ0～IRQ7) become high level then makes the set of IRR corresponding positions when one or more interrupt request line; Producing high level at the INT end simultaneously delivers on the corresponding IR of main Interrupt Control Chip;

(3) main Interrupt Control Chip is received after the interrupt request of Interrupt Control Chip, makes the set of IRR corresponding positions, simultaneously produces high level at the INT end and delivers on the external interrupt on the isa bus;

(4) on the INTA of all Interrupt Control Chip pin, send two negative pulses after the interrupt request on the CPU response INT, first INTA pulse is finished by main Interrupt Control Chip, main Interrupt Control Chip will be done two things after accepting: 1. make corresponding ISR set, represent that it has responded the interrupt request of sending from Interrupt Control Chip, 2. at level line CAS0, CAS1, output is from the corresponding numbering of interrupting input pin of Interrupt Control Chip on the CAS2 pin;

(5) all receive the numbering that main interrupt control sheet is sent from Interrupt Control Chip, numbering in the time of immediately with initial configuration is separately compared, have only corresponding equating from the Interrupt Control Chip discovery, corresponding makes corresponding ISR set on the one hand from Interrupt Control Chip, when receiving that CPU sends second INTA pulse here interrupt vector address is sent to CPU;

(6) CPU judges according to the interrupt vector address that sends from Interrupt Control Chip and interrupts numbering, changes corresponding interrupt handling routine over to, returns master routine after being finished.

Claims

1. interruption expanded circuit is by interrupting input end, optical coupling isolation circuit, select toggle switch and ISA joint to form from interrupting control chip group, main Interrupt Control Chip, logical circuit, interruption; It is characterized in that, multichannel interrupt source inserts through interrupting input end, by being input to after the light-coupled isolation from interrupting control chip group, receive main Interrupt Control Chip and delivered to by main Interrupt Control Chip on the isa bus of computing machine from interrupting control chip group, wherein logical circuit is used for isa bus, main Interrupt Control Chip and from interrupting the logic control between the control chip group three.

2. circuit according to claim 1 is characterized in that, described interrupting input end can be for 64 tunnel terminals that interrupt input for having; Independently 64 tunnel photoelectric coupled circuit that optical coupling isolation circuit is made up of optocoupler; Interrupt Control Chip is become from interrupting control chip group with eight by a slice master Interrupt Control Chip; Logical circuit is made up of logic chip.

3. circuit according to claim 2, it is characterized in that, 64 tunnel look-at-mes are input to the optocoupler input end through interrupting input end, the output terminal of optocoupler is received eight interruption input pin IR0～IR7 from Interrupt Control Chip respectively, eight interruption output pin INT from Interrupt Control Chip receive the interruption input pin IR0～IR7 of main Interrupt Control Chip successively, and the interruption output pin INT of main Interrupt Control Chip directly is connected on a certain external interrupt on the Computer I SA bus by interrupting selector switch; Eight cascade pin CAS0 from control chip and main Interrupt Control Chip, CAS1, the CAS2 correspondence links together; Eight eight bit data spool pin D0～D7 from Interrupt Control Chip and main Interrupt Control Chip receive on the eight bit data line of isa bus by logic chip two; BIOR signal and interruption input signal INT produce the interrupt acknowledge signal INTA that Interrupt Control Chip need by logic chip three on the isa bus; The lowest order A0 of the BIOR of all Interrupt Control Chip, IOW and address wire is connected on the isa bus by logic chip one; Address wire A1 on the isa bus～A9 obtains the chip selection signal CS0～CS8 of all Interrupt Control Chip by comparable chip and coding chip.

4, according to claim 1 or 3 described circuit, it is characterized in that, logical circuit is meant logic chip one, logic chip two, logic chip three and comparable chip and coding chip, and isa bus is meant industrial standard architecture bus, is used to interrupt being connected of expander board and computing machine.