CN211604104U - TBT's general expansion interface circuit of PCIE passageway - Google Patents

Abstract

The utility model provides a general extension interface circuit of PCIE passageway of TBT, it includes interface connector, TBT chip, bridging chip and PCIE4X interface, interface connector is connected with the TBT chip, the PCIE4X signal terminal of TBT chip is connected with the port electricity that goes upward of bridging chip, the port and the multiunit PCIE4X interface electricity that go down of bridging chip are connected. Adopt the technical scheme of the utility model, the firmware development that TBT was compared to the design firmware is more nimble, has saved development cycle, and it is more convenient to use.

Description

TBT's general expansion interface circuit of PCIE passageway

Technical Field

The utility model relates to an interface circuit especially relates to a general extension interface circuit of PCIE passageway of TBT.

Background

TBT (tunnel boring technology), namely an Intel turbo technology, is an automatic overclocking technology provided by intel corporation, and a type C interface form is adopted, so that a PCIE USB DP high-speed interface of a mainboard is connected to receiving equipment through a TBT cable, and the purpose that one cable transmits various protocol data is achieved. At present, in the extension of PCIE on a motherboard, there is an obvious defect that a single TBT chip can only convert a group of PCIE4X signals, and if more PCIE4X are needed, it can be implemented by cascading another plurality of TBT chips. The expansion needs a TBT special chip, the design is complex, the customized firmware is needed to realize, the development process is long, and the use is inconvenient.

SUMMERY OF THE UTILITY MODEL

To the technical problem, the utility model discloses a TBT's general extension interface circuit of PCIE passageway, the development cycle has been shortened in the extension of more convenient PCIE.

To this end, the technical scheme of the utility model is that:

the utility model provides a general extension interface circuit of PCIE passageway of TBT, its includes interface connector, TBT chip, bridging chip and PCIE4X interface, interface connector is connected with the TBT chip, and the PCIE4X signal end of TBT chip is connected with bridging chip's ascending port electricity, bridging chip's descending port and multiunit PCIE4X interface electricity are connected.

As a further improvement of the utility model, the interface connector is the type C connector, the type C connector passes through the TBT cable and is connected with the mainboard.

As a further improvement, the line is walked between TBT chip and the bridging chip and is satisfied: the length of the circuit layout is less than 8inch, and the total matching length is less than 4 mils. If the traditional TBT topological connection is adopted, the TBT signal part has higher requirement on the routing and higher requirement on the routing length; it requires a layout length of less than 2inch and a matching total length of less than 2 mils. Adopt the technical scheme of the utility model, the requirement of walking the line has been reduced.

As a further improvement, the bridge chip adopts a set of LDO power supply.

Compared with the prior art, the beneficial effects of the utility model are that:

by adopting the technical scheme of the utility model, PCIE4X is used as the uplink port of the PCIE bridging chip, and the output of a plurality of groups of PCIE4X signals can be realized by utilizing the PCIE4X interface of the downlink port of the bridging chip; the bridge chip has universality and can be provided by different chip manufacturers, and compared with the firmware development of TBT, the design firmware is more flexible, the development period is saved, and the use is more convenient; and moreover, the wiring requirement and the number of power supplies are reduced, and the cost is reduced.

Drawings

Fig. 1 is a schematic structural diagram of the PCIE channel general expansion interface circuit of the TBT.

Fig. 2 is a schematic diagram of power supply of the bridge chip of the present invention.

Fig. 3 is a schematic connection diagram of the PCIE bridge chip of the present invention.

Detailed Description

Preferred embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

As shown in fig. 1, a PCIE channel general expansion interface circuit of a TBT includes an interface connector, a TBT chip, a bridge chip, and a PCIE4X interface, where the interface connector is connected to the TBT chip, a PCIE4X signal end of the TBT chip is electrically connected to an uplink port of the bridge chip, and a downlink port of the bridge chip is electrically connected to multiple sets of PCIE4X interfaces. Wherein, interface connector is type C connector, type C connector passes through the TBT cable and is connected with the mainboard. The bridging chip adopts a universal PCIE bridging chip.

The topology structure of the PCIE bridging chip is used, the PCIE signal is taken as the main part, the requirement of the routing length is reduced, and the routing between the TBT chip and the PCIE bridging chip meets the following requirements: the length of the circuit layout is less than 8inch, and the total matching length is less than 4 mils. The routing requirement of the topological connection of the existing TBT is lower.

In addition, the bridge chip is powered by a set of LDO power supplies, as shown in fig. 2. The existing chip special for the TBT needs two TBT chips, two groups of internal switching power supplies and two power inductors, taking the implementation requirement of two paths of PCIE4X as an example, and has certain requirements on the layout of a circuit board due to the switching power supplies so as to reduce the noise of the switching power supplies. The utility model discloses use PCIE bridging chip, adopt conventional LDO to supply power to the chip, use a set of power can, use LDO mains operated moreover, can need not consider the noise problem of power itself. The connection diagram of the PCIE bridge chip is shown in fig. 3.

By adopting the technical scheme, the bridge chip only needs to be connected with the PCIE4X signal of the TBT chip, other lines are designed in a standard way, and different PCIE equipment can be expanded according to specific application. Moreover, the 4X signals from the PCIE can be expanded into two or more sets of PCIE4X signals through the bridge chip. In the design of using TBT, the similar scheme can directly adopt the bridge chip without needing intel to provide adaptive firmware, and software in the chip is directly butted with a bridge chip manufacturer, so that the time cost is reduced, and the development period is shortened.

The above-mentioned embodiments are the preferred embodiments of the present invention, and the scope of the present invention is not limited to the above-mentioned embodiments, and the scope of the present invention includes and is not limited to the above-mentioned embodiments, and all equivalent changes made according to the shape and structure of the present invention are within the protection scope of the present invention.

Claims (4)

1. A kind of PCIE channel general expansion interface circuit of TBT, characterized by that: the system comprises an interface connector, a TBT chip, a bridging chip and a PCIE4X interface, wherein the interface connector is connected with the TBT chip, a PCIE4X signal end of the TBT chip is electrically connected with an uplink port of the bridging chip, and a downlink port of the bridging chip is electrically connected with a plurality of groups of PCIE4X interfaces.

2. The PCIE channel universal expansion interface circuit of the TBT of claim 1, wherein: the interface connector is a type C connector, and the type C connector is connected with the main board through a TBT cable.

3. The PCIE lane universal expansion interface circuit of claim 2, wherein: the routing between the TBT chip and the bridging chip meets the following requirements: the length of the circuit layout is less than 8inch, and the total matching length is less than 4 mils.

4. The PCIE channel universal expansion interface circuit of the TBT of claim 3, wherein: the bridge chip is powered by a group of LDO power supplies.

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