TWI809132B - Manufacturing method of semiconductor chip and manufacturing method of semiconductor device - Google Patents

Abstract

A manufacturing method of a semiconductor chip of the present embodiment obtains a semiconductor chip by forming a first modified layer in a first region from a circuit-forming surface of a semiconductor wafer to a depth of 215 µm in the semiconductor wafer by irradiating the semiconductor wafer with a laser beam from the back side of the semiconductor wafer; forming a second modified layer in a second region from the back surface of the semiconductor wafer to a depth of 215 µm in the semiconductor wafer and an area closer to the back surface side than the first modified layer by irradiating the semiconductor wafer with a laser beam from the back surface side of the semiconductor wafer; grinding the back surface of the semiconductor wafer; and dividing the semiconductor wafer in areas in the first modified layer and the second modified layer by applying a force to the semiconductor wafer while grinding.

Description

Method for manufacturing semiconductor wafer and method for manufacturing semiconductor device

The present invention relates to a method of manufacturing a semiconductor wafer and a method of manufacturing a semiconductor device. This application claims priority based on Patent Application No. 2018-124158 filed in Japan on June 29, 2018, the contents of which are cited here.

Dividing Semiconductor Wafers When manufacturing semiconductor wafers, so-called blade dicing is widely used, which uses dicing blades to cut semiconductor wafers. On the other hand, as methods for dividing semiconductor wafers other than blade dicing, for example, the following methods using laser light irradiation are known (see Patent Documents 1 to 2).

In this method, first, laser light is irradiated with a focus on a set focal point inside the semiconductor wafer, and a modified layer is formed inside the semiconductor wafer. This modified layer is applied as a starting point for splitting (cutting) of the semiconductor wafer because cracks are generated in the direction of both surfaces of the semiconductor wafer inside the semiconductor wafer due to external force. Next, a force is applied to the semiconductor wafer, and the semiconductor wafer is divided at the portion of the modified layer to obtain a semiconductor wafer. A semiconductor wafer is generally thinned by polishing the surface (back surface) opposite to the circuit-formed surface, but the semiconductor wafer may be divided by a force applied to the semiconductor wafer during the polishing. The division method of the semiconductor wafer accompanying the formation of such a modified layer is called stealth dicing (registered trademark). Although the semiconductor wafer is irradiated with laser light to remove the semiconductor wafer at the irradiated part, it is different from the Laser dicing, which cuts off the surface of the semiconductor wafer, is fundamentally different.

Such a method of manufacturing semiconductor wafers with the formation of modified layers is different from the above-mentioned methods of dicing with blades and laser dicing, because it does not involve grinding of semiconductor wafers, and is advantageous in terms of obtaining more semiconductor wafers. [Prior Art Literature] [Patent Document]

[Patent Document 1] Japanese Patent No. 4402708 [Patent Document 2] Japanese Patent Publication No. 2016-76522

[Problems to be Solved by the Invention]

However, conventional semiconductor wafer manufacturing methods involving the formation of modified layers, including the methods described in Patent Documents 1 to 2, have a problem that they are not suitable for manufacturing small-sized semiconductor wafers. In such a manufacturing method, generally, in order to divide the semiconductor wafer efficiently, the modifying layer is formed linearly along the circuit formation surface in a region not on the back side but on the circuit formation side inside the semiconductor wafer.

Fig. 1 is a schematic perspective view of a semiconductor wafer on which such a modified layer is formed. In the semiconductor wafer 9 shown here, a linear modifying layer 91 is formed in a region on the side of the circuit formation surface 9 a inside the semiconductor wafer 9 . The modified layer 91 is formed parallel or substantially parallel to the circuit formation surface 9 a of the semiconductor wafer 9 and is formed along the circuit formation surface 9 a. Here, for the sake of convenience, the modified layer 91 is schematically shown as a single line, but actually, it expands in the thickness direction of the semiconductor wafer 9 . Here, only six reforming layers 91 extending in the same direction are shown, but usually the number of reforming layers is more than this, and many are also formed in a direction perpendicular to the illustrated direction. In other words, FIG. 1 shows a state in which the formation of the target number of modified layers has not been completed and is in the middle. On the other hand, within the semiconductor wafer 9 , no modified layer is formed in the region on the back surface 9 b side.

In the reformed layer 91 , actually, unlike the portions other than the reformed layer 91 , fine cracks exist. Therefore, only the cracked part of the modified layer 91 protrudes from the parts other than the modified layer 91, slightly increases in volume, and decreases in density. Therefore, after the modified layer 91 is formed, in the semiconductor wafer 9, the region on the circuit forming surface 9a side where the modified layer 91 exists has a larger volume than the region on the back surface 9b side where the modified layer 91 does not exist. The larger the effect, the larger the number of lines in the modified layer. At this time, in the thickness direction of the semiconductor wafer 9 , there is a non-negligible difference in the volume of the semiconductor wafer 9 . In order to obtain a small-sized semiconductor wafer, such a state is just formed because the number of lines of the modified layer formed on the semiconductor wafer increases. Then, the semiconductor wafer is curved such that the circuit formation surface 9a is a convex surface (in other words, the back surface 9b is a concave surface). Such warping is particularly likely to occur when it is intended to manufacture a semiconductor wafer with a side length of 2 mm or less. Fig. 2 schematically shows an enlarged cross-sectional view of a semiconductor wafer in a curved state due to the formation of a modified layer.

When a semiconductor wafer is bent in this way, defects in steps occur. For example, a warped semiconductor wafer becomes difficult to transport. Also, as mentioned above, when grinding the back surface of the semiconductor wafer after the modified layer is formed, the back surface of the semiconductor wafer is tightly bonded to a special workbench, and is adsorbed and fixed to the workbench, but the curved semiconductor wafer cannot be tightly bonded to the workbench. , because it cannot be fixed to the table, its backside cannot be ground.

An object of the present invention is to provide a semiconductor wafer manufacturing method capable of suppressing warping of the semiconductor wafer even when a small-sized semiconductor wafer is manufactured by forming a modified layer inside the semiconductor wafer. [Means to solve the problem]

The present invention provides a method for manufacturing a semiconductor wafer, comprising a first modifying step of irradiating the semiconductor wafer with laser light from the back side of the semiconductor wafer, and in the interior of the semiconductor wafer, from the circuit of the semiconductor wafer In the first region from the formation surface to a depth of 215 μm (micrometer), a first modification layer is formed; in the second modification step, laser light is irradiated to the semiconductor wafer from the back side, and in the interior of the semiconductor wafer, In the second region from the above-mentioned back surface to a depth of 215 μm (micrometer), and on the side of the above-mentioned back surface than the above-mentioned first modified layer, a second modified layer is formed; 2. After the reforming step, while polishing the back surface of the semiconductor wafer, along with the polishing, due to the force applied to the semiconductor wafer, the parts of the first modified layer and the second modified layer are transmitted through the divided The above-mentioned semiconductor wafer is obtained as a semiconductor wafer.

In the method for manufacturing a semiconductor wafer according to the present invention, the thickness of the half wafer when performing the first reforming step and the second reforming step may be equal to or greater than the length of the shortest side of the semiconductor wafer. In addition, the present invention provides a method for manufacturing a semiconductor device. According to the above-mentioned method for manufacturing a semiconductor wafer, after obtaining a wafer group in which a plurality of semiconductor wafers are arranged, a stacking step is included, using a support sheet and a film-like bonding agent formed on the support sheet. For the bonded chip, the above-mentioned film-like bonding agent in the above-mentioned bonded chip is pasted to the above-mentioned back surface of the semiconductor chip in the above-mentioned semiconductor chip group after grinding, and a laminate of the above-mentioned semiconductor chip group and the above-mentioned bonded chip is produced; and the step of picking up , for the above-mentioned laminate, by applying force from the support sheet side, the above-mentioned film-like adhesive in the above-mentioned laminate is cut along the above-mentioned semiconductor wafer, pulled away from the above-mentioned support sheet, and the back side is picked up to prepare the cut-off above-mentioned film The above-mentioned semiconductor wafer in the form of bonding agent. [Invention effect]

According to the method of manufacturing a semiconductor wafer to which the present invention is applied, by forming the reforming layer inside the semiconductor wafer, even when a small-sized semiconductor wafer is manufactured, it is possible to suppress warping of the semiconductor wafer.

>>Manufacturing method of semiconductor wafer>> According to a method of manufacturing a semiconductor wafer according to an embodiment of the present invention, there is a first modifying step of irradiating the semiconductor wafer with laser light from the back side of the semiconductor wafer, in the inside of the semiconductor wafer, from the semiconductor In the first region where the circuit formation surface of the wafer reaches a depth of 215 μm (micrometers), a first modification layer is formed; in the second modification step, the semiconductor wafer is irradiated with laser light from the back side, and the surface of the semiconductor wafer is In the inside, in the second region from the back surface to a depth of 215 μm (micrometer), and on the back side of the first modified layer, a second modified layer is formed; and in the dividing step, the first modified layer is implemented. After the reforming step and the second reforming step, while grinding the back surface of the semiconductor wafer, along with this grinding, due to the force applied to the semiconductor wafer, the surface of the first reforming layer and the second reforming layer Part, by dividing the above-mentioned semiconductor wafer, obtains the semiconductor wafer.

According to the semiconductor wafer manufacturing method of the present embodiment, even when a small-sized semiconductor wafer is manufactured (in other words, when stealth dicing (registered trademark) is applied) by forming the modified layer inside the semiconductor wafer, the Forming the first modifying layer and the second modifying layer inside the circle can also suppress the bending of the semiconductor wafer. Therefore, the semiconductor wafer on which the first modified layer and the second modified layer have been formed before being divided into semiconductor wafers can be easily transported, and when the back surface is ground, it can be firmly fixed to the dedicated table because it can be firmly fixed. Grind its back. In addition, the manufacturing method of this embodiment is applicable not only to small-sized semiconductor wafers but also to the manufacture of medium-sized or large-sized semiconductor wafers.

The manufacturing method of the semiconductor wafer accompanied by the formation of modified layers such as the first modified layer and the second modified layer is different from the method of using the above-mentioned blade dicing or laser dicing, because it is not accompanied by grinding of the semiconductor wafer. The aspect of multiple semiconductor wafers is advantageous. In addition, in the case of blade dicing, because the contact between the semiconductor wafer and the dicing blade is cut while water (sometimes referred to as "cutting water") flows, especially in the manufacture of small semiconductor wafers, the distance between the semiconductor wafer and water The longer contact time may adversely affect the characteristics of the semiconductor wafer. On the other hand, the method of manufacturing a semiconductor wafer accompanying the formation of the modified layer described above is advantageous in that such defects can be suppressed.

In the manufacturing method of this embodiment, the side length of the target semiconductor wafer is preferably 2 mm or less, for example, 1.5 mm or less, or 0.9 mm or less. When the side length is below the upper limit, the effect of suppressing warping of the semiconductor wafer becomes higher when a small-sized semiconductor wafer is produced by forming a modified layer inside the semiconductor wafer.

In the manufacturing method of this embodiment, the lower limit of the side length of the target semiconductor wafer is not particularly limited. From the viewpoint of easier manufacture of the semiconductor wafer, the above-mentioned length is preferably 0.5 mm or more.

However, in this embodiment, for the thickness of the semiconductor wafer when performing the first reforming step and the second reforming step described later, it is desirable to form the shortest side length of the semiconductor wafer equal to or more ([the shortest side length of the semiconductor wafer] ≧[thickness of the semiconductor wafer when performing the first modifying step and the second modifying step]). Thereby, through the formation of the modified layer inside the semiconductor wafer, even when a small-sized semiconductor wafer is manufactured, the effect of suppressing the bending of the semiconductor wafer becomes higher.

In this specification, "the shortest side of the semiconductor wafer" means the side with the shortest length among the plurality of sides constituting the outer periphery of the semiconductor wafer. For example, when there are plural shortest sides constituting the outer periphery of a semiconductor wafer having a square planar shape, the "shortest side of the semiconductor wafer" means these shortest sides.

Hereinafter, the method for manufacturing a semiconductor wafer according to the present embodiment will be described in detail step by step while referring to the drawings. In addition, all the drawings used in the description in this specification may show main parts in enlarged scale for the sake of easy understanding of the features of the invention, and the dimensional ratio of each component may not necessarily be the same as the actual one.

>First Embodiment> Fig. 3 is an enlarged cross-sectional view for schematically illustrating the first modifying step and the second modifying step in the method for manufacturing a semiconductor wafer according to the first embodiment of the present invention, and corresponds to the perspective view of Fig. 5 . In addition, in the drawings after FIG. 4 , the same symbols as those shown in the already described drawings are attached to the same components as those shown in the already described drawings, and detailed description thereof will be omitted.

[The first modifying step in the first embodiment] In the above-mentioned first modifying step in the first embodiment, as shown in Fig. 3(a) and Fig. 5(a), the The back surface (that is, the surface opposite to the circuit formation surface 8a) 8b side irradiates the semiconductor wafer 8 with laser light R ₁ , and in the inside of the semiconductor wafer 8, from the circuit formation surface 8a of the semiconductor wafer 8 to 215 μm (micrometer) In the deep first region 80a, the first modified layer 81 is formed. In Fig. 3, symbol D ₁ indicates the depth of the first region 80a, which is 215 μm in this embodiment (D ₁ =215 μm). The first region 80a, inside the semiconductor wafer 8, is the region between the circuit formation surface 8a and the distance _D1 from the circuit formation surface 8a in the thickness _T8 direction of the semiconductor wafer 8.

The thickness T ₈ of the semiconductor wafer 8 when the first modifying step is performed is not particularly limited, but is preferably 725 to 775 μm. The semiconductor wafer 8 having such a thickness _T8 is more excellent in usability and rigidity.

The semiconductor wafer 8 provided in the first modifying step may or may not be subjected to polishing for adjusting its thickness. In particular, the non-polished semiconductor wafer 8 is ideal because it has no grinding marks that may cause damage, and is more excellent in usability.

Also, in the first embodiment, the thickness T ₈ of the semiconductor wafer 8 when performing the first modifying step and the second modifying step described later is desirably equal to or less than the shortest side length of the target semiconductor wafer. Since such a condition is satisfied, the effect of suppressing warpage of the semiconductor wafer becomes higher even when a small-sized semiconductor wafer is produced via the reformed layer formation inside the semiconductor wafer.

In the first embodiment, the semiconductor wafer 8 is preferably provided with the protective film 7 on the circuit formation surface 8a. The protective film 7 covers the circuit formation surface 8a, protects the circuit formation surface 8a, and is a film for maintaining the semiconductor wafer group in which a plurality of semiconductor wafers are arranged in a division step described later. The protective film 7 may be a well-known film, for example, known Backglide tape (adhesive tape).

In the first reforming step, the first reforming layer 81 is formed in a linear shape along the circuit formation surface 8a in the first region 80a in order to obtain a semiconductor wafer having a target size in a dividing step described later. The linear first modifying layer 81 is parallel or substantially parallel to the circuit formation surface 8a. In FIG. 5 , the first modified layer 81 is roughly shown as a single line.

When forming the linear first modified layer 81, first, in order to focus on the starting point in the first region 80a, more specifically, the focus set near the peripheral portion of the semiconductor wafer 8, from the semiconductor wafer 8 The back surface 8b side is irradiated with laser light R ₁ . In this way, the first modified layer 81 is first partially formed. Further, this operation is repeated while shifting the irradiation position of the laser light _R1 in the direction of the arrow _M1 in FIG. 5 , and finally the linear first modified layer 81 is formed.

In the thickness T8 direction of the semiconductor wafer ₈ , the enlarged width of the first modified layer 81 (in other words, the height of the first modified layer 81) is not particularly limited, but is preferably 10 to 50 μm, more preferably 20 to 40 μm. The aforementioned expansion width can be adjusted according to the irradiation conditions of the laser light _R1 , for example.

In the first embodiment, the formation position of the first modified layer 81 in the thickness T8 direction of the semiconductor wafer ₈ is shown as the central position of the first modified layer 81 in the same direction unless otherwise stated.

In the first embodiment, in the first region 80a inside the semiconductor wafer 8, it is only necessary to form the first modified layer 81 so that at least a part of the linear first modified layer 81 exists. The linear first modified layer 81 entirely forms the first modified layer 81 .

In the first embodiment, as described above, the first modifying layer 81 is formed inside the semiconductor wafer 8 at a depth of 215 μm (micrometer) from the circuit formation surface 8 a of the semiconductor wafer 8 . Since the formation position of the first modified layer 81 satisfies such conditions, and the formation position of the second modified layer 82 described later also satisfies the conditions described later, while the above-mentioned effect of suppressing the curvature of the semiconductor wafer is obtained, in the division step described later, Semiconductor wafers can also be divided well. In order to obtain such an effect more remarkably, in the inside of the semiconductor wafer 8, from the circuit formation surface 8a of the semiconductor wafer 8 to the position where the depth is preferably 195 μm, more preferably 175 μm, and more preferably 155 μm, a second layer is formed. 1 Modified layer 81 is also acceptable.

On the other hand, in the first embodiment, the position where the first modified layer 81 is formed inside the semiconductor wafer 8, and the minimum value of the depth from the circuit formation surface 8a are not particularly limited, for example, considering the target semiconductor wafer thickness, etc. , as long as it is properly selected. In consideration of the thickness of a general-purpose semiconductor wafer, etc., the first modified layer is formed in the semiconductor wafer 8 from the circuit formation surface 8a of the semiconductor wafer 8 to a position deeper than 65 μm, more preferably 75 μm. 81 is also available.

In the first embodiment, the formation position of the first modified layer 81 can be appropriately adjusted within the range in which the aforementioned ideal lower limit and upper limit are set in any combination. For example, in one embodiment, the formation position of the first modified layer 81 is preferably 65 to 215 μm from the circuit formation surface 8a of the semiconductor wafer 8, more preferably 65 to 195 μm, and more preferably 65 to 175 μm. Even more ideally, any position in the region with a depth of 65 to 155 μm is fine. However, these are examples of the positions where the first modified layer 81 is formed.

The linear first modifying layer 81 may be linear or non-linear, and may be appropriately selected in consideration of the shape of the target semiconductor wafer, but it is usually preferably linear.

The linear first modified layer 81 may be formed in a continuous linear shape in appearance, but may be discontinuous (in other words, intermittent) dotted linear shape depending on the irradiation conditions of the laser light _R1 . In the first embodiment, the linear first modified layer 81 may have a solid line shape or a dotted line shape as long as the overall shape is linear.

The wavelength of the laser light _R1 is not particularly limited as long as it is more than 1050nm (nanometer), but it is ideally 1050 to 1500 nm in consideration of practicality, for example, 1342nm is also possible. Laser light R ₁ having a wavelength of 1050 nm or more is not absorbed by silicon, which is a material of the semiconductor wafer, and is suitable for forming the first modified layer 81 .

[Second modification step in the first embodiment] After forming the linear first modification layer 81, in the second modification step in the first embodiment, as in steps 3(b) and 5(b) As shown in the figure, when the semiconductor wafer 8 is irradiated with laser light _R2 from the back surface 8b side, in the inside of the semiconductor wafer 8, in the second region 80b from the back surface 8b to a depth of 215 μm and lower than the first modified layer 81 and the second modified layer 82 are formed on the above-mentioned rear side 8b. In Fig. 3, symbol D ₂ represents the depth of the second region 80b, which is 215 μm in the first embodiment (D ₂ =215 μm). The second region 80b is the region between the back surface 8b and the distance of _D2 from the back surface 8b in the thickness _T8 direction of the semiconductor wafer 8 in the interior of the semiconductor wafer 8 .

The second modified layer 82 can be formed by the same method as that of the first modified layer 81 except that the location in the semiconductor wafer 8 is different. More specifically, in the second reforming step, the second reforming layer 82 is formed in a linear shape along the back surface 8b in the second region 80b in order to obtain a semiconductor wafer having a target size in a dividing step described later. The linear second modifying layer 82 is formed parallel or substantially parallel to the back surface 8b. In FIG. 5 , the second modified layer 82 is roughly shown as a single line.

When forming the linear second modified layer 82, first, in order to focus on the starting point in the second region 80b, more specifically, the focus set near the peripheral portion of the semiconductor wafer 8, also from the semiconductor wafer 8 The back surface 8b side is irradiated with laser light R ₂ . Thereby, first, the second modified layer 82 is partially formed. Further, this operation is repeated while shifting the irradiation position of the laser light _R2 in the direction of the arrow _M2 in FIG. 5, and finally the linear second modified layer 82 is formed.

The expanded width (in other words, the height of the second modified layer 82) of the second modified layer 82 in the thickness T of the semiconductor wafer ₈ in the direction is not particularly limited, and the same numerical range as the expanded width of the first modified layer 81 is also used. Can. The above-mentioned enlarged width of the second modified layer 82 can be adjusted by the same method as that of the above-mentioned enlarged width of the first modified layer 81 .

In the first embodiment, the formation position of the second modified layer 82 in the thickness T8 direction of the semiconductor wafer ₈ is represented by the central position of the second modified layer 82 in the same direction unless otherwise specified.

In the first embodiment, in the second region 80b inside the semiconductor wafer 8, it is only necessary to form the second modified layer 82 so that at least a part of the linear second modified layer 82 exists. The second modified layer 82 is formed as a striped second modified layer 82 .

In the first embodiment, as described above, the second modified layer 82 is formed in the semiconductor wafer 8 from the back surface 8b of the semiconductor wafer 8 to a depth of 215 μm (micrometer). Since the formation position of the second modified layer 82 satisfies such conditions, and the formation position of the first modified layer 81 also satisfies the above-mentioned conditions, while obtaining the above-mentioned suppression effect of semiconductor wafer bending, in the dividing step described later, it is also possible to Good separation of semiconductor wafers. In order to obtain such an effect more remarkably, in the inside of the semiconductor wafer 8, form the second modification at a position from the back surface 8b of the semiconductor wafer 8 to a depth of preferably 195 μm, more preferably 175 μm, and more preferably 155 μm. Layer 82 is also possible.

On the other hand, in the first embodiment, the minimum value of the depth from the rear surface 8b at the position where the second modified layer 82 is formed inside the semiconductor wafer 8 is not particularly limited. Just choose appropriately. In consideration of the thickness of a general-purpose semiconductor wafer, etc., the second modified layer 82 may be formed at a position deeper than 65 μm, more preferably 70 μm, from the back surface 8 b of the semiconductor wafer 8 inside the semiconductor wafer 8 .

In the first embodiment, the formation position of the second modified layer 82 can be appropriately adjusted within the range in which the aforementioned ideal lower limit and upper limit are set in any combination. For example, in one embodiment, the formation position of the second modified layer 82 is preferably 65 to 215 μm from the back surface 8b of the semiconductor wafer 8, more preferably 65 to 195 μm, and more preferably 65 to 175 μm, and furthermore. Ideally, any position in the region with a depth of 65 to 155 μm is fine. However, these are examples of the positions where the second modified layer 82 is formed.

The shape of the linear second modified layer 82 may be the same as the shape of the aforementioned linear first modified layer 81 .

The wavelength of the laser light _R2 is the same as the wavelength of the laser light _R1 for the same reason as in the case of the laser light _R1 . Therefore, it is desirable to make the wavelength of the laser light _R2 coincide with the wavelength of the laser light _R1 .

The distance _Δ12 between the first modified layer 81 and the second modified layer 82 is not particularly limited as long as the effect of the present invention is not impaired, but is preferably 275 to 615 μm, more preferably 405 to 605 μm. Since the above-mentioned _Δ12 is in such a range, the effect of suppressing warpage of the semiconductor wafer becomes higher. The aforementioned Δ ₁₂ means the distance between the upper end of the first modified layer 81 and the lower end of the second modified layer 82 in the thickness T ₈ direction of the semiconductor wafer 8 .

The linear second modified layer 82 is ideally parallel to the linear first modified layer 81 . In other words, the direction of the arrow _M2 in FIG. 5 is ideally parallel to the direction of the arrow _M1 . Thereby, the effect of suppressing bowing of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later.

Also, as described above, when the two directions are parallel, in this embodiment, the direction in which the linear second modified layer 82 is formed is the same as the direction in which the linear first modified layer 81 is formed (that is, the direction of arrow _M1 ). It is also possible, and vice versa. However, as will be described later, when the light source of the laser light _R2 is also the light source of the laser light _R1 , as shown in FIG. 2, the above-mentioned directions are ideally opposite (ie, the direction of the arrow _M2 ). In this case, after the linear first modifying layer 81 is formed, the second modifying step can be performed immediately without returning the light source to the original position, and the time required for the first modifying step and the second modifying step can be shortened. .

In the second modifying step, it is desirable to form the second modified layer 82 directly above the first modified layer 81 in the thickness _T8 direction of the semiconductor wafer 8 . Thereby, the effect of suppressing bowing of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later. In this specification, "the second modified layer is formed directly above the first modified layer in the thickness direction of the semiconductor wafer" means "the position of the second modified layer is higher than that of the first modified layer in the thickness direction of the semiconductor wafer." The position of the layer is on the back side of the semiconductor wafer, and in a direction parallel to the surface of the semiconductor wafer (in other words, a direction perpendicular to the thickness direction of the semiconductor wafer), the position of the second modified layer is the same as the position of the first modified layer. Similarly, the second modified layer is formed".

The length of the linear second modified layer 82 in the longitudinal direction is ideally 90 to 110% of the length of the linear first modified layer 81 in the longitudinal direction. 81 have the same length in the long side direction) is more ideal. Thereby, the effect of suppressing bowing of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later.

In a direction parallel to the circuit-forming surface 8a or the back surface 8b of the semiconductor wafer 8, the position of one end of the linear second modified layer 82 may coincide with the position of one end of the linear first modified layer 81, or may not coincide. Yes, but the ideal is to be consistent. By aligning these positions, the effect of suppressing bowing of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later. The relationship between the position of the other end of the linear second modified layer 82 and the position of the other end of the linear first modified layer 81 is also the same as that of the one end described above.

In the first embodiment, as described above, after forming the first modified layer 81 far away from the light source of the laser light _R1 , the formation of the second modified layer 82 close to the light source of the laser light _R2 is not accompanied by abnormal steps, The first modified layer 81 and the second modified layer 82 can be formed. After forming the second modified layer 82, it is difficult to form the first modified layer 81 because the second modified layer 82 hinders the transmission of the laser light _R1 .

As the light source of the laser light _R2 , the light source of the laser light _R1 can also be used (the light source of the laser light _R2 can also be used as the light source of the laser light _R1 ).

In the first embodiment, in the above cross-section, in the direction connecting the circuit formation surface 8a and the back surface 8b of the semiconductor wafer 8, the number of linear first modified layers and second modified layers formed in a row is the same. it's 1. In this specification, the "direction connecting the circuit formation surface 8a and the back surface 8b of the semiconductor wafer 8" may or may not coincide with the direction of the thickness _T8 of the semiconductor wafer 8. Therefore, in the direction of the thickness T8 of the semiconductor wafer ₈ , the number of linear first modified layers and second modified layers formed in a row is ideally one.

In the first embodiment, in a direction parallel to the circuit formation surface 8a or the back surface 8b of the semiconductor wafer 8, the linear first modifying layer is repeatedly applied over the entire area of the semiconductor wafer 8 while shifting its position. 81 and the formation of the second modifying layer 82 (that is, repeating the first modifying step and the second modifying step), whereby, as shown in Figures 3(c) and 5(c), a plurality of strips are respectively formed. Linear first modified layer 81 and second modified layer 82 . The linear first modified layer 81 and the second modified layer 82 formed repeatedly in this way may be formed by the same method as the linear first modified layer 81 and the second modified layer 82 described so far. . Also, in Figure 5(c), for the sake of convenience, only six linear first modified layers 81 and second modified layers 82 are shown, but these modified layers, considering the size of the manufactured semiconductor wafer, A number of lines more than these are formed.

At this time, all the linear first modifying layers 81 are preferably formed parallel to each other. Likewise, all the linear second modifying layers 82 are ideally formed parallel to each other.

In the first embodiment, like this, along the circuit formation surface 8a of the semiconductor wafer 8, a large number of linear first modified layers 81 are formed in the first region 80a, and along the back surface 8b of the semiconductor wafer 8, the second Many linear second modifying layers 82 are formed in the region 80b. As a result, a semiconductor wafer 8 is obtained, which has a single-layer arrangement of a plurality of (plural) linear first modifying layers 81 in the first region 80a, and has a single-layer arrangement of a plurality of (plural) linear first modifying layers 81 in the second region 80b. ) layer of the linear second modifying layer 82 .

In the first embodiment, as shown in FIGS. 3(d) and 5(d), a plurality of layers similar to the above-mentioned first modified layer 81 are additionally formed in the first region 80a by the same method as that of the above-mentioned first modified layer 81. The linear first modified layer 83 intersecting the modified layer 81 is additionally formed in the second region 80b by the same method as in the case of the second modified layer 82 described above. The second modified layer 84 . At this time, as in the case of forming the first modified layer 81 and the second modified layer 82 , after the first modified layer 83 is formed, the second modified layer 84 is formed.

Also, in Figure 5(d), for the sake of convenience, only six linear first modified layers 83 and second modified layers 84 are shown, but these modified layers, considering the size of the semiconductor wafer to be produced, A number of lines more than these are formed. In addition, Fig. 3(d) shows a situation where both the first modified layer 83 and the second modified layer 84 overlap in the cross section of the semiconductor wafer 8, but according to the cross section position of the semiconductor wafer 8, in this cross section , sometimes the first modified layer 83 and the second modified layer 84 do not overlap.

The intersecting angle between the linear first modified layer 83 and the linear first modified layer 81 may be appropriately adjusted according to the shape of the target semiconductor wafer. When both the linear first modified layer 83 and the linear first modified layer 81 are linear, these intersecting angles are generally ideally 90° (that is, the linear first modified layer 83 and the linear first modified layer 81 orthogonal). The intersection angle between the linear second modified layer 84 and the linear second modified layer 82 can be set in the same manner as above. Also, when two linear lines intersect, there are two angles in which the "intersection angle" of these lines is greater than 0° and less than 180°. However, when these angles are different from each other, the term "intersection angle" in this specification means these the smaller angle.

In the thickness _T8 direction of the semiconductor wafer 8, the enlarged width of the first modified layer 83 (in other words, the height of the first modified layer 83) is not particularly limited, and may be the same as the enlarged width of the first modified layer 81 described above. The numerical range of is ideally a value approximately the same as the enlarged width of the first modified layer 81 . In this specification, the two values to be compared are "values of the same degree", which means "the same value or not, although there is a small error, the influence caused is negligibly slight". The aforementioned enlarged width of the first modified layer 83 can be adjusted by the same method as that of the aforementioned enlarged width of the first modified layer 81 .

The same applies to the second modified layer 84 . That is, in the thickness _T8 direction of the semiconductor wafer 8, the enlarged width of the second modified layer 84 (in other words, the height of the second modified layer 84) is not particularly limited, and it is the same as the enlarged width of the second modified layer 82 described above. The same numerical range is also possible, and it is preferably a value on the same level as the enlarged width of the second reforming layer 82 described above. The aforementioned enlarged width of the second modified layer 82 can be adjusted by the same method as that of the aforementioned enlarged width of the first modified layer 81 .

The distance between the linear first modified layers 81, the distance between the linear first modified layers 83, the distance between the linear second modified layers 82, and the distance between the linear second modified layers 84 All the intervals can be appropriately adjusted according to the size of the target semiconductor wafer. In this specification, the so-called "interval between linear first modified layers 81" means "the shortest distance between the ends of adjacent linear first modified layers 81", for example, "linear first modified layers 81". The same applies to the space between the modified layers 83 of the same type, etc. However, in the first embodiment, as described above, for the thickness T ₈ of the semiconductor wafer 8 when performing the first modifying step and the second modifying step, it is desirable to set the interval between these modified layers so that the semiconductor wafer The lengths of the shortest sides are equal or greater.

According to the above, the semiconductor wafer 8 is obtained. In the first region 80a, a plurality of linear first modified layers 81 and a plurality of linear first modified layers 83 form a mesh. Similarly, the second region 80b Among them, a plurality of linear second modified layers 82 and a plurality of linear second modified layers 84 form a mesh.

[Segmentation procedure in the first embodiment] Fig. 4 is an enlarged cross-sectional view for schematically explaining the dividing step in the manufacturing method of the semiconductor wafer according to the first embodiment of the present invention, and Fig. 6 is a corresponding perspective view. In the above-mentioned dividing step, as shown in FIGS. 4(a) and 6(a), the back surface 8b of the semiconductor wafer 8 is ground after the first modifying step and the second modifying step are performed. The back surface 8 b of the semiconductor wafer 8 in FIGS. 4( a ) and 6 ( a ) is the surface when it is polished by the polishing means 6 . Also, the arrow G in Fig. 4(a) indicates the operation of the polishing means 6 during polishing. Here, on the back surface 8b of the semiconductor wafer 8, the polishing means 6 is moved along the back surface 8b to draw a circle, and the above-mentioned back surface 8b is polished. Also, the grinding means 6 is not shown in section.

Therefore, at the same time as this polishing, the first modified layer 81, the first modified layer 83, the second modified layer 82, and the second modified layer 84 are In the parts, the semiconductor wafer 8 is divided. At this time, the force applied to the semiconductor wafer 8 is a force in the direction from the back surface 8 b of the semiconductor wafer 8 toward the circuit formation surface 8 a. Reference numeral 89 in Fig. 4 indicates that cracks are formed on the semiconductor wafer 8 in the direction connecting the back surface 8b and the circuit formation surface 8a due to such force. These cracks 89 form a semiconductor wafer (semiconductor wafer 8') which will be described later. Here, more specifically, the crack 89 is formed penetrating through the first modified layer 81 and the second modified layer 82 , and formed through the first modified layer 83 and the second modified layer 84 (illustration omitted). In addition, in Fig. 6(a), illustration of these cracks is omitted for easy viewing.

Like this, in the thickness _T8 direction of semiconductor wafer 8, the grinding surface of semiconductor wafer 8, namely the position of back surface 8b during grinding, reaches the first modified layer 81 and the first modified layer 81 and the first in semiconductor wafer 8 before grinding by continuing grinding. 1. The position of the modified layer 83 is further to the circuit formation surface 8a side of the semiconductor wafer 8. Finally, as shown in FIGS. 4(b) and 6(b), the first modified layer 81, the first The modified layer 83, the second modified layer 82, and the second modified layer 84 disappear, and a plurality of semiconductor wafers 8' are obtained. Also, in FIG. 6(b), one semiconductor wafer 8' is clearly shown for convenience, but there are plural (many) semiconductor wafers 8' obtained in this step.

In Figures 4(b) and 6(b), the symbol S ₈ ′ represents the length of one side of the semiconductor wafer 8 ′. Here, as the semiconductor wafer 8', it is shown that its planar shape is a square, and its four side lengths (S ₈ ′) are all the same, where S ₈ ′ is the length of the shortest side of the semiconductor wafer 8'. In addition, in this embodiment, the side lengths of the semiconductor wafers may be all the same, all may be different, or only some of them may be the same.

In the dividing step, the method of grinding the back surface 8b of the semiconductor wafer 8 may be a well-known method using a grinding machine as the grinding means 6 .

In this embodiment, since the protective film 7 is first provided on the circuit formation surface 8a of the semiconductor wafer 8 before the dividing step, a plurality of semiconductor wafers 8' are all obtained in a semiconductor wafer group 8A arranged on the protective film 7 through the dividing step. '. All of these semiconductor wafers 8' are stably held by the protective film 7 while the circuit formation surface 8a' is protected by the protective film 7. In FIGS. 4(b) and 6(b), reference numeral 8b' denotes the back surface of the semiconductor wafer 8' (that is, the surface opposite to the circuit formation surface 8a').

Figure 4(a) shows that in the thickness _T8 direction of the semiconductor wafer 8, the position of the grinding surface (back surface during grinding) 8b of the semiconductor wafer 8 does not reach the second modified layer 82 and the second modified layer 82 through grinding. The state of the position of the modified layer 84 (in other words, the stage where the second modified layer 82 and the second modified layer 84 have not disappeared through polishing) is the state of the crack 89 . However, such a state of cracks 89 is an example. In the division step in the first embodiment, when the crack 89 is formed, for example, the above-mentioned position on the polished surface (back surface) 8b of the semiconductor wafer 8 is superimposed on the second modified layer 82 and the second modified layer by polishing. 84 (in other words, the stage in which the second modified layer 82 and the second modified layer 84 are disappearing through grinding) may also pass through the position of the second modified layer 82 and the second modified layer 84 by grinding. The stage before reaching the position of the first modified layer 81 and the first modified layer 83 (in other words, the second modified layer 82 and the second modified layer 84 disappear through grinding, and the first modified layer 81 and The stage where the first modified layer 83 has not disappeared) can also be

Also, Fig. 4(a) shows a state where all the cracks 89 are formed in the same manner in this section. However, the state of such fissures 89 is an example, and the states of the plurality of fissures 89 may be the same or different in any stage of the dividing step. For example, the lengths of the plurality of fissures 89 may be the same or different from each other. In addition, the position of one end of the crack 89 in the thickness _T8 direction of the semiconductor wafer 8 may be the same or different among the plurality of cracks 89 . Similarly, the positions of the other ends of the cracks 89 may be the same or different among the plurality of cracks 89 .

Also, as shown in Figures 4(b) and 6(b), until the first modified layer 81, the first modified layer 83, the second modified layer 82, and the second modified layer 84 are all disappeared by grinding, The state of grinding the back surface 8 b of the semiconductor wafer 8 . In this case, all of the first modified layer 81, the first modified layer 83, the second modified layer 82, and the second modified layer 84 do not exist in the obtained semiconductor wafer 8'. However, the final position of such a polished surface (back surface during polishing) 8b is an example. For example, in the dividing step, the second modified layer 82 and the second modified layer 84 are eliminated by grinding, and the semiconductor wafer 8 is ground without removing the first modified layer 81 and the first modified layer 83 by grinding. 8b on the back. In this case, at least a part of the first modified layer 81 or the first modified layer 83 exists in the obtained semiconductor wafer 8' (for example, the peripheral portion of the semiconductor wafer 8'). However, the semiconductor wafer 8' having the first modified layer 81 or the first modified layer 83 in this way may have a low mechanical strength. , until the first modified layer 81 and the first modified layer 83 disappear by polishing, preferably, the back surface 8b of the semiconductor wafer 8 is polished.

In the dividing step of the first embodiment, the semiconductor wafer 8 ( No cracks 89) may be formed. The reason is that even if the semiconductor wafer 8 is not divided in part of these modified layers, the above-mentioned portion will be surely divided (cut) in a pick-up step described later. However, in order to more reliably manufacture the target semiconductor wafer, in the dividing step, it is desirable to divide all parts of the first modified layer 81, the first modified layer 83, the second modified layer 82, and the second modified layer 84. Semiconductor Wafer 8 . In this way, whether or not to divide the semiconductor wafer 8 in all the modified layers can be adjusted according to the force applied to the semiconductor wafer 8 when, for example, the back surface 8b is ground.

In the dividing step of the first embodiment, when the grinding of the back surface 8b is completed, there may be a region where the semiconductor wafer 8' is not formed (in other words, the dividing of the semiconductor wafer 8 may not be completed). The reason is that even if the division of the semiconductor wafer 8 is not completed in this way, the above-mentioned portion is surely divided (cut) in the pick-up step described later. However, in order to manufacture the target semiconductor wafer more reliably, it is desirable to complete the division of the semiconductor wafer 8 in the division step. Whether the division of the semiconductor wafer 8 is completed in this way can be adjusted, for example, through the magnitude of the force applied to the semiconductor wafer 8 during the grinding of the back surface 8b. These points are also the same in the division steps of other embodiments described later.

Here, as a first embodiment, a description will be given of a case where the number of linear first modified layers and second modified layers is one in the direction connecting the circuit formation surface and the rear surface of the semiconductor wafer in the above cross section. The method for manufacturing a semiconductor wafer, but the method for manufacturing a semiconductor wafer in this embodiment is not limited to such a method. Hereinafter, a method of manufacturing such another semiconductor wafer will be described.

>Second Embodiment> Fig. 7 is an enlarged cross-sectional view for schematically explaining the first modifying step and the second modifying step in the manufacturing method of the semiconductor wafer according to the second embodiment of the present invention. In the present embodiment, in the above-mentioned cross section (more specifically, a cross section of the semiconductor wafer in a direction perpendicular to the circuit formation surface or the back surface of the semiconductor wafer), in the direction connecting the circuit formation surface and the back surface of the semiconductor wafer, a row is formed. The method of manufacturing a semiconductor wafer when the number of linear first modifying layers and the number of second modifying layers are both 2.

[The first modifying step in the second embodiment] In the above-mentioned first modifying step in the second embodiment, as shown in FIG. 8 is irradiated with laser light _R1 , and in the inside of the semiconductor wafer 8, the first modified layer 811 and the first modified layer 811 are formed in the first region 80a at a depth of 215 μm (micrometer) from the circuit formation surface 8a of the semiconductor wafer 8 to a depth of 215 μm (micrometer). The modified layer 811 further includes a first modified layer 812 on the back surface 8 b side. In this way, by forming a plurality of first modified layers in the first region 80a, the semiconductor wafer can be divided with higher precision in the dividing step described later.

In the first modifying step in the second embodiment, in the first region 80a, instead of forming a linear first modified layer (that is, the first modified layer 81), except that the semiconductor wafer 8 has a thickness _T8 The first modifying step in the first embodiment is the same as that of the first embodiment except that two linear first modifying layers (namely, the first modifying layer 811 and the first modifying layer 812 ) are formed at positions separated from each other in the direction.

In the first modifying step in the second embodiment, the first modified layer 811 and the first modified layer 812 are formed in the first region 80a along the The circuit formation surface 8a is formed in a linear shape. Both the linear first modified layer 811 and the first modified layer 812 are parallel or substantially parallel to the circuit formation surface 8 a.

In the first modifying step in the second embodiment, both the first modified layer 811 and the first modified layer 812 can be formed in different positions in the first region 80a, and the same method as in the first embodiment can be used. The first reforming layer 81 in the first reforming step in the configuration is formed in the same manner.

In the second embodiment, the formation positions of the first modified layer 811 and the first modified layer 812 in the first region 80a are the same as the formation positions of the first modified layer 81 in the first embodiment. However, the formation positions of the first modified layer 811 and the first modified layer 812 are changed from each other.

For example, in the first embodiment, the ideal formation position of the first modified layer 81 in the first region 80a was described, but in the second embodiment, it is preferable that the first modified layer 811 and the first modified layer At least one of 812 satisfies such an ideal formation position condition, and it is better that both the first modified layer 811 and the first modified layer 812 satisfy such an ideal formation position condition. For example, in the second embodiment, the formation positions of the first modified layer 811 and the first modified layer 812 are both separated from the circuit formation surface 8a of the semiconductor wafer 8, preferably 65 to 215 μm, and more preferably 65 to 195 μm. , and more preferably 65-175 μm, particularly ideally any position in the region of 65-155 μm depth.

Both the first modified layer 811 and the first modified layer 812 have the same shape as the first modified layer 81 in the first embodiment. Therefore, the linear first modified layer 811 and the first modified layer 812 may have the same shape or different shapes. For example, the enlarged width of the first modified layer 811 (in other words, the height of the first modified layer 811) in the thickness _T8 direction of the semiconductor wafer 8 is different from the enlarged width of the first modified layer 812 (in other words, the height of the first modified layer 811). The height of the layer 812) may be the same or different.

The distance Δ ₁₁ between the first modified layer 811 and the first modified layer 812 is not particularly limited as long as the effect of the present invention is not impaired, but is preferably 0 to 60 μm, more preferably 20 to 50 μm. Since the above-mentioned _Δ11 is in such a range, both the first modified layer 811 and the first modified layer 812 are formed, and the effect produced becomes higher. The above Δ ₁₁ means the distance between the upper end of the first modified layer 811 and the lower end of the first modified layer 812 in the thickness T ₈ direction of the semiconductor wafer 8 . _Δ11 is 0 μm when the upper end of the first modified layer 811 is in contact with the lower end of the first modified layer 812 .

The linear first modified layer 811 and the first modified layer 812 are ideally parallel to each other. Thereby, the effect of suppressing warpage of the semiconductor wafer is increased, and the semiconductor wafer can be divided with higher precision in the dividing step described later.

In the first modifying step in the second embodiment, it is desirable to form the first modified layer 812 directly above the first modified layer 811 in the thickness _T8 direction of the semiconductor wafer 8 . In this way, the bowing suppression effect of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later. In this specification, "the first modified layer is formed directly above the first modified layer in the thickness direction of the semiconductor wafer" means "the positions of these first modified layers are different in the thickness direction of the semiconductor wafer, and In the direction parallel to the surface of the semiconductor wafer (in other words, the direction perpendicular to the thickness direction of the semiconductor wafer), in order to make the positions of these first modified layers the same, the position of one of the first modified layers is considered, and the other is formed. The first modified layer of one side". The same applies to the case of the second modified layer described later.

In the first modifying step in the second embodiment, the first modified layer 81 and the second modified layer 82 in the first embodiment are formed in the same manner as the first modified layer far from the light source of the laser light _R1 . After 811, the first modified layer 812 close to the light source of the laser light _R1 is formed. Thereby, the first modified layer 811 and the first modified layer 812 can be formed without step abnormality. After forming the first modified layer 812, it is difficult to form the first modified layer 811 because the first modified layer 812 hinders the transmission of the laser light _R1 .

The light source of the laser light _R1 used when forming the first modified layer 812 may be the same as the light source of the laser light _R1 used when forming the first modified layer 811 (the above-mentioned light source when forming the first modified layer 811, The light source described above when forming the first modified layer 812 may also be used).

The length of the linear first modified layer 812 in the longitudinal direction is ideally 90 to 110% or 100% of the length of the linear first modified layer 811 in the longitudinal direction (in other words, it is as long as the linear first modified layer 811). The same length in the side direction) is more ideal. Thereby, in the dividing step described later, the semiconductor wafer can be divided with higher precision.

In a direction parallel to the circuit formation surface 8a or the back surface 8b of the semiconductor wafer 8, the position of one end of the linear first modified layer 812 may coincide with the position of one end of the linear first modified layer 811, or may not coincide. Yes, but the ideal is to be consistent. Since these positions coincide, the semiconductor wafer can be divided with higher accuracy in the dividing step described later. The relationship between the position of the other end of the linear first modified layer 812 and the position of the other end of the linear first modified layer 811 is also the same as that of the above-mentioned one end.

[Second Modification Step in Second Embodiment] In the above-mentioned second modification step in the second embodiment, as shown in FIG. The circle 8 is irradiated with laser light R ₂ , and in the inside of the semiconductor wafer 8, in the second region 80b from the back surface 8b to a depth of 215 μm (micrometer), the second modified layer 812 is further formed on the side of the back surface 8b. The modified layer 821 and the second modified layer 821 are further formed on the rear surface 8b side. In this way, by forming the plurality of second modified layers in the second region 80b, the semiconductor wafer can be divided with higher precision in the dividing step described later.

In the second embodiment, both the second modified layer 821 and the second modified layer 822 are formed in the direction of the thickness _T8 of the semiconductor wafer 8 from the first modified layer (i.e., the first modified layer formed on the side of the rear surface 8b most described above). Modified layer 812) is formed toward the above-mentioned rear surface 8b side.

In the second modification step in the second embodiment, in the second region 80b, instead of forming a linear second modification layer (that is, the second modification layer 82), the thickness T of the semiconductor wafer 8 in the ₈ direction The second modifying step in the first embodiment is the same as that in the first embodiment except for the two linear second modifying layers (ie, the second modifying layer 821 and the second modifying layer 822 ) at positions separated from each other.

The second modified layer 821 and the second modified layer 822 can be formed by the same method as that of the first modified layer 811 except that the places where they are formed in the semiconductor wafer 8 are different. More specifically, in the second modifying step in the second embodiment, the second modified layer 821 and the second modified layer 822 are formed in the second region 80b in order to obtain a semiconductor wafer having a target size in the dividing step described later. , all form a line along the back surface 8b. Both the linear second modified layer 821 and the second modified layer 822 are parallel or substantially parallel to the back surface 8b.

In the second modifying step in the second embodiment, the second modified layer 821 and the second modified layer 822 can be formed in different positions in the second region 80b, and the same method as in the first embodiment can be used. The second reforming layer 82 in the second reforming step is formed by the same method.

In the second embodiment, the formation positions of the second modified layer 821 and the second modified layer 822 in the second region 80b are the same as those of the second modified layer 82 in the first embodiment. However, the formation positions of the second modified layer 821 and the second modified layer 822 are changed from each other.

For example, in the first embodiment, the ideal position for forming the second modified layer 82 in the second region 80b was described, but in the second embodiment, the second modified layer 821 and the second modified layer 822 are preferably formed. At least one of them satisfies such an ideal formation position condition, and it is more preferable that both the second modified layer 821 and the second modified layer 822 satisfy such an ideal formation position condition. For example, in the second embodiment, the formation positions of the second modified layer 821 and the second modified layer 822 are both away from the back surface 8b of the semiconductor wafer 8, preferably 65-215 μm, more preferably 65-195 μm, and More preferably, it is 65 to 175 μm, particularly preferably, any position in the depth region of 65 to 155 μm is acceptable.

Both the second modified layer 821 and the second modified layer 822 have the same shape as the second modified layer 82 in the first embodiment. Therefore, the linear second modified layer 821 and the second modified layer 822 may have the same shape or different shapes. For example, the expanded width of the second modified layer 821 (in other words, the height of the second modified layer 821) in the thickness _T8 direction of the semiconductor wafer 8 is different from the width of the second modified layer 822 (in other words, the height of the second modified layer 821). The height of the layer 822) may be the same as or different from each other.

The distance _Δ22 between the second modified layer 821 and the second modified layer 822 is not particularly limited as long as it does not impair the effect of the present invention, but it is ideally within the same numerical range as the above-mentioned distance _Δ11 , and the value of _Δ22 is the same as The values of _Δ11 may be the same or different. Since the above-mentioned _Δ22 is in such a numerical range, both the second modified layer 821 and the second modified layer 822 are formed, and the effect produced becomes higher. The aforementioned Δ ₂₂ means the distance between the upper end of the second modified layer 821 and the lower end of the second modified layer 822 in the thickness T ₈ direction of the semiconductor wafer 8 .

The linear second modified layer 821 and the second modified layer 822 are ideally parallel to each other. Thereby, the effect of suppressing warpage of the semiconductor wafer is increased, and the semiconductor wafer can be divided with higher precision in the dividing step described later.

In the second modifying step in the second embodiment, it is desirable to form the second modified layer 821 directly above the first modified layer 812 in the thickness _T8 direction of the semiconductor wafer 8 . In this way, the bowing suppression effect of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later.

Similarly, in the second modifying step in the second embodiment, it is desirable to form the second modified layer 822 directly above the second modified layer 821 in the thickness _T8 direction of the semiconductor wafer 8 . Thereby, the effect of suppressing warpage of the semiconductor wafer is increased, and the semiconductor wafer can be divided with higher precision in the dividing step described later.

In the second modified layer step in the second embodiment, the situation of the first modified layer 811 and the second modified layer 812 in the first modified layer step in the second embodiment is the same, and the light source of the laser light R ₂ is formed. After the second modified layer 821 far away, the second modified layer 822 close to the light source of the laser light _R2 is formed. Thereby, the second modified layer 821 and the second modified layer 822 can be formed without step abnormality. After forming the second modified layer 822, it is difficult to form the second modified layer 821 because the second modified layer 822 hinders the transmission of the laser light _R2 .

The light source of the laser light _R2 used when forming the second modified layer 822 may be the same as the light source of the laser light _R2 used when forming the second modified layer 821 (the above-mentioned light source when forming the second modified layer 821, The light source described above when forming the second modified layer 822 may also be used).

Moreover, the light source of the laser light _R2 used when forming the second modified layer 821 or the second modified layer 822 is the same as the light source of the laser light _R1 used when forming the first modified layer 811 or the first modified layer 812. The same is also possible (the light source of the laser light _R2 and the light source of the laser light _R1 are also possible).

The length of the linear second modified layer 822 in the longitudinal direction is ideally 90 to 110% or 100% of the length of the linear second modified layer 821 in the longitudinal direction (in other words, the same as the linear second modified layer 821 The same length in the long side direction) is more desirable. Thereby, in the dividing step described later, the semiconductor wafer can be divided with higher precision.

In a direction parallel to the circuit-formed surface 8a or the back surface 8b of the semiconductor wafer 8, the position of one end of the linear second modified layer 822 may coincide with the position of one end of the linear second modified layer 821, or may not coincide. Yes, but the ideal is to be consistent. Since these positions coincide, the semiconductor wafer can be divided with higher accuracy in the dividing step described later. The relationship between the position of the other end of the linear second modified layer 822 and the position of the other end of the linear second modified layer 821 is also the same as that of the above-mentioned one end.

The distance Δ ₁₂ between the first modified layer 812 and the second modified layer 821 in the second embodiment is the same as the distance Δ ₁₂ between the first modified layer 81 and the second modified layer 82 in the first embodiment Similarly, the effect of achieving that is also the same as that of the first embodiment. In the second embodiment, the aforementioned _Δ12 means the distance between the upper end of the first modified layer 812 and the lower end of the second modified layer 821 in the thickness _T8 direction of the semiconductor wafer 8 . Thus, in this specification, when there are plural numbers of either or both of the first modified layer and the second modified layer forming a row in the thickness direction of the semiconductor wafer, the so-called "first modified layer and second modified layer The inter-layer distance Δ ₁₂ ” means “the shortest distance existing between the first modified layer and the second modified layer in the thickness direction of the semiconductor wafer”.

The linear second modified layer 821 and the second modified layer 822 are ideally parallel to the linear first modified layer 811 and the first modified layer 812 . Thereby, the effect of suppressing bowing of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later.

In the second modifying step in the second embodiment, it is desirable to form the second modified layer 821 directly above the first modified layer 811 and the first modified layer 812 in the thickness _T8 direction of the semiconductor wafer 8. and the second modified layer 822 . In this way, the bowing suppression effect of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later.

The length of the linear second modified layer 821 and the second modified layer 822 in the longitudinal direction is ideally 90 to 110% of the length of the linear first modified layer 811 and the first modified layer 812 in the longitudinal direction. , 100% (in other words, the same length as the linear first modified layer 811 and the first modified layer 812 in the longitudinal direction) is more ideal. Thereby, the bowing suppressing effect of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later.

In the direction parallel to the circuit formation surface 8a or the back surface 8b of the semiconductor wafer 8, the position of one end of the linear second modified layer 821 and the second modified layer 822 is close to the linear first modified layer 811 and the first linear modified layer 811. The position of one end of the reforming layer 812 may or may not be the same, but is ideally the same. Since these positions match, the effect of suppressing warpage of the semiconductor wafer becomes higher, and the semiconductor wafer can be divided with higher precision in the dividing step described later. The relationship between the position of the other end of the linear second modified layer 821 and the second modified layer 822 and the position of the other end of the linear first modified layer 811 and the first modified layer 812 is also the same as that of the above-mentioned one end. same.

In the second embodiment, in the above cross-section, in the direction connecting the circuit formation surface 8a and the back surface 8b of the semiconductor wafer 8, the number of linear first modified layers and second modified layers formed in a row is the same. is 2. Therefore, in the thickness T8 direction of the semiconductor wafer ₈ , the number of linear first modified layers and second modified layers forming a row is ideally two.

In the second embodiment, in this way, in a direction parallel to the circuit formation surface 8a or the back surface 8b of the semiconductor wafer 8, while shifting positions, the linear first modifying layer is repeatedly applied over the entire area of the semiconductor wafer 8. 811 and the first modifying layer 812 and the linear second modifying layer 821 and the second modifying layer 822 (that is, repeating the first modifying step and the second modifying step), whereby, as in the seventh (c) As shown in the figure, a plurality of linear first modified layers 811 , first modified layers 812 , second modified layers 821 and second modified layers 822 are respectively formed. The linear first modified layer 811, the first modified layer 812, the second modified layer 821, and the second modified layer 822 formed repeatedly in this way only need to use the linear first modified layer 811, The first modified layer 812, the second modified layer 821, and the second modified layer 822 may be formed by the same method. Also, in Fig. 7(c), for the sake of convenience, only six linear first modified layers 811, 1st modified layer 812, second modified layer 821, and second modified layer 822 are shown. , but these modifying layers are formed in a larger number than these in consideration of the size of the semiconductor wafer to be produced.

At this time, all the linear first modifying layers 811 are ideally formed parallel to each other. Likewise, all linear first modifying layers 812 are ideally formed parallel to each other. Likewise, all the linear second modifying layers 821 are ideally formed parallel to each other. Likewise, all the linear second modifying layers 822 are ideally formed parallel to each other.

In the second embodiment, in this way, a large number of linear first modified layers 811 and 812 are formed in the first region 80a along the circuit formation surface 8a of the semiconductor wafer 8, and along the semiconductor wafer 8 8, a large number of linear second modified layers 821 and second modified layers 822 are formed in the second region 80b. As a result, a semiconductor wafer 8 is obtained, which has a layer in which a large number of (plural) linear first modified layers 811 and 812 are arranged in one layer in the first region 80a, and has one layer in the second region 80b. A plurality of (plural) linear second modified layers 821 and second modified layers 822 are arranged in layers.

In the second embodiment, as shown in FIG. 7(d), by the same method as in the case of the above-mentioned first modified layer 811, in the first region 80a, a large number of layers intersecting with the above-mentioned first modified layer 811 are additionally formed. In the first region 80a, a large number of linear first modified layers crossing the first modified layer 812 are additionally formed in the first region 80a by the same method as in the case of the above-mentioned first modified layer 812. 832. In addition, a large number of linear second modified layers 841 intersecting the second modified layer 821 are separately formed in the second region 80b by the same method as in the case of the second modified layer 821 described above. In the same manner as in the case of the modified layer 822, a large number of linear second modified layers 842 intersecting the above-mentioned second modified layer 822 are separately formed in the second region 80b. At this time, as in the case of forming the first modified layer 811 and the first modified layer 812 , after the first modified layer 831 is formed, the first modified layer 832 is formed. Then, as in the case of forming the second modified layer 821 and the second modified layer 822 , the second modified layer 842 is formed after the second modified layer 841 is formed.

In addition, FIG. 7(d) shows the situation where the first modified layer 831, the first modified layer 832, the second modified layer 841, and the second modified layer 842 all overlap in the cross section of the semiconductor wafer 8. , but depending on the cross-sectional position of the semiconductor wafer 8, these modified layers may not overlap in this cross-section.

The crossing angle between the linear first modified layer 831 and the linear first modified layer 811 , the crossing angle between the linear first modified layer 832 and the linear first modified layer 812 , the linear second modified layer 841 The angle of intersection with the linear second modified layer 821 and the angle of intersection between the linear second modified layer 842 and the linear second modified layer 822 can be set to those of the linear first modified layer in the first embodiment. The intersecting angles of the layer 83 and the linear first modified layer 81 are the same.

In the thickness _T8 direction of the semiconductor wafer 8, the enlarged width of the first modified layer 831 (in other words, the height of the first modified layer 831) is not particularly limited, and may be the same as the enlarged width of the first modified layer 811 described above. The numerical range of is ideally a value approximately the same as the enlarged width of the first modified layer 811 . The relationship between the expanded width of the first modified layer 812 and the expanded width of the first modified layer 832 in the thickness _T8 direction of the semiconductor wafer 8 is also the same. In the thickness _T8 direction of the semiconductor wafer 8, the enlarged width of the second modified layer 841 (in other words, the height of the second modified layer 841) is not particularly limited, and may be the same as the enlarged width of the second modified layer 821 described above. The numerical range of is ideally a value approximately the same as the enlarged width of the second modified layer 821 . The relationship between the expanded width of the second modified layer 842 and the expanded width of the second modified layer 822 in the thickness _T8 direction of the semiconductor wafer 8 is also the same.

The distance between the linear first modified layers 811, the distance between the linear first modified layers 812, the distance between the linear first modified layers 831, the distance between the linear first modified layers 832 interval, the interval between the linear second modified layers 821, the interval between the linear second modified layers 822, the interval between the linear second modified layers 841, and the interval between the linear second modified layers 842 The distance between them can be properly adjusted according to the size of the target semiconductor wafer. However, in the second embodiment, as described above, for the thickness T ₈ of the semiconductor wafer 8 when performing the first modifying step and the second modifying step, it is desirable to set the interval between these modified layers so that the semiconductor wafer The lengths of the shortest sides are equal or greater.

According to the above, the semiconductor wafer 8 is obtained. In the first region 80a, a plurality of linear first modified layers 811 and a plurality of linear first modified layers 831 form a mesh, and a plurality of linear The first modified layer 812 and the plurality of linear first modified layers 832 form a mesh. Similarly, in the second region 80b, the plurality of linear second modified layers 821 and the plurality of linear second modified layers The modified layer 841 forms a mesh, and the plurality of linear second modified layers 822 and the plurality of linear second modified layers 842 form a mesh.

[Segmentation procedure in the second embodiment] Fig. 8 is an enlarged cross-sectional view for schematically explaining the dividing step in the manufacturing method of the semiconductor wafer according to the second embodiment of the present invention. In the above dividing step in the second embodiment, as shown in FIG. 8(a), the back surface 8b of the semiconductor wafer 8 is ground after the first modifying step and the second modifying step are performed. In the above-mentioned dividing step in the second embodiment, the semiconductor wafer used as the semiconductor wafer 8 has the first modified layer 811 and the first modified layer 831 instead of the first modified layer 81 and the first modified layer 83 . , the first modified layer 812 and the first modified layer 832, and instead of the second modified layer 82 and the second modified layer 84, there are a second modified layer 821, a second modified layer 841, a second modified layer Except for the layer 822 and the second modified layer 842, the division procedure in the first embodiment is the same. The back surface 8 b of the semiconductor wafer 8 in FIG. 8( a ) is the surface when it is polished by the polishing means 6 .

In the second embodiment, at the same time as this polishing, the first modified layer 811, the first modified layer 831, the first modified layer 812, and the first modified layer 811, the first modified layer 831, the first modified layer 812, and the first modified layer In the modified layer 832 , the second modified layer 821 , the second modified layer 841 , the second modified layer 822 , and the second modified layer 842 , the semiconductor wafer 8 is divided. Here, the crack 89 is formed through the first modified layer 811, the first modified layer 812, the second modified layer 821, and the second modified layer 822, and is formed through the first modified layer 831, the first modified layer 832, the second modified layer 841, and the second modified layer 842 are formed (not shown).

Like this, in the thickness _T8 direction of semiconductor wafer 8, the grinding surface of semiconductor wafer 8, namely the position of back surface 8b during grinding, reaches the first modified layer 811 and the first modified layer 811 and the first in semiconductor wafer 8 before grinding through continuous grinding. 1. The position of the modified layer 831 is further to the circuit formation surface 8a side of the semiconductor wafer 8. Finally, as shown in FIG. 8(b), all the first modified layer 811, the first modified layer 831, The first modified layer 812, the first modified layer 832, the second modified layer 821, the second modified layer 841, the second modified layer 822, and the second modified layer 842 disappear, and a plurality of semiconductor wafers 8' are obtained . The semiconductor wafer 8' and the semiconductor wafer group 8A' obtained in the second embodiment are the same as the semiconductor wafer 8' and the semiconductor wafer group 8A' shown in FIG. 4(b) obtained in the first embodiment.

Figure 8(a) shows that in the thickness _T8 direction of the semiconductor wafer 8, the position of the grinding surface (back surface during grinding) 8b of the semiconductor wafer 8 does not reach the second modified layer 822 and the second modified layer 822 through grinding. The state of the position of the modified layer 842 (in other words, the stage where the second modified layer 822 and the second modified layer 842 have not disappeared through polishing) is the state of the crack 89 . However, such a crack 89 state is an example.

In the division step in the second embodiment, when the crack 89 is formed, for example, the above-mentioned position on the polished surface (back surface) 8b of the semiconductor wafer 8 is superimposed on the second modified layer 821 and the second modified layer by polishing. 841 or the stage of the second modified layer 822 and the second modified layer 842 (in other words, the stage where the second modified layer 821 and the second modified layer 841 are disappearing through grinding, or the second modified layer 822 and the second modified layer 842 are disappearing through grinding) can also be; The stage where the position of the second modified layer 822 and the second modified layer 842 is passed through the grinding, and the position of the second modified layer 821 and the second modified layer 841 is not reached (in other words, the second modified layer 822 and the second modified layer The modified layer 842 disappears through grinding, and the stage where the second modified layer 821 and the second modified layer 841 do not disappear through grinding) is also possible; The stage where the position of the first modified layer 812 and the first modified layer 832 is not reached by grinding through the position of the second modified layer 821 and the second modified layer 841 (in other words, the second modified layer 821, the second modified layer The modified layer 841, the second modified layer 822, and the second modified layer 842 disappear through grinding, and the first modified layer 811, the first modified layer 831, the first modified layer 812, and the first modified layer The stage where the stratum layer 832 has not disappeared) can also be; The stage where the first modified layer 812 and the first modified layer 832 are overlapped by grinding (in other words, the stage where the first modified layer 812 and the first modified layer 832 are disappearing through grinding) is also possible; The stage where the position of the first modified layer 811 and the first modified layer 831 is not reached by grinding through the position of the first modified layer 812 and the first modified layer 832 (in other words, the first modified layer 812 and the first modified layer The modified layer 832 disappears through grinding, and the stage where the first modified layer 811 and the first modified layer 831 are not disappeared through grinding) is also possible; The state of the crack 89 in the second embodiment is the same as the state of the crack 89 in the above-mentioned first embodiment.

Also, as shown in Figure 8(b), until the first modified layer 811, the first modified layer 831, the first modified layer 812, the first modified layer 832, the second modified layer 821, the second modified layer The rear surface 8 b of the semiconductor wafer 8 is polished until the modified layer 841 , the second modified layer 822 , and the second modified layer 842 are all eliminated by polishing. In this case, none of these modified layers exists in the obtained semiconductor wafer 8'. However, the final position of such a polished surface (back surface during polishing) 8b is an example.

For example, in the dividing step of the second embodiment, the second modified layer 821, the second modified layer 841, the second modified layer 822, and the second modified layer 842 may also be eliminated by grinding without making the first The modified layer 811 , the first modified layer 831 , the first modified layer 812 , and the first modified layer 832 disappear due to polishing, and the back surface 8 b of the semiconductor wafer 8 is polished. In this case, at least a part of the first modified layer 811, the first modified layer 831, the first modified layer 812, or the first modified layer exists in the semiconductor wafer 8' (for example, the peripheral portion of the semiconductor wafer 8'). stratum 832 . In addition, the second modified layer 821, the second modified layer 841, the second modified layer 822, the second modified layer 842, the first modified layer 812, and the first modified layer 832 can also be eliminated by grinding, Furthermore, the back surface 8b of the semiconductor wafer 8 is ground without making the first modified layer 811 and the first modified layer 831 disappear by grinding. In this case, at least a part of the first modified layer 811 or the first modified layer 831 is present in the semiconductor wafer 8' (for example, the peripheral portion of the semiconductor wafer 8'). However, the semiconductor wafer 8' in which any modified layer exists may have low mechanical strength. In the dividing step, as shown in FIG. 8(b), it is desirable to grind until the first modified layer 811 and the second 1 The back surface 8b of the semiconductor wafer 8 is ground until the modified layer 831 disappears.

Here, as a second embodiment, the case where the number of the linear first modified layer and the number of the second modified layer formed in a row in the direction connecting the circuit formation surface and the rear surface of the semiconductor wafer in the above cross section is described. The manufacturing method of semiconductor wafers, but the number of these modifying layers can also be different.

>Third Embodiment> Fig. 9 is an enlarged cross-sectional view schematically illustrating the first modifying step and the second modifying step in the manufacturing method of the semiconductor wafer according to the third embodiment of the present invention. In the present embodiment, in the above cross section (more specifically, a cross section of the semiconductor wafer in a direction perpendicular to the circuit formation surface or the back surface of the semiconductor wafer), in the direction connecting the circuit formation surface and the back surface of the semiconductor wafer, a A method of manufacturing a semiconductor wafer when the number of linear first modified layers in a row is two and the number of linear second modified layers is one.

[The first reforming step in the third embodiment] The above-mentioned first modifying step in the third embodiment is the same as the first modifying step in the second embodiment, as shown in Fig. 9(a). In this way, by forming a plurality of first modified layers in the first region 80a, the semiconductor wafer can be divided with higher precision in the dividing step described later.

[Second reforming step in the third embodiment] In the second modifying step in the third embodiment, as shown in FIG. 9(b), in addition to forming the second modified layer 82 instead of the second modified layer 821 and the second modified layer 822, and The second modification step in the second embodiment is the same. In the second modifying step in the third embodiment, for example, neither the second modified layer 821 nor the second modified layer 822 is formed, and the modified layer to be formed is other than the second modified layer 82. The method is the same as that of the second modifying step in the second embodiment. In other words, in the second modifying step in the third embodiment, instead of having the first modified layer 81, the semiconductor wafer 8 having the first modified layer 811 and the first modified layer are used as the semiconductor wafer 8 to be formed with the second modified layer. Except for the semiconductor wafer of the layer 812, it can be performed by the same method as the second modification step in the first embodiment.

The distance _Δ12 between the first modified layer 812 and the second modified layer 82 in the third embodiment is the same as the distance _Δ12 between the first modified layer 81 and the second modified layer 82 in the first embodiment Similarly, the effect achieved in this case is also the same as that of the first embodiment. In the third embodiment, the aforementioned Δ ₁₂ means the distance between the upper end of the first modified layer 812 and the lower end of the second modified layer 82 in the thickness T ₈ direction of the semiconductor wafer 8 .

In the third embodiment, in the above cross-section, the number of linear first modified layers formed in a row in the direction connecting the circuit formation surface 8a and the rear surface 8b of the semiconductor wafer 8 is two, and the linear second modified layers are two. The number of layers is 1. Therefore, ideally, in the thickness _T8 direction of the semiconductor wafer 8, the number of linear first modified layers forming a row is two, and the number of linear second modified layers is one.

In the third embodiment, in a direction parallel to the circuit formation surface 8a or the back surface 8b of the semiconductor wafer 8, the linear first modifying layer is repeatedly applied over the entire area of the semiconductor wafer 8 while shifting its position. 811 and the formation of the first modification layer 812 and the formation of the linear second modification layer 82 (that is, repeating the first modification step and the second modification step), thereby, as shown in FIG. 9(c) As shown, a plurality of linear first modified layers 811, first modified layers 812, and second modified layers 822 are respectively formed.

In the third embodiment, in this way, a large number of linear first modified layers 811 and 812 are formed in the first region 80a along the circuit formation surface 8a of the semiconductor wafer 8, and along the semiconductor wafer 8 8, a large number of linear second modifying layers 82 are formed in the second region 80b. As a result, a semiconductor wafer 8 is obtained, which has a layer in which a large number of (plural) linear first modified layers 811 and 812 are arranged in one layer in the first region 80a, and has one layer in the second region 80b. A plurality of (plural) linear second modifying layers 82 are arranged in layers.

In the third embodiment, as shown in FIG. 9(d), by the same method as in the case of the above-mentioned first modified layer 811, in the first region 80a, a large number of intersecting layers with the above-mentioned first modified layer 811 are additionally formed. In the first region 80a, a large number of linear first modified layers crossing the first modified layer 812 are additionally formed in the first region 80a by the same method as in the case of the above-mentioned first modified layer 812. 832. Also, a large number of linear second modified layers 84 intersecting the second modified layer 82 are separately formed in the second region 80b by the same method as in the case of the second modified layer 82 described above. At this time, after the first modified layer 831 is formed, the first modified layer 832 is formed.

The distance between the linear first modified layers 811, the distance between the linear first modified layers 812, the distance between the linear first modified layers 831, the distance between the linear first modified layers 832 The intervals, the intervals between the linear second modified layers 82 and the intervals between the linear second modified layers 84 may be appropriately adjusted according to the size of the target semiconductor wafer. However, in the third embodiment, as described above, for the thickness T8 of the semiconductor wafer ₈ when performing the first modifying step and the second modifying step, it is desirable to set the interval between these modified layers so that the semiconductor wafer The lengths of the shortest sides are equal or greater.

According to the above, the semiconductor wafer 8 is obtained. In the first region 80a, a plurality of linear first modified layers 811 and a plurality of linear first modified layers 831 form a mesh, and a plurality of linear Shaped first modified layer 812 and a plurality of linear first modified layers 832 form a mesh. Similarly, in the second region 80b, a plurality of linear second modified layers 82 and a plurality of linear first modified layers 2 Modified layer 84 forms a mesh.

[Segmentation procedure in the third embodiment] Fig. 10 is an enlarged cross-sectional view for schematically explaining the dividing step in the manufacturing method of the semiconductor wafer according to the third embodiment of the present invention. In the division step in the third embodiment, as shown in FIG. 10(a), as the semiconductor wafer 8, a semiconductor wafer is used instead of the second modified layer 821, the second modified layer 841, the second modified layer 822 and the second modified layer 842 can be performed by the same method as the division step in the second embodiment except that the second modified layer 82 and the second modified layer 84 are included. In other words, in the dividing step in the third embodiment, as the semiconductor wafer 8, the semiconductor wafer used instead of the first modified layer 81 and the first modified layer 83 has the first modified layer 811, the first modified layer 831, the first modified layer 812, and the first modified layer 832 can be performed by the same method as the division step in the first embodiment.

In the third embodiment, at the same time as this polishing, the first modified layer 811, the first modified layer 831, the first modified layer 812, and the first modified layer 811, the first modified layer 831, the first modified layer 812, and the first modified layer In the modified layer 832 , the second modified layer 82 , and the second modified layer 84 , the semiconductor wafer 8 is divided. Here, the crack 89 is formed through the first modified layer 811, the first modified layer 812, and the second modified layer 82, and is formed through the first modified layer 831, the first modified layer 832, and the second modified layer. 84 is formed (illustration omitted).

Like this, in the thickness _T8 direction of semiconductor wafer 8, the grinding surface of semiconductor wafer 8, namely the position of back surface 8b during grinding, reaches the first modified layer 811 and the first modified layer 811 and the first in semiconductor wafer 8 before grinding through continuous grinding. 1. The position of the modified layer 831 is further to the side of the circuit formation surface 8a of the semiconductor wafer 8. Finally, as shown in FIG. 10(b), all the first modified layer 811, the first modified layer 831, The first modified layer 812, the first modified layer 832, the second modified layer 82, and the second modified layer 84 disappear, and a plurality of semiconductor wafers 8' are obtained. The semiconductor wafer 8' and the semiconductor wafer group 8A' obtained in the third embodiment are the same as the semiconductor wafer 8' and the semiconductor wafer group 8A' shown in FIG. 4(b) obtained in the first embodiment.

As in the case of the first and second embodiments described above, in the third embodiment, the timing of forming the crack 89, the final position of the polishing surface (back surface during polishing) 8b, etc. can be appropriately adjusted according to the purpose. .

Here, as a third embodiment, a case in which the number of linear first modified layers is two and the linear second modified layer is formed in the direction connecting the circuit formation surface and the rear surface of the semiconductor wafer in the above cross section will be described. The manufacturing method of the semiconductor wafer when the number is 1, but the number of these modifying layers can also be different.

>Fourth Embodiment> Fig. 11 is an enlarged cross-sectional view for schematically explaining the first modifying step and the second modifying step in the manufacturing method of the semiconductor wafer according to the fourth embodiment of the present invention. In the present embodiment, in the above cross section (more specifically, a cross section of the semiconductor wafer in a direction perpendicular to the circuit formation surface or the back surface of the semiconductor wafer), in the direction connecting the circuit formation surface and the back surface of the semiconductor wafer, a A method of manufacturing a semiconductor wafer when the number of linear first modified layers in a row is one and the number of linear second modified layers is two.

[The first reforming step in the fourth embodiment] The above-mentioned first modifying step in the fourth embodiment is the same as the first modifying step in the first embodiment, as shown in Fig. 11(a). In other words, in the first modifying step in the fourth embodiment, instead of forming two linear first modified layers (namely, the first modified layer 811 and the first modified layer 812 ) in the first region 80a Except for the formation of one linear first modifying layer (that is, the first modifying layer 81 ), the procedure is the same as that of the first modifying step in the second embodiment. For example, in the first modifying step in the fourth embodiment, neither the first modified layer 811 nor the first modified layer 812 is formed, but the formed modified layer is used as the first modified layer 81, It can be performed by the same method as the first reforming step in the second embodiment.

[Second reforming step in the fourth embodiment] In the second modifying step in the fourth embodiment, as shown in FIG. 11(b), instead of having the first modified layer 811 and the first modified The layer 812 can be performed by the same method as the second modifying step in the second embodiment, except that the semiconductor wafer having the first modifying layer 81 is used. Both the second modified layer 821 and the second modified layer 822 can be formed by the same method as in the second embodiment. In this way, by forming the plurality of second modified layers in the second region 80b, the semiconductor wafer can be divided with higher precision in the dividing step described later.

The distance _Δ12 between the first modified layer 81 and the second modified layer 821 in the fourth embodiment is the same as the distance _Δ12 between the first modified layer 81 and the second modified layer 82 in the first embodiment Similarly, the effect achieved in this case is also the same as that of the first embodiment. In the fourth embodiment, the aforementioned Δ ₁₂ means the distance between the upper end of the first modified layer 81 and the lower end of the second modified layer 821 in the thickness T ₈ direction of the semiconductor wafer 8 .

In the fourth embodiment, in the above cross-section, the number of linear first modified layers formed in a row in the direction connecting the circuit formation surface 8a and the rear surface 8b of the semiconductor wafer 8 is one, and the linear second modified layer is one. The number of layers is 2. Therefore, ideally, in the thickness _T8 direction of the semiconductor wafer 8, the number of linear first modified layers forming a row is one, and the number of linear second modified layers is two.

In the fourth embodiment, in this way, in a direction parallel to the circuit formation surface 8a or the back surface 8b of the semiconductor wafer 8, the linear first modifying layer is repeatedly formed over the entire area of the semiconductor wafer 8 while shifting its position. 81 and the formation of linear second modifying layers 821 and 822 (that is, repeating the first modifying step and the second modifying step), whereby, as shown in FIG. 11(c), plural The strip-shaped first modified layer 81 , the second modified layer 821 and the second modified layer 822 .

In the fourth embodiment, like this, along the circuit formation surface 8a of the semiconductor wafer 8, a large number of linear first modified layers 81 are formed in the first region 80a, and along the back surface 8b of the semiconductor wafer 8, the second A large number of linear second modified layers 821 and 822 are formed in the region 80b. As a result, a semiconductor wafer 8 is obtained, which has a single-layer arrangement of a plurality of (plural) linear first modifying layers 81 in the first region 80a, and has a single-layer arrangement of a plurality of (plural) linear first modifying layers 81 in the second region 80b. ) The layers of the linear second modified layer 821 and the second modified layer 822 .

In the fourth embodiment, as shown in FIG. 11(d), by the same method as in the case of the above-mentioned first modified layer 81, in the first region 80a, a large number of layers intersecting with the above-mentioned first modified layer 81 are additionally formed. linear first modifying layer 83 . In addition, a large number of linear second modified layers 841 intersecting the second modified layer 821 are separately formed in the second region 80b by the same method as in the case of the second modified layer 821 described above. In the same manner as in the case of the modified layer 822, a large number of linear second modified layers 842 intersecting the above-mentioned second modified layer 822 are separately formed in the second region 80b. At this time, after the second modified layer 841 is formed, the second modified layer 842 is formed.

The distance between the linear first modified layers 81, the distance between the linear first modified layers 83, the distance between the linear second modified layers 821, and the distance between the linear second modified layers 822 The intervals, the intervals between the linear second modified layers 841 and the intervals between the linear second modified layers 842 may be appropriately adjusted according to the size of the target semiconductor wafer. However, in the fourth embodiment, as described above, for the thickness T ₈ of the semiconductor wafer 8 when the first modifying step and the second modifying step are performed, it is desirable to set the interval between these modified layers so that the semiconductor wafer The lengths of the shortest sides are equal or greater.

According to the above, the semiconductor wafer 8 is obtained. In the first region 80a, a plurality of linear first modified layers 81 and a plurality of linear first modified layers 83 form a mesh. Similarly, the second region 80b Among them, a plurality of linear second modified layers 821 and a plurality of linear second modified layers 841 form a mesh, and a plurality of linear second modified layers 822 and a plurality of linear second modified layers Modified layer 842 forms a mesh.

[Segmentation procedure in the fourth embodiment] Fig. 12 is an enlarged cross-sectional view schematically illustrating a division step in the manufacturing method of the semiconductor wafer according to the fourth embodiment of the present invention. The division step in the fourth embodiment is as shown in FIG. 12(a). For example, as the semiconductor wafer 8, a semiconductor wafer is used instead of the first modified layer 811, the first modified layer 831, and the first modified layer. Except for the modified layer 812 and the first modified layer 832 having the first modified layer 81 and the first modified layer 83, it can be performed by the same method as the division step in the second embodiment. In other words, in the dividing step in the fourth embodiment, instead of having the second modified layer 82 and the second modified layer 84, the semiconductor wafer used has the second modified layer 821, the second modified layer 841, the second modified layer Except for the modified layer 822 and the second modified layer 842, it can be performed by the same method as the division step in the first embodiment.

In the fourth embodiment, at the time of polishing, the first modified layer 81, the first modified layer 83, the second modified layer 821, the second modified layer In the modified layer 841 , the second modified layer 822 , and the second modified layer 842 , the semiconductor wafer 8 is divided. Here, the crack 89 is formed through the first modified layer 81, the second modified layer 821, and the second modified layer 822, and is formed through the first modified layer 83, the second modified layer 841, and the second modified layer. 842 is formed (illustration omitted).

Like this, in the thickness _T8 direction of semiconductor wafer 8, the grinding surface of semiconductor wafer 8, namely the position of back surface 8b during grinding, reaches the first modified layer 81 and the first modified layer 81 and the first in semiconductor wafer 8 before grinding by continuing grinding. 1. The position of the modified layer 83 is further to the circuit formation surface 8a side of the semiconductor wafer 8. Finally, as shown in FIG. 12(b), all the first modified layer 81, the first modified layer 83, The second modified layer 821, the second modified layer 841, the second modified layer 822 and the second modified layer 842 disappear, and a plurality of semiconductor wafers 8' are obtained. The semiconductor wafer 8' and semiconductor wafer group 8A' obtained in the fourth embodiment are the same as the semiconductor wafer 8' and semiconductor wafer group 8A' shown in FIG. 4(b) obtained in the first embodiment.

As in the case of the first embodiment and the second embodiment described above, in the fourth embodiment, the timing of forming the crack 89, the final position of the polishing surface (the back surface during polishing) 8b, etc. can be appropriately adjusted according to the purpose. .

Here, as a fourth embodiment, a case in which the number of the linear first modified layer is one and the linear second modified layer is formed in the direction connecting the circuit formation surface and the rear surface of the semiconductor wafer in the above cross section will be described. The manufacturing method of the semiconductor wafer when the number is 2, but the number of these modifying layers can also be different.

The method of manufacturing a semiconductor wafer according to this embodiment is not limited to the first to fourth embodiments described above. For example, in the method of manufacturing a semiconductor wafer according to this embodiment, within the range that does not impair the effects of the present invention, some configurations in the first to fourth embodiments may be changed or deleted, or other configurations may be added to the first to fourth embodiments.

For example, in the first to fourth embodiments, a semiconductor wafer in which the first region and the second region are separated from each other is used as the semiconductor wafer, but in the above-mentioned manufacturing method, a part of the first region and a part of the second region are used A portion of duplicated semiconductor wafers is also possible. Depending on the thickness of the semiconductor wafer when the first modifying step and the second modifying step are carried out, as such, the first region and the second region can exist inside the semiconductor wafer. In the above-mentioned manufacturing method, even in this case , as long as the second modified layer is formed on the back side of the first modified layer in the semiconductor wafer.

In addition, in the first to fourth embodiments, in the direction connecting the circuit formation surface and the back surface of the semiconductor wafer in the above cross-section, the number of linear first modifying layers in a row is 1 or 2, and the linear first modifying layers are 2 A method of manufacturing a semiconductor wafer when the number of modifying layers is 1 or 2. In this way, both the number of linear first modified layers and the number of linear second modified layers forming a row may be three or more. However, it is desirable that the number of these modifying layers is all one or two in order to simplify the manufacturing method of the above-mentioned semiconductor wafer and fully obtain the effect of the present invention.

In this embodiment, by performing the first modifying step, the second modifying step, and the dividing step described so far, as described above, a plurality of semiconductor wafer groups in the above-mentioned semiconductor wafer arrangement state are obtained. In this embodiment, a target semiconductor wafer is obtained from the semiconductor wafer group described above.

>>Manufacturing method of semiconductor device>> According to the above method of manufacturing a semiconductor wafer, after obtaining a semiconductor wafer group, a semiconductor device can be manufactured using this semiconductor wafer group. That is, the method for manufacturing a semiconductor device according to an embodiment of the present invention is based on the above-mentioned method for manufacturing a semiconductor wafer. After obtaining a semiconductor wafer group in which a plurality of semiconductor wafers are arranged, a stacking step is included, using a support sheet and a film formed on the support sheet. Wafer bonding agent, by sticking the above-mentioned film-like bonding agent in the above-mentioned bonding wafer to the above-mentioned back surface of the semiconductor wafer in the above-mentioned semiconductor chip group after grinding, the laminate of the above-mentioned semiconductor chip group and the above-mentioned bonding chip is produced; and picking up The step is to cut the above-mentioned film-like bonding agent in the above-mentioned laminated product along the above-mentioned semiconductor wafer by applying a force from the side of the support sheet to the above-mentioned laminate, and prepare the above-mentioned semiconductor wafer with the cut-off film-like bonding agent on the back, from The above-mentioned supporting sheet is pulled apart and picked up.

Fig. 13 is an enlarged cross-sectional view schematically illustrating the above-mentioned stacking step and pick-up step in the method of manufacturing a semiconductor device according to an embodiment of the present invention.

[Stacking steps] In the above lamination step in this embodiment, as shown in FIG. 13( a ), a die attach 101 including a support sheet 10 and a film-like adhesive 13 formed on the support sheet 10 is used. The support sheet 10 includes a base material 11 and an adhesive layer 12 formed on the base material 11 . The adhesive layer 12 is provided with a film-like adhesive 13 on a surface 12 a opposite to the base material 11 . That is, the substrate 11 , the adhesive layer 12 , and the film-like bonding agent 13 are laminated in this order in these thickness directions to form the bonded die 101 .

The die bonding 101 can be well known. The film bonding agent 13 is used for die bonding by bonding and fixing the semiconductor chip 8' to the circuit surface of the substrate or another semiconductor chip as will be described later. The thermosetting film-like bonding agent 13 (that is, the thermosetting film-like bonding agent 13') which is cut by the above-mentioned manufacturing method becomes Hardened. The adhesive layer 12 adjusts the bonding force between the support sheet 10 and the film adhesive 13 .

In the above lamination step, according to the semiconductor wafer manufacturing method described above, after obtaining the semiconductor wafer group 8A' in which a plurality of semiconductor wafers 8' are arranged, the adhesive wafer 101 is used to stick the film-like adhesive 13 in the adhesive wafer 101 to the The back surface 8b' of the semiconductor wafer 8' in the semiconductor wafer group 8A' after grinding is used to produce a laminate 801 of the semiconductor wafer group 8A' and the bonded wafer 101. At this time, usually, one sticky wafer 101 is attached to the entire semiconductor wafer group 8A'. In addition, in this specification, unless otherwise specified, only the description of "laminated product" means "a laminated product of a semiconductor wafer group and a bonded wafer" shown here.

Here, as the die bonding, it is shown that the substrate 11 , the adhesive layer 12 and the film bonding agent 13 are included. Such a die bonding can be used as a dicing die bonding sheet. Therefore, in this embodiment, other well-known bonded dies may be used. As other die bonding, for example, the die bonding 101 omits the adhesive layer 12; in addition to the substrate 11, the adhesive layer 12, and the film bonding agent 13, an intermediate layer of die bonding is included between any two of these layers.

In the manufacturing method of the semiconductor wafer described above, when the protective film 7 was used up to the above-mentioned dividing step, in this embodiment, the protective film 7 is removed from the semiconductor wafer 8' as shown in FIG. 13(b). In addition, in this specification, regardless of the presence or absence of a protective film, a plurality of semiconductor wafers are referred to as a "semiconductor wafer group" in an arrayed state.

[Pick up steps] In the above-mentioned pick-up step in this embodiment, as shown in FIG. 13(c), for the above-mentioned laminate 801, by applying force from the support sheet 10 side, the laminate is cut along the outer periphery 80' of the semiconductor wafer 8'. For the film bonding agent 13 in 801 , the semiconductor wafer 8 ′ with the cut film bonding agent 13 ′ on the back surface 8 b ′ is pulled away from the support sheet 10 and picked up. Here, in the film bonding agent, only the picked-up portion together with the semiconductor wafer 8' is given the symbol 13', and the symbol 13 is maintained for the rest of the portion. In addition, in this specification, the semiconductor wafer provided with the cut|disconnected film-form bonding agent on the back surface may be summed up as "semiconductor wafer with film-form bonding agent attached like this".

The pick-up step can be performed by a well-known method. In the pick-up step, for example, as a pick-up means for a semiconductor wafer, a means including a push-up portion for urging an object to be picked up and a pull-up portion for pulling the semiconductor wafer away from the support sheet is used.

The pick-up means shown here includes a protrusion (leg) 51 as the above-mentioned lifting part, and a vacuum chuck 52 as the above-mentioned pulling-up part. Therefore, here, in the example shown, in the above-mentioned pick-up means, the protruding protrusion 51, since the front end of the protrusion 51 pushes up the bonded wafer 101 from the substrate 11 side, for the laminate 801, the protruding direction P ₁ of the protrusion 51 Applying force, and pulling up the vacuum chuck 52, the adsorbed semiconductor wafer 8' is pulled away from the support sheet ₁₀ in the pulling direction P2 of the vacuum chuck 52 along with the film bonding agent 13'. At this time, the protrusion amount (jacking amount) of the protrusion 51, the protrusion speed (jacking speed), the protrusion state retention time (jacking retention time) and other jacking conditions and the pulling-up conditions such as the pulling-up speed of the vacuum chuck 52, can be adjusted appropriately. In Fig. 13, only the laminate 801 is shown in cross section.

In the pick-up step, after the cutting of the film bonding agent 13 is completed, the semiconductor wafer 8' including the cut film bonding agent 13' may be pulled from the support sheet 10, and the cutting of the film bonding agent 13 is completed. Before pulling away from the support sheet 10 the semiconductor wafer 8' including the film bonding agent 13d being cut, the cutting of the film bonding agent 13 may be completed after this pulling, and the timing of cutting the film bonding agent 13 is The sequence of timings for detaching from the semiconductor wafer 8' is not particularly limited. These timing sequences can be appropriately adjusted by adjusting the pick-up conditions such as the above-mentioned jacking conditions and pull-up conditions, or the characteristics of the film adhesive 13 .

Here, one projection 51 is shown to apply force to the laminate 801 , but in this embodiment, the number of projections 51 is not particularly limited, and may be two or more, as long as it is appropriately selected.

Here, as a method of applying a force to the laminate 801, a method of applying a force by protruding through a protruding portion constituted by a protrusion will be described, but the force may be applied by another method. As such another method, for example, use a jacking portion composed of a slide rail with an inclined surface, move along the surface of the base material 11 while making the above-mentioned dumping surface contact the surface of the base material 11 in the support sheet 10, thereby The method of applying force and other well-known methods.

Here, in the above-mentioned picking-up step, after the laminated product 801 is produced, the film-like adhesive 13 in the laminated product 801 is cut by applying force from the side of the support sheet 10 to the laminated product 801 maintained in its original state, and then picked up. The case of the semiconductor wafer 8' including the cut film bonding agent 13'. This method (hereinafter, sometimes referred to as "pick-up method (1)") has a small number of steps because it can be carried out at room temperature, which is advantageous in terms of simplification of steps. Again, this method ("pick-up method (1)") ) is suitable for the manufacture of small semiconductor wafers, and is particularly suitable for carrying out the steps from the above-mentioned first modification step to the division step which continue to be suitable for the manufacture of small semiconductor wafers of the same size.

On the other hand, in the above-mentioned picking-up step, methods other than the above-mentioned picking-up method (1) may be used. For example, after fabricating the laminate 801, instead of applying force from the side of the support sheet 10 to the laminate 801 maintained in its original state, first, the cooled laminate 801 is expanded (pulled) in a direction parallel to the surface of the bonded wafer 101 therein. long). In this way, while increasing the distance between the semiconductor wafers 8', the film-like bonding agent 13 in the laminate 801 is cut along the outer periphery 80' of the semiconductor wafer 8', and the cut film-like bonding agent 13 is prepared on the rear surface 8b'. 'The semiconductor wafer 8'. Next, in the laminated product 801 in the state where the film adhesive 13 is expanded and cut, the vicinity of the peripheral edge of the bonded wafer 101 where the semiconductor wafer 8' is not disposed is heat-treated. Next, for this heat-treated laminate 801, use the same method as the case of the above-mentioned pick-up method (1), by applying force from the support sheet 10 side, pull the back surface 8b' from the support sheet 10 to prepare the cut. The semiconductor wafer 8' of the film bonding agent 13' (the already produced semiconductor wafer with the film bonding agent) is picked up again. In this method (hereinafter, sometimes referred to as "pickup method (2)"), a wide variety of bonded die 101 can be used. On the other hand, this method ("pick-up method (2)") requires an additional step whose main purpose is to cut off the film-like adhesive. The number of steps is large, and it is also necessary to cool the laminate. It is complicated and cannot be said to be the most suitable for small sizes. semiconductor wafer manufacturing. Therefore, in this embodiment, in the picking-up step, instead of the picking-up method (2), it is desirable to use the picking-up method (1).

In the method of manufacturing a semiconductor device according to this embodiment, a semiconductor device can be manufactured by using the semiconductor wafer with a film-like bonding agent obtained in the above-mentioned pick-up step, and thereafter by a well-known method. For example, the above-mentioned semiconductor wafer with film-like bonding agent is wafer-bonded to the circuit surface of the substrate with its film-like bonding agent. If necessary, this semiconductor wafer is laminated with one or more semiconductor wafers. Resin sealing, semiconductor package can be manufactured. Thus, using this semiconductor package, a target semiconductor device can be manufactured.

◎Stick chip Next, the above-mentioned bonding chip 101 suitable for use in the lamination step and the picking step will be described in more detail.

○Substrate The above-mentioned base material constituting the support sheet in the above-mentioned bonded wafer (for example, the base material 11 constituting the support sheet 10 in the bonded chip 101 ) is in the form of a sheet or a film, and its constituent materials are, for example, various resins.

As the resin, for example, polyethylene (polyethylene), polypropylene (polypropylene), polybutene (polybutene), polybutadiene (polybutadiene), polymethylpentene (polymethylpentene), norbornene (norbornene) resin, etc. Polyolefin; ethylene/vinyl acetate copolymer, ethylene methacrylic acid copolymer, ethylene methacrylic acid ester copolymer ), ethylene based copolymer (copolymer obtained by using ethylene as a monomer) such as ethylene norbornene copolymer; vinyl chloride such as polyvinylchloride and ethylene dichloride copolymer base resin (resin obtained by using vinyl chloride as a monomer); polystyrene; polycycloolefin; polyethylene terephthalate, polyethylene naphthalate naphthalate), polybutylene terephthalate (polybutylene terephthalate), polyethylene isophthalate (polyethylene isophthalate), polyethylene 2,6-naphthalate (POLYETHYLENE 2,6-NAPHTHALENEDICARBOXYLATE), Polyesters such as wholly aromatic polyesters having aromatic ring groups in all of their constituent units; copolymers of two or more of the above-mentioned polyesters; polymethacrylates; polyurethanes; polyurethanes acrylate); polyimide; polyamide; polycarbonate; fluororesin; polyacetal; modified polyphenylene oxide; polyphenylene sulfide Ether (Polyphenylenesulfide); Polysulfone (polysulfone); Polyetherketone (Polyetherketone), etc. Moreover, as said resin, there exist polymer alloys, such as a mixture of the said polyester (polyester) and other resin, for example. Also, as the above-mentioned resin, for example, there is also a cross-linked resin in which one or more of the above-mentioned resins exemplified so far are cross-linked; for example, an ionomer (ionomer) using one or more of the above-mentioned resins exemplified so far and other modified resins.

The resin constituting the base material may be only one type, or two or more types, and in the case of two or more types, these combinations and ratios may be selected arbitrarily.

The base material may be composed of one layer (single layer), or may be composed of multiple layers of two or more layers. When the multiple layers are constituted, these plural layers may be the same as or different from each other, and the combination of these plural layers is not particularly limited. . In addition, in this specification, regardless of the base material, "a plurality of layers may be the same or different" means "whether all the layers are the same, all the layers are different, or only a part of the layers are the same. ", and the so-called "plural layers are different from each other" means "at least one of the constituent materials and thickness of each layer is different from each other.".

The thickness of the substrate is not particularly limited, but is preferably 50 to 300 μm (micrometer), more preferably 60 to 140 μm. Here, the "thickness of the base material" means the thickness of the entire base material, for example, the thickness of the base material composed of multiple layers means the total thickness of all the layers constituting the base material.

The base material may contain various well-known additives such as fillers, colorants, antistatic agents, antioxidation agents, organic lubricants, softeners (plasticizers), and the like in addition to the main constituent materials such as the above-mentioned resins.

Substrate, in order to improve the bondability with the layer provided thereon (for example, adhesive layer, film-like adhesive, etc.), roughening treatment caused by sand blasting (sand blasting), solvent treatment, etc.; corona discharge (corona discharge) , Electron beam irradiation treatment, plasma treatment, ozone. Oxidation treatments such as ultraviolet treatment, flame treatment, chromic acid treatment, hot air treatment, etc. can also be performed on the surface. In addition, the surface of the substrate may be subjected to plasma treatment.

The substrate can be produced by a well-known method. For example, a substrate containing a resin can be produced by molding a resin composition containing the above-mentioned resin.

◎Adhesive layer The above-mentioned adhesive layer constituting the support sheet in the above-mentioned die-bonding (for example, the adhesive layer 12 constituting the support sheet 10 in the die-bonding 101 ) is in the form of a sheet or film and contains an adhesive. Examples of the aforementioned binder include acrylic resin, urethane resin, rubber resin, silicone resin, epoxy resin, polyvinyl ether, polycarbonate, Adhesive resins such as ester resins.

In addition, in this specification, "adhesive resin" includes both an adhesive resin and an adhesive resin. For example, the above-mentioned adhesive resins include not only the adhesiveness of the resin itself, but also resins exhibiting adhesiveness due to the combination with other components such as additives, and resins exhibiting adhesiveness due to the presence of triggers such as heat or water.

The adhesive layer may be composed of one layer (single layer), or may be composed of multiple layers of two or more layers. When composed of multiple layers, these multiple layers may be the same or different from each other, and the combination of these multiple layers is not particularly limited. .

The thickness of the adhesive layer is not particularly limited, but is preferably 1 to 100 μm, more preferably 1 to 60 μm, and particularly preferably 1 to 30 μm. Here, the "thickness of the adhesive layer" means the thickness of the entire adhesive layer, for example, the thickness of the adhesive layer consisting of a plurality of layers means the total thickness of all the layers constituting the adhesive layer.

The adhesive layer may be formed using an energy ray-curable adhesive or may be formed using a non-energy ray-curable adhesive. That is, the adhesive layer may be both energy ray curable and non-energy ray curable. The energy ray hardening adhesive layer can easily adjust its physical properties before and after hardening.

In this specification, the term "energy rays" means energy quanta in electromagnetic waves or charged particle rays, for example, ultraviolet rays, radiation rays, electron rays, and the like. Ultraviolet rays can be irradiated by using, for example, a high-pressure mercury lamp, a fusion lamp, a xenon lamp, a black light, or an LED (light emitting diode) lamp as an ultraviolet light source. Electron beams can irradiate things produced by electron beam accelerators and the like. In addition, in this specification, "energy ray curability" means the property of being cured by irradiation of energy ray, and "non-energy ray curability" means the property of not being cured even when irradiated with energy ray.

The adhesive layer can be formed using an adhesive composition containing an adhesive. For example, the adhesive composition can be applied on the surface to be formed of the adhesive layer and dried as necessary, so that the adhesive layer can be formed on the target site. The content ratio of the components that do not evaporate at room temperature in the adhesive composition is usually the same as the content ratio of the above-mentioned components in the adhesive layer. In this specification, "normal temperature" refers to a temperature that is not particularly cold or hot, that is, an ordinary temperature, for example, a temperature of 15 to 25° C., and the like.

Coating of the adhesive composition may be carried out by a well-known method, for example, using an air knife coater, blade coater, bar coater, gravure coater, roll coater, hob coater, etc. Coater, Curtain Coater, Die-cast Coater, Blade Coater, Screen Coater, Meyer Bar Coater, Kiss Coater, etc. Methods.

When the adhesive layer is provided on the base material, for example, the adhesive composition is coated on the base material and dried as needed, as long as the adhesive layer is laminated on the base material, and when the adhesive layer is provided on the base material, for example, The adhesive composition is coated on the release film, dried as necessary, an adhesive layer is formed on the release film, and the exposed surface of the adhesive layer is bonded to the surface of the base material to laminate the adhesive layer on the base material. The peeling film at this time may be removed at any timing during the manufacturing process or the use process of the bonded wafer.

When the adhesive layer is energy ray curable, the energy ray curable adhesive composition includes, for example, a non-energy ray curable adhesive resin (I-1a) (hereinafter, sometimes referred to as "adhesive resin (I-1a) -1a) ") and an energy ray-curable adhesive composition (I-1); energy ray-curable adhesive resin (I-1a) containing an unsaturated group introduced into the side chain of the non-energy ray-curable adhesive resin (I-1a) An adhesive composition (I-2) containing the adhesive resin (I-2a) (hereinafter, sometimes referred to as "adhesive resin (I-2a)"); and an adhesive composition (I-2) containing the above adhesive resin (I-2a) and Adhesive composition (I-3) of an energy ray-curable compound.

When the adhesive layer is non-energy ray-curable, the non-energy ray-curable adhesive composition is, for example, the adhesive composition (I-4) containing the above-mentioned non-energy ray-curable adhesive resin (I-1a). wait.

[Adhesive resin (I-1a)] The above adhesive composition (I-1), adhesive composition (I-2), adhesive composition (I-3) and adhesive composition (I-4) (hereinafter, including these adhesive compositions, The above-mentioned adhesive resin (I-1a) in the adhesive composition (I-1) to (I-4)) is summarized, preferably an acrylic resin.

As the above-mentioned acrylic resin, for example, an acrylic polymer having at least a constituent unit derived from methacrylic acid alkyl ester. As the above-mentioned methacrylic acid alkyl ester, for example, the carbon number of the alkyl group constituting the alkyl ester (alkyl ester) is 1 to 20, and the above-mentioned alkyl group is preferably a straight chain or a branched chain.

The above-mentioned acrylic polymer desirably has a constituent unit derived from a functional group-containing monomer in addition to the constituent unit derived from methacrylic acid alkyl ester. As the above-mentioned functional group-containing monomer, for example, by reacting the above-mentioned functional group with a cross-linking agent described later to become a starting point of cross-linking, or by reacting the above-mentioned functional group with an unsaturated group in an unsaturated group-containing compound described later, unsaturation can be introduced. group into the side chain of the acrylic polymer.

As the above-mentioned functional group-containing monomer, for example, a hydroxyl group-containing monomer, a carboxy group-containing monomer, an aluminum group-containing monomer, an epoxy resin-containing monomer, and the like.

The above-mentioned acrylic polymer may have constituent units derived from other monomers in addition to the constituent units derived from methacrylic acid alkyl ester and the constituent units derived from functional group-containing monomers. The above-mentioned other monomers are not particularly limited as long as they can be copolymerized with methacrylic acid alkyl ester or the like. Examples of the above-mentioned other monomers include styrene, α-methylstyrene, vinyl toluene, formic acid vinyl, vinyl acetate, acrylonitrile ( acrylic nitrole), acrylamide (acrylic amid), etc.

In the adhesive compositions (I-1) to (I-4), the constituent units of the above-mentioned acrylic resin such as the above-mentioned acrylic polymer may be only one type, or two or more types may be used. When there are two or more types, any Choose from these combinations and ratios.

In the above-mentioned acrylic polymer, the content of the structural unit derived from the functional group-containing monomer is preferably 1 to 35% by mass based on the total amount of the structural unit.

The adhesive resin (1-1a) contained in the adhesive composition (I-1) or the adhesive composition (I-4) may be only one type, or two or more types may be used. If there are two or more types, it may be arbitrarily selected These combinations and ratios.

In the adhesive composition (I-1) or the adhesive composition (I-4), the adhesive resin (1- 1a) The ratio of the content is ideally 5 to 99% by mass.

[Adhesive resin (I-2a)] The above-mentioned adhesive resin (I-2a) in the above-mentioned adhesive composition (I-2) and (I-3), for example, reacts the functional group in the adhesive resin (I-1a) and has energy ray polymerizable non- Saturated groups are obtained from unsaturated group-containing compounds.

The above-mentioned unsaturated group-containing compound has a group capable of bonding to the adhesive resin (I-1a) by reacting with a functional group in the adhesive resin (I-1a) in addition to the above-mentioned energy ray polymerizable unsaturated group. compound. As the above energy ray polymerizable unsaturated group, for example, acryl (meth acryloyl), vinyl (vinyl, ethyl), allyl (2-propenyl) etc., preferably acryl (meth acryloyl) . As the group that can be bonded to the functional group in the adhesive resin (1-1a), for example, an isocyanate group (isocyanate) and a glycidyl group (glycidyl) that can be bonded to a hydroxyl group (hydroxyl) or an amino group (amino) and Hydroxyl, amino, etc. that can be combined with carboxy or epoxy.

Examples of the unsaturated group-containing compound include meth acryloyl oxyethyl isocyanate, meth acryloyl isocyanate, glycidyl (meth) acrylate and the like.

The adhesive resin (I-2a) contained in the adhesive composition (I-2) or (I-3) may be only one type, or two or more types may be used. If there are two or more types, these combinations and ratios may be selected arbitrarily .

In the adhesive composition (I-2) or (I-3), the ratio of the content of the adhesive resin (1-2a) to the total mass of the adhesive composition (I-2) or (I-3), ideally It is 5 to 99% by mass.

[Energy Beam Curing Compound] Examples of the above-mentioned energy ray-curable compounds in the above-mentioned adhesive compositions (I-1) and (I-3) include energy ray-polymerizable unsaturated groups that can be cured by energy ray irradiation or oligomers.

Among the energy ray-curing compounds, examples of monomers include trimethylolpropane tri(meth)acrylate, pentaerythritol (meth)acrylate, and pentaerythritol tetra(meth)acrylate. acrylate), dipentaerythritol hexa(meth)acrylatel), 1,4 butylene glycol di(meth)acrylate, 1,6-hexanediol acrylate (1 , 6-hexanediol (meth)acrylate) and other polyvalent acrylates; urethane (meth)acrylate; acrylate polyester (polyester (meth)acrylate); acrylic polyether (polyether (meth)acrylate); Epoxy (meth) acrylate, etc. Among the energy ray-curable compounds, the oligomer is, for example, an oligomer obtained by polymerizing the monomers exemplified above.

The above-mentioned energy ray-curing compounds contained in the adhesive composition (I-1) or (I-3) may be only one type, or two or more types may be used. If there are two or more types, these combinations and ratios may be selected arbitrarily.

In the above adhesive composition (I-1), the ratio of the content of the energy ray-curable compound to the total mass of the adhesive composition (I-1) is desirably 1 to 95% by mass. In the adhesive composition (I-3), the content of the energy ray-curable compound is preferably 0.01 to 300 parts by mass based on 100 parts by mass of the adhesive resin (I-2a).

[Crosslinking agent] When the above-mentioned acrylic polymer used as the adhesive resin (I-1a) has a constituent unit derived from a functional group-containing monomer in addition to a constituent unit derived from a methacrylic acid alkyl ester, the adhesive Composition (I-1) or (I-4) preferably further contains a crosslinking agent. Also, when the above-mentioned acrylic polymer having the same structural unit derived from a functional group-containing monomer as in the adhesive resin (I-1a) is used as the adhesive resin (I-2a), the adhesive composition (I-2a) -2) It may also contain a crosslinking agent.

The above-mentioned cross-linking agent in the above-mentioned adhesive resin (I-1a) and (I-2a), for example, reacts with the above-mentioned functional group to cross-link the adhesive resin (I-1a) or the adhesive resin (I-2a )between. As the crosslinking agent, for example, isocyanates such as tolylene diisocyanate, hexamethylene diisocyanate, xylylene diisocyanate, and adducts of these diisocyanates (isocyanate) cross-linking agent (cross-linking agent with isocyanate group); epoxy-based cross-linking agent (cross-linking agent with epoxypropyl group) such as ethylene glycol glycidyl ether; six [1 - (2-Methyl) - aziridinyl] trifluoromethanesulfonate triazine (hexa [1- (2-methyl) - aziridinyl] triflate male fan triazine) and other aziridine cross-linking agents (with aziridinyl based crosslinking agent); aluminum chelate and other metal chelate crosslinking agents (crosslinking agents with metal chelate structure); isocyanurate (isocyanurate) crosslinking agents (isocyanurate) Cyanuric acid skeleton (isocyanuric acid skeleton) and so on.

The crosslinking agent contained in the adhesive composition (I-1), (I-2) or (I-4) may be only one type, or two or more types may be used. If there are two or more types, these combinations and ratio.

In the above adhesive composition (I-1) or (I-4), the crosslinking agent content is preferably 0.01 to 50 parts by mass based on 100 parts by mass of the adhesive resin (I-1a) content. In the above adhesive composition (I-2), the content of the crosslinking agent is preferably 0.01 to 50 parts by mass relative to 100 parts by mass of the adhesive resin (I-2a) content.

[Photopolymerization Initiator] Adhesive composition (I-1), (I-2) or (I-3) (hereinafter, including these adhesive compositions, are summarized as "adhesive composition (I-1)~(I-3)" ), may also include a photopolymerization initiator. Adhesive compositions (I-1) to (I-3) containing a photopolymerization initiator fully progressed the curing reaction even when irradiated with relatively low-energy energy rays such as ultraviolet rays.

Examples of the aforementioned photopolymerization initiator include benzoin, benzoin methyl ether, benzoin ethyl ether, benzoin isopropyl ether, benzoin Benzoin isobutyl ether, benzoin benzoic acid, methyl benzoin benzoic acid methyl, benzoin dimethyl ketal, etc. Benzoin compounds; acetophenone, 2-hydroxy-2-methyl-1-phenyl-propane-1-one (2-hydroxy-2-methyl-1-phenyl-propane-1-one) , 2,2-dimethoxy-1,2-diphenylethane-1-one (2,2-dimethoxy-1,2-diphenylethane-1-one) and other acetophenone compounds; bis(2, 4,6-trimethylbenzoyl) phenyl phosphine oxide (bis (2,4,6-trimethylbenzoyl) phenyl phosphine oxide), 2,4,6-trimethylbenzoyl diphenyl phosphine oxide (2 , 4,6-trimethylbenzoyl diphenyl phosphine oxide) and other acylphosphine oxide compounds; benzyl phenyl sulfide, tetramethylthiuram monosulfide and other sulfide compounds ; 1-hydroxycyclohexyl phenyl ketone (1-hydroxycyclohexyl phenyl ketone) and other alpha-ketol (alpha-ketol) compounds; azobisisobutyronitrile (azobisisobutyronitrile) and other azo (Azo) compounds; ) and other cyclopentadienyl titanium compounds; thioxanthone (thioxanthone) and other thioxanthone compounds; peroxide (peroxide) compounds; diacetyl (diacetyl) and other diketone (diketone) compounds; benzil); bibenzyl (dibenzyl); benzophenone (benzophenone); 2, 4-diethylthioxanthone (diethylthioxanthone); 1, 2-diphenylmethane (1, 2-diphenylmethane); 2-hydroxy -2-methyl-1-[4-(1-methylvinyl)phenylacetone (2-hydroxy-2-methyl-1-[4-(1-methylvinyl)phenyl]propanone); 1-chloroanthraquinone (1-chloroanthraquinone), 2-chloroanthraquinone (2-chloroanthraquinone) and other quinone compounds. Moreover, as said photopolymerization initiator, photosensitizers, such as an amine, etc. can also be used, for example.

The photopolymerization initiators contained in the adhesive compositions (I-1) to (I-3) may be only one type, or two or more types may be used. If there are two or more types, these combinations and ratios may be selected arbitrarily.

The content of the photopolymerization initiator in the adhesive composition (I-1) is preferably 0.01 to 20 parts by mass based on 100 parts by mass of the energy ray-curable compound. The content of the photopolymerization initiator in the adhesive composition (I-2) is preferably 0.01 to 20 parts by mass based on 100 parts by mass of the adhesive resin (I-2a). The content of the photopolymerization initiator in the adhesive composition (I-3) is preferably 0.01 to 20 parts by mass based on 100 parts by mass of the total content of the adhesive resin (I-2a) and the energy ray-curable compound. share.

[Other additives] Adhesive compositions (I-1) to (I-4) may contain other additives that do not correspond to any of the above-mentioned components, as long as the effects of the present invention are not impaired. Other additives mentioned above include antistatic agents, antioxidation agents, softeners (plasticizers), fillers, antirust agents, colorants (pigments, dyes), sensitizers, adhesion imparting agents, and reaction delay agents. , crosslinking accelerator (catalyst) and other well-known additives. In addition, the so-called reaction delaying agent is, for example, due to the catalytic action mixed in the adhesive composition (I-1) to (I-4), in the adhesive composition (I-1) to (I-4) during storage , can inhibit the non-target cross-linking reaction. As a reaction delaying agent, for example, a chelate complex is formed by using a chelate with a catalyst, and more specifically, there are two or more carbonyl groups (-C(=O)-) in one molecule.

The other additives contained in the adhesive compositions (I-1) to (I-4) may be only one kind, or two or more kinds, and if there are two or more kinds, these combinations and ratios may be selected arbitrarily.

The content of other additives in the adhesive compositions (I-1) to (I-4) is not particularly limited, and may be appropriately selected according to the type.

[solvent] The adhesive compositions (I-1) to (I-4) may contain a solvent. Since the adhesive compositions (I-1) to (I-4) contain a solvent, the coating suitability to the surface to be coated is improved.

The above-mentioned solvent is preferably an organic solvent, and as the above-mentioned organic solvent, for example, ketones (ketones) such as methyl ethyl ketone (methyl ethyl ketone) and acetone (acetone); esters (esters) (carboxylates) such as ethyl acetate (ethyl acetate) (carboxylic acid ester)); ethers such as tetrahydrofuran and dioxane; aliphatic carbohydrates such as cyclohexane and n-hexane, etc.; toluene ( Aromatic carbohydrates such as toluene and xylene; alcohols such as 1-propanol and 2-propanol, etc.

The solvents contained in the adhesive compositions (I-1) to (I-4) may be only one kind, or two or more kinds, and if there are two or more kinds, these combinations and ratios may be selected arbitrarily.

The solvent content of the adhesive compositions (I-1) to (I-4) is not particularly limited, and may be appropriately adjusted.

○Manufacturing method of adhesive composition Adhesive compositions such as adhesive compositions (I-1) to (I-4) are obtained by blending the above-mentioned adhesive and, if necessary, components constituting the adhesive composition such as components other than the above-mentioned adhesive. The order of addition of each component is not particularly limited, and two or more kinds may be added simultaneously. The method of mixing the components at the time of compounding is not particularly limited, and the method of mixing such as rotating a stirring bar or stirring paddle; mixing with a stirrer; mixing with ultrasonic waves, etc. may be appropriately selected from well-known methods. The temperature and time for the addition and mixing of each component are not particularly limited as long as the components are not deteriorated, as long as they are appropriately adjusted, and the temperature is preferably 15 to 30°C.

○Film adhesive The film adhesive constituting the die attach (for example, the film adhesive 13 constituting the die attach 101 ) desirably has thermosetting properties and preferably has pressure-sensitive bonding properties. The film-like adhesive with thermosetting and pressure-sensitive bonding properties can be pasted by lightly pressing each adherend in the uncured state. In addition, the film-like adhesive may be bonded to various adherends by heating and softening. The film adhesive, after hardening, finally becomes a hardened product with high impact resistance. This hardened product can withstand severe high temperatures. Sufficient bonding properties can be maintained even under high humidity conditions.

The film-like adhesive may be composed of one layer (single layer), or may be composed of multiple layers of two or more layers. When composed of multiple layers, these plural layers may be the same as or different from each other. The combination is not particularly limited.

The thickness of the film adhesive is not particularly limited, but is preferably 1 to 100 μm (micrometer), more preferably 1 to 60 μm, and particularly preferably 1 to 30 μm. Here, the "thickness of the film adhesive" means the thickness of the entire film adhesive, for example, the thickness of a film adhesive composed of a plurality of layers means the total thickness of the layers constituting the film adhesive.

The film-like adhesive can be formed using an adhesive composition containing its constituent components. For example, the adhesive composition can be applied on the surface to be formed of the film adhesive, and dried as necessary to form the film adhesive on the target site. In the adhesive composition, the content ratio of the components that do not evaporate at normal temperature is usually the same as the content ratio of the above-mentioned components in the film adhesive.

The cement composition can be applied by the same method as the cement composition described above.

When the film-like adhesive is provided on the support sheet, for example, the adhesive composition is coated on the support sheet and dried if necessary, and the film-like adhesive may be laminated on the support sheet. In addition, when the film adhesive is provided on the support sheet, for example, the adhesive composition is coated on a release film, dried if necessary, and the film adhesive is first formed on the release film, and the exposed surface of the film adhesive is aligned with the target surface of the support sheet. The surfaces are bonded to each other, and a film-like adhesive can be laminated on the support sheet. The peeling film at this time may be removed at any timing during the manufacturing process or the use process of the bonded wafer.

A thermosetting adhesive composition is mentioned as an ideal adhesive composition. The thermosetting adhesive composition contains, for example, a polymer component (a) and an epoxy-based thermosetting resin (b). Hereinafter, each component is demonstrated.

[Polymer component (a)] The polymer component (a) is regarded as a component formed during the polymerization reaction of a polymerizable compound, and is used to improve the bonding property to bonding objects such as semiconductor wafers by imparting film-forming properties or flexibility to the film-like bonding agent. (adhesive) polymer components. Moreover, the polymer component (a) also has a component which does not correspond to the epoxy resin (b1) and thermosetting agent (b2) mentioned later.

The polymer component (a) contained in the adhesive composition and the film-like adhesive may be only one type, or two or more types may be used, and if there are two or more types, these combinations and ratios may be selected arbitrarily.

As the polymer component (a), for example, acrylic resin, polyester, urethane resin, acrylic urethane resin, silicone resin, rubber resin, phenoxy (phenoxy) resin, thermosetting polyimide (polyimide), etc., preferably acrylic (acrylic) resin.

Well-known acrylic polymers are mentioned as said acrylic (acrylic) resin in a polymer component (a).

The above-mentioned acrylate (methacrylic acid ester) constituting the acrylic (acrylic) resin, for example, the alkyl group constituting the alkyl ester (alkyl ester), the above-mentioned methacrylic acid alkyl ester (methacrylic acid alkyl) having a chain structure of 1 to 18 carbon atoms acrylate cycloalkyl ester ((meth)acrylate cycloalkyl ester); acrylate aralkyl ester ((meth)acrylate aralkyl ester); acrylate cycloalkenyl ester ((meth)acrylate cycloalkenyl ester); (meth)acrylate cycloalkenyl oxylkyl ester); acrylic imide ((meth)acrylate imide); containing glycidyl acrylate; containing hydroxyl (hydroxyl) acrylate; containing replacement amino (amino) acrylate, etc. Here, the "substituted amino group" means a group in which one or two hydrogen atoms of an amino group are replaced with a group other than a hydrogen atom.

In addition, in this specification, "acrylic acid ((meth)acrylate)" includes both concepts of "(meth)acrylate" and "acrylate". The same applies to terms similar to acrylic acid ((meth)acrylate).

Acrylic resin (acrylic resin), for example, in addition to the above-mentioned methacrylic acid ester (methacrylic acid ester), from acrylic acid (methacrylic acid), methylene succinic acid (itaconic), vinyl acetate (vinyl acetate), acrylonitrile (acrylonitrile) ), styrene (styrene) and N-methylol acrylamide (N-methylol acrylamide) and other selected one or two or more monomers may be formed by copolymerization.

Acrylic resin (acrylic resin), in addition to the above-mentioned hydroxyl (hydroxyl), has other compounds such as vinyl (vinyl) group, acrylic (methacrylic) group, amino group (amino), carboxy group, isocyanate group (isocyanate) and so on. Bondable functional groups are also possible. These functional groups including hydroxyl groups of acrylic resin may be bonded to other compounds via a crosslinking agent (f) described later, or may be directly bonded to other compounds without using a crosslinking agent (f). Since the acrylic resin (acrylic resin) is combined with other compounds through the above-mentioned functional group, the reliability of the package obtained by using the film-like adhesive tends to be improved.

The monomers constituting the acrylic resin (acrylic resin) may be only one kind, or two or more kinds. When there are two or more kinds, these combinations and ratios may be selected arbitrarily.

In this embodiment, instead of using acrylic resin as the polymer component (a), thermoplastic resins other than acrylic resins (hereinafter, sometimes simply referred to as "thermoplastic resins") may be used alone or in combination with acrylic resins. . Examples of the thermoplastic resin include polyester, polyurethane, phenoxy resin, polybutene, polybutadiene, polystyrene )wait.

The above-mentioned thermoplastic resin contained in the adhesive composition and the film adhesive may be only one type, or two or more types may be used. When there are two or more types, these combinations and ratios may be selected arbitrarily.

In the composition of the adhesive composition, the content ratio of the polymer component (a) to the total content of all components except the solvent (that is, the polymer component (a) in the film adhesive to the total mass of the film adhesive content ratio), regardless of the type of polymer component (a), it is ideally 20 to 75% by mass.

[Epoxy Thermosetting Resin (b)] The epoxy-based thermosetting resin (b) is composed of an epoxy resin (b1) and a thermosetting agent (b2). The epoxy-based thermosetting resin (b) contained in the adhesive composition and the film adhesive may be only one type, or two or more types may be used. When there are two or more types, these combinations and ratios may be selected arbitrarily.

(Epoxy resin (b1)) Examples of the epoxy resin (b1) include well-known ones such as polyfunctional epoxy resins, biphenyl, bisphenol A diglycidyl ether and its hydrogenated products, o-cresol Novolac epoxy (ortho-cresol novolak epoxy) resin, dicyclopentadiene (dicyclopentadiene) type epoxy resin, biphenyl (biphenyl) type epoxy resin, bisphenol (bisphenol) A type epoxy resin, bisphenol (bisphenol) ) F-type epoxy resin, phenylene (phenylene) skeleton type epoxy resin, etc., epoxy compounds with more than two functions.

The epoxy resin (b1) contained in the adhesive composition and the film adhesive may be only one type, or two or more types may be used, and in the case of two or more types, these combinations and ratios may be selected arbitrarily.

(Thermohardener (b2)) The thermosetting agent (b2) acts as a curing agent for the epoxy resin (b1). The thermosetting agent (b2) is, for example, a compound having two or more functional groups capable of reacting with epoxy groups in one molecule. As the above-mentioned functional group, for example, a phenolic hydroxyl group, an alcoholic hydroxyl group, an amino group, a carboxy group, an anhydrided group of an acid group, etc., preferably an anhydrided group of a phenolic hydroxyl group, an amino group, or an acid group, more preferably Ideally, it is a phenolic hydroxyl group or an amino group.

Among the thermosetting agents (b2), as the phenolic curing agent having a phenolic hydroxyl group, for example, polyfunctional phenol resin, biphenol (biphenol), novolac (novolak) type phenol resin, dicyclopentadiene ( dicyclopentadiene) type phenol resin, aralkyl type phenol resin and the like. Among the thermosetting agents (b2), dicyandiamide (DICY) and the like are examples of the amino-based curing agent having an amino group.

The thermosetting agent (b2) contained in the adhesive composition and the film adhesive may be only one type, or two or more types may be used. When there are two or more types, these combinations and ratios may be selected arbitrarily.

In the adhesive composition and film adhesive, the content of the thermosetting agent (b2) is preferably 0.1 to 500 parts by mass relative to 100 parts by mass of the epoxy resin (b1) content.

In the adhesive composition and the film adhesive, the content of the epoxy-based thermosetting resin (b) (the total content of the epoxy resin (b1) and the thermosetting agent (b2)) is different from that of the polymer component (a ) content of 100 parts by mass, ideally 5 to 100 parts by mass.

In order to improve various physical properties, the above-mentioned film adhesive may contain other components other than the polymer component (a) and the epoxy-based thermosetting resin (b) if necessary. Other components contained in the above-mentioned film adhesive include, for example, curing accelerator (c), filler (d), coupling agent (e), crosslinking agent (f), energy ray curable resin (g), photopolymerization Starter (h), general additives (i), etc. Among these, ideal examples of the aforementioned other components include a curing accelerator (c), a filler (d), a coupling agent (e), and a general-purpose additive (i).

[hardening accelerator (c)] The hardening accelerator (c) is a component for adjusting the hardening speed of the cement composition. As ideal hardening accelerator (c), for example, triethylenediamine (triethylenediamine), benzyldimethylamine (benzyldimethylamine), triethanolamine (triethanolamine), dimethylaminoethanol (dimethylaminoethanol), tris(dimethyl Aminomethyl) phenol (tris dimethyl aminomethyl phenol) and other tertiary amines; 2-methylimidazole (2-methylimidazole), 2-phenylimidazole (2-phenylimidazole), 2-phenyl-4-methylimidazole ( 2-phenyl-4-methylimidazole), 2-phenyl-4,5-dimethylimidazole (2-phenyl-4,5-dihydroxy methylimidazole), 2-phenyl-4-methyl-5-hydroxymethyl Imidazoles such as 2-phenyl-4-methyl-5-hydroxy methylimidazole (imidazoles in which one or more hydrogen atoms are replaced by groups other than hydrogen atoms); tributyl phosphine, diphenyl phosphine Phosphine), triphenylphosphine and other organic phosphine (phosphine with more than one hydrogen atom replaced by an organic group); tetraphenylphosphonium tetraphenylborate, tetraphenylborontriphenylphosphine Tetraphenylboron salts such as triphenylphosphonium tetraphenylborate; crystal cage compounds using the above-mentioned imidazoles as guest compounds; and the like.

The curing accelerator (c) contained in the adhesive composition and the film adhesive may be of only one type, or two or more types may be used. When there are two or more types, these combinations and ratios may be selected arbitrarily.

When the hardening accelerator (c) is used, the content of the hardening accelerator (c) in the adhesive composition and the film adhesive is preferably 100 parts by mass of the content of the epoxy-based thermosetting resin (b). 0.01 to 10 parts by mass.

filler (d) Since the film adhesive contains the filler (d), it is easy to adjust the thermal expansion coefficient. By optimizing the thermal expansion coefficient for the object to be pasted with the film adhesive, the reliability of the package obtained by using the film adhesive is further improved. Moreover, since the film adhesive contains the filler (d), it is also possible to reduce the moisture absorption rate of the cured film adhesive and improve heat dissipation.

The filler (d) may be an organic filler or an inorganic filler, but is preferably an inorganic filler. As an ideal inorganic filler, for example, silica (silica), alumina (alumina), talc (talc), calcium carbonate (calcium carbonate), titanium white (titanium white), iron oxide (red oxide), silicon carbide (silicon carbide), boron nitride and other powders; spheroidized beads of these inorganic fillers; surface modified products of these inorganic fillers; single crystal fibers of these inorganic fillers; glass fibers, etc. Among these, the inorganic filler is preferably silicon dioxide (silica) or aluminum oxide (alumina).

The filler (d) contained in the adhesive composition and the film-like adhesive may be only one type, or two or more types may be used. When there are two or more types, these combinations and ratios may be selected arbitrarily.

When the filler (d) is used, the content ratio of the filler (d) to the total content of all components other than the solvent in the adhesive composition (that is, in the film adhesive, the filling ratio of the total mass of the film adhesive to the total mass of the film adhesive) Material (d) content ratio) is ideally 5 to 80% by mass.

[Coupling agent (e)] Since the film-like adhesive contains the coupling agent (e), the adhesiveness and adhesiveness to the adherend are improved. In addition, since the film-like adhesive contains the coupling agent (e), its hardened product does not impair heat resistance and improves water resistance. The coupling agent (e) has a functional machine capable of reacting with an inorganic compound or an organic compound.

The coupling agent (e) is preferably a compound having a functional group that can react with a functional group of the polymer component (a), epoxy-based thermosetting resin (b), and more preferably a silane coupling agent.

The coupling agent (e) contained in the adhesive composition and the film adhesive may be only one type, or two or more types may be used. When there are two or more types, these combinations and ratios may be selected arbitrarily.

When using the coupling agent (e), the content of the coupling agent (e) in the adhesive composition and the film-like adhesive is 100% relative to the total content of the polymer component (a) and the epoxy-based thermosetting resin (b). Parts by mass, ideally 0.03 to 20 parts by mass.

[Crosslinking agent (f)] As the polymer component (a), there are used vinyl, acryloyl ((meth)acryloyl), amino, hydroxyl, carboxy ), isocyanate and other functional groups, the adhesive composition and the film-like adhesive may contain a crosslinking agent (f) that binds and crosslinks the above functional groups with other compounds. By crosslinking with the crosslinking agent (f), the initial bonding strength and cohesive strength of the film-shaped adhesive can be adjusted.

As the crosslinking agent (f), for example, an organic polyvalent isocyanate compound, an organic polyvalent imine compound, a metal chelate crosslinking agent (a crosslinking agent having a metal chelate structure), aziridine Aziridine crosslinking agent (crosslinking agent having an aziridinyl group) and the like.

When an organic polyvalent isocyanate compound is used as the crosslinking agent (f), it is desirable to use a hydroxyl group (hydroxyl)-containing polymer as the polymer component (a). When the crosslinking agent (f) has an isocyanate group (isocyanate) and the polymer component (a) has a hydroxyl group (hydroxyl), crosslinking can be easily introduced due to the reaction between the crosslinking agent (f) and the polymer component (a). Constructed into film cement.

The crosslinking agent (f) contained in the adhesive composition and the film adhesive may be one type, or two or more types, and in the case of two or more types, these combinations and ratios may be selected arbitrarily.

When using the crosslinking agent (f), the content of the crosslinking agent (f) in the adhesive composition is preferably 0.01 to 20 parts by mass relative to 100 parts by mass of the polymer component (a) content.

[energy ray curable resin (g)] Since the film adhesive contains an energy ray curable resin (g), its properties can be changed by irradiation of energy ray.

The energy ray curable resin (g) is obtained by polymerizing (curing) an energy ray curable compound. As the above-mentioned energy ray curable compound, for example, a compound having at least one polymerizable double bond in the molecule is preferably an acrylic (meth)acrylate compound having an acryl group ((meth)acryloyl).

The energy ray-curable resin (g) contained in the adhesive composition may be only one type, or two or more types may be used, and in the case of two or more types, these combinations and ratios may be selected arbitrarily.

When the energy ray-curable resin (g) is used, the content ratio of the energy ray-curable resin (g) in the cement composition to the total mass of the cement composition is preferably 1 to 95% by mass.

[Photopolymerization initiator (h)] When the adhesive composition contains the energy ray curable resin (g), it may contain a photopolymerization initiator (h) in order to efficiently carry out the polymerization reaction of the energy ray curable resin (g).

The photopolymerization initiator (h) in the adhesive composition is, for example, the same as the photopolymerization initiator contained in the adhesive compositions (I-1) to (I-3) described above.

The photopolymerization initiator (h) contained in the adhesive composition may be only one type, or two or more types may be used. When there are two or more types, these combinations and ratios may be selected arbitrarily.

When using a photopolymerization initiator (h), the content of the photopolymerization initiator (h) in the adhesive composition is preferably 0.1 to 20 parts by mass relative to 100 parts by mass of the energy ray-curable resin (g). parts by mass.

General Additives (i) The general-purpose additive (i) may be well known, and may be arbitrarily selected according to the purpose, and is not particularly limited. As desirable general-purpose additives (i), for example, plasticizers, antistatic agents, antioxidation agents, colorants (dyes, pigments), gettering agents, and the like.

The general-purpose additive (i) contained in the adhesive composition and the film adhesive may be only one type, or two or more types may be used. When there are two or more types, these combinations and ratios may be selected arbitrarily. The content of the general-purpose additive (i) contained in the adhesive composition and the film adhesive is not particularly limited, and may be appropriately selected according to the purpose.

[solvent] The cement composition preferably further contains a solvent. The adhesive composition containing the solvent has good usability. The above-mentioned solvent is not particularly limited, but as an ideal solvent, for example, carbohydrates such as toluene (toluene) and xylene (xylene); methanol (methanol), ethanol (ethanol), 2-diisopropylbarbituric acid (2-proponal ), isobutyl alcohol (2-methylpropane-1-ol) (2-methylpropane-1-ol), 1-butanol (1-butanol) and other alcohols (alcohol); ethyl acetate ( Esters such as ethyl acetate; Ketones such as acetone and methyl ethyl ketone; Ethers such as tetrahydrofuran; Dimethylformamide ), methylpyrrolidone (N-methylpyrrolidone) and other amides (amides (compounds having an amide bond)) and the like. The solvent contained in the bonding agent composition may be only one kind, or two or more kinds, and in case of two or more kinds, these combinations and ratios may be selected arbitrarily.

The solvent contained in the cement composition is desirably methyl ethyl ketone (methyl ethyl ketone) or the like because the components contained in the cement composition can be more uniformly mixed.

○Method for producing cement composition The cement composition is obtained by blending the components constituting it. The cement composition can be produced by the same method as that of the cement composition described above except that the ingredients are different.

>As a pick-up method (1) with a suitable die stick (1)-1> In the above-mentioned pick-up step, the die bonder of one embodiment suitable for use when the pick-up method (1) described above is applied has a peeling force of 0.02 to 0.2 N/25mm at the interface between the support sheet and the film-like adhesive, And the elongation at break of the test piece obtained by depositing the film-like adhesive before hardening to a total thickness of 200 μm (micrometer) was 450% or less (hereinafter, sometimes referred to as "chip bonding (1)-1"). By using the bonded die (1)-1 satisfying such elongation at break condition, when the pick-up method (1) is applied in the pick-up step, by using the above-mentioned laminate (ie, the semiconductor die group and the bonded die (1) )-1 laminate) Applying force can cut the film-like adhesive in the laminate more easily. In addition, by using the bonded wafer (1)-1 satisfying such a peeling force condition, when the pick-up method (1) is applied in the pick-up step, the semiconductor wafer with the film-like bonding agent after cutting is not accompanied by abnormality in the step, It can be easily pulled away from the support sheet, making it easier to pick up semiconductor wafers with film-like bonding agent. The film-like adhesive composite sheet disclosed in "International Publication No. 2016/140248" is mentioned as a die-attach (1)-1 which satisfies such conditions of peeling force and elongation at break.

[Elongation at break of test piece of film adhesive before hardening] The elongation at break (elongation at break under tension) of the test piece before hardening may be 450% or less, for example, 445% or less to obtain the above-mentioned effect more remarkably. On the other hand, the lower limit value of the elongation at break of the test piece before curing is not particularly limited. However, the above-mentioned elongation at break is preferably 50% or more, for example, 100% or more, in order to allow more stable use of the die-bonding (1)-1.

The above-mentioned elongation at break of the test piece before hardening can be appropriately adjusted within the range in which the above-mentioned ideal lower limit and upper limit are set in any combination. For example, in one embodiment, the elongation at break is preferably 50 to 450%, but may be 100 to 445%.

In this specification, the so-called "elongation at break is X% (in the formula, X is a positive number)" means that in the measurement method described later, when the above-mentioned test piece is stretched, the test piece is only extended by the original length in the stretching direction (in other words, without When the length of X% of the stretched length), that is, the overall length of the test piece in the stretching direction becomes [1+X/100] times the length before stretching, the test piece breaks.

In this specification, all the elongation at break of the film adhesive or the laminate obtained by laminating it, including the elongation at break of the above-mentioned test piece, is based on JIS K7161-1994 (ISO 527-1) or JIS K7127:1999 (ISO 527 -3) find out. When the measurement object (test piece) has no yield point, the tensile failure deformation is measured, and when it has a yield point, the deformation caused by tensile failure is measured, and the elongation at break is obtained using these measured values.

The elongation at break of the test piece, in other words, the elongation at break of the film adhesive, can be appropriately adjusted by adjusting the types and amounts of components contained in the film adhesive. For example, the molecular weight or content of the above-mentioned polymer component (a) contained in the film adhesive; the component structure, softening point or content of the epoxy-based thermosetting resin (b); by adjusting the filler (d ) content, etc., can adjust the elongation at break of the test piece. However, these are just examples of methods for adjusting the elongation at break of the test piece.

The above-mentioned test piece is not particularly limited as long as it is made of a film-like adhesive and has a thickness of 200 μm (micrometer). However, it is desirable to produce the above-mentioned test piece using a film-shaped bonding agent having the same thickness as the film-shaped bonding agent included in the die bonding (1)-1 used in the above-mentioned pick-up step.

The elongation at break of the above-mentioned film adhesive is greater as its thickness is thicker, and if the elongation at break of the test piece of the film adhesive with a thickness of less than 200 μm is 450% or less, the test of a film adhesive with the same composition and a thickness of 200 μm The elongation at break of the sheet is of course also 450% or less.

The above-mentioned elongation at break, for example, test piece, width 15mm, length 100mm, thickness 200μm, is fixed in two places so that the distance between the fixed places is 75mm (mm), and the tensile speed is 200mm/min (mm/min). Stretch the above-mentioned test piece between fixed places, and obtain it by measuring the elongation of the test piece when the test piece breaks.

[Peel force at the interface between the support sheet and the film adhesive] The peel force at the interface between the support sheet and the film adhesive is 0.02 to 0.2 N/25mm, preferably 0.02 to 0.15 N/25mm, more preferably 0.02 to 0.1N/25mm. Since the above-mentioned peeling force is above the above-mentioned lower limit value, in the above-mentioned pick-up step, when the semiconductor wafer is pulled away from the support sheet along with the film-like adhesive (more specifically, the film-like adhesive after cutting), the film-like The bonding agent suppresses simultaneous peeling from the support sheet not only from the object of the target semiconductor wafer, but also from the adjacent semiconductor wafer, and also from the non-target semiconductor wafer. In addition, since the above-mentioned peeling force is below the above-mentioned upper limit, when the semiconductor wafer is pulled away from the support sheet along with the film-form adhesive, the film-form adhesive provided on the target semiconductor wafer is surely peeled from the support sheet. Like this, because delamination is sure, for example, when above-mentioned laminate (for example, laminate 801 etc.) is applied force, strictly limit condition (for example, above-mentioned jack-up part of exerting force accelerates jack-up speed) etc., the condition when picking up Changes are not required, and the occurrence of semiconductor wafer cracks and the like seen when such changes are made is suppressed.

The above-mentioned peeling force, for example, the type and amount of components contained in the above-mentioned film adhesive; the material constituting the surface of the film adhesive on which the above-mentioned support sheet is provided; Surface state), etc., can be adjusted appropriately. However, these are merely examples of the method for adjusting the peeling force described above. In addition, in a film-like adhesive, when the above-mentioned elongation at break is large, the above-mentioned peeling force also becomes large, and when the above-mentioned elongation at break is small, the above-mentioned peeling force also tends to be small.

The above-mentioned surface state of the support sheet can be obtained by, for example, performing a surface treatment previously performed to improve the adhesion with other layers of the base material, that is, roughening treatment such as sandblasting treatment, solvent treatment, etc.; corona discharge treatment, electron beam irradiation treatment, etc. , Plasma treatment, ozone. UV irradiation treatment, flame treatment, chromic acid treatment, hot air treatment and other oxidation treatments; primer treatment, etc., can be adjusted.

The above-mentioned peeling force was obtained by the following method. That is, when the adhesive wafer (1)-1 with a width of 25 mm and an arbitrary length is attached to the adhesive with its film adhesive, and the support sheet is peeled off at a peeling speed of 300 mm/min from the film adhesive attached to the adhesive 180° angle is formed between the contacting surfaces of the film adhesive and the support sheet, and the force applied when the support sheet is peeled off (180° peeled off) in the longitudinal direction (the length direction of the bonded chip (1)-1) is measured (Peel force). Then, this measured value was used as the above-mentioned peeling force. The length of the bonded wafer (1)-1 provided for measurement is not particularly limited as long as it is within the range where the measurement force can be stably detected, but is ideally 200-300 mm. The above-mentioned peeling force can be measured under the conditions of a temperature of 25° C. and a relative humidity of 50%. In addition, when measuring, stick the wafer (1)-1 to the state of the adhesive, ideally let it stand for 30 minutes at a temperature of 25°C and a relative humidity of 50%, and stabilize the wafer (1)-1 first. Paste state.

The thickness of the film bonding agent may be, for example, preferably 1 to 50 μm, more preferably 3 to 25 μm, and more preferably 5 to 15 μm in the die bonding (1)-1 as described above. Since the thickness of the film-form bonding agent is more than the said lower limit, the bonding force of the film-form bonding agent with respect to an adherend (semiconductor wafer) becomes high. Since the thickness of the film-shaped adhesive is not more than the above-mentioned upper limit, the film-shaped adhesive can be cut more easily in the above-mentioned pick-up step.

>A die-bonding method suitable for the pick-up method (1) (1)-2> In the above-mentioned pick-up step, as an embodiment of the die-bonding method suitable for use when the previously described pick-up method (1) is applied, there is a substrate A curable film-like adhesive with a thickness of 1 to 50 μm is placed on the support sheet. The bonding force of the semiconductor wafer with the above-mentioned film-like adhesive before hardening is the bonding force K (N/24mm). The elongation at break of the test piece with a total thickness of 200 μm is the elongation at break L (%), and when the breaking strength of the above test piece is taken as the breaking strength Q (MPa), it also satisfies the formula (E1): Chip bonding (hereinafter, sometimes referred to as "chip bonding (1)-2"). By using the bonded chip (1)-2 satisfying the relationship of formula (E1), when the pick-up method (1) is applied in the pick-up step, the above-mentioned laminate (that is, the semiconductor chip group and the bonded chip (1) )-2 laminate) Applying force, the film-like adhesive in the laminate can be cut off more easily. Also, when the pick-up method (1) is applied in the pick-up step, the semiconductor wafer with the film-like bonding agent after cutting can be pulled away from the support sheet more easily without abnormality in the step, and the semiconductor wafer with the film-like bonding agent attached Picking up just got easier. The film adhesive composite sheet disclosed in "International Publication No. 2017/145979" is exemplified as the die bonding (1)-2 satisfying the conditions of such peeling force and elongation at break.

[Adhesive force K to semiconductor wafer of film adhesive before hardening] The bonding force K (N/24 mm) of the above-mentioned film bonding agent to the semiconductor wafer before curing was obtained by the following method. That is, a laminated sheet of a film adhesive and an adhesive tape having a width of 24 mm and an arbitrary length was produced. The laminated sheet is formed by laminating a film-like adhesive on the adhesive surface of an adhesive tape. As the adhesive tape, for example, a tape with a width of 24 mm manufactured by Nichiban Co., Ltd. (Cellotape (registered trademark) No. 405) can be used. Next, stick this laminated sheet to a semiconductor wafer with a film-like adhesive heated to 60°C. The adhesive tape, film-like adhesive, and semiconductor wafer are laminated in these thickness directions in this order to produce a laminated body. Immediately after production, place the laminated body in the standard environment specified in JIS Z0237 2009 for 30 minutes, and then remove the laminated sheet of the film bonding agent and the adhesive tape from the semiconductor wafer, so that the surface of the film bonding agent and the semiconductor wafer is in contact with each other. An angle of 180° is formed between them, and so-called 180° peeling is performed at a peeling speed of 150 mm/min. The peeling force at this time was measured, and this measured value was taken as joining force K (N/24mm). The length of the above-mentioned laminated sheet to be measured is not particularly limited as long as it is within a range in which the peeling force can be stably measured.

The joining force K is not particularly limited as long as it satisfies the relationship of the above-mentioned formula (E1), but is preferably 0.3 N/24 mm or more, and more preferably 0.4 N/24 mm or more. Also, the joining force K may be, for example, any one of 15 N/24 mm or less, 11 N/24 mm or less, and 7 N/24 mm or less.

The joining force K can be appropriately adjusted within the range in which the aforementioned ideal lower limit and upper limit are set in any combination. For example, in one embodiment, the joining force K is desirably 0.3-15N/24mm, more desirably 0.3-11N/24mm, and still more desirably 0.4-7N/24mm. In addition, in one embodiment, the bonding force K may be 0.45 N/24 mm or more and less than 10 N/24 mm, or may be 0.45 N/24 mm or more and 5.8 N/24 mm or less.

The bonding force K of the film bonding agent can be adjusted by adjusting the types and amounts of components contained in the film bonding agent, the thickness of the film bonding agent, the material constituting the surface of the film bonding agent on which the above-mentioned support sheet is placed, and the state of the surface ( Surface state), etc., can be adjusted appropriately. For example, the bonding force K can be adjusted by adjusting the type or amount of the above-mentioned coupling agent (e) contained in the film bonding agent. Also, for example, the above-mentioned surface state of the support sheet can be adjusted by the same method as in the above-described bonding of the wafer (1)-1. However, these are merely examples of the method of adjusting the joining force K.

[Elongation at break L of test piece of film cement before hardening] The above-mentioned elongation at break L in the die-bonding (1)-2 is the same as the elongation at break of the test piece in the above-mentioned die-bonding (1)-1.

The elongation at break L (%) is not particularly limited as long as it satisfies the relationship of the above formula (E1). For example, in one embodiment, the elongation at break L is preferably 1200% or less, more preferably 30 to 1200%, still more preferably 40 to 1100%, and particularly preferably 45 to 1050%. Since the elongation at break L is not more than the above-mentioned upper limit, the film-shaped adhesive can be cut more easily in the above-mentioned pick-up step. Also, in one embodiment, the elongation at break L is preferably 900% or less, more preferably 700% or less, particularly preferably 500% or less, for example, 30 to 500%, 40 to 500%, 45 to 500%, and 50% ~440% etc. Any one is also possible. Since the breaking elongation L is below the above-mentioned upper limit, the film-shaped adhesive can be cut more easily by various means in the above-mentioned pick-up step. That is, as a method of applying force to the above-mentioned laminate, not only the method of the most general raised portion made of protrusions described above, but also the method of moving the raised portion made of slide rails can also be used to cut the film-shaped joint more easily. agent.

[Test piece breaking strength Q of film cement before hardening] The breaking strength Q (MPa), when measuring the breaking elongation L (%), the tensile stress when the test piece is broken (destroyed), that is, the tensile failure stress, can be measured simultaneously with the breaking elongation L.

The breaking strength Q (MPa) is not particularly limited as long as it satisfies the relationship of the above formula (E1). For example, in one embodiment, the breaking strength Q is preferably 0.4 to 17 MPa, more preferably 0.5 to 15 MPa, and particularly preferably 0.6 to 13 MPa. Also, in one embodiment, the breaking strength Q may be 0.8 to 11 MPa, or 2.5 to 11 MPa.

[K/(L×Q)] The [K/(L×Q)] value is at least 0.0005, preferably at least 0.0006, more preferably at least 0.0007. On the other hand, the upper limit of [K/(L×Q)] is not particularly limited. The value of [K/(L×Q)] may be, for example, any of 0.0170 or less, 0.0140 or less, and 0.0115 or less, and these are examples of K/(L×Q) values.

The value of K/(L×Q) can be appropriately adjusted within the range in which the above-mentioned ideal lower limit and upper limit are set in any combination. For example, in one embodiment, the value of K/(L×Q) may be any one of 0.0005-0.0170, 0.0006-0.0140 and 0.0007-0.0115. Also, in one embodiment, the value of K/(L×Q) may be 0.0008 to 0.0125, and any of 0.0008 to 0.0105.

The breaking elongation L and breaking strength Q of the test piece, in other words, the breaking elongation and breaking strength of the film adhesive, can be appropriately adjusted by adjusting the types and amounts of components contained in the film adhesive. For example, the molecular weight or content of the above-mentioned polymer component (a) contained in the film adhesive; the component structure, softening point or content of the epoxy-based thermosetting resin (b); by adjusting the filler (d ) content, etc., can adjust the above-mentioned elongation at break L and strength at break Q. However, these are merely examples of methods for adjusting the elongation at break L and the strength at break Q.

The thickness of the film bonding agent is, as described above, 1 to 50 μm in the die bonding (1)-2, for example, preferably 3 to 25 μm (micrometer), more preferably 5 to 15 μm. Since the thickness of the film-form bonding agent is more than the said lower limit, the bonding force of the film-form bonding agent with respect to an adherend (semiconductor wafer) becomes high. Since the thickness of the film-shaped adhesive is not more than the above-mentioned upper limit, the film-shaped adhesive can be cut more easily in the above-mentioned pick-up step. [Example]

Hereinafter, the present invention will be described in more detail based on specific examples. However, the present invention is not limited in any way by the Examples shown below.

>>Manufacturing of semiconductor wafers, evaluation of semiconductor wafers>> [Example 1] According to the method (first embodiment) described with reference to FIGS. 3 to 6, a semiconductor wafer is manufactured and picked up. Specifically, it is as follows.

[1st modification step, 2nd modification step] Backglide tape (adhesive tape) ("Adwill E-3100TN" manufactured by Lintec Corporation) was pasted on the circuit formation surface of an 8-inch semiconductor wafer (thickness 725 μm).

Next, use a Stealth dicing (registered trademark) laser saw ("DFL7361" manufactured by Disco Corporation) in the first area inside the semiconductor wafer and at the peripheral edge of the semiconductor wafer. In the nearby place, from the back side of the semiconductor wafer, the laser light is irradiated with an output of 1W (watt), and the first modified layer is formed at a position 85 μm deep from the circuit formation surface of the semiconductor wafer. Then, the semiconductor wafer In a direction parallel to the circuit formation surface, the formation of the partial first modified layer is repeated while shifting the irradiation position of the laser light, thereby forming a linear first modified layer (first modification step) In the thickness direction of the semiconductor wafer, the expanded width of the first modified layer (in other words, the height of the first modified layer) is about 30 μm.

Then, without changing the light source, from the back side of the semiconductor wafer, the second region inside the semiconductor wafer is irradiated with laser light at an output of 1W (Watt), at a depth of 85 μm from the back surface of the semiconductor wafer and at the second area. The position directly above the 1 modified layer forms the 2nd modified layer. At this time, the second modified layer is formed on the back side of the first modified layer in the semiconductor wafer. Then, similarly to the formation of the first modified layer, in a direction parallel to the circuit formation surface of the semiconductor wafer, while shifting the irradiation position of the laser light, the formation of the partial second modified layer is repeated, whereby a 1 A second modification layer in the form of a line (second modification step). In the thickness direction of the semiconductor wafer, the expanded width of the second modified layer (in other words, the height of the second modified layer) was about 30 μm. In this example, the average value of _Δ12 is 555 μm.

In this way, after the formation of each of the first and second modified layers in parallel to each other, the formation of the first and second modified layers in the linear form was repeated several times. At this time, the newly formed linear first modified layer and the second modified layer are adjusted to be parallel to the already formed linear first modified layer and the second modified layer. Also, using the same method as in the past, a plurality of linear first modified layers intersecting such a plurality of linear first modified layers at an intersection angle of 90° and a plurality of linear second modified layers are newly formed. A multi-line second modification layer in which layers intersect at a crossing angle of 90° (above, the first modification step and the second modification step are repeated). In this way, by repeating the formation of the first modified layer and the second modified layer over the entire area of the semiconductor wafer, the first modified layer is formed in a mesh shape at a position 85 μm deep from the circuit formation surface of the semiconductor wafer. At a depth of 85 μm from the back surface of the semiconductor wafer, a second modified layer was formed in a mesh shape. As described above, a semiconductor wafer on which the first modified layer and the second modified layer were formed was obtained. A total of five semiconductor wafers on which such a first modified layer and a second modified layer were formed were produced.

[Confirmation of bowing suppression effect of semiconductor wafer] For each of the five semiconductor wafers obtained above, the magnitude of warpage was measured. More specifically, it is as follows. The circuit-forming surface of the semiconductor wafer is brought into contact with a flat surface, and the semiconductor wafer is mounted on the above-mentioned flat surface. Next, visually observe the semiconductor wafer in this state from the side, measure the distance between the outer periphery of the semiconductor wafer and the above-mentioned plane directly below, and the maximum value is the curvature of the semiconductor wafer. By this method, warpage magnitudes were obtained for all five semiconductor wafers obtained above, and the maximum value among them was adopted as the warpage magnitude of the final semiconductor wafer. As a result, the curvature of the semiconductor wafer in this example was less than 0.5 mm (millimeter) as shown in Table 1. That is, warping of the semiconductor wafer on which the first modified layer and the second modified layer were formed in the present example was significantly suppressed. Also, for these five semiconductor wafers, contrary to the above, the back surface was brought into contact with a flat surface, the semiconductor wafer was mounted on the above-mentioned flat surface, and the semiconductor wafer in this state was visually observed from the side by the same method as above. As a result, no gap is allowed between the outer periphery of the semiconductor wafer and the above-mentioned plane directly below it.

[Evaluation of transportability of semiconductor wafers] Using a grinder ("DFG8760" manufactured by Disco Co., Ltd.), it was tried to transfer the five semiconductor wafers obtained above one at a time by suctioning the transfer arm. Then, the transportability of the semiconductor was evaluated according to the following evaluation criteria. As a result, in this example, the evaluation result was "A". The evaluation results are shown in Table 1 together with the number of transportable semiconductor wafers. The description of "5/5" in the evaluation result column of this item in Table 1 means that 5 semiconductor wafers were evaluated, which means that all 5 semiconductor wafers could be transported without abnormal adsorption. The contents described in this column are the same for the following examples and comparative examples. (evaluation criteria) A: All five semiconductor wafers could be transported without abnormal adsorption. B: 1 to 4 semiconductor wafers could be transferred without abnormal adsorption, but the remaining semiconductor wafers could not be transferred due to abnormal adsorption. C: All five semiconductor wafers could not be transported due to abnormal adsorption.

[Split step] Of the five semiconductor wafers whose warpage suppression effect and transportability were evaluated, one was used, and the division procedure shown below was performed. That is, the back surface of the semiconductor wafer after the completion of the first reforming step and the second reforming step was ground using a grinder ("DFG8760" manufactured by Disco Corporation). At this time, Z1-axis grinding is performed with a grinding material with a particle size of 360, Z2-axis grinding is performed with a grinding material with a particle size of 6000, and the above-mentioned back surface is ground by dry polishing for Z3-axis grinding. Then, until the thickness of the semiconductor wafer becomes 40 μm, the above-mentioned back surface is polished to completely disappear the first modified layer and the second modified layer. In the portion of the second modified layer, the semiconductor wafer is divided. According to the above, there was no modified layer inside, and a group of semiconductor wafers was obtained in which a large number of semiconductor wafers with a size of 2 mm x 2 mm and a thickness of 40 μm were arranged on the Backglide tape.

[Stacking steps] Next, using a Multi-wafer mounter (manufactured by Lintec "RAD-2510 F/12"), the rear surfaces (polished surfaces) of all the semiconductor wafers in the semiconductor wafer group obtained above were ground and pasted. 1 sticky chip ("Adwill LD01D-7 P8AK" manufactured by Lintec). The die-bond includes a substrate (made of polyolefin, thickness 80 μm) and a film-like adhesive (thickness 7 μm) formed on the substrate, and the support sheet is equivalent to a die-bond formed only with the base material. Here, the above-mentioned film-like bonding agent in this wafer bond is adhered to the back surface of the semiconductor wafer. Thereby, a laminate of the above-mentioned semiconductor wafer group and the above-mentioned bonded wafers is produced.

[Pick-up procedure, evaluation of pick-up suitability of semiconductor wafer] Next, Backglide tape (adhesive tape) is removed from the said circuit formation surface of a semiconductor wafer. Second, use pick up. Die bonding device ("BESTEM02" manufactured by Canon Machinery Co., Ltd.), after fixing the above-mentioned laminate at room temperature, a height difference of 4mm is newly generated between the above-mentioned laminate and the ring frame (Ring frame) on which it is fixed. . Then, in this state, for the above-mentioned laminate, by pushing up from the base material side, the above-mentioned film-like bonding agent in the above-mentioned laminate is cut along the outer periphery of the above-mentioned semiconductor wafer, and an attempt is made to prepare the back surface after cutting. The semiconductor wafer of the film-like bonding agent is pulled apart from the above-mentioned substrate to pick up. At this time, one protrusion (pin) was used as the jacking portion, and the jacking height was 0.35 mm, the jacking speed was 20 mm/s, and the jacking holding time was 1 second, to jack up the above laminate.

This step is continuously performed 27 times on the above-mentioned one semiconductor wafer. Then, the number of times that the target semiconductor wafer with a size of 2 mm×2 mm cannot be picked up as a semiconductor wafer with a film-like bonding agent (that is, the number of times of poor pick-up) was confirmed. Based on this number, the pick-up suitability of the semiconductor wafer was evaluated according to the following evaluation criteria. As a result, as shown in Table 1, in this example, the evaluation result was "A". (evaluation criteria) A: The number of bad pick-ups is 0. B: The number of times of picking up bad ones is 1 to 3 times. C: The number of times of picking up a defect is 4 or more.

[Example 2] According to the method (second embodiment) described with reference to FIGS. 7 to 8, a semiconductor wafer is manufactured and picked up. Specifically, it is as follows.

[First reforming step, second reforming step] Instead of forming the first reforming layer at a position 85 μm deep from the circuit forming surface of the semiconductor wafer, a position 75 μm deep and a position 135 μm deep from the circuit forming surface of the semiconductor wafer Except for forming the first modified layer, two linear first modified layers were formed by the same method as in the case of Example 1 (first modifying step). In this embodiment, the average value of _Δ11 is 30 μm.

Also, instead of forming the second modified layer at a depth of 85 μm from the back surface of the semiconductor wafer and directly above the first modified layer, a position 75 μm deep from the back surface of the semiconductor wafer and directly above the first modified layer and a distance from the semiconductor wafer In addition to forming the second modified layer at a depth of 135 μm on the back surface of the wafer and directly above the first modified layer, two linear second modified layers ( 2nd modification step). At this time, the second modified layer is formed on the back side of the first modified layer in the semiconductor wafer. In this embodiment, the average value of _Δ22 is 30 μm, and the average value of _Δ12 is 455 μm.

In this way, after forming two parallel first modified layers and two second modified layers each, the formation of the first modified layer and the second modified layer was repeated several times. At this time, the newly formed linear first modified layer and the second modified layer are adjusted to be parallel to the already formed linear first modified layer and the second modified layer. In addition, by the same method as before, the multi-linear first modified layer intersecting the multi-linear first modified layer at an intersection angle of 90° and the multi-linear second modified layer were newly formed. The multi-line second modifying layer intersected at a crossing angle of 90° (repetition of the first modifying step and the second modifying step above). In this way, by repeatedly forming the first modified layer and the second modified layer throughout the entire area of the semiconductor wafer, the first modified layer is formed in a mesh shape at the position at a depth of 75 μm and at a position at a depth of 135 μm from the circuit formation surface of the semiconductor wafer, respectively. In the modified layer, the second modified layer was formed in a mesh shape at the position at a depth of 75 μm and at a position at a depth of 135 μm from the back surface of the semiconductor wafer. As described above, a semiconductor wafer on which the first modified layer and the second modified layer were formed was obtained. A total of five semiconductor wafers on which such a first modified layer and a second modified layer were formed were produced.

[Confirmation of bowing suppression effect of semiconductor wafer] Using the five semiconductor wafers obtained above, the warpage of the semiconductor wafers was confirmed by the same method as in Example 1. As shown in Table 1, it was less than 0.5 mm. That is, warping of the semiconductor wafer on which the first modified layer and the second modified layer were formed in the present example was significantly suppressed. Also, in this embodiment, the back surface of the semiconductor wafer is brought into contact with the flat surface, and as a result of mounting the semiconductor wafer on the above-mentioned flat surface, no gap is allowed between the outer periphery of the semiconductor wafer and the above-mentioned flat surface directly below.

[Evaluation of transportability of semiconductor wafers] Regarding the five semiconductor wafers obtained above, the transferability was evaluated by the same method as in the case of Example 1. As a result, in this example, the evaluation result was "A". The evaluation results are shown in Table 1 together with the number of semiconductor wafers that can be transported.

[division step, layering step] In the same manner as in Example 1, except for using one of the five semiconductor wafers that were evaluated for the effect of suppressing warpage and transportability, an internally unmodified layer was produced, with a size of 2 mm x 2 mm and a thickness of 40 μm. A plurality of semiconductor wafers are arranged on the backglide tape (adhesive tape) of the semiconductor wafer group (dividing step), and a laminate of this semiconductor wafer group and the above-mentioned adhesive wafer is produced (lamination step).

[Evaluation of pick-up procedure, semiconductor wafer pick-up suitability] Except using the laminate obtained above, by the same method as in Example 1, an attempt was made to pick up a target semiconductor wafer with a size of 2mm x 2mm at the same time as the film bonding agent (pickup step), and the semiconductor wafer was evaluated. Pickup suitability. As a result, as shown in Table 1, in this example, the evaluation result was "A".

[Example 3] According to the method (third embodiment) described with reference to FIGS. 9 to 10, a semiconductor wafer is manufactured and picked up. Specifically, it is as follows.

[First modifying step, second modifying step] A position at a depth of 85 μm from the circuit formation surface of the semiconductor wafer, instead of forming the first modification layer, a position at a depth of 75 μm from the circuit formation surface of the semiconductor wafer and a position at a depth of 135 μm Except for the positional formation of the first modified layer, two linear first modified layers were formed by the same method as in Example 1 (first modified step). In this embodiment, the average value of _Δ11 is 30 μm.

Also, instead of forming the second modified layer at a depth of 85 μm from the back surface of the semiconductor wafer and directly above the first modified layer, a second modified layer is formed at a depth of 75 μm from the back surface of the semiconductor wafer and directly above the first modified layer. Except for the modified layer, a linear second modified layer was formed by the same method as in Example 1 (second modified step). At this time, the second modified layer is formed on the back side of the first modified layer in the semiconductor wafer. In this example, the average value of _Δ12 is 515 μm.

In this way, two parallel first modified layers are formed, one second modified layer is formed, and the formation of the first modified layer and the second modified layer is repeated several times. At this time, the newly formed linear first modified layer and the second modified layer are adjusted to be parallel to the already formed linear first modified layer and the second modified layer. Also, by the same method as before, the multi-linear first modified layer intersecting the multi-linear first modified layer at an intersection angle of 90° and the multi-linear second modified layer are newly formed. The multi-line second modifying layer intersecting at a crossing angle of 90° (the above, the first modifying step and the second modifying step are repeated). However, so far, in the direction parallel to the circuit formation surface of the semiconductor wafer, the distance between adjacent linear first modified layers and the distance between adjacent linear second modified layers are all the same as in Example 1. 1/2 of the time. In this way, by repeating the formation of the first modified layer and the second modified layer throughout the entire area of the semiconductor wafer, the positions at a depth of 75 μm and at a position at a depth of 135 μm from the circuit formation surface of the semiconductor wafer are respectively formed in a mesh shape. As for the modified layer, a second modified layer was formed in a mesh shape at a position at a depth of 75 μm from the back surface of the semiconductor wafer. As described above, a semiconductor wafer on which the first modified layer and the second modified layer were formed was obtained. A total of 5 such semiconductor wafers on which the first modified layer and the second modified layer were formed were fabricated.

[Confirmation of the effect of suppressing bowing of semiconductor wafers] Using the five semiconductor wafers obtained above, the warpage of the semiconductor wafers was confirmed by the same method as in Example 1. As shown in Table 1, it was less than 0.5 mm. That is, warping of the semiconductor wafer on which the first modified layer and the second modified layer were formed in the present example was significantly suppressed. Also, in this embodiment, the back surface of the semiconductor wafer is brought into contact with the plane, and as a result of mounting the semiconductor wafer on the plane, no gap is allowed between the outer periphery of the semiconductor wafer and the front plane directly below it.

[Evaluation of transportability of semiconductor wafers] Regarding the five semiconductor wafers obtained above, the transferability was evaluated by the same method as in the case of Example 1. As a result, in this example, the evaluation result was "A". The evaluation results are shown in Table 1 together with the number of semiconductor wafers that can be transported.

[division step, layering step] In the same manner as in Example 1, except for using one of the five semiconductor wafers that were evaluated for the effect of suppressing warpage and the transferability, an internally unmodified layer was produced, with a size of 1 mm x 1 mm and a thickness of 40 μm. A plurality of semiconductor wafers are arranged on the backglide tape (adhesive tape) of the semiconductor wafer group (dividing step), and a laminate of this semiconductor wafer group and the above-mentioned adhesive wafer is produced (lamination step).

[Evaluation of pick-up procedure, semiconductor wafer pick-up suitability] Except for using the laminate obtained above, by the same method as in Example 1, an attempt was made to pick up a target semiconductor wafer with a size of 1 mm x 1 mm at the same time as the film bonding agent (pick-up step), and the semiconductor wafer was evaluated. Pickup suitability. As a result, as shown in Table 1, in this example, the evaluation result was "A".

[Example 4] According to the method (second embodiment) described with reference to FIGS. 7 to 8, a semiconductor wafer is manufactured and picked up. Specifically, it is as follows.

[First modification step, second modification step] In the direction parallel to the circuit formation surface of the semiconductor wafer, the distance between adjacent linear first modification layers and the distance between adjacent linear second modification layers The distances were all other than 1/2, and by the same method as in Example 2, a semiconductor wafer on which the first modified layer and the second modified layer had been formed was obtained. In this embodiment, the average value of _Δ11 and _Δ22 is 30 μm, and the average value of _Δ12 is 455 μm. A total of 5 such semiconductor wafers on which the first modified layer and the second modified layer were formed were produced.

[Confirmation of bowing suppression effect of semiconductor wafer] Using the five semiconductor wafers obtained above, the warpage of the semiconductor wafers was confirmed by the same method as in Example 1. As shown in Table 1, it was less than 0.5 mm. That is, warping of the semiconductor wafer on which the first modified layer and the second modified layer were formed in the present example was significantly suppressed. Also, in this embodiment, the back surface of the semiconductor wafer is brought into contact with the flat surface, and as a result of mounting the semiconductor wafer on the above-mentioned flat surface, no gap is allowed between the outer periphery of the semiconductor wafer and the above-mentioned flat surface directly below.

[Evaluation of transportability of semiconductor wafers] Regarding the five semiconductor wafers obtained above, the transferability was evaluated by the same method as in the case of Example 1. As a result, in this example, the evaluation result was "A". The evaluation results are shown in Table 1 together with the number of semiconductor wafers that can be transported.

[division step, layering step] In the same manner as in Example 1, except for using one of the five semiconductor wafers that were evaluated for the effect of suppressing warpage and the transferability, an internally unmodified layer was produced, with a size of 1 mm x 1 mm and a thickness of 40 μm. A plurality of semiconductor wafers are arranged on the backglide tape (adhesive tape) of the semiconductor wafer group (dividing step), and a laminate of this semiconductor wafer group and the above-mentioned adhesive wafer is produced (lamination step).

[Evaluation of pick-up procedure, semiconductor wafer pick-up suitability] Except for using the laminate obtained above, by the same method as in Example 1, an attempt was made to pick up a target semiconductor wafer with a size of 1 mm x 1 mm at the same time as the film bonding agent (pick-up step), and the semiconductor wafer was evaluated. Pickup suitability. As a result, as shown in Table 1, in this example, the evaluation result was "A".

[Example 5] According to the method (second embodiment) described with reference to FIGS. 7 to 8, a semiconductor wafer is manufactured. Specifically, it is as follows.

[First modification step, second modification step] In the direction parallel to the circuit formation surface of the semiconductor wafer, the distance between adjacent linear first modification layers and the distance between adjacent linear second modification layers The distances were all other than 1/4, and by the same method as in Example 2, a semiconductor wafer on which the first modified layer and the second modified layer had been formed was obtained. In this embodiment, the average value of _Δ11 and _Δ22 is 30 μm, and the average value of _Δ12 is 455 μm. A total of 5 such semiconductor wafers on which the first modified layer and the second modified layer were formed were fabricated.

[Confirmation of bowing suppression effect of semiconductor wafer] Using the five semiconductor wafers obtained above, the curvature of the semiconductor wafer was confirmed by the same method as in Example 1. As shown in Table 1, it was 1 mm. That is, warping of the semiconductor wafer on which the first modified layer and the second modified layer were formed in this embodiment was sufficiently suppressed. Also, in this embodiment, the back surface of the semiconductor wafer is brought into contact with the flat surface, and as a result of mounting the semiconductor wafer on the above-mentioned flat surface, no gap is allowed between the outer periphery of the semiconductor wafer and the above-mentioned flat surface directly below.

[Evaluation of transportability of semiconductor wafers] Regarding the five semiconductor wafers obtained above, the transferability was evaluated by the same method as in the case of Example 1. As a result, in this example, the evaluation result was "B". The evaluation results are shown in Table 1 together with the number of semiconductor wafers that can be transported. The description of "2/5" in the evaluation result column of this item in Table 1 means that 5 semiconductor wafers were evaluated, 2 semiconductor wafers could be transported without adsorption abnormality, and 3 semiconductor wafers could not be transported due to adsorption abnormality.

[division step, layering step] Except for using one of the five semiconductor wafers that can be transported out of the five semiconductor wafers that have been evaluated for the effect of suppressing warpage and the transportability, the same method as in Example 1 was used to fabricate an internally unmodified layer with a size of 0.5mm× 0.5mm, 40μm thick semiconductor wafer group in the state of arrangement on Backglide tape (tape) (dividing step), and make a laminate of this semiconductor wafer group and the above-mentioned bonded wafer (lamination step).

[Evaluation of pick-up procedure, semiconductor wafer pick-up suitability] Except for using the laminate obtained above, by the same method as in Example 1, an attempt was made to pick up a target semiconductor wafer with a size of 0.5mm×0.5mm at the same time as the film bonding agent (pickup step), and the evaluation Pick-up suitability of semiconductor wafers. As a result, as shown in Table 1, in this example, the evaluation result was "A".

[Example 6] According to the method (second embodiment) described with reference to FIGS. 7 to 8, a semiconductor wafer is manufactured. Specifically, it is as follows.

[First modification step, second modification step] In the direction parallel to the circuit formation surface of the semiconductor wafer, the distance between adjacent linear first modification layers and the distance between adjacent linear second modification layers The distances were all other than 3/8, and by the same method as in Example 2, a semiconductor wafer on which the first modified layer and the second modified layer had been formed was obtained. In this embodiment, the average value of _Δ11 and _Δ22 is 30 μm, and the average value of _Δ12 is 455 μm. A total of 5 such semiconductor wafers on which the first modified layer and the second modified layer were formed were fabricated.

[Confirmation of bowing suppression effect of semiconductor wafer] Using the five semiconductor wafers obtained above, the warpage of the semiconductor wafers was confirmed by the same method as in Example 1. As shown in Table 1, it was less than 0.5 mm. That is, warping of the semiconductor wafer on which the first modified layer and the second modified layer were formed in the present example was significantly suppressed. Also, in this embodiment, the back surface of the semiconductor wafer is brought into contact with the flat surface, and as a result of mounting the semiconductor wafer on the above-mentioned flat surface, no gap is allowed between the outer periphery of the semiconductor wafer and the above-mentioned flat surface directly below.

[Evaluation of transportability of semiconductor wafers] Regarding the five semiconductor wafers obtained above, the transferability was evaluated by the same method as in the case of Example 1. As a result, in this example, the evaluation result was "A". The evaluation results are shown in Table 1 together with the number of semiconductor wafers that can be transported.

[division step, layering step] In the same manner as in Example 1, except for using one of the five semiconductor wafers that had been evaluated for the effect of suppressing warpage and transportability, a size of 0.75 mm x 0.75 mm was produced without an internal modified layer. A semiconductor wafer group in which a large number of semiconductor wafers with a thickness of 40 μm are arranged on Backglide tape (separation step), and a laminate of this semiconductor wafer group and the above-mentioned bonded wafers is produced (lamination step).

[Evaluation of pick-up procedure, semiconductor wafer pick-up suitability] Except for using the laminate obtained above, by the same method as in Example 1, an attempt was made to pick up a target semiconductor wafer with a size of 0.75mm×0.75mm at the same time as the film bonding agent (pickup step), and the evaluation Pick-up suitability of semiconductor wafers. As a result, as shown in Table 1, in this example, the evaluation result was "A".

[Comparative example 1] [1st reforming step] In the direction parallel to the circuit formation surface of the semiconductor wafer, the distance between adjacent linear first modifying layers is 1/2, and the second modifying layer is not formed (in other words, the second modifying step is not performed) , using the same method as in Example 1, a semiconductor wafer on which the first modified layer was formed was obtained. That is, in this comparative example, the first modified layer was formed in a mesh shape at a position at a depth of 85 μm from the circuit formation surface of the semiconductor wafer, and no modified layer was formed in the rest. A total of five such semiconductor wafers on which the first modified layer was formed were fabricated.

[Confirmation of bowing suppression effect of semiconductor wafer] Using the five semiconductor wafers obtained above, the curvature of the semiconductor wafer was confirmed by the same method as in Example 1. As shown in Table 1, it was 1.5 mm. That is, warping of the semiconductor wafer on which the first modified layer was formed in this comparative example was not suppressed.

[Evaluation of transportability of semiconductor wafers] Regarding the five semiconductor wafers obtained above, the transferability was evaluated by the same method as in the case of Example 1. As a result, in this comparative example, the evaluation result was "C". The evaluation results are shown in Table 1 together with the number of semiconductor wafers that can be transported.

[Segmentation step, lamination step, pick-up step, evaluation of pick-up suitability of semiconductor wafer] In this comparative example, manufacture of a semiconductor wafer with a size of 1 mm×1 mm was attempted, and as shown in Table 1, all five semiconductor wafers could not be transported due to abnormal adsorption. Therefore, in this comparative example, the subsequent dividing step, lamination step, and pick-up step could not be performed, a semiconductor wafer could not be manufactured, and the pick-up suitability of the semiconductor wafer could not be evaluated.

[Comparative example 2] [1st reforming step] A semiconductor wafer on which the first modified layer was formed was obtained by the same method as in Example 3 except that the second modified layer was not formed (in other words, the second modified step was not performed). That is, in this comparative example, the first modifying layer was formed in a mesh shape at the positions at a depth of 75 μm and at a position at a depth of 135 μm from the circuit formation surface of the semiconductor wafer, and no modifying layer was formed at all the rest. A total of five such semiconductor wafers on which the first modified layer was formed were produced.

[Confirmation of bowing suppression effect of semiconductor wafer] Using the five semiconductor wafers obtained above, the curvature of the semiconductor wafer was confirmed by the same method as in Example 1. As shown in Table 1, it was 1.5 mm. That is, warping of the semiconductor wafer on which the first modified layer was formed in this comparative example was not suppressed.

[Evaluation of transportability of semiconductor wafers] Regarding the five semiconductor wafers obtained above, the transferability was evaluated by the same method as in the case of Example 1. As a result, in this comparative example, the evaluation result was "C". The evaluation results are shown in Table 1 together with the number of transportable semiconductor wafers.

[Segmentation step, lamination step, pick-up step, evaluation of pick-up suitability of semiconductor wafer] In this comparative example, manufacture of a semiconductor wafer with a size of 1 mm×1 mm was attempted, and as shown in Table 1, all five semiconductor wafers could not be transported due to abnormal adsorption. Therefore, in this comparative example, the subsequent dividing step, lamination step, and pick-up step could not be performed, a semiconductor wafer could not be manufactured, and the pick-up suitability of the semiconductor wafer could not be evaluated.

[Comparative example 3] [1st reforming step] In the direction parallel to the circuit formation surface of the semiconductor wafer, the distance between adjacent linear first modifying layers is 3/8, and the second modifying layer is not formed (in other words, the second modifying step is not performed) , using the same method as in Example 1, a semiconductor wafer on which the first modified layer was formed was obtained. That is, in this comparative example, the first modified layer was formed in a mesh shape at a position at a depth of 85 μm from the circuit formation surface of the semiconductor wafer, and no modified layer was formed in the rest. A total of five such semiconductor wafers on which the first modified layer was formed were fabricated.

[Confirmation of bowing suppression effect of semiconductor wafer] Using the five semiconductor wafers obtained above, the curvature of the semiconductor wafer was confirmed by the same method as in Example 1. As shown in Table 1, it was 3 mm. That is, warping of the semiconductor wafer on which the first modified layer was formed in this comparative example was not suppressed.

[Evaluation of transportability of semiconductor wafers] Regarding the five semiconductor wafers obtained above, the transferability was evaluated by the same method as in the case of Example 1. As a result, in this comparative example, the evaluation result was "C". The evaluation results are shown in Table 1 together with the number of transportable semiconductor wafers.

[Segmentation step, lamination step, pick-up step, evaluation of pick-up suitability of semiconductor wafer] In this comparative example, manufacture of semiconductor wafers with a size of 0.75 mm×0.75 mm was attempted, and as shown in Table 1, five semiconductor wafers could not be transported due to abnormal adsorption. Therefore, in this comparative example, the subsequent dividing step, lamination step, and pick-up step could not be performed, a semiconductor wafer could not be manufactured, and the pick-up suitability of the semiconductor wafer could not be evaluated.

[Table 1] ^*1 Thickness of the semiconductor wafer when the 1st modification step and the 2nd modification step are performed. ^*2 The size of the actually obtained semiconductor wafer when the dividing step can be performed, and the expected size of the semiconductor wafer when the dividing step cannot be performed.

As is clear from the above results, in Examples 1 to 6, the semiconductor wafer on which the first modified layer and the second modified layer were formed had a bending dimension of 1 mm or less, and the bending of the semiconductor wafer was suppressed. As a result, in these Examples, the transferability of the above-mentioned semiconductor wafer was good. In particular, in Examples 1 to 4 and 6, the bending dimension of the above-mentioned semiconductor wafer was less than 0.5 mm, the effect of suppressing the bending was remarkably high, and the transportability of the semiconductor wafer was particularly excellent. Because, in Examples 1 to 4 and 6, the shortest side of the semiconductor wafer is longer than 0.75 mm (0.75 to 2 mm), and the thickness of the first modified layer and the second modified semiconductor wafer is 0.725 mm. The length of the shortest side of the wafer is a value larger than the aforementioned thickness. In Example 5, the length of the shortest side of the semiconductor wafer is 0.5 mm, the thickness of the semiconductor wafer on which the first modification layer and the second modification have been formed is 0.725 mm, and the length of the shortest side of the semiconductor wafer is smaller than the above-mentioned thickness. value. Due to this difference, there is a difference in the degree of effect from the case of other embodiments.

Reflecting the effect of suppressing warpage, in Examples 1 to 6, the semiconductor wafers with the formed first modified layer and the second modified layer can be bonded and transported to a dedicated table, and since they can be firmly fixed, they can be ground. On the back, the segmentation step can be performed well. Also, in these Examples, the subsequent lamination step and pick-up step can be performed well, and the suitability for semiconductor wafers is excellent.

In this way, in Examples 1 to 6, through the formation of the modified layer inside the semiconductor wafer, even when a small-sized semiconductor wafer is produced, the occurrence of bowing of the semiconductor wafer can be suppressed. As a result, the steps from picking up to picking up the semiconductor wafer with the film-like bonding agent can be performed without any problem.

On the other hand, in Comparative Examples 1 to 3, since the conventional method of not forming the second modified layer, the bending dimension of the semiconductor wafer on which the modified layer was formed (in other words, only the first modified layer) was 1.5 mm or more , did not suppress the bending of the above-mentioned semiconductor wafer. As a result, in these comparative examples, the above-mentioned semiconductor wafer could not be transported, and the subsequent dividing step, stacking step, and pick-up step could not be performed.

Thus, in Comparative Examples 1 to 3, when a small-sized semiconductor wafer was produced through the formation of the reforming layer inside the semiconductor wafer, the occurrence of bowing of the semiconductor wafer could not be suppressed. As a result, a semiconductor wafer with a film-like bonding agent cannot be manufactured. [industrial availability]

The present invention can be utilized in the manufacture of semiconductor wafers and semiconductor devices.

6: grinding means; 7: protective film; 8: semiconductor wafer; 8a: circuit formation surface of semiconductor wafer; 8b: backside of semiconductor wafer; 8': semiconductor wafer; 8a': circuit formation surface; 8A': Semiconductor wafer group; 9: semiconductor wafer; 9a: circuit formation surface; 9b: back surface; 10: support sheet; 11: base material; 12: adhesive layer; 13: film bonding agent; 13': film after cutting 51: protrusion; 52: vacuum chuck; 80': the outer periphery of the semiconductor wafer; 80a: the first area inside the semiconductor wafer; 80b: the second area inside the semiconductor wafer; 81: the first modification layer; 82: the second modified layer; 83: the first modified layer; 84: the second modified layer; 89: cracks; 91: modified layer; 101: bonded chip; 801: semiconductor chip group and bonded chip 811: the first modified layer; 812: the first modified layer; 821: the second modified layer; 822: the second modified layer; 831: the first modified layer; 832: the first modified layer layer; 841: the second modified layer; 842: the second modified layer; D ₁ : the depth of the 1st region 80a; D ₂ : the depth of the 2nd region 80b; P ₁ : the protruding direction; P ₂ : the pulling direction ; R ₁ : laser light; R ₂ : laser light; S ₈ ': the length of one side of the semiconductor wafer (the length of the shortest side of the semiconductor wafer); and T ₈ : the semiconductor when implementing the first modification step and the second modification step wafer thickness.

[Fig. 1] is a perspective view schematically showing a conventional semiconductor wafer on which a modified layer is formed; [Fig. 2] is an enlarged cross-sectional view schematically showing a conventional semiconductor wafer in a bent state due to the formation of a modified layer; [Fig. 3] is an enlarged cross-sectional view for schematically illustrating the first modifying step and the second modifying step in the manufacturing method of the semiconductor wafer according to the first embodiment of the present invention; [FIG. 4] is an enlarged cross-sectional view for schematically explaining the dividing steps in the manufacturing method of the semiconductor wafer according to the first embodiment of the present invention; [Figure 5] is a perspective view corresponding to Figure 3; [Figure 6] is a perspective view corresponding to Figure 4; [FIG. 7] is an enlarged cross-sectional view for schematically illustrating the first modifying step and the second modifying step in the manufacturing method of the semiconductor wafer according to the second embodiment of the present invention; [FIG. 8] is an enlarged cross-sectional view for schematically illustrating the division steps in the manufacturing method of the semiconductor wafer according to the second embodiment of the present invention; [FIG. 9] is an enlarged cross-sectional view for schematically illustrating the first modifying step and the second modifying step in the manufacturing method of the semiconductor wafer according to the third embodiment of the present invention; [FIG. 10] is an enlarged cross-sectional view for schematically illustrating the dividing step in the manufacturing method of the semiconductor wafer according to the third embodiment of the present invention; [Fig. 11] is an enlarged cross-sectional view for schematically illustrating the first modifying step and the second modifying step in the manufacturing method of the semiconductor wafer according to the fourth embodiment of the present invention; [FIG. 12] is an enlarged cross-sectional view schematically illustrating the division step in the manufacturing method of the semiconductor wafer according to the fourth embodiment of the present invention; and [FIG. 13] is an enlarged cross-sectional view schematically illustrating a build-up step and a pick-up step in a method of manufacturing a semiconductor device according to an embodiment of the present invention.

7: Protective film

8: Semiconductor wafer

8a: Circuit formation surface of semiconductor wafer

8b: Backside of semiconductor wafer

80a: the first region inside the semiconductor wafer

80b: The second area inside the semiconductor wafer

81: The first modified layer

82: The second modified layer

83: The first modified layer

84: The second modification layer

D ₁ : Depth of the first area 80a

D ₂ : the depth of the second area 80b

R ₁ : laser light

R ₂ : laser light

T ₈ : Thickness of the semiconductor wafer when implementing the first modification step and the second modification step

_Δ12 : the distance between the upper end of the first modified layer 81 and the lower end of the second modified layer 82 in the thickness T8 direction of the semiconductor wafer ₈

Claims (2)

A method of manufacturing a semiconductor wafer, comprising: a first modifying step, by irradiating the semiconductor wafer with laser light from the back side of the semiconductor wafer, in the inside of the semiconductor wafer, from the circuit formation surface of the semiconductor wafer In the first region with a depth of 215 μm (micrometer), a first modification layer is formed; in the second modification step, by irradiating laser light on the semiconductor wafer from the back side, the inside of the semiconductor wafer is In the second region from the back surface to a depth of 215 μm (micrometer), and further to the back side than the first modified layer, a second modified layer is formed, wherein compared with the first modified step and the second modified The thickness of the above-mentioned semiconductor wafer during the modification step is such that the length of the shortest side of the above-mentioned semiconductor wafer is equal to or more; Simultaneously, with this polishing, the semiconductor wafer is obtained by dividing the semiconductor wafer at the positions of the first modified layer and the second modified layer due to the force applied to the semiconductor wafer. A method for manufacturing a semiconductor device. According to the method for manufacturing a semiconductor wafer described in item 1 of the patent scope of the application, after obtaining a semiconductor wafer group in which a plurality of semiconductor wafers are arranged, it includes: a layering step, using a support sheet and forming a chip on the support sheet. The above-mentioned film-like bonding agent in the above-mentioned bonding chip is pasted to the above-mentioned back surface of the semiconductor wafer in the above-mentioned semiconductor chip group after grinding, and a laminate of the above-mentioned semiconductor chip group and the above-mentioned bonding chip is produced. and a pick-up step, for the above-mentioned laminate, by applying force from the side of the support sheet, the above-mentioned film-like adhesive in the above-mentioned laminate is cut along the above-mentioned semiconductor wafer, pulled away from the above-mentioned support sheet and picked up on the back side for preparation The above-mentioned semiconductor wafer of the above-mentioned film bonding agent after cutting.