TWI808639B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

Info

Publication number
TWI808639B
TWI808639B TW111104503A TW111104503A TWI808639B TW I808639 B TWI808639 B TW I808639B TW 111104503 A TW111104503 A TW 111104503A TW 111104503 A TW111104503 A TW 111104503A TW I808639 B TWI808639 B TW I808639B
Authority
TW
Taiwan
Prior art keywords
conductive
insulating
layer
channel structure
conductive channel
Prior art date
Application number
TW111104503A
Other languages
English (en)
Other versions
TW202245198A (zh
Inventor
林孟良
莊博堯
鄭心圃
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202245198A publication Critical patent/TW202245198A/zh
Application granted granted Critical
Publication of TWI808639B publication Critical patent/TWI808639B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16501—Material at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81484—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/8349—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Packaging For Recording Disks (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)

Abstract

提供一種封裝結構。封裝結構包括一轉接板，轉接板包括一絕緣結構、一導電墊、一第一導線、以及一第一導電通道結構。絕緣結構具有一第一表面以及與第一表面相對的一第二表面，導電墊位於第一表面之上，第一導線位於絕緣結構內且電性連接導電墊，第一導電通道結構部分位於絕緣結構內並連接第一導線。封裝結構包括一電子元件接合至導電墊。封裝結構包括一晶片結構接合至第一導電通道結構的第一端部。封裝結構包括一第一導電凸塊連接於晶片結構與第一導電通道結構的第一端部之間。第一端部延伸入第一導電凸塊內並直接接觸第一導電凸塊。

Description

封裝結構及其形成方法
本發明實施例是關於封裝結構製造技術，特別是關於具有導電通道結構的封裝結構及其形成方法。
半導體元件可用於各種電子應用中，例如個人電腦、手機、數位相機和其他電子設備。半導體元件的製造方式包括在半導體基底上依序沉積絕緣層或介電層、導電層和半導體層，並使用微影製程和蝕刻製程對不同材料層進行圖案化，以在半導體基底上形成電路組件和元件。
通常會在一半導體晶圓上製作數十或數百個積體電路。可藉由沿著切割線鋸切積體電路的方式切割出多個晶粒。然後，封裝各個晶粒。半導體工業通過不斷減少最小特徵尺寸的方式來持續提高各種電子元件（例如，電晶體、二極體、電阻、電容等）的積體密度（integration density），故可將更多元件積集到一固定面積內。然而，由於特徵尺寸持續地減少，製程持續地變得更加難以執行。因此，用高積集度（high integration density）的電子元件形成可靠的封裝體是一個挑戰。
根據一些實施例，提供一種封裝結構。此封裝結構包括：一轉接板，包括一絕緣結構、一導電墊、一第一導線、以及一第一導電通道結構，其中絕緣結構具有一第一表面以及與第一表面相對的一第二表面，導電墊位於第一表面之上，第一導線位於絕緣結構內且電性連接導電墊，第一導電通道結構部分位於絕緣結構內並連接第一導線，第一導電通道結構的一第一端部突出於絕緣結構的第二表面，且第一導電通道結構的一第一寬度係沿著遠離第一表面的一方向減少；一電子元件接合至導電墊；一晶片結構接合至第一導電通道結構的第一端部；以及一第一導電凸塊連接於晶片結構與第一導電通道結構的第一端部之間，其中第一端部延伸入第一導電凸塊內並直接接觸第一導電凸塊。
根據另一些實施例，提供一種封裝結構。此封裝結構包括：一轉接板，包括一絕緣結構、一導電墊、一第一導線、以及一第一導電通道結構，其中絕緣結構具有一第一表面以及一第二表面，導電墊位於第一表面上，第一導線與第一導電通道結構係位於絕緣結構內且彼此電性連接，第一導電通道結構的一第一端部突出於絕緣結構的第二表面，且第一導電通道結構的一第一寬度係沿著遠離第一表面的一方向減少；一第一電子元件接合至導電墊；一絕緣層位於絕緣結構的第二表面上；一第二電子元件位於絕緣層上；以及一導電結構連接於第二電子元件以及第一導電通道結構的第一端部之間並且貫穿絕緣層，其中導電結構與第一導電通道結構共同形成一連接結構，且在連接結構的一剖面圖中，連接結構具有一沙漏狀。
根據又另一些實施例，提供一種形成封裝結構的方法。此方法包含提供一轉接板，其中轉接板包括一絕緣結構、一導電墊、一第一導線以及一第一導電通道結構，絕緣結構具有一第一表面以及與第一表面相對的一第二表面，導電墊係位於第一表面之上，第一導線與第一導電通道結構係位於絕緣結構內且相互電性連接，且第一導電通道結構的一第一寬度係沿著遠離第一表面的一方向減少；將一電子元件接合至導電墊；從絕緣結構的第二表面移除一部分的絕緣結構，其中在移除部分的絕緣結構之後，第一導電通道結構的一第一端部突出於第二表面；以及將一晶片結構經由一第一導電凸塊接合至第一導電通道結構的第一端部。
以下內容提供許多不同實施例或範例，用於實施本發明實施例之標的之不同特徵。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用於限定本發明實施例。舉例來說，敘述中若提及第一部件形成於第二部件上或上方，可能包含形成第一部件和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一部件和第二部件之間，使得第一部件和第二部件不直接接觸的實施例。另外，本發明實施例在不同範例中可重複使用參考標號及/或字母。此重複是為了簡化和清楚之目的，並非用以限定所討論的各種實施例及/或配置之間的關係。
此外，本文可能使用空間相對用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」及類似的用詞，這些空間相對用語係為了便於描述如圖所示之一個（或一些）元件或部件與另一個（或另一些）元件或部件之間的關係。這些空間相對用語包含使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（例如旋轉90度或其他方位），則在此所使用的空間相對形容詞也將依轉向後的方位來解釋。
本技術領域中具有通常知識者將理解說明書中的用語「大致上」（例如「大致上平坦」或「大致上共平面」等）的意義。在一些實施例中，可以移除形容詞「大致上」。在適當的情況下，用語「大致上」也可以包含具有「整個」、「完全」、「全部」等實施例。用語「大致上」可以在不同技術中變化並且在本技術領域中具有通常知識者所理解的偏差範圍內。舉例來說，用語「大致上」也可以涉及指定值的90%或更高，例如指定值的95%或更高，特別是指定值的99%或更高，包含指定值的100%，但本發明不限於此。此外，例如「大致上平行」或「大致上垂直」的用語可以解釋為不排除與指定排列的微小偏差，並且可以包含例如高達10°的偏差。單詞「大致上」不排除「完全」，例如「大致上不含」Y的組合物可以完全不含Y。
術語“約”可以在不同的技術中變化，並且在本領域技術人員理解的偏差範圍內變化。與特定距離或尺寸結合的術語“大約”應被解釋為不排除與特定距離或尺寸的微小偏差。例如，術語“約”可包括高達指定值的10%的偏差，但本發明不限於此。與數值x相關的術語“約”可涵蓋x±5％或10％，但本發明不限於此。
下文係描述本發明實施例中的一些實施例。可以在這些實施例中描述的階段之前、期間及/或之後加入額外的製程或操作。對於不同的實施例，可以替換或取消所描述的一些步驟。可以將額外的特徵或結構添加到半導體元件結構。對於不同的實施例，可以替換或除去以下描述的一些特徵或結構。雖然以採用特定順序進行的製程或操作描述一些實施例，但也可以採用其他符合邏輯的順序來進行這些製程或操作。
其他特徵和製程亦可包括在內。舉例來說，可以包括測試結構以幫助對3D封裝或3DIC元件進行驗證測試。測試結構可以包括例如形成在重線路層中或在基板上的測試接墊，其允許測試3D封裝或3DIC、使用探針及/或探針卡等。驗證測試可以在中間結構以及最終結構上執行。此外，本文描述的結構和方法可以與已知良好的晶片（known good die）的中間驗證的測試方法結合使用，以增加產量並降低成本。
第1A～1L圖是根據一些實施例之用於形成封裝結構的製程的各個階段的剖面圖。如第1A圖所示，根據一些實施例，提供一載板110。根據一些實施例，載板110係用於在隨後的處理步驟期間提供臨時地機械性和結構性支撐。
根據一些實施例，載板110包括玻璃、矽、氧化矽、氧化鋁、金屬、及前述之組合等。根據一些實施例，載板110包括金屬框架。
如第1A圖所示，根據一些實施例，一轉接板（interposer substrate）120形成在載板110上。轉接板120的形成製程包括：在載板110上方形成一絕緣層121a；在絕緣層121a上方以及絕緣層121a的多個通孔（through hole）121a1和121a2中形成一線路層（wiring layer）122；在絕緣層121a與線路層122上方形成一絕緣層121b；在絕緣層121b上和絕緣層121b的多個通孔121b1中形成一線路層123；在絕緣層121b和線路層123之上形成一絕緣層121c；在絕緣層121c上方和絕緣層121c的多個通孔121c1中形成一線路層124；在絕緣層121c與線路層124上方形成一絕緣層121d；在絕緣層121d上方和絕緣層121d的通孔121d1中形成一線路層125。
根據一些實施例，絕緣層121a、121b、121c和121d共同形成一絕緣結構121。根據一些實施例，絕緣結構121具有兩個相對的表面121e和121f。根據一些實施例，線路層122、123、124和125彼此電性連接。
根據一些實施例，線路層122包括導線122a和122c以及導電通道結構（conductive via structure）122b和122d。根據一些實施例，導線122a和122c在絕緣層121a上方。根據一些實施例，導電通道結構122b和122d穿過絕緣層121a。根據一些實施例，導電通道結構122b和122d分別在導線122a和122c下方並連接到導線122a和122c。
根據一些實施例，各導電通道結構122b的寬度W122b沿著一遠離絕緣結構121的表面121e的方向V1減少。根據一些實施例，各導電通道結構122d的寬度W122d係沿著遠離絕緣結構121的表面121e的方向V1減少。
根據一些實施例，導電通道結構122d比導電通道結構122b寬。根據一些實施例，當寬度W122b和W122d在相同水平下測量時，寬度W122d大於寬度W122b。
根據一些實施例，線路層123包括導線123a和導電通道結構123b。根據一些實施例，導線123a在絕緣層121b上方。根據一些實施例，導電通道結構123b穿過絕緣層121b。根據一些實施例，導電通道結構123b在導線123a之下並連接到導線123a。根據一些實施例，各導電通道結構123b的寬度W123b沿著遠離絕緣結構121的表面121e的方向V1減少。
根據一些實施例，線路層124包括導線124a和導電通道結構124b。根據一些實施例，導線124a在絕緣層121c上方。根據一些實施例，導電通道結構124b穿過絕緣層121c。根據一些實施例，導電通道結構124b在導線124a之下並連接到導線124a。根據一些實施例，各導電通道結構124b的寬度W124b沿著遠離絕緣結構121的表面121e的方向V1減少。
根據一些實施例，線路層125包括導電墊125a、導線（未繪示）、和導電通道結構125b。根據一些實施例，導電墊125a和導線在絕緣層121d上方並且彼此連接。根據一些實施例，導電通道結構125b穿過絕緣層121d。
根據一些實施例，導電通道結構125b在導電墊125a和導線之下並連接到導電墊125a和導線。根據一些實施例，各導電通道結構125b的寬度W125b係沿著遠離絕緣結構121的表面121e的方向V1減少。在一些其他實施例中，並未形成導線。
根據一些實施例，絕緣結構121的材質為高分子材料（例如聚苯並噁唑、聚酰亞胺、或感光材料）、氮化物（例如氮化矽）、氧化物（例如氧化矽）、氮氧化矽等絕緣材料。根據一些實施例，線路層122、123、124和125係由導電材料製成，導電材料例如為金屬（如銅、鋁或鎢）。
如第1B圖所示，根據一些實施例，晶片結構130A和130B以及電子元件130C通過導電凸塊140接合到轉接板120。各晶片結構130A和130B包括單晶片系統（又稱：片上系統，System on a Chip：SoC）結構、記憶體晶片結構（例如，動態隨機存取記憶體晶片結構）或其他適合的晶片結構。根據一些實施例，晶片結構130A和130B也被稱為電子元件。
根據一些實施例，各晶片結構130A和130B都具有一基板132、一元件層134和一內連線層（interconnect layer）136。在一些實施例中，基板132由元素半導體材料製成，元素半導體材料包括單晶結構、多晶結構或非晶結構的矽或鍺。
在其他一些實施例中，基板132由化合物半導體製成，例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體，例如矽鍺（SiGe）或磷砷鎵（GaAsP），或其組合。基板132還可包括多層半導體、絕緣體上半導體（SOI）（例如絕緣體上矽或絕緣體上鍺）、或其組合。
在一些實施例中，基板132係為一元件晶片，其包括各種元件單元。在一些實施例中，各種元件單元形成在基板132之中及/或之上。為了簡單和清楚的目的，沒有在圖中繪示出元件單元。各種元件單元例如包括主動元件、被動元件、其他適合的元件或其組合。主動元件可以包括形成在基板132的表面處的電晶體或二極體（未繪示）。被動元件包括電阻、電容、或其他適合的被動元件。
例如，電晶體可以是金屬氧化物半導體場效應電晶體（MOSFET）、互補式金屬氧化物半導體（CMOS）電晶體、雙極性接面型電晶體（bipolar junction transistor, BJT）、高壓電晶體、高頻電晶體、p型通道及/或n型通道場效應電晶體（PFET/NFET）等。執行各種製程，例如生產線前端（front-end-of-line, FEOL）半導體製造製程，以形成各種元件單元。FEOL半導體製造製程可包括沉積、蝕刻、佈植（implantation）、微影、退火、平坦化、一種或多種其他適合的製程、或其組合。
在一些實施例中，隔離結構（未繪示）形成在基板132中。隔離結構用於限定主動區並且電性隔離在主動區中的基板132中及/或上方形成的各種元件單元。在一些實施例中，隔離結構包括淺溝槽隔離（STI）結構、矽局部氧化（LOCOS）結構、其他適合的隔離結構或其組合。
根據一些實施例，基板132具有一面向轉接板120的底面132a。根據一些實施例，元件層134係位於底面132a之上。根據一些實施例，元件層134包括電子元件（未繪示）、介電層134a和導電墊134b。
在一些實施例中，電子元件形成在基板132之上或之中。根據一些實施例，電子元件包括主動元件（例如電晶體、二極體等）及/或被動元件（例如電阻、電容、電感等）。根據一些實施例，介電層134a形成在底面132a上並覆蓋電子元件。
根據一些實施例，導電墊134b係嵌入在介電層134a中並且電性連接到電子元件。根據一些實施例，導電墊134b由導電材料製成，導電材料例如為金屬（例如，銅、鋁、鎳或其組合）。
根據一些實施例，內連線層136係形成在元件層134之上。根據一些實施例，內連線層136包括內連線結構（interconnect structure，未繪示）和介電層（未繪示）。根據一些實施例，內連線結構在介電層中並且電性連接到導電墊134b。
根據一些實施例，電子元件130C包括主動元件及/或被動元件。根據一些實施例，主動元件包括電晶體或二極體。被動元件包括電阻、電容、電感或其他適合的被動元件。在一些實施例中，電子元件130C為一晶片封裝體，其包括一或多個晶片，例如單晶片系統（system-on-chips，SoC）、高帶寬記憶體（high bandwidth memory，HBM）晶片、動態隨機存取記憶體（DRAM）晶片及/或其他適合的晶片。
根據一些實施例，多個導電凸塊140連接在多個導電墊125a和內連線層136之間，以通過內連線層136的內連線結構將導電墊125a電性連接到導電墊134b。根據一些實施例，導電凸塊140係由焊料材料製成，例如錫（Sn）和銀（Ag）、或另一種適合的導電材料（例如，金）。根據一些實施例，導電凸塊140是焊球。
如第1B圖所示，根據一些實施例，在晶片結構130A和130B與轉接板120之間以及在電子元件130C與轉接板120之間形成一底填層150。根據一些實施例，底填層150圍繞導電凸塊140和導電墊125a。根據一些實施例，底填層150由絕緣材料製成，例如高分子材料或由環氧樹脂和填充材料組成的封裝膠體材料（molding compound material）。
如第1B圖所示，根據一些實施例，一封膠層（molding layer）160係形成在轉接板120上方。根據一些實施例，封膠層160圍繞晶片結構130A和130B、電子元件130C和底填層150。根據一些實施例，封膠層160填充晶片結構130A和130B與電子元件130C之間的間隙G1和G2。封膠層160由高分子材料或其他適合的絕緣材料製成。
根據一些實施例，封膠層160的形成包括：在晶片結構130A和130B、電子元件130C、底填層150和轉接板120上方形成封膠材料層（未繪示）；以及移除位於晶片結構130A和130B以及電子元件130C上方的封膠材料層。
根據一些實施例，移除製程包括一平坦化製程，例如化學機械研磨製程。因此，根據一些實施例，晶片結構130A和130B、電子元件130C和封膠層160的頂面131A、131B、131C和162大致上彼此齊平（或共平面）。
如第1C圖所示，根據一些實施例，一載板170係接合到晶片結構130A和130B、電子元件130C和封膠層160。根據一些實施例，載板170係作為在後續處理步驟的期間內提供臨時地機械性和結構性支撐。根據一些實施例，載板170包括玻璃、矽、氧化矽、氧化鋁、金屬、及前述之組合等。
如第1D圖所示，根據一些實施例，將轉接板120倒置。此後，如第1D圖所示，根據一些實施例，移除載板110。
如第1E圖所示，根據一些實施例，從絕緣結構121的表面121f移除絕緣層121a的上部。根據一些實施例，在移除絕緣層121a的上部之後，導電通道結構122b和122d的多個端部122b1和122d1從絕緣結構121的表面121f突出。
根據一些實施例，在移除絕緣層121a的上部之後，絕緣層121a比絕緣層121d薄。根據一些實施例，移除製程包括蝕刻製程，例如乾式蝕刻製程或濕式蝕刻製程。
如第1F圖所示，根據一些實施例，在絕緣層121a以及導電通道結構122b和122d的端部122b1和122d1上方形成一晶種層180。根據一些實施例，晶種層180共形地覆蓋絕緣層121a以及導電通道結構122b和122d的端部122b1和122d1。
根據一些實施例，晶種層180係由一導電材料製成，導電材料例如為金屬（例如，銅、鋁、金、銀或鎢）或其合金。根據一些實施例，使用例如物理氣相沉積製程或化學氣相沉積製程等沉積製程來形成晶種層180。
如第1F圖所示，根據一些實施例，在晶種層180上方形成一罩幕層190。根據一些實施例，罩幕層190具有多個開口192。根據一些實施例，開口192暴露出導電通道結構122d上方的晶種層180。根據一些實施例，罩幕層190係由一與晶種層180的材料不同的材料製成，例如高分子材料（例如，光阻材料）。
如第1G圖所示，根據一些實施例，在罩幕層190的開口192中形成一導電層210。根據一些實施例，導電層210位於導電通道結構122d之上的晶種層180之上。根據一些實施例，導電層210共形地覆蓋導電通道結構122d上方的晶種層180。因此，根據一些實施例，導電層210具有在導電通道結構122d上方的多個突出部分211。根據一些實施例，位於單一開口192中的導電層210具有一倒U形。
根據一些實施例，導電層210係由例如金屬（例如，銅、鋁、金、銀或鎢）或其合金等導電材料製成。根據一些實施例，導電層210使用鍍膜製程（plating process）形成，例如電鍍製程。
然後，如第1G圖所示，根據一些實施例，在罩幕層190的開口192中形成焊料層220a。根據一些實施例，焊料層220a在導電層210之上。根據一些實施例，焊料層220a由例如金屬（例如，錫、銀等）或其合金等導電材料製成。根據一些實施例，焊料層220a係使用鍍膜製程形成，例如電鍍製程。
此後，如第1G和1H圖所示，根據一些實施例，移除罩幕層190。之後，如第1G和1H圖所示，根據一些實施例，移除未被導電層210覆蓋的晶種層180。
如第1G和1H圖所示，根據一些實施例，單一開口192中的導電層210和保留在其下方的晶種層180共同形成一導電柱212。根據一些實施例，各導電柱212在對應的導電通道結構122d的端部122d1上方。根據一些實施例，移除製程包括蝕刻製程，例如乾式蝕刻製程或濕式蝕刻製程。
此後，如第1H和1I圖所示，根據一些實施例，在焊料層220a上執行退火製程以將焊料層220a轉變為導電凸塊220。根據一些實施例，各導電凸塊220位於對應的導電柱212和導電通道結構122d的對應的端部122d1上方。
第1J-1圖是根據一些實施例之第1J圖的封裝結構的區域R的放大剖面圖。如第1J和1J-1圖所示，根據一些實施例，電子元件230A和230B通過導電凸塊240接合到導電通道結構122b的端部122b1。
在一些實施例中，各電子元件230A和230B包括主要部分232和導電柱234。根據一些實施例，主要部分232與第1L圖的晶片結構130A和130B或電子元件130C相似或大致上相同。
根據一些實施例，導電柱234在主要部分232的底面232a之下並連接到底面232a。根據一些實施例，導電柱234電性連接到主要部分232。根據一些實施例，導電柱234由一導電材料製成，導電材料例如為金屬（例如，銅、鋁、金、銀或鎢）或其合金。
根據一些實施例，導電凸塊240連接在導電柱234和導電通道結構122b的端部122b1之間。根據一些實施例，端部122b1延伸入對應的導電凸塊240中，這增加了端部122b1和對應的導電凸塊240之間的接合強度。例如，整個端部122b1在對應的導電凸塊240中。
根據一些實施例，導電凸塊240覆蓋其下方的整個端部122b1。根據一些實施例，端部122b1與對應的導電凸塊240直接接觸。根據一些實施例，導電凸塊220比導電凸塊240寬。
根據一些實施例，由於實施例沒有在導電通道結構122b上方形成導電墊（即凸塊底金屬層，under-bump metallurgy layer，UBM layer），因此，導電凸塊240直接接合到導電通道結構122b的端部122b1，故可形成自對準接點。
根據一些實施例，由於導電通道結構122b的端部122b1小於導電墊，因此，接合到端部122b1的導電凸塊240會小於接合到導電墊的導電凸塊（未繪示）。因此，根據一些實施例，實施例係藉由不形成導電墊來減少導電凸塊240的尺寸（例如，寬度和高度）。
因此，根據一些實施例，前述設計可減少這些導電凸塊240的中心之間的距離（即，間距，pitch），故可形成小間距接點（fine-pitch joints）、或小間距佈線（fine-pitch routings），其可達到高輸入/輸出量（high I/O throughput）。因此，根據一些實施例，前述設計提升了設計的靈活度。
此外，根據一些實施例，導電凸塊240之間的距離減少。根據一些實施例，由於實施例不形成導電墊，故節省了用於形成導電墊的製程和材料的成本。
如第1J-1圖所示，根據一些實施例，在絕緣層121a的表面121a3的同一高度處的導電通道結構122b的寬度W122b係等於或小於導電凸塊240的寬度W240。根據一些實施例，寬度W122b約為1微米（μm）至25微米。如第1J和1J-1圖所示，導電柱234的中心之間的距離D234大於寬度W240。根據一些實施例，距離D234約為1微米至約50微米。
如第1J-1圖所示，根據一些實施例，端部122b1的厚度T122b1係小於或等於導電凸塊240的厚度T240。根據一些實施例，厚度T122b1約為0.1微米至約10微米。
如第1J-1圖所示，根據一些實施例，各導電凸塊240具有合金層242和主體部分244。根據一些實施例，導電凸塊240的合金層242係於將主體部分244接合到導電通道結構122b的端部122b1之時形成。
根據一些實施例，在將主體部分244接合至導電通道結構122b的端部122b1之時，主體部分244的導電材料（例如，錫）容易與其下方的導電通道結構122b的導電材料（例如，銅）接合，而在主體部分244和導電通道結構122b之間形成合金層242（例如，銅錫合金層）。根據一些實施例，合金層242包括其上的主體部分244和其下的導電通道結構122b的材料。
根據一些實施例，在合金層242形成之後，由於合金層242的形成消耗了其下方的導電通道結構122b的端部122b1的上部（包括邊緣部分），所以端部122b1具有端面B1，其為弧形的凸頂面。
此外，根據一些實施例，合金層242具有弧形的凸頂表面S242。根據一些實施例，合金層242的形成消耗了端部122b1的邊緣部分，這防止應力集中在端部122b1的邊緣部分。因此，根據一些實施例，前述設計提高了導電凸塊240的可靠度和良率。
如第1J-1圖所示，根據一些實施例，導電通道結構122b的寬度W122b小於導電凸塊240的寬度W240。如第1J和1J-1圖所示，根據一些實施例，一底填層250形成在電子元件230A和230B與轉接板120之間。
根據一些實施例，底填層250圍繞導電凸塊240。根據一些實施例，底填層250係由絕緣材料製成，例如高分子材料、或由環氧樹脂和填充材料組成的封裝膠體材料。
如第1J-1圖所示，根據一些實施例，導電凸塊240和其下方的導電通道結構122b共同形成連接結構C。根據一些實施例，連接結構C呈沙漏狀。
如第1K圖所示，根據一些實施例，載板170被移除。如第1K圖所示，根據一些實施例，轉接板120設置在框架（或載體）A上方。如第1K圖所示，根據一些實施例，沿著預定切割線B切割轉接板120和封膠層160以形成多個晶片封裝體100。
為了簡化起見，第1L圖僅示出了諸多晶片封裝體100中的一個。如第1L圖所示，根據一些實施例，晶片封裝體100通過導電凸塊220接合到一線路基板260。根據一些實施例，電子元件230A和230B係位於轉接板120和線路基板260之間。
在一些實施例中，部分的電子元件230A和230B係位於線路基板260中。根據一些實施例，線路基板260具有凹槽267和268。根據一些實施例，部分的電子元件230A和230B分別位於凹槽267和268中。
根據一些實施例，線路基板260包括介電層261、導電墊262、線路層264和導電墊266。根據一些實施例，線路層264以及導電墊262和266係位於介電層261中。
根據一些實施例，導電凸塊220接合到導電墊266。根據一些實施例，各線路層264包括導線264a和導電通孔264b。根據一些實施例，導電通孔264b連接在不同線路層264的導線264a之間、以及導線264a與導電墊262和266之間。
根據一些實施例，線路層264與導電墊262和266彼此電性連接。介電層261係由高分子材料或其他適合的材料製成。介電層261例如包括纖維材料（例如玻璃纖維材料）、預浸材料（prepreg material）（例如高分子材料）、ABF膜（ABF，Ajinomoto Build-up Film）、防焊材料（solder resist material）、或其組合。根據一些實施例，線路層264以及導電墊262和266係由導電材料（例如銅、鋁、或鎢）製成。
然後，如第1L圖所示，根據一些實施例，在晶片封裝體100和線路基板260之間形成一底填層（underfill layer）270。根據一些實施例，底填層270圍繞導電凸塊220、導電柱212、電子元件230A和230B、以及底填層250。
根據一些實施例，底填層270位於凹槽267和268中以隔開電子元件230A和230B與線路基板260。根據一些實施例，底填層270係由絕緣材料製成，例如高分子材料、或由環氧樹脂和填充材料組成的封裝膠體材料。
然後，如第1L圖所示，根據一些實施例，在導電墊262上方形成導電凸塊280。根據一些實施例，在此步驟中，封裝結構200大致上形成。根據一些實施例，導電凸塊280係由焊料材料製成，例如錫和銀、或另一種適合的導電材料（例如，金）。根據一些實施例，導電凸塊280是焊球。
第2A～2F圖是根據一些實施例之用於形成封裝結構的製程的各個階段的剖面圖。根據一些實施例，在第1E圖的步驟之後，如第2A圖所示，在絕緣結構121的表面121f上方形成絕緣層310。根據一些實施例，絕緣層310具有多個開口312和314。
根據一些實施例，這些開口312分別暴露導電通道結構122b的端部122b1。根據一些實施例，這些開口314分別暴露導電通道結構122d的端部122d1。根據一些實施例，絕緣層310與各導電通道結構122b的端部122b1的端面B1和側壁B2直接接觸。根據一些實施例，絕緣層310與各導電通道結構122d的端部122d1的端面D1和側壁D2直接接觸。
根據一些實施例，絕緣層310與絕緣結構121的表面121f直接接觸。根據一些實施例，絕緣層310的材質為絕緣材料，例如為高分子材料（例如聚苯並噁唑、聚酰亞胺、或感光材料）、氮化物（例如氮化矽）、氧化物（例如氧化矽）、氮氧化矽。
如第2B圖所示，執行第1F和1G圖的步驟以形成晶種層180、罩幕層190、導電層210和焊料層220a。根據一些實施例，導電層210在絕緣層310的開口314上方或導電通道結構122d上方具有凹槽213。根據一些實施例，位於罩幕層190的其中一開口192中的導電層210呈U形狀。
如第2C圖所示，根據一些實施例，執行第1H圖的步驟以移除罩幕層190以及未被導電層210覆蓋的晶種層180。如第2B和2C圖所示，根據一些實施例，位於一開口192中的導電層210和保留在其下方的晶種層180共同形成一導電柱212。根據一些實施例，各導電柱212位於對應的導電通道結構122d的端部122d1的上方。
如第2D圖所示，根據一些實施例，在焊料層220a上執行退火製程以將焊料層220a轉變為多個導電凸塊220。根據一些實施例，各導電凸塊220在對應的導電柱212和對應的導電通道結構122d的端部122d1上方。
第2E-1圖是根據一些實施例之第2E圖的封裝結構的區域R的放大剖面圖。之後，如第2E和2E-1圖所示，根據一些實施例，執行第1J圖的步驟以形成電子元件230A和230B、導電凸塊240和底填層250。
根據一些實施例，電子元件230A和230B形成在絕緣層310上方。根據一些實施例，導電凸塊240形成在絕緣層310的開口312中。根據一些實施例，導電凸塊240穿過絕緣層310。根據一些實施例，導電凸塊240連接在電子元件230A和230B的導電柱234與導電通道結構122b的端部122b1之間。
如第2E-1圖所示，根據一些實施例，導電凸塊240的厚度T240大於開口312的深度D312。根據一些實施例，與導電通道結構122b鄰接的導電凸塊240的寬度W3小於與導電柱234鄰接的導電凸塊240的寬度W4。
根據一些實施例，寬度W4小於或等於與導電凸塊240鄰接的導電通道結構122b的寬度W2。根據一些實施例，寬度W2小於與導線122a鄰接的導電通道結構122b的寬度W1。
如第2E-1圖所示，根據一些實施例，各導電凸塊240具有合金層242以及位於合金層242上方的主體部分244。根據一些實施例，在將主體部分244接合到導電通道結構122b的端部122b1之時形成導電凸塊240的合金層242。
根據一些實施例，在將主體部分244接合至導電通道結構122b的端部122b1之時，主體部分244的導電材料（例如，錫）容易與其下方的導電通道結構122b的導電材料（例如，銅）接合，進而在主體部分244和導電通道結構122b之間形成合金層242（例如，銅錫合金層）。根據一些實施例，合金層242包括其上的主體部分244和其下的導電通道結構122b的材料。
如第2E-1圖所示，根據一些實施例，導電凸塊240和其下方的導電通道結構122b共同形成連接結構C。根據一些實施例，連接結構C呈沙漏狀。根據一些實施例，導電凸塊240包括焊料凸塊。
根據一些實施例，如第2F圖所示，執行第1K與1L圖的步驟以形成多個晶片封裝體100A，通過導電凸塊220將這些晶片封裝體100A的其中之一接合至線路基板260，並形成底填層270與導電凸塊280。根據一些實施例，在此步驟中，大致上形成一封裝結構200A。
根據一些實施例，底填層270形成在晶片封裝體100A和線路基板260之間。根據一些實施例，底填層270直接接觸絕緣層310、導電柱212、導電凸塊220、電子元件230A和230B、底填層250、以及線路基板260。
根據一些實施例，絕緣層310用來作為應力緩衝層和導電凸塊侷限層（conductive bump confinement layer），其防止相鄰導電凸塊240橋接。根據一些實施例，能夠通過調整絕緣層310的設計來調整導電凸塊240的尺寸（例如，寬度），這提高了設計的靈活度。
第3A圖是根據一些實施例之封裝結構200B的剖面圖。第3B圖是根據一些實施例之第3A圖的封裝結構200B的第一區域R1的放大剖面圖。第3C圖是根據一些實施例之第3A圖的封裝結構200B的第二區域R2的放大剖面圖。
根據一些實施例，如第3A、3B與3C圖所示，一封裝結構200B與一晶片封裝體100B分別與第2F圖的封裝結構200A與晶片封裝體100A相似，不同之處在於絕緣層310的開口312與314分別暴露出導電通道結構122b和122d的整個端部122b1和122d1。
如第3B圖所示，根據一些實施例，絕緣層310的各開口314暴露出對應的導電通道結構122d的端部122d1的端面D1和側壁D2。根據一些實施例，導電柱212覆蓋對應的端部122d1的端面D1和側壁D2。
根據一些實施例，導電柱212直接接觸對應的端部122d1的端面D1和側壁D2。根據一些實施例，端部122d1位於對應的導電柱212中。
如第3C圖所示，根據一些實施例，絕緣層310的各開口312暴露出對應的導電通道結構122b的端部122b1的端面B1和側壁B2。根據一些實施例，導電凸塊240覆蓋對應的端部122b1的端面B1和側壁B2。
根據一些實施例，導電凸塊240直接接觸對應的端部122b1的端面B1和側壁B2。根據一些實施例，端部122b1位於對應的導電凸塊240中。
如第3C圖所示，根據一些實施例，導電凸塊240的厚度T240大於開口312的深度D312。根據一些實施例，厚度T240與深度D312的比率範圍約為1～6。根據一些實施例，深度D312的範圍約為1微米至10微米。根據一些實施例，位於與絕緣層121a的表面121a3的相同水平處的導電通道結構122b的寬度W2小於與導線122a鄰接的導電通道結構122b的寬度W1。
根據一些實施例，寬度W1小於或等於與導電通道結構122b鄰接的導電凸塊240的寬度W3。根據一些實施例，寬度W3小於與導電柱234鄰接的導電凸塊240的寬度W4。
第4A～4D圖是根據一些實施例之用於形成封裝結構的製程的各個階段的剖面圖。根據一些實施例，在第2A圖的步驟之後，如第4A圖所示，在絕緣層310以及導電通道結構122b和122d的端部122b1和122d1上方形成一晶種層180。根據一些實施例，晶種層180共形地覆蓋絕緣層310以及導電通道結構122b和122d的端部122b1和122d1。
此後，如第4A圖所示，根據一些實施例，在晶種層180上方形成罩幕層410。根據一些實施例，罩幕層410具有多個開口412。根據一些實施例，開口412暴露導電通道結構122b上方的晶種層180。根據一些實施例，暴露的晶種層180位於絕緣層310的開口312中。然後，如第4A圖所示，根據一些實施例，在暴露的晶種層180上方形成導電層420。
根據一些實施例，導電層420係由導電材料製成，導電材料例如為金屬（例如，銅、鋁、金、銀、或鎢）或其合金。根據一些實施例，導電層420係以鍍膜製程形成，例如電鍍製程。
如第4B圖所示，根據一些實施例，移除罩幕層410。如第4B圖所示，根據一些實施例，在晶種層180上方形成一罩幕層430。根據一些實施例，罩幕層430具有多個開口432。根據一些實施例，開口432暴露導電通道結構122d上方的晶種層180。根據一些實施例，罩幕層430係由與晶種層180的材料不同的材料製成，例如高分子材料（例如，光阻材料）。
如第4B圖所示，根據一些實施例，在罩幕層430的開口432中形成導電層440。根據一些實施例，導電層440位於導電通道結構122d之上的晶種層180之上。根據一些實施例，導電層440共形地覆蓋導電通道結構122d上方的晶種層180。因此，根據一些實施例，導電層440在導電通道結構122d的端部122d1上方具有凹槽441。根據一些實施例，在這些開口432之一中的導電層440呈U形。
根據一些實施例，導電層440係由導電材料製成，導電材料例如為金屬（例如，銅、鋁、金、銀、或鎢）或其合金。根據一些實施例，導電層440係以鍍膜製程形成，例如電鍍製程。
然後，如第4B圖所示，根據一些實施例，在罩幕層430的開口432中形成焊料層450a。根據一些實施例，焊料層450a位於導電層440之上。根據一些實施例，焊料層450a係由導電材料製成，例如金屬（例如，錫、銀等）或其合金。根據一些實施例，焊料層450a係使用鍍膜製程形成，例如電鍍製程。
此後，如第4B和4C圖所示，根據一些實施例，移除罩幕層430。之後，如第4B和4C圖所示，根據一些實施例，移除未被導電層440覆蓋的晶種層180。如第4B和4C圖所示，根據一些實施例，在這些開口432之一中的導電層440和保留在其下方的晶種層180共同形成一導電柱442。根據一些實施例，各導電柱442位於對應的導電通道結構122d的端部122d1上方。
根據一些實施例，在移除晶種層180之時，一併移除位於絕緣層310的開口312之外的導電層420。根據一些實施例，在移除製程之後，保留在這些開口312之一中的導電層420以及保留在其下方的晶種層180共同形成一導電結構422。根據一些實施例，導電結構422包括導電柱。
根據一些實施例，導電結構422和其下方的導電通道結構122b共同形成連接結構C1。根據一些實施例，連接結構C1具有沙漏形狀。根據一些實施例，移除製程包括蝕刻製程，例如乾式蝕刻製程或濕式蝕刻製程。
第4D-1圖是根據一些實施例之第4D圖的封裝結構的區域R的放大剖面圖。如第4D和4D-1圖所示，根據一些實施例，執行第1I-1L圖的步驟以將焊料層450a轉變為多個導電凸塊450，形成電子元件230A和230B、多個導電凸塊240、一底填層250、以及多個晶片封裝體100C，透過導電凸塊450將晶片封裝體100C接合到線路基板260，以及形成底填層270和導電凸塊280。在該步驟中，根據一些實施例，大致上形成一封裝結構200C。
如第4D-1圖所示，根據一些實施例，導電凸塊240的厚度T240約為1微米（微米）至20微米。根據一些實施例，導電結構422的厚度T422約為1微米至10微米。根據一些實施例，與導電通道結構122b鄰接的導電結構422的寬度W422U係小於與導電凸塊240鄰接的導電結構422的寬度W422L。
根據一些實施例，寬度W422L小於或等於導電凸塊240的寬度W240。根據一些實施例，寬度W240小於或等於在與絕緣層121a的表面121a3的相同水平處的導電通道結構122b的寬度W2。根據一些實施例，寬度W2小於與導線122a鄰接的導電通道結構122b的寬度W1。
第5A圖是根據一些實施例之封裝結構200D的剖面圖。第5B圖是根據一些實施例之第5A圖的封裝結構200D的區域R的放大剖面圖。第5C圖是根據一些實施例之第5A圖的區域R512中的導電結構422a和422b的底視圖。
如第5A圖所示，根據一些實施例，封裝結構200D與晶片封裝體100D分別類似於第4D圖的封裝結構200C與晶片封裝體100C，不同之處在於絕緣層310的開口314暴露出導電通道結構122d的整個端部122d1，以及絕緣層310的開口312a暴露出導電通道結構122b的整個端部122b1。
如第5A圖所示，根據一些實施例，絕緣層310的開口314暴露出導電通道結構122d的端部122d1的端面D1和側壁D2。根據一些實施例，各導電柱442覆蓋並直接接觸對應的端部122d1的端面D1和側壁D2。
如第5A和5B圖所示，根據一些實施例，絕緣層310的開口312a暴露導電通道結構122b的端部122b1的端面B1和側壁B2。根據一些實施例，各導電結構422a覆蓋並直接接觸對應的端部122b1的端面B1和側壁B2。
根據一些實施例，導電結構422a類似於第4D圖的導電結構422，除了各導電結構422a係圍繞其上方的導電通道結構122b的端部122b1。根據一些實施例，端部122b1延伸到其下方的導電結構422a中。根據一些實施例，各導電結構422b與第4D圖的導電結構422相似或相同。
如第5B圖所示，根據一些實施例，位於與絕緣層121a的表面121a3的同一高度處的導電通道結構122b的寬度W2小於鄰近導線122a的導電通道結構122b的寬度W1。根據一些實施例，寬度W1小於或等於與導電通道結構122b鄰接的導電結構422的寬度W422U。
根據一些實施例，寬度W422U小於與導電凸塊240鄰接的導電結構422a的寬度W422L。根據一些實施例，W422L小於或等於導電凸塊240的寬度W240。
如圖所示。如第5A和5C圖所示，根據一些實施例，導電結構422a比導電結構422b寬。根據一些實施例，導電結構422a圍繞導電結構422b。根據一些實施例，導電結構422a位於電子元件510的外圍區域P之上。根據一些實施例，導電結構422b位於電子元件510的中央區C’之上。
根據一些實施例，由於中央區C’的線路密度大於外圍區P的線路密度，因此位於中央區C’上方的導電結構422b的數量密度（或分佈密度）大於位於外圍區域P之上的導電結構422a的數量密度。根據一些實施例，導電結構422b之間的距離D422b小於導電結構422a之間的距離D422a。
根據一些實施例，由於周邊區P的電路密度較低，因此導電結構422a可具有較大的寬度以增加導電結構422a與導電凸塊240之間的接合面積，從而防止電子元件510翹曲。根據一些實施例，由於導電結構422a和導電凸塊240之間的接合面積增加，故增加了流過接合面積的電流，從而提高封裝結構200D的性能。
根據一些實施例，封裝結構200D包括用以替代第4D圖的封裝結構200C的電子元件230A和230B的電子元件510。根據一些實施例，電子元件510包括主要部分512和導電柱514和516。主要部分512與第1L圖的晶片結構130A和130B或電子元件130C相似或基本相同。
根據一些實施例，導電柱514和516位於主要部分512之上並連接到主要部分512。根據一些實施例，導電柱514將主要部分512電性連接到導電結構422a。根據一些實施例，導電柱516將主要部分512電性連接到導電結構422b。
根據一些實施例，導電柱514比導電柱516寬。根據一些實施例，導電柱514和516係由導電材料製成，例如金屬（例如，銅、鋁、金、銀、或鎢）或其合金。
第6圖是根據一些實施例之封裝結構200E的剖面圖。如第6圖所示，根據一些實施例，封裝結構200E與晶片封裝體100E分別與第1L圖的封裝結構200與晶片封裝體100相似，只是封裝結構200E的電子元件230A與230B不位於線路基板260中。
根據一些實施例，第6圖的線路基板260不具有第1L圖的線路基板260的凹槽267和268。在一些實施例中，電子元件230A或230B的表面231與絕緣層121a之間的距離D231小於絕緣層121a與線路基板260之間的距離D260。
根據一些實施例，距離D260的範圍約為50微米至200微米。根據一些實施例，導電柱212的厚度T212與導電凸塊220的厚度T220的比率範圍約為0.5到5。
根據一些實施例，距離D231的範圍約為90微米至270微米。根據一些實施例，表面231和線路基板260之間的距離D232約為10微米至30微米。
用於形成封裝結構200A、200B、200C、200D和200E以及晶片封裝體100A、100B、100C、100D和100E的製程和材料可相似或相同於用於形成封裝結構200和晶片封裝體100的製程和材料。
根據一些實施例，提供一種封裝結構及其形成方法。用於形成封裝結構的方法係將導電凸塊接合到導電通道結構的末端部分，而非接合到接墊，這能夠形成自對準和小間距接點（或小間距佈線），從而能夠實現高輸入/輸出量。因此，提高了設計的靈活度。
根據一些實施例，提供一種封裝結構。封裝結構包括一轉接板，轉接板包括一絕緣結構、一導電墊、一第一導線、以及一第一導電通道結構。絕緣結構具有一第一表面以及與第一表面相對的一第二表面，導電墊位於第一表面之上，第一導線位於絕緣結構內且電性連接導電墊，第一導電通道結構部分位於絕緣結構內並連接第一導線，第一導電通道結構的一第一端部突出於絕緣結構的第二表面，且第一導電通道結構的一第一寬度係沿著遠離第一表面的一方向減少。封裝結構包括一電子元件接合至導電墊。封裝結構包括一晶片結構接合至第一導電通道結構的第一端部。封裝結構包括一第一導電凸塊連接於晶片結構與第一導電通道結構的第一端部之間。第一端部延伸入第一導電凸塊內並直接接觸第一導電凸塊。
在一些實施例中，絕緣結構包括一第一絕緣層以及一第二絕緣層，第一導線位於第一絕緣層上，第一導電通道結構貫穿第一絕緣層，第二絕緣層係位於第一絕緣層以及第一導線上，導電墊係位於第二絕緣層上，以及第一絕緣層比第二絕緣層薄。
在一些實施例中，第一導電凸塊覆蓋第一導電通道結構的整個第一端部。
在一些實施例中，第一導電通道結構的第一端部具有一弧形的凸面。
在一些實施例中，第一導電凸塊具有一主體部分與一合金層，合金層位於主體部分與第一導電通道結構的第一端部之間，合金層包括構成主體部分的一第一材料以及構成第一導電通道結構的一第二材料，且合金層具有一弧形的表面。
在一些實施例中，轉接板更包括一第二導線以及一第二導電通道結構，第二導線位於絕緣結構內且電性連接導電墊，第二導電通道結構部分位於絕緣結構內且連接第二導線，第二導電通道結構的一第二端部突出於絕緣結構的第二表面，第二導電通道結構的一第二寬度係沿著遠離第一表面的方向減少，以及第二導電通道結構比第一導電通道結構寬。
在一些實施例中，封裝結構更包括：一導電柱位於第二導電通道結構的第二端部之上；以及一第二導電凸塊位於導電柱之上，其中第二導電凸塊比第一導電凸塊寬。
在一些實施例中，封裝結構更包括：一線路基板，其中第二導電凸塊接合至線路基板，以及晶片結構係位於轉接板與線路基板之間。
在一些實施例中，晶片結構的一部分係位於線路基板中。
根據一些實施例，提供一種封裝結構。封裝結構包括一轉接板，轉接板包括一絕緣結構、一導電墊、一第一導線、以及一第一導電通道結構。絕緣結構具有一第一表面以及一第二表面，導電墊位於第一表面上，第一導線與第一導電通道結構係位於絕緣結構內且彼此電性連接，第一導電通道結構的一第一端部突出於絕緣結構的第二表面，且第一導電通道結構的一第一寬度係沿著遠離第一表面的一方向減少。封裝結構包括一第一電子元件接合至導電墊。封裝結構包括一絕緣層位於絕緣結構的第二表面上。封裝結構包括一第二電子元件位於絕緣層上。封裝結構包括一導電結構連接於第二電子元件以及第一導電通道結構的第一端部之間並且貫穿絕緣層。導電結構與第一導電通道結構共同形成一連接結構，且在連接結構的一剖面圖中，連接結構具有一沙漏狀。
在一些實施例中，導電結構包括一焊料凸塊。
在一些實施例中，導電結構包括一導電柱，且封裝結構更包括連接於導電柱與第二電子元件之間的一導電凸塊。
在一些實施例中，絕緣層直接接觸第一導電通道結構的第一端部的一側壁。
在一些實施例中，第一導電通道結構的第一端部係位於導電結構中。
根據一些實施例，提供一種形成封裝結構的方法。前述方法包括提供一轉接板包括一絕緣結構、一導電墊、一第一導線以及一第一導電通道結構。絕緣結構具有一第一表面以及與第一表面相對的一第二表面，導電墊係位於第一表面之上，第一導線與第一導電通道結構係位於絕緣結構內且相互電性連接，且第一導電通道結構的一第一寬度係沿著遠離第一表面的一方向減少。前述方法包括將一電子元件接合至導電墊。前述方法包括從絕緣結構的第二表面移除一部分的絕緣結構。在移除部分的絕緣結構之後，第一導電通道結構的一第一端部突出於第二表面。前述方法包括將一晶片結構經由一第一導電凸塊接合至第一導電通道結構的第一端部。
在一些實施例中，第一導電通道結構的第一端部係位於第一導電凸塊內且直接接觸第一導電凸塊。
在一些實施例中，轉接板更包括一第二導線以及一第二導電通道結構，第二導線以及第二導電通道結構係位於絕緣結構中且彼此連接，第二導電通道結構的一第二寬度係沿著遠離第一表面的方向減少，且在移除絕緣結構的部分之後，第二導電通道結構的一第二端部突出於第二表面，以及第二導電通道結構比第一導電通道結構寬。
在一些實施例中，形成封裝結構的方法更包括：在第二導電通道結構的第二端部上形成一第二導電凸塊，其中第二導電凸塊比第一導電凸塊寬；以及藉由第二導電凸塊將轉接板接合至一線路基板。
在一些實施例中，形成封裝結構的方法更包括：在移除部分的絕緣結構之後且在將晶片結構接合至第一導電通道結構的第一端部之前，在絕緣結構的第二表面上形成一絕緣層，其中絕緣層具有一開口暴露出第一端部，且第一導電凸塊係位於開口內。
在一些實施例中，形成封裝結構的方法更包括：在移除部分的絕緣結構之後且在將晶片結構接合至第一導電通道結構的第一端部之前，在絕緣結構的第二表面上形成一絕緣層，其中絕緣層具有暴露出第一端部的一開口；以及在開口中形成一導電柱，其中第一導電凸塊係接合至導電柱。
以上概述數個實施例之元件，使本技術領域中具有通常知識者可以更加理解本發明實施例的各個面向。本技術領域中具有通常知識者應該理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優點。本技術領域中具有通常知識者也應該理解到，此類等效的結構並未悖離本發明實施例的精神與範圍，而且他們能在不違背本發明實施例的精神和範圍下，做各式各樣的改變、取代、和調整。
100,100A,100B,100C,100D,100E:晶片封裝體 110:載板 120:轉接板 121:絕緣結構 121a,121b,121c,121d,310:絕緣層 121a1,121a2,121b1,121c1,121d1:通孔 121e,121f,121a3:表面 122,123,124,125,264:線路層 122a,122c,123a,124a,264a:導線 122b,122d,123b,124b,125b:導電通道結構 122b1,122d1:端部 125a:導電墊 130A,130B:晶片結構 130C:電子元件 140:導電凸塊 132:基板 134:元件層 136:內連線層 132a,232a:底面 134a,261:介電層 134b,262,266:導電墊 136:內連線層 140,220,240:導電凸塊 150,250,270:底填層 160:封膠層 G1,G2:間隙 131A、131B、131C,162:頂面 170:載板 180:晶種層 190,410,430:罩幕層 192,312,314,412,432:開口 200,200A,200B,200C,200D,200E:封裝結構 210,420,440:導電層 211:突出部分 212,234,442,514,516:導電柱 213,267,268,441:凹槽 220a,450a:焊料層 230A,230B:電子元件 232,512:主要部分 242:合金層 244:主體部分 260:線路基板 264b:導電通孔 280:導電凸塊 422,422a,422b:導電結構 510:電子元件 A:框架（或載體） B:預定切割線 B1,D1:端面 B2,D2:側壁 C,C1:連接結構 C’:中央區 D231,D232,D234,D260:距離 D312:深度 P:外圍區域 R,R512:區域 R1:第一區域 R2:第二區域 S242:弧形的凸頂表面 T122b1,T212,T220,T240,T422:厚度 V1:方向 W1,W2,W3,W4,W122b,W122d,W123b,W124b,W125b,W240,W422U,W422L:寬度
藉由以下的詳細描述配合所附圖式，可以更加理解本發明實施例的內容。需強調的是，根據產業上的標準慣例，許多部件並未按照比例繪製。事實上，為了能清楚地討論，各種部件的尺寸可能被任意地增加或減少。 第1A～1L圖是根據一些實施例之用於形成封裝結構的製程的各個階段的剖面圖。 第1J-1圖是根據一些實施例之第1J圖的封裝結構的一區域的放大剖面圖。 第2A～2F圖是根據一些實施例之用於形成封裝結構的製程的各個階段的剖面圖。 第2E-1圖是根據一些實施例之第2E圖的封裝結構的一區域的放大剖面圖。 第3A圖是根據一些實施例之封裝結構的剖面圖。 第3B圖是根據一些實施例之第3A圖的封裝結構的一第一區域的放大剖面圖。 第3C圖是根據一些實施例之第3A圖的封裝結構的一第二區域的放大剖面圖。 第4A～4D圖是根據一些實施例之用於形成封裝結構的製程的各個階段的剖面圖。 第4D-1圖是根據一些實施例之第4D圖的封裝結構的一區域的放大剖面圖。 第5A圖是根據一些實施例之封裝結構的剖面圖。 第5B圖是根據一些實施例之第5A圖的封裝結構的一區域的放大剖面圖。 第5C圖是根據一些實施例之第5A圖的一區域中的導電結構的底視圖。 第6圖是根據一些實施例之封裝結構的剖面圖。
100:晶片封裝體
120:轉接板
121a:絕緣層
121f:表面
122,123,124,125,264:線路層
122b,122d:導電通道結構
125a:導電墊
130A,130B:晶片結構
130C:電子元件
132:基板
140:導電凸塊
200:封裝結構
212,234:導電柱
220,240:導電凸塊
230A,230B:電子元件
250,270:底填層
260:線路基板
261:介電層
262,266:導電墊
264a:導線
264b:導電通孔
267,268:凹槽
280:導電凸塊
D234:距離

Claims (9)

  1. 一種封裝結構，包括：一轉接板，包括一絕緣結構、一導電墊、一第一導線、以及一第一導電通道結構，其中該絕緣結構具有一第一表面以及與該第一表面相對的一第二表面，該導電墊位於該第一表面之上，該第一導線位於該絕緣結構內且電性連接該導電墊，該第一導電通道結構係部分位於該絕緣結構內並連接該第一導線，該第一導電通道結構的一第一端部突出於該絕緣結構的該第二表面，且該第一導電通道結構的一第一寬度係沿著遠離該第一表面的一方向減少，其中該第一導電通道結構的該第一端部具有一弧形的凸面；一電子元件接合至該導電墊；一晶片結構接合至該第一導電通道結構的該第一端部；以及一第一導電凸塊連接於該晶片結構與該第一導電通道結構的該第一端部之間，其中該第一端部延伸入該第一導電凸塊內並直接接觸該第一導電凸塊。
  2. 如請求項1之封裝結構，其中該絕緣結構包括一第一絕緣層以及一第二絕緣層，該第一導線位於該第一絕緣層上，該第一導電通道結構貫穿該第一絕緣層，該第二絕緣層係位於該第一絕緣層以及該第一導線上，該導電墊係位於該第二絕緣層上，以及該第一絕緣層比該第二絕緣層薄。
  3. 如請求項1-2中任一項之封裝結構，其中該轉接板更包括一第二導線以及一第二導電通道結構，該第二導線位於該絕緣結構內且電性連接該導電墊，該第二導電通道結構部分位於該絕緣結構內且連接該第二導線，該第二導電通道結構的一第二端部突出於該絕緣結構的該第二表面，該第二導電通道結構的一第二寬度係沿著遠離該第一表面的該方向減少，以及該第二導電通道 結構比該第一導電通道結構寬，以及該封裝結構更包括：一導電柱位於該第二導電通道結構的該第二端部之上；一第二導電凸塊位於該導電柱之上，其中該第二導電凸塊比該第一導電凸塊寬；以及一線路基板，其中該第二導電凸塊接合至該線路基板，以及該晶片結構係位於該轉接板與該線路基板之間，以及該晶片結構的一部分係位於該線路基板中。
  4. 一種封裝結構，包括：一轉接板，包括一絕緣結構、一導電墊、一第一導線、以及一第一導電通道結構，其中該絕緣結構具有一第一表面以及一第二表面，該導電墊位於該第一表面上，該第一導線與該第一導電通道結構係位於該絕緣結構內且彼此電性連接，該第一導電通道結構的一第一端部突出於該絕緣結構的該第二表面，且該第一導電通道結構的一第一寬度係沿著遠離該第一表面的一方向減少，其中該第一導電通道結構的該第一端部具有一弧形的凸面；一第一電子元件接合至該導電墊；一絕緣層位於該絕緣結構的該第二表面上；一第二電子元件位於該絕緣層上；以及一導電結構連接於該第二電子元件以及該第一導電通道結構的該第一端部之間並且貫穿該絕緣層，其中該導電結構與該第一導電通道結構共同形成一連接結構，且在該連接結構的一剖面圖中，該連接結構具有一沙漏狀。
  5. 如請求項4之封裝結構，其中該導電結構包括一導電柱，且該封裝結構更包括連接於該導電柱與該第二電子元件之間的一導電凸塊。
  6. 如請求項4-5中任一項之封裝結構，其中該第一導電通道結構的 該第一端部係位於該導電結構中。
  7. 一種形成封裝結構的方法，包括：提供一轉接板，其中該轉接板包括一絕緣結構、一導電墊、一第一導線以及一第一導電通道結構，該絕緣結構具有一第一表面以及與該第一表面相對的一第二表面，該導電墊係位於該第一表面之上，該第一導線與該第一導電通道結構係位於該絕緣結構內且相互電性連接，且該第一導電通道結構的一第一寬度係沿著遠離該第一表面的一方向減少；將一電子元件接合至該導電墊；從該絕緣結構的該第二表面移除一部分的該絕緣結構，其中在移除該部分的該絕緣結構之後，該第一導電通道結構的一第一端部突出於該第二表面，其中該第一導電通道結構的該第一端部具有一弧形的凸面；以及將一晶片結構經由一第一導電凸塊接合至該第一導電通道結構的該第一端部。
  8. 如請求項7之形成封裝結構的方法，其中該第一導電通道結構的該第一端部係位於該第一導電凸塊內且直接接觸該第一導電凸塊。
  9. 如請求項7-8中任一項之形成封裝結構的方法，其中該轉接板更包括一第二導線以及一第二導電通道結構，該第二導線以及該第二導電通道結構係位於該絕緣結構中且彼此連接，該第二導電通道結構的一第二寬度係沿著遠離該第一表面的該方向減少，且在移除該絕緣結構的該部分之後，該第二導電通道結構的一第二端部突出於該第二表面，以及該第二導電通道結構比該第一導電通道結構寬，以及該形成封裝結構的方法，更包括：在該第二導電通道結構的該第二端部上形成一第二導電凸塊，其中該第二導電凸塊比該第一導電 凸塊寬；以及藉由該第二導電凸塊將該轉接板接合至一線路基板。
TW111104503A 2021-05-13 2022-02-08 封裝結構及其形成方法 TWI808639B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202163188132P 2021-05-13 2021-05-13
US63/188,132 2021-05-13
US17/411,701 US20220367399A1 (en) 2021-05-13 2021-08-25 Package structure and method for forming the same
US17/411,701 2021-08-25

Publications (2)

Publication Number Publication Date
TW202245198A TW202245198A (zh) 2022-11-16
TWI808639B true TWI808639B (zh) 2023-07-11

Family

ID=83287752

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111104503A TWI808639B (zh) 2021-05-13 2022-02-08 封裝結構及其形成方法

Country Status (3)

Country Link
US (2) US20220367399A1 (zh)
CN (1) CN115101502A (zh)
TW (1) TWI808639B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201203483A (en) * 2010-07-13 2012-01-16 Taiwan Semiconductor Mfg Recessed pillar structure and manufacturing method thereof
TW201810458A (zh) * 2016-05-23 2018-03-16 恆勁科技股份有限公司 封裝基板及其製法
TW201919165A (zh) * 2017-10-31 2019-05-16 台灣積體電路製造股份有限公司 形成晶片封裝體的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653443B2 (en) * 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
JP6816964B2 (ja) * 2016-03-10 2021-01-20 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
KR20220021615A (ko) * 2020-08-14 2022-02-22 삼성전자주식회사 반도체 패키지

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201203483A (en) * 2010-07-13 2012-01-16 Taiwan Semiconductor Mfg Recessed pillar structure and manufacturing method thereof
TW201810458A (zh) * 2016-05-23 2018-03-16 恆勁科技股份有限公司 封裝基板及其製法
TW201919165A (zh) * 2017-10-31 2019-05-16 台灣積體電路製造股份有限公司 形成晶片封裝體的方法

Also Published As

Publication number Publication date
CN115101502A (zh) 2022-09-23
TW202245198A (zh) 2022-11-16
US20240047401A1 (en) 2024-02-08
US20220367399A1 (en) 2022-11-17

Similar Documents

Publication Publication Date Title
US11670577B2 (en) Chip package with redistribution structure having multiple chips
US9728496B2 (en) Packaged semiconductor devices and packaging devices and methods
US10629580B2 (en) Packaging mechanisms for dies with different sizes of connectors
CN116072551A (zh) 形成封装结构及管芯的方法
JP6076020B2 (ja) 半導体装置及び半導体装置の製造方法
TW201947711A (zh) 晶片封裝結構
CN104299920A (zh) 形成封装结构的机制
TWI727879B (zh) 封裝結構及製作所述封裝結構的方法
US7122748B2 (en) Semiconductor device having packaging structure
CN113809040A (zh) 封装结构及其制作方法
US20230307381A1 (en) Chip package structure
CN112530913A (zh) 封装结构及其制造方法
US11855039B2 (en) Chip package structure
TWI769888B (zh) 封裝結構
KR102634695B1 (ko) 링 구조물을 갖는 칩 패키지 구조물 및 이의 형성 방법
TWI756907B (zh) 封裝結構及其製作方法
US20230369274A1 (en) Integrated circuit package and method of forming same
TWI808639B (zh) 封裝結構及其形成方法
US11450588B2 (en) Method for forming chip package structure with heat conductive layer
US11764168B2 (en) Chip package structure with anchor structure and method for forming the same
US20230011353A1 (en) Chip package structure and method for forming the same
US20240203918A1 (en) Chip stack structure with conductive plug and method for forming the same
TWI792982B (zh) 封裝結構及其形成方法
US20240038642A1 (en) Semiconductor package
TW202310314A (zh) 探針頭結構