TWI804960B - Method for manufacturing memory, and capacitor - Google Patents

Abstract

A method for manufacturing a memory includes forming a first interconnection structure, wherein the first interconnection structure includes a capacitor conductive column, a bit line conductive column, and a first dielectric layer between the capacitor conductive column and the bit line conductive column; forming a first bit line conductive plug, wherein the first bit line conductive plug includes a metal conductive column electrically connected to the bit line conductive column and a second dielectric layer around the metal conductive column; sequentially forming a third dielectric layer and a hard mask layer; patterning hard mask layer;etching the second dielectric layer and the third dielectric layer using the patterned hard mask layer as a mask to form a deep hole; removing the patterned hard mask layer so that the deep hole exposes the capacitor conductive column; forming a first electrode layer; forming a highdielectric constant ferroelectric oxide layer and a second electrode layer; and forming a metal connection portion, a plate line, and a bit line.

Description

Manufacturing method of memory and capacitor

. The present invention relates to the technical field of memory. Specifically, the present invention relates to a manufacturing method of a memory and a capacitor.

. Ferroelectric memory is a non-volatile memory made with a special process. When an electric field is applied to a ferroelectric crystal, the central atom stops in the first low-energy state position along the electric field, and when an electric field reversal is applied to the same ferroelectric crystal, the central atom moves in the crystal along the direction of the electric field and Stop in the second lowest energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarized charges under the action of an electric field. The polarization charge formed by the ferroelectric domain reversal under the electric field is higher, and the polarization charge formed by the ferroelectric domain without reversal under the electric field is lower. The binary stable state of this ferroelectric material makes ferroelectricity can be used as Memory.

. When the electric field is removed, the central atom stays in a low-energy state and remains unchanged, and the state of the memory is preserved and will not disappear. Therefore, the ferroelectric domain can be used to reverse under the electric field to form a high polarization charge, or without reversal to form a low Polarization charges are used to determine whether the memory cell is in the "1" or "0" state. The inversion of ferroelectric domain does not require high electric field, only general working voltage can change the state of memory cell is "1" or "0"; it also does not need charge pump to generate high voltage data erasing, so there is no erasing write delay phenomenon. This feature enables the ferroelectric memory to continue to save data after power failure, has a fast writing speed and has an unlimited writing life, and is not easy to write to damage. Moreover, compared with the existing non-volatile memory technology, the ferroelectric memory has a higher write speed and a longer read and write life.

. FIG. 1 shows a schematic circuit diagram of an exemplary ferroelectric memory cell 100. Ferroelectric memory cell 100 is a memory element of ferroelectric memory and can include various designs and configurations. As shown in FIG. 1 , the ferroelectric memory cell 100 is a “1T-1C” cell, which includes a capacitor 12 and a transistor 14 . Transistor 14 is an NMOS transistor. The source S of transistor 14 is electrically connected to bit line BL. The gate of transistor 14 is electrically connected to word line WL. The drain D of the transistor 14 is electrically connected to the lower electrode 16 of the capacitor 12 . The upper electrode 18 of the capacitor 12 is connected to the plate line PL.

. FIG. 2 shows a perspective view of an exemplary ferroelectric memory unit 100. In order to ensure that a strong signal can be obtained when the polarization of the ferroelectric capacitor of the ferroelectric memory unit 100 changes, the area of the ferroelectric capacitor must be large enough. As shown in FIG. 2 , the existing planar capacitor 12 occupies a relatively large area, which limits the integration of the ferroelectric memory unit.

. The purpose of the present invention is to provide a method of manufacturing memory and capacitors to improve the integration of ferroelectric memory and reduce the cost of ferroelectric memory chips.

. According to one embodiment of the present invention, a method of manufacturing a memory is provided, including: A semiconductor substrate is provided, the semiconductor substrate includes a ferroelectric memory cell area, and the ferroelectric memory cell area has a source area, a drain area, a gate area, a spacer area, and electrodes and interconnection metal lines above each functional area; forming a first interconnection structure, the first interconnection structure including capacitor conductive pillars, bit line conductive pillars, and a first dielectric layer between the conductive pillars; forming a first bit line conductive plug, the first bit line conductive plug includes a metal conductive column electrically connected to the bit line conductive column and a second dielectric layer between the metal conductive column; sequentially forming a third dielectric layer and a hard mask layer; The hard mask layer is patterned by photolithography and etching processes, and the patterned hard mask layer is used as a mask for etching to form deep holes in the second dielectric layer and the third dielectric layer, and then remove the hard mask layer. a mask layer, the bottom of the deep hole exposes the conductive column of the capacitor; forming a first electrode layer; forming a high dielectric constant ferroelectric oxide layer and a second electrode layer; and Metal interconnects, platelines and bitlines are formed.

. In one embodiment of the present invention, forming the first electrode layer includes: depositing the first electrode layer; and removing the first electrode layer on the top surface of the third dielectric layer, leaving only the first electrode layer on the bottom and sides of the deep hole.

. In one embodiment of the present invention, the manufacturing method of the memory further includes: after forming the high dielectric constant ferroelectric oxide layer and the second electrode layer, depositing tungsten metal, and then removing the third dielectric layer by chemical instrument grinding The tungsten metal, the high dielectric constant ferroelectric oxide layer and the second electrode layer on the top surface only retain the tungsten metal, the high dielectric constant ferroelectric oxide layer and the second electrode layer in the deep hole.

. In one embodiment of the present invention, forming the metal interconnection, the plate line and the bit line includes: forming a fourth dielectric layer on the top surface of the third dielectric layer; drilling holes on the fourth dielectric layer and forming a conductive structure, The conductive structure is electrically connected to the second electrode layer and the first bit line conductive plug respectively; a plate line is formed above the conductive structure, and the plate line is electrically connected to the second electrode layer; and a bit line is formed above the plate line. line and an external pad, and the bit line is electrically connected to the first bit line conductive plug.

. In one embodiment of the present invention, the manufacturing method of the memory further includes: after forming the high dielectric constant ferroelectric oxide layer and the second electrode layer, removing part of the first part of the top surface by photolithography, etching and other processes An electrode layer, a high dielectric constant ferroelectric oxide layer and a second electrode layer, only the first electrode layer, the high dielectric constant ferroelectric oxide layer and the second electrode layer around the sidewall, bottom and top of the deep hole are reserved, Thus making each capacitor separate from each other.

. In one embodiment of the present invention, forming the metal interconnection, the plate line and the bit line includes: forming a fourth dielectric layer on the top surface of the third dielectric layer; drilling holes on the fourth dielectric layer and forming a conductive structure, The conductive structures are respectively electrically connected to the second electrode layer and the first bit line conductive plug, wherein the conductive structure electrically connected to the second electrode layer extends from the second electrode layer at the bottom of the deep hole to the top of the fourth dielectric layer, or A conductive structure electrically connected to the second electrode layer extends from the second electrode layer around the top of the deep hole to the top of the fourth dielectric layer; a plate line is formed above the conductive structure, and the plate line is electrically connected to the second electrode layer; And forming a bit line and an external pad above the plate line, the bit line is electrically connected to the first bit line conductive plug.

. In one embodiment of the present invention, the manufacturing method of the memory further includes: after forming the deep hole and removing the hard mask layer, expanding the top of the deep hole to form the expanded hole, the expanded hole is located at the bottom of the deep hole The top and the cross-sectional area is larger than the cross-sectional area of the deep hole.

. In one embodiment of the present invention, forming the first electrode layer includes: depositing the first electrode layer; removing the first electrode layer on the top surface of the third dielectric layer, the sidewall and the bottom of the expanded hole, and only retaining the deep hole below the expanded hole The first electrode layer on the bottom and side; forming a high dielectric constant ferroelectric oxide layer and a second electrode layer, so that the second electrode layer completely fills the deep hole and expands the hole; and removes the third electrode layer by chemical mechanical grinding. A high dielectric constant ferroelectric oxide layer and a second electrode layer on the top surface of the dielectric layer.

. In one embodiment of the present invention, the second dielectric layer and the third dielectric layer are formed individually or in combination by stacking at least two different insulating materials, and the method further includes forming the deep hole and removing the hard mask After the layer, the sidewalls of the deep hole are processed by wet etching that has different etch rates for at least two different insulating materials, thereby forming one or more protrusions on the sidewalls of the deep hole.

. According to another embodiment of the present invention, a memory capacitor is provided, comprising: A semiconductor substrate, the semiconductor substrate includes a ferroelectric memory unit area, the ferroelectric memory unit area has a source area, a drain area, a gate area, a spacer area, and electrodes and interconnected metal lines above each functional area, A first interconnection structure disposed above the semiconductor substrate, the first interconnection structure comprising capacitor conductive pillars, bit line conductive pillars, and a first dielectric layer between the conductive pillars; A first bit line conductive plug, the first bit line conductive plug includes a metal conductive column electrically connected to the bit line conductive column and a second dielectric layer between the metal conductive columns; a third dielectric layer stacked on the second dielectric layer; deep holes formed in the second dielectric layer and the third dielectric layer, the deep holes exposing the conductive pillars of the capacitor; sequentially depositing a first electrode layer, a high-k ferroelectric oxide layer, and a second electrode layer on the sidewalls and bottom of the deep hole; and A plate line and a bit line, the plate line is connected to the second electrode layer through the metal interconnection, and the bit line is connected to the first bit line conductive plug through the metal interconnection.

. In another embodiment of the present invention, the second dielectric layer and the third dielectric layer are formed by stacking at least two different insulating materials alone or in combination, and the sidewall of the deep hole has one or more raised.

. In another embodiment of the present invention, the capacitor of the memory also includes a reaming hole formed by etching the top of the deep hole, the reaming hole is located at the top of the deep hole and has a cross-sectional area greater than that of the deep hole, so The first electrode layer is only arranged on the bottom and side of the deep hole below the expanded hole, and the high dielectric constant ferroelectric oxide layer and the second electrode layer are formed on the sidewall and bottom of the deep hole and the expanded hole.

. In the manufacturing method of the memory provided by the present invention and the capacitor, by forming a plurality of deep holes, the lower electrode layer, the ferroelectric material layer and the upper electrode layer of the capacitor are sequentially formed in each deep hole, and at the same time, between the capacitor A bit line is formed between them, and the bit line is extended to the capacitor, realizing a three-dimensional ferroelectric capacitor. This structure of the present invention is also referred to as a Ferroelectric Capacitor Under Bitline (FCUB). The lower electrode and the upper electrode with a deep hole structure can significantly increase the equivalent remanent polarization strength of the ferroelectric capacitor under the same facing area, so that the ferroelectric memory can continue to be scaled down while still providing a large enough The voltage window is lower than the 130nm process node, which can realize the three-dimensionalization of ferroelectric capacitors and increase the storage density of ferroelectric capacitors.

. The manufacturing method of the memory of the present invention is completely compatible with the CMOS process, which facilitates integration and reduces manufacturing costs.

. In the following description, the present invention is described with reference to various embodiments. One skilled in the art will recognize, however, that the various embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the various embodiments of the invention. Similarly, for purposes of explanation, specific quantities, materials and configurations are set forth in order to provide a thorough understanding of embodiments of the invention. However, the invention may be practiced without these specific details. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

. In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

. In general terms can be understood at least in part according to the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or any combination of features, structures or characteristics in the plural, depending at least in part on the context. Similarly, terms such as "a", "an", or "the" may in turn be understood to express singular usage or to express plural usage, depending at least in part on the context.

. It will be readily understood that the meanings of "on", "over", and "above" in the present invention should be interpreted in the broadest manner such that "on ” not only refers to being directly on something, but can also include being on something with an intermediate feature or intermediate layer in between, and “over” or “over” Not only means being on or over something, but can also include being on or over something without an intervening feature or layer in between (ie directly on something).

. In addition, space-related terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein for convenience in describing an element or feature The relationship shown in a drawing with respect to another element or feature. Spatially relative terms are intended to cover other orientations of the device in use or operation in addition to the orientation of the device as depicted in the figures. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

. The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself can be patterned. Materials added over the substrate can be patterned, or can remain unpatterned. In addition, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may also be made of an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

. The term "layer" as used herein refers to a portion of material comprising a region having a thickness. A layer may extend over all of the underlying or overlying structure, or may have less extension than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes, or at the top or bottom of the continuous structure. Layers may extend horizontally, vertically, and/or along the tapered surface. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or one or more layers thereon. A layer may include multiple layers. For example, interconnect layers may include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

. FIGS. 3A to 3O show cross-sectional views of a process of forming a capacitor of a ferroelectric memory cell according to an embodiment of the present invention. FIG. 4 shows a flow diagram of forming a capacitor for a ferroelectric memory cell according to one embodiment of the present invention. The process of forming the capacitor of the ferroelectric memory unit is described with reference to FIG. 3A to FIG. 3O and FIG. 4 .

. First, in step 410, a semiconductor substrate 310 is provided, as shown in FIG. 3A. The semiconductor substrate 310 may have completed the manufacturing process of the functional region. For example, the semiconductor substrate 310 includes a circuit region 311 and a ferroelectric memory cell region 312 . The circuit region 311 and the ferroelectric memory unit region 312 have been formed with source regions, drain regions (not shown in the figure), gate regions 313, spacer regions 314, electrodes and interconnection metal lines above each functional region of the device (Fig. not shown). In order to clarify and simplify the description of the present invention, in FIG. 3A, only part of the circuit region 311 and the ferroelectric memory cell region 312 are shown. The circuit area 311 can be used to control the ferroelectric memory cell area 312 .

. Next, in step 420, a first interconnection structure is formed on the semiconductor substrate 310. As shown in FIG. 3B, in one embodiment of the present invention, forming the first interconnection structure may include: forming a dielectric layer 321 on the surface of the substrate; forming a via hole in the dielectric layer 321 through processes such as via lithography and etching. , the through hole exposes the external electrodes of each functional area on the semiconductor substrate 310; an adhesive layer and a tungsten metal layer are sequentially deposited to fill the through hole; finally, a chemical mechanical polishing process is performed to remove the excess dielectric layer 321, the adhesive layer and the tungsten The metal layer forms a plurality of tungsten conductive pillars extending from the surface electrodes of the semiconductor substrate 310 to the top surface of the dielectric layer 321 . In the specific embodiment shown in FIG. 3B , titanium nitride can be formed as an adhesive layer (not shown in the figure) between the tungsten conductive pillar and the surface electrode of the semiconductor substrate 310 and between the tungsten conductive pillar and the dielectric layer. The plurality of tungsten conductive pillars may include circuit conductive pillars 323, capacitor conductive pillars 324, bit line conductive pillars 325, and the like. The circuit conductive column 323 is connected to the surface electrode of the circuit area 311, the capacitor conductive column 324 is used to electrically connect the doped region (source or drain) of the transistor in the ferroelectric memory cell area 312 with the capacitor, and the bit line conductive column 325 It is used to electrically connect another doped region (drain or source) of the transistor of the ferroelectric memory cell region 312 to the bit line.

. In an embodiment of the present invention, the dielectric layer 321 can be silicon oxide, silicon oxynitride, borosilicate glass, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated glass silicate Inorganic materials such as salt glass (FSG) or low dielectric constant dielectric; it can also be polyimide, photosensitive epoxy resin, solder resist ink, green paint, dry film, photosensitive build-up material, diphenylcyclobutene Organic materials such as resin (BCB) or phenylbenzobisoxazole resin (PBO). The dielectric layer can be produced by chemical vapor deposition, rolling, spin coating, spray coating, printing, non-spin coating, hot pressing, vacuum lamination, soaking or pressure lamination. The dielectric layer 321 can be a single material layer, or a composite material layer formed by laminating multiple layers of materials.

. Those skilled in the art should understand that the method for forming the first interconnection structure is not limited to the above specific examples. In addition, other processes may be performed before or after the formation of the first interconnection structure, for example, forming one or more other conductive interconnection structures.

. Then, in step 430, a first bit line conductive plug is formed, as shown in FIG. 3C. In one embodiment of the present invention, forming the first bit line conductive plug may include forming a dielectric layer 331 on the surface of the first interconnection structure; forming a via hole in the dielectric layer 331 through a process such as via photolithography and etching, The through hole exposes the top surface of the bit line conductive pillar 325; sequentially deposits an adhesive layer and a tungsten metal layer to fill the through hole; finally performs a chemical mechanical polishing process to remove the excess dielectric layer 331 and the tungsten metal layer to form a slave bit line The top surface of the conductive column 325 extends to the tungsten conductive column on the top surface of the dielectric layer 331 as the first bit line conductive plug 332 . Simultaneously with the formation of the first bit line conductive plug, a tungsten conductive column electrically connected to the circuit conductive column 323 may be formed above the circuit region 311 , so that the circuit conductive column 323 extends to the top surface of the dielectric layer 331 .

. In an embodiment of the present invention, the dielectric layer 331 can be the same material as the dielectric layer 321, or it can be a different material from the dielectric layer 321.

In actual operation, one or more dielectric layers and the first bit line conductive plug 341 located in the dielectric layer can be repeatedly formed, as shown in FIG. 3D, so as to form the first bit line conductive plug with the required height Plug 341. Likewise, while forming the first bit line conductive plug 341 with one or more layers of structure in the memory cell region, one or more layers of tungsten conductive pillars electrically connected to the circuit conductive pillars 323 are formed above the circuit region 311 . In the example shown in FIG. 3D, the first bit line conductive plug 341 has a two-layer tungsten conductive column structure, but those skilled in the art should understand that in other embodiments of the present invention, the first bit line conductive plug 341 There may be only one layer of tungsten conductive column structure, or three or more layers of tungsten conductive column structure. The dielectric materials used in each layer structure of the first bit line conductive plug 341 may be the same or different.

Next, in step 440, a dielectric layer 351, a carbon layer 352 and a silicon oxynitride layer 353 are sequentially formed as a hard mask for deep hole etching, as shown in FIG. 3E. In the embodiment of the present invention, the process and size of the dielectric layer 351 , the carbon layer 352 and the silicon oxynitride layer 353 can be selected according to specific requirements.

. In step 450, the capacitor deep hole 361 is formed by an etching process, and the carbon layer 352 and the silicon oxynitride layer 353 are removed, as shown in FIG. 3F. In an embodiment of the present invention, forming the capacitor deep hole 361 through an etching process may include forming a window in the silicon oxynitride layer 353 to expose the underlying carbon layer 352 through a photolithography process, and using the silicon oxynitride layer 353 as a mask to etch Etch the carbon layer 352 to form a window to expose the lower dielectric layer 351, use the carbon layer 352 as a mask to etch the dielectric layers 351, 342 and 331 until the top of the capacitor conductive column 324 is exposed, and finally remove the carbon layer 352 and the silicon oxynitride layer 353 . The diameter of the bottom of the capacitor deep hole is greater than the size of the top of the capacitor conductive post 324 . In some embodiments, when etching the deep hole, the etching stops when the capacitor conductive pillar 324 is etched, but the dielectric layer around the conductive pillar 324 continues to be etched downward, forming a depression around the capacitor conductive pillar.

. In step 460, a first electrode layer 371 is formed on the bottom and sidewalls of the capacitor deep hole 361. The first electrode layer 371 is an electrode layer of a capacitor, for example, it can be one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), titanium aluminum nitride (TiAlNx ), titanium carbonitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), tungsten carbonitride (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), doped polysilicon, transparent conductive oxide (Transparent Conductive Oxide, TCO) or iridium oxide (IrOx) or a composite of these materials. Through atomic layer deposition (atomic layer deposition, ALD), chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), electron beam (electron beam) evaporation deposition, molecular beam epitaxy The first electrode layer 371 is deposited by one or more processes of molecular beam epitaxy (MBE) deposition, pulsed laser deposition (PLD) and similar deposition processes, as shown in FIG. 3G . Then the material layer on the top surface of the dielectric layer is removed, and only the material layer on the bottom and sides of the capacitor deep hole 361 remains, as shown in FIG. 3H .

. In step 470, a high dielectric constant ferroelectric oxide layer 381 and a second electrode layer 382 are formed, as shown in FIG. 3I. The high dielectric constant ferroelectric oxide layer 381 is the dielectric layer of the capacitor, for example, it can be one or more of the following materials: the ferroelectric material includes oxygen and one or more ferroelectric metals, and the ferroelectric metal includes zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), nickel (Ni) and/or iron (Fe), etc., and ferroelectric materials can be doped with group II elements (such as calcium (Ca), strontium (Sr) or barium (Ba)); group III elements (such as scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga), and indium (In)); and lanthanides (ie, Lanthanum (La), cerium (Ce), 鐠 (Pr), neodymium (Nd), 鉕 (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), 鋱 (Tb), dysprosium (Dy), ™ (Ho), erbium (Er), 銩 (Tm), ytterbium (Yb), 鑥 (Lu)) or a composite of these materials. Atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam (electron beam) evaporation deposition, molecular beam epitaxy (MBE) deposition, pulsed laser deposition (PLD) ) and one or more of similar deposition processes to deposit the first deposition layer. The second electrode layer 382 is another electrode layer of the capacitor, for example, it can be one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), titanium aluminum nitride ( TiAlNx), titanium carbonitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), carbonitride Tungsten (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), doped polysilicon, transparent conductive oxide (TCO) or iridium oxide (IrOx) or composites of these materials. Atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam (electron beam) evaporation deposition, molecular beam epitaxy (MBE) deposition, pulsed laser deposition (PLD) ) and one or more of similar deposition processes to deposit the second electrode layer 382 .

. In step 480, the tungsten metal 391 is filled, as shown in FIG. 3J , and then the tungsten metal 391, the high dielectric constant ferroelectric oxide layer 381 and the second electrode layer 382 on the top surface of the dielectric layer 351 are removed by chemical instrument grinding, As shown in FIG. 3K , only the tungsten metal 391 , the high-k ferroelectric oxide layer 381 and the second electrode layer 382 in the capacitor deep hole 361 remain.

. Next, in step 490, metal interconnects, plate lines and bit lines are formed. In one embodiment of the present invention, forming metal interconnections, plate lines and bit lines may include: first forming a layer of dielectric layer 392 on the top surface of dielectric layer 351, as shown in FIG. 3L ; drilling holes on dielectric layer 392 And form a plurality of conductive columns 390, the conductive columns 390 are connected to the tungsten metal 391, the circuit conductive column 323 and the first bit line conductive plug 341, as shown in Figure 3M; and then form a layer of dielectric layer 395 on the dielectric layer 392 , etch openings on the dielectric layer 395, deposit metal copper in the openings to form metal lines, as plate lines 393, and form metal interconnections 394, as shown in FIG. 3N; then form on the dielectric layer 395 Dielectric layer 396, and then grooves are made on the dielectric layer 396, and then metal copper is deposited in the grooves to form metal lines as bit lines 397, as shown in FIG. 3O. So far, the ferroelectric capacitors, plate lines and bit lines of the memory are formed, and then the dielectric layer, metal interconnection and other metal layers are formed above the plate lines and bit lines to form external connections. Explain in detail.

. The dielectric layer 392 can be the same material as the dielectric layer 321, or it can be a different material from the dielectric layer 321.

. In the foregoing embodiments, the dielectric layer 321 forming the first interconnection structure can be called the first dielectric layer, and the dielectric layers 331, 342, and 351 forming the ferroelectric capacitor can be collectively referred to as the second dielectric layer, covering the ferroelectric capacitor. The dielectric layer 392 may be referred to as a third dielectric layer, the dielectric layer 395 above the third dielectric layer may be referred to as a fourth dielectric layer, and the dielectric layer 396 above the fourth dielectric layer 395 may be referred to as a fifth dielectric layer.

. In the above embodiment, the manufacturing process of the metal interconnection in the peripheral circuit area 311 is combined with the manufacturing process of the capacitor and the metal interconnection in the ferroelectric memory cell area 312, so that the peripheral circuit area 311 is completed at the same time as the capacitor is formed Interconnecting with the metal part of the ferroelectric memory cell region 312 and leading it out is beneficial to simplify the process steps and reduce the manufacturing cost.

. After the deposition of the metal-insulator-metal (MIM) film of the ferroelectric capacitor, it will be planarized by a chemical mechanical polishing process, and the MIM film outside the deep hole will be removed to form an independent ferroelectric capacitor structure, as shown in Figure 5, through the planarization process, metal ions are likely to remain at the circle marks in Figure 5, resulting in leakage of the upper and lower electrodes. The direct short circuit of the electrodes; therefore, the embodiment of FIG. 6 to FIG. 8 proposes a new solution for the above problems.

. Figure 6 shows a flow chart of forming a capacitor for a ferroelectric memory cell according to one embodiment of the present invention. In the embodiment shown in FIG. 6 , steps 610 to 650 are similar to steps 410 to 450 shown in FIG. 4 above, and detailed descriptions of steps 610 to 650 are omitted for simplicity of description.

. In step 660, a first electrode layer 711, a high dielectric constant ferroelectric oxide layer 712 and a second electrode layer 713 are sequentially formed, as shown in FIG. 7A. The materials and formation process of the first electrode layer 711, the high dielectric constant ferroelectric oxide layer 712 and the second electrode layer 713 are the same as those of the above-mentioned first electrode layer, high dielectric constant ferroelectric oxide layer and the second electrode layer. The forming process is similar, so it will not be described in detail.

. In step 670, fill the dielectric layer, and then remove part of the first electrode layer 711, high dielectric constant ferroelectric oxide layer 712 and second electrode layer 713 on the top surface by photolithography, etching and other processes, leaving only deep holes 714 sidewall, bottom and surrounding first electrode layer 711 , high dielectric constant ferroelectric oxide layer 712 and second electrode layer 713 , so that each capacitor is separated from each other, as shown in FIG. 7B . FIG. 8 shows a schematic perspective view of separated capacitor units after photolithography and etching in step 670 according to an embodiment of the present invention. As shown in the figure, different from the traditional planar capacitor, the capacitor has a three-dimensional structure.

. Next, in step 680, metal interconnects, plate lines and bit lines are formed. In an embodiment of the present invention, forming metal interconnections, plate lines and bit lines may include forming a dielectric layer 715, as shown in FIG. 7C, drilling holes in the dielectric layer 715, and forming a plurality of conductive columns 731, 732, 733, the conductive columns 731, 732, 733 are respectively connected to the second electrode layer 713, the circuit conductive column 716 and the first bit line conductive plug 717, wherein the conductive column 731 connected to the second electrode layer 713 is located at the center of the capacitor . In the embodiment shown in FIG. 7C , the conductive pillar 731 extends from the bottom of the capacitor well to the top of the dielectric layer 715 . In another embodiment of the present invention, the conductive column 731 connected to the second electrode layer 713 of the capacitor can be disposed at the top edge of the deep hole of the capacitor, as shown in FIG. 7D . After forming the conductive post 731 connected to the second electrode layer of the capacitor, the remaining steps can refer to the step in FIG. 3N, using copper metal to form the plate line 393 connected to the conductive post 731, and then refer to the step in FIG. 3O to form a dielectric layer , and the bit line 397 connected to the conductive pillar 733 is formed with copper metal.

. Figure 9 shows a flow diagram of forming a capacitor for a ferroelectric memory cell according to one embodiment of the present invention. In the embodiment shown in FIG. 9, step 910 to step 950 and step 990 are similar to steps 410 to 450 and step 490 shown in FIG.

. In step 951, the top of the deep hole 101 is reamed, as shown in Figure 10A. Specifically, the top of the deep hole 101 may be reamed by dry etching to form the reamed hole 102 .

. In step 960, the first electrode layer 103 is formed, as shown in FIG. 10B. The first electrode layer 103 is the bottom electrode layer of the capacitor. Then remove the material layer on the top surface of the dielectric layer, the sidewall and bottom of the reamed hole, and only keep the material layer on the bottom and side of the deep hole 101 below the reamed hole, as shown in FIG. 10C .

. In step 970, a high dielectric constant ferroelectric oxide layer 104 and a second electrode layer 105 are formed, wherein the high dielectric constant ferroelectric oxide layer 104 completely covers the first electrode layer in the deep hole 101 and the expanded hole 102 The inner surface, as shown in Figure 10D. The second electrode layer 105 completely fills the deep hole 101 and the expanded hole 102 .

. In step 980, the redundant high dielectric constant ferroelectric oxide layer 104 and the second electrode layer 105 on the surface of the crystal substrate are ground away by means of chemical mechanical grinding, so as to form a ferroelectric capacitor structure, as shown in FIG. 10E.

. In step 990, a dielectric layer 106 is formed above the ferroelectric capacitor structure, a via hole is formed on the dielectric layer 106, and a conductive column 107 connected to the upper electrode of the ferroelectric capacitor structure is formed in the via hole. Then, metal interconnections, plate lines and bit lines are formed on the dielectric layer 106, as shown in FIG. 10F. For specific steps of forming metal interconnects, plate lines and bit lines, reference may be made to FIG. 3N and FIG. 3O , and the metal interconnects, plate lines and bit lines are formed in combination with the description of step 490 of the previous embodiment.

. Figures 11A and 11B show another embodiment of the present invention, which provides a method of forming a capacitor for a ferroelectric memory cell. In this embodiment, the method for forming the capacitor of the ferroelectric memory unit may be similar to the processes shown in FIG. 4 , FIG. 6 and FIG. 9 above. The main difference of this embodiment is that in the aforementioned embodiment shown in FIG. 3O, the dielectric layers 331, 342 and 351 are collectively referred to as the second dielectric layer, wherein the dielectric layers 331, 342 and 351 are formed by stacking at least two different insulating materials. , and after steps 450, 650 and 950, wet etching is added to process the sidewall of the deep hole of the capacitor to form one or more protrusions on the sidewall of the deep hole. FIG. 11A shows a schematic cross-sectional view of the capacitor deep hole after forming the capacitor deep hole through an etching process and removing the carbon layer and the silicon oxynitride layer according to an embodiment of the present invention. As shown in FIG. 11A , the second dielectric layer includes three first insulating material layers 111 and two second insulating material layers 112 , and each first insulating material layer 111 and second insulating material layer 112 are stacked alternately in sequence. When forming the deep hole of the ferroelectric capacitor structure, the deep hole 113 whose sidewall is flush as shown in FIG. 11A is formed first. After the structure of FIG. 11A is formed by etching, wet etching is performed on the structure formed in FIG. 11A . Through this wet etching process, the etching rates of different insulating materials in the dielectric layer are different, and different etching depths are formed, so that the degree of sidewall depression between different layers is different, and the protruding structure 114 between different layers is formed. . For example, the etching rate of the first insulating material layer 111 is lower than the etching rate of the second insulating material layer 112. After a certain time, the first insulating material layer 111 protrudes relative to the second insulating material layer 112, as shown in FIG. 11B Therefore, the area of the capacitor can be increased under the same aperture, and the ferroelectric performance can be improved. Then, deposit the lower electrode layer, the ferroelectric material layer and the upper electrode layer of the ferroelectric capacitance structure in the deep hole formed by the protruding structure 114 with different layers. For the specific steps, please refer to the aforementioned 460-490, 660- Description of steps 690 and 960-990. Those skilled in the art should understand that the second dielectric layer used to be formed in the deep hole of the ferroelectric capacitor structure is not limited to the three-layer first insulating material layer 111 and the two-layer second insulating material layer 112 shown in FIG. 11A Alternately stacked structure, the second dielectric layer used to form the deep hole of the ferroelectric capacitor structure can include a stacked structure of three or more insulating materials, and the thickness and position of each layer of insulating material can be set according to actual needs. The material used to form the second dielectric layer in the deep hole of the ferroelectric capacitor structure can be selected from: silicon oxide, silicon oxynitride, borosilicate glass, phosphosilicate glass (PSG), borophosphosilicate glass Inorganic materials such as (BPSG), fluorinated glass silicate glass (FSG) or low dielectric constant dielectric; it can also be polyimide, photosensitive epoxy resin, solder resist ink, green paint, dry film, photosensitive Build-up materials, organic materials such as bis-benzocyclobutene resin (BCB) or phenylbenzobisoxazole resin (PBO), or a combination thereof. The wet etching process may be etched with an acidic solution such as hydrochloric acid, phosphoric acid, or hydrofluoric acid.

. Although the aforementioned embodiments have introduced the steps of several embodiments, the steps described in the aforementioned different embodiments are not completely inseparable, and the specific steps and structures of each embodiment can also be replaced or combined with each other, and will not be repeated here One by one examples.

. In the manufacturing method of the memory provided by the present invention and the capacitor, by forming a plurality of deep holes, the lower electrode layer, the ferroelectric material layer and the upper electrode layer of the capacitor are sequentially formed in each deep hole, and at the same time, between the capacitor A bit line is formed between them, and the bit line is extended to the capacitor, realizing a three-dimensional ferroelectric capacitor. This structure of the present invention is also referred to as a Ferroelectric Capacitor Under Bitline (FCUB). The lower electrode and the upper electrode with a deep hole structure can significantly increase the equivalent remanent polarization strength of the ferroelectric capacitor under the same facing area, so that the ferroelectric memory can continue to be scaled down while still providing a large enough The voltage window of the 130 nm process node can realize the three-dimensionalization of ferroelectric capacitors and increase the storage density of ferroelectric capacitors.

. The manufacturing method of the memory of the present invention is completely compatible with the CMOS process, which facilitates integration and reduces manufacturing costs.

. While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the above-disclosed exemplary embodiments, but should be defined only in accordance with the appended patent claims and their equivalents.

. 4: Upper electrode 12: Capacitor 14: Transistor 16: Bottom electrode 18: Upper electrode 100: ferroelectric memory cell 101: deep hole 102: Reaming 103: The first electrode layer 104: ferroelectric oxide layer 105: Second electrode layer 106: medium layer 107: Conductive column 111: the first insulating material layer 112: the second insulating material layer 113: deep hole 114: Protruding structure 310: Semiconductor substrate 311: circuit area 312: Ferroelectric memory unit area 313: gate area 314: spacer 321: medium layer 323: circuit conductive column 324: Capacitor conductive column 325: bit line conductive column 331: medium layer 332: first bit line conductive plug 341: first bit wire conductive plug 342: medium layer 351: medium layer 352: carbon layer 353: silicon oxynitride layer 361: capacitor deep hole 371: the first electrode layer 381: High dielectric constant ferroelectric oxide layer 382: second electrode layer 390: conductive column 391: Tungsten metal 392: medium layer 393: metal wire 394: Metal interconnection 395: medium layer 396: medium layer 397: bit line 410,420,430,440,450,460,470,480,490: steps 610, 620, 630, 640, 650, 660, 670, 680: steps 711: the first electrode layer 712: High dielectric constant ferroelectric oxide layer 713: second electrode layer 714: deep hole 715: medium layer 716: circuit conductive column 717: first bit wire conductive plug 731: Conductive column 732: Conductive column 733: Conductive column 910, 920, 930, 940, 950, 951, 960, 970, 980, 990: steps BL: bit line D: drain PL: plate line S: source WL: word line

. [ Fig. 1 ] A schematic circuit diagram showing an exemplary ferroelectric memory cell. [ Fig. 2 ] A schematic perspective view showing an exemplary ferroelectric memory cell. [ FIG. 3A ] to [ FIG. 3O ] are cross-sectional views illustrating a process of forming a capacitor of a ferroelectric memory cell according to one embodiment of the present invention. [ Fig. 4 ] A flowchart showing a capacitor forming a ferroelectric memory cell according to an embodiment of the present invention. [ Fig. 5 ] A schematic cross-sectional view showing a planarization process for a capacitor according to an embodiment of the present invention. [ Fig. 6 ] A schematic cross-sectional view showing a planarization process for a capacitor according to an embodiment of the present invention. [ FIG. 7A ] to [ FIG. 7D ] are schematic perspective views of the ferroelectric capacitor of FIG. 6 . [ Fig. 8 ] A schematic perspective view showing a divided capacitor unit according to an embodiment of the present invention. [ Fig. 9 ] A flowchart showing a capacitor forming a ferroelectric memory cell according to an embodiment of the present invention. [ FIG. 10A ] to [ FIG. 10F ] are cross-sectional views illustrating a process of forming a capacitor of a ferroelectric memory cell according to an embodiment of the present invention. [ FIG. 11A ] shows a schematic cross-sectional view of the capacitor deep hole part after forming the capacitor deep hole through an etching process and removing the carbon layer and the silicon oxynitride layer according to an embodiment of the present invention. [ FIG. 11B ] A schematic cross-sectional view showing a deep hole portion of a capacitor having a sidewall having protrusions according to an embodiment of the present invention.

410,420,430,440,450,460,470,480,490: steps

Claims (18)

A method of manufacturing a memory, which includes: providing a semiconductor substrate, wherein the semiconductor substrate includes a ferroelectric memory unit area, and the ferroelectric memory unit area has a plurality of functional areas and electrodes and interconnection metals above each functional area line, the plurality of functional areas include a source area, a drain area, a gate area and a spacer area; a first interconnection structure is formed, wherein the first interconnection structure includes a capacitor conductive column, a bit line conductive column, and in the The first dielectric layer between the capacitor conductive column and the bit line conductive column; form a first bit line conductive plug, wherein the first bit line conductive plug includes a metal electrically connected to the bit line conductive column Conductive pillars and a second dielectric layer around the metal conductive pillars; sequentially forming a third dielectric layer and a hard mask layer; patterning the hard mask layer through photolithography and etching processes; The patterned hard mask layer is used as a mask for etching to form deep holes in the second dielectric layer and the third dielectric layer; the patterned hard mask layer is removed to make the The bottom of the deep hole exposes the conductive pillar of the capacitor; sequentially forming a first electrode layer, a high dielectric constant ferroelectric oxide layer and a second electrode layer; removing part of the first electrode layer, high dielectric constant ferroelectric oxide layer and the second electrode layer, only the first electrode layer, the high dielectric constant ferroelectric oxide layer and the second electrode layer around the sidewall, bottom and top of the deep hole remain, so that the first electrode layer , the ferroelectric capacitor formed by the high dielectric constant ferroelectric oxide layer and the second electrode layer are separated from each other; a fourth dielectric layer is formed on the top surface of the third dielectric layer; Drill holes on the fourth dielectric layer to form a plurality of conductive structures, wherein the plurality of conductive structures are respectively electrically connected to the second electrode layer and the first bit line conductive plug, and are connected to the first bit line conductive plug. The conductive structure electrically connected to the two electrode layers extends from the second electrode layer at the bottom of the deep hole to the top of the fourth dielectric layer; a plate line is formed above the conductive structure, wherein the plate line passes through and connects with the first electrode layer. The conductive structure in which the two electrode layers are electrically connected is electrically connected to the second electrode layer; and a bit line and an external pad are formed above the plate line, wherein the bit line is electrically connected to the first bit line conductive plug. The connected conductive structure is electrically connected to the first bit line conductive plug. The manufacturing method of the memory according to claim 1, wherein the first interconnection structure further includes an adhesive layer covering the periphery of the bit line conductive pillar. The memory manufacturing method according to claim 1, further comprising: after forming the deep hole and removing the hard mask layer, expanding the top of the deep hole to form an expanded hole, wherein the expanded hole is at The top of the deep hole has a cross-sectional area greater than that of the deep hole. The manufacturing method of memory according to claim 1, wherein at least one of the second dielectric layer and the third dielectric layer is formed by stacking at least two different insulating materials, and the deep hole is formed and removed After the hard mask layer, the method further includes: processing the sidewall of the deep hole by wet etching, the wet etching has different etching rates for the at least two different insulating materials, thereby One or more protrusions are formed on sidewalls of the well. A memory capacitor, comprising: a semiconductor substrate, which includes a ferroelectric memory unit area, wherein the ferroelectric memory unit area has a plurality of functional areas and electrodes and interconnected metal lines above each functional area, the plurality of The functional area includes source area, drain area, gate area and spacer area; A first interconnection structure, which is disposed above the semiconductor substrate, and includes a capacitor conductive column, a bit line conductive column, and a first dielectric layer between the capacitor conductive column and the bit line conductive column; the first A bit line conductive plug, which includes a metal conductive column electrically connected to the bit line conductive column and a second dielectric layer between the metal conductive columns; a third dielectric layer, which is stacked on the second dielectric layer top; a deep hole, which is formed in the second dielectric layer and the third dielectric layer, and exposes the conductive column of the capacitor; the first layer stacked in sequence around the sidewall, bottom and top of the deep hole An electrode layer, a high dielectric constant ferroelectric oxide layer and a second electrode layer; a fourth dielectric layer, which is arranged on the top surface of the third dielectric layer; a plurality of conductive structures, which are respectively connected to the second electrode layer Electrically connected to the first bit line conductive plug, wherein the conductive structure electrically connected to the second electrode layer extends from the second electrode layer at the bottom of the deep hole to the top of the fourth dielectric layer; plate line , which is electrically connected to the second electrode layer through a conductive structure electrically connected to the second electrode layer; and a bit line, which is electrically connected to the second electrode layer through a conductive structure electrically connected to the first bit line conductive plug. The first bit line conductive plug. The memory capacitor according to claim 5, wherein at least one of the second dielectric layer and the third dielectric layer is formed by stacking at least two different insulating materials, and the sidewall of the deep hole has one or more a bump. The capacitor of the memory according to claim 5, which further includes a reamed hole formed by etching the top of the deep hole, the reamed hole is located at the top of the deep hole and its cross-sectional area is larger than that of the deep hole The cross-sectional area, the first electrode layer is only arranged on the bottom and side of the deep hole below the expanded hole, the high dielectric constant ferroelectric oxide layer and the second electrode layer are formed on the deep hole and the The side walls and bottom of the reamed hole. A method of manufacturing a memory, comprising: forming a memory cell area and a peripheral circuit area on a semiconductor substrate, wherein a transistor is formed on the semiconductor substrate in the memory cell area, and the transistor includes a source electrode and a drain electrode and gate; deposit a first dielectric layer on the transistor layer of the semiconductor substrate in the memory cell area and the peripheral circuit area, and form the source and drain of the transistor in the first dielectric layer The first through hole and the second through hole corresponding to each other, a first bit line conductive column is formed in the first through hole, and a capacitor conductive column is formed in the second through hole; in the first dielectric layer A second dielectric layer is deposited on top; a deep hole is formed on the second dielectric layer at a position corresponding to the capacitive conductive column to expose the capacitive conductive column; a lower electrode layer, a ferroelectric conductive column are sequentially deposited in the deep hole a material layer and an upper electrode layer to form a ferroelectric capacitor structure; a third through hole is formed in the second dielectric layer corresponding to the first bit line conductive column; a third through hole is formed in the third through hole Two-bit line conductive column; form a third dielectric layer above the ferroelectric capacitor structure; remove the part of the ferroelectric capacitor structure outside the deep hole and the part of the third dielectric layer to form a separate ferroelectric capacitor a container structure; forming a fourth dielectric layer on the top surface of the third dielectric layer; Form a bit line via hole in the second dielectric layer and the fourth dielectric layer corresponding to the second bit line conductive column, and form a bit line connected to the second bit line conductive column in the bit line via hole The third bit line conductive column; forming a through hole in the part corresponding to the central area of the upper electrode layer of the ferroelectric capacitor structure in the second dielectric layer, the third dielectric layer and the fourth dielectric layer, And forming a capacitor metal conductive column connected to the upper electrode layer in the through hole; forming a fifth dielectric layer above the fourth dielectric layer, forming a capacitor metal conductive column connected to the capacitor metal conductive column on the fifth dielectric layer metal plate line, forming a fourth via hole in the portion of the fifth dielectric layer corresponding to the bit line conductive metal, and forming a metal bit line conductive plug in the fourth via hole; and forming a metal bit line conductive plug in the fourth via hole; A sixth dielectric layer is formed above the five dielectric layers, and a metal bit line connected to the metal bit line conductive plug is formed on the sixth dielectric layer. The method according to claim 8, wherein the second dielectric layer comprises a multi-layer structure, and the method further includes: in the multi-layer structure, the part of each layer corresponding to the bit line conductive column of the previous layer forms a via hole and a bit Conductive wire column. The method according to claim 8, wherein the step of forming the deep hole further comprises: forming a dielectric anti-reflective coating on the second dielectric layer as a hard mask for etching the deep hole, the anti-reflective coating The reflective coating includes a carbon layer and a silicon oxynitride layer. The method according to claim 8, wherein the step of forming a deep hole further comprises: first etching to form a deep hole with a first cross-sectional size, and then etching above the deep hole to form a reamed hole, the reamed hole is in the The top of the deep hole and its cross-sectional area is larger than the cross-sectional area of the deep hole. The method according to claim 8, further comprising: forming a first adhesive layer covering the periphery of the first bit line conductive pillar in the first through hole; A second adhesive layer covering the periphery of the second bit line conductive pillar is formed in the third through hole; and a third adhesive layer covering the periphery of the third bit line conductive pillar is formed in the bit line through hole. adhesive layer. The method of claim 9, wherein the step of forming a deep hole by etching further includes: first etching the multilayer structure to form a flat inner wall of the deep hole; and then performing wet etching to form Protruding structures between different layers of the multilayer structure. The method of claim 9, wherein the bit line conductive post is made of tungsten, and the metal bit line conductive plug is made of copper. The method according to claim 8, wherein when depositing the ferroelectric capacitive structure in the deep hole, further comprising: depositing a protective layer before depositing the lower electrode layer, and depositing a protective layer after depositing the upper electrode layer layer. The method as claimed in claim 8, wherein the step of removing a part of the ferroelectric capacitor structure outside the deep hole is a photomask etching process. The method according to claim 8, wherein when the deep hole is formed in the part of the second dielectric layer corresponding to the capacitive conductive column to expose the capacitive conductive column, the etching stops when the capacitive conductive column is reached, and The dielectric layer around the conductive pillar of the capacitor is etched downwards to form a depression around the conductive pillar of the capacitor. The method of claim 8, wherein the materials of the upper electrode layer and the lower electrode layer of the ferroelectric capacitor structure include at least one of the following: titanium nitride (TiN), titanium silicon nitride (TiSiNx), nitride Titanium aluminum (TiAlNx), titanium carbonitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), Tungsten carbonitride (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), polydoped crystalline silicon, transparent conductive oxide (TCO) and iridium oxide (IrOx); and said iron The material of the electrical material layer includes oxygen and one or more of the following materials: Ferroelectric metals and doped with calcium (Ca), strontium (Sr), barium (Ba), scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga), indium (In), lanthanum (La ), cerium (Ce), 鐠 (Pr), neodymium (Nd), 鉕 (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), 鋱 (Tb), dysprosium (Dy), « (Ho ), erbium (Er), 銩 (Tm), ytterbium (Yb) or 鑥 (Lu) of the ferroelectric metal, and the ferroelectric metal includes zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum ( One or more of Al), nickel (Ni) and iron (Fe).

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