CN116209257B

CN116209257B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN116209257B
Application number: CN202310492394.6A
Authority: CN
Inventors: 罗荣峰; 熊内隆宏
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-05-05
Filing date: 2023-05-05
Publication date: 2023-07-21
Anticipated expiration: 2043-05-05
Also published as: CN116209257A

Abstract

The present disclosure relates to the field of semiconductor technology, and provides a semiconductor device and a method for manufacturing the same, the semiconductor device comprising: a substrate including an array region and a peripheral region; the array region has a first transistor, and the peripheral region has a second transistor; a capacitor on the substrate of the array region; the lower electrode of the capacitor is connected with the first transistor; a first contact stud located on the capacitor; the first contact post is connected with the upper electrode of the capacitor; a contact structure on a substrate in a peripheral region, comprising: a second contact column and a third contact column stacked in sequence; the second contact post is connected with the second transistor, and the third contact post is contacted with the second contact post; the dimensions of the second contact post and the dimensions of the capacitor are substantially the same in a direction perpendicular to the plane of the substrate. This improves the uniformity of the peripheral region contact structure and the uniformity between the plurality of contact structures.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.

Background

With the continuous development of mobile devices, mobile devices with battery power, such as mobile phones, tablet computers, wearable devices and the like, are increasingly applied to life, a memory is used as an indispensable element in the mobile devices, and great demands are put forward by people on the small size and integration of the memory.

Currently, dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used in mobile devices at its fast transmission speed. However, current DRAMs have poor uniformity of conductive Contacts (CT) and poor uniformity among multiple conductive contacts, affecting the electrical performance of the DRAM.

Disclosure of Invention

According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor device including:

a substrate, comprising: an array region and a peripheral region; wherein the array region has a first transistor and the peripheral region has a second transistor;

a capacitor on the substrate of the array region; wherein a lower electrode of the capacitor is connected with the first transistor;

a first contact stud located on the capacitor; wherein the first contact post is connected with the upper electrode of the capacitor;

a contact structure on the substrate in the peripheral region, comprising: a second contact column and a third contact column stacked in sequence; wherein the second contact stud is connected to the second transistor and the third contact stud is in contact with the second contact stud; the second contact post has a dimension substantially the same as the capacitor along a direction perpendicular to the plane of the substrate.

According to a second aspect of embodiments of the present disclosure, there is provided a method for manufacturing a semiconductor device, including:

providing a substrate; wherein the substrate comprises an array region having a first transistor and a peripheral region having a second transistor;

forming a capacitor on the substrate of the array region; wherein a lower electrode of the capacitor is connected with the first transistor;

forming a second contact post on the substrate of the peripheral region; wherein the second contact stud is connected with the second transistor; the second contact post has a size substantially the same as the capacitor in a direction perpendicular to the plane of the substrate;

forming a first contact stud over the capacitor; wherein the first contact post is connected with the upper electrode of the capacitor;

forming a third contact stud on the second contact stud; the third contact post is contacted with the second contact post, and the second contact post and the third contact post form a contact structure.

In the embodiment of the disclosure, the contact structure is arranged in the peripheral area, and comprises the second contact post and the third contact post which are connected, the contact structure is manufactured together by utilizing the manufacturing flow of the capacitor, and the good verticality and uniformity of etching in the capacitor process are utilized, so that the non-uniformity of the contact structure in the peripheral area caused by overhigh contact structure is improved, the electrical performance of the semiconductor device is improved, the contact structure has good verticality, and the Top size (Top CD) and the Bottom size (Bottom CD) of the contact structure have no larger difference, so that the contact structure has better consistency.

In addition, the uniformity and consistency of the peripheral area contact structure are improved, so that the process window of the metal wiring in the back-end process of the semiconductor device is increased, the process difficulty of the metal wiring is reduced, and the process precision of the metal wiring is improved.

Drawings

Fig. 1 is a schematic diagram of a semiconductor device shown according to an exemplary embodiment;

fig. 2 is a schematic diagram of a semiconductor device shown in accordance with an embodiment of the present disclosure;

FIG. 3a is a schematic diagram of one contact structure shown in accordance with an embodiment of the present disclosure;

FIG. 3b is a schematic diagram of another contact structure shown in accordance with an embodiment of the present disclosure;

fig. 4 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a process for fabricating a semiconductor device according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram ii of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure;

fig. 7 is a top view of a process for fabricating a semiconductor device according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram three of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram four of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure;

Fig. 10 is a schematic diagram five of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram six of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure;

fig. 12 is a schematic diagram seven of a manufacturing process of a semiconductor device according to an embodiment of the disclosure;

fig. 13 is a schematic view eight of a manufacturing process of a semiconductor device according to an embodiment of the disclosure;

fig. 14 is a schematic diagram nine of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure;

fig. 15 is a top view of a second fabrication process of a semiconductor device according to an embodiment of the present disclosure;

fig. 16 is a schematic view showing a manufacturing process of a semiconductor device according to an embodiment of the present disclosure;

fig. 17 is a schematic diagram eleven of a manufacturing process of a semiconductor device according to an embodiment of the disclosure.

Detailed Description

The technical scheme of the present disclosure will be further elaborated with reference to the drawings and examples. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It will be understood that the meanings of the disclosure "on … …", "over … …" and "over … …" are to be interpreted in the broadest sense such that "on … …" means not only that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.

In the presently disclosed embodiments, the terms "first," "second," "third," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers.

As the integration level increases, the feature size of the DRAM is continuously reduced, and accordingly, the aspect ratio of the capacitor in the DRAM is continuously increased, which has a great influence on the contact pillars (Concat, CT) of the subsequent front and rear stages, as will be described below with reference to fig. 1.

Fig. 1 is a schematic diagram of a semiconductor device 100 shown according to an exemplary embodiment. Referring to fig. 1, the semiconductor device 100 includes a capacitor 115 located in the array region 100a and a contact pillar 116 located in the peripheral region 100 b. Here, the semiconductor device 100 may be a DRAM. However, in other embodiments, semiconductor device 100 may also be other types of memory.

Still referring to fig. 1, the aspect ratio of the contact pillars 116 is primarily determined by the height of the capacitor 115. Typically after the formation of the capacitor 115 in the array region 100 a; a plurality of contact pillars 116 (only one is shown) penetrating the insulating layer 121 are formed in the peripheral region 100b, so as to respectively draw out the transistors in the peripheral region, such as a source electrode, a drain electrode and a gate electrode.

As the aspect ratio of the capacitor 115 increases, the process challenges (e.g., etch difficulty of deep holes) of the contact pillars 116 increase, resulting in a larger difference between the top dimension (Top Critical dimension, TCD) W1 and the bottom dimension (Bottom Critical dimension, BCD) W2 of the finally formed contact pillars 116, and poor uniformity of the contact pillars 116.

Also, as the process challenges of the contact pillars 116 increase, the uniformity between the plurality of contact pillars 116 decreases, resulting in poor uniformity between the plurality of contact pillars 116, affecting the electrical performance of the DRAM.

In view of the above, embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and a memory.

Fig. 2 is a schematic diagram of a semiconductor device 200 shown in accordance with an embodiment of the present disclosure. Referring to fig. 2, the semiconductor device 200 includes:

a substrate, comprising: an array region 200a and a peripheral region 200b; wherein the array region 200a has a first transistor and the peripheral region 200b has a second transistor;

a capacitor 215 on the substrate of the array region 200 a; wherein a lower electrode of the capacitor 215 is connected to the first transistor;

a first contact stud 219 located on the capacitor 215; wherein the first contact stud 219 is connected to the upper electrode of the capacitor 215;

a contact structure on the substrate of the peripheral region 200b, comprising: a second contact stud 216 and a third contact stud 220 stacked in sequence; wherein the second contact stud 216 is connected to the second transistor and the third contact stud 220 is in contact with the second contact stud 216; the dimensions of the second contact pillars 216 are substantially the same as the dimensions of the capacitors 215 in a direction perpendicular to the plane of the substrate.

The semiconductor device 200 includes a memory cell array located in the array region 200a and a peripheral circuit located in the peripheral region 200b, the peripheral circuit being connected to the memory cell array, the peripheral circuit being configured to control a logic operation (e.g., writing or reading, etc.) of the memory cell array. The semiconductor device 200 includes, but is not limited to, a DRAM, and the embodiment of the present disclosure will be described by taking the semiconductor device 200 as a DRAM.

The substrate includes a first active region 201 located in the array region 200a and a second active region 202 located in the peripheral region 200b, the first active region 201 and the second active region 202 being isolated by shallow trench isolation 203. Here, the active region may be formed by doping the substrate, and the active region includes a source electrode, a drain electrode, and a channel between the source electrode and the drain electrode.

The material of the substrate comprises: elemental semiconductor materials (e.g., silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. The materials of the shallow trench isolation 203 include: at least one of silicon oxide, silicon nitride or silicon oxynitride is exemplified by the shallow trench isolation 203 as a silicon oxide-silicon nitride-silicon oxide composite film in the embodiment of the present disclosure.

The semiconductor device 200 further includes: a word line 204 and a bit line 206, the extending direction of the word line 204 and the extending direction of the bit line 206 are parallel to the plane of the substrate and intersect; where word line 204 is connected to a first gate of a first transistor and bit line 206 is connected to a first active region 201 (e.g., drain or source).

Here, the first active region 201, the first gate electrode, and the first gate dielectric layer between the first active region and the first gate electrode constitute a first transistor, which serves as a selection transistor of the memory cell array; the second active region 202, the second gate electrode, and the second gate dielectric layer between the second active region and the second gate electrode constitute a second transistor, which serves as a driving transistor of the peripheral circuit.

In one embodiment, the word line 204 is a buried word line and the bit line 206 is connected to the first active region 201 through a bit line contact 205. It will be appreciated that in this example, the word line is located in the substrate and the bit line is connected to the first active region by a bit line contact. In other embodiments, the word line may be located over the substrate, and the bit line may be directly connected to the first active region, which is not particularly limited by the present disclosure. The material of the bit line contacts 205 includes a conductive material, such as polysilicon or doped polysilicon.

The first insulating structure 214 and the second insulating structure 221 are stacked on the substrate in sequence, with the bit line 206 between the substrate and the first insulating structure 214. Here, a third insulating structure (not shown) is further disposed between the substrate and the first insulating structure 214, and the bit line 206 is located in the third insulating structure. The materials of the first, second and third insulating structures 214, 221 include: silicon oxide, silicon nitride, or silicon oxynitride, etc. The materials of the first, second and third insulating structures 214, 221 may be the same or different, and the present disclosure is not particularly limited.

The memory cell array includes a plurality of memory cells including a first transistor and a capacitor 215 connected to the first transistor. The capacitor 215 includes a lower electrode, an upper electrode, and a capacitive dielectric layer between the lower electrode and the upper electrode. The materials of the lower electrode and the upper electrode comprise conductive materials, and the materials of the capacitance dielectric layer comprise dielectric materials. The capacitor 215 includes a single-sided cylindrical capacitor, a double-sided cylindrical capacitor, or the like, and the capacitor 215 is exemplified as a double-sided cylindrical capacitor in the embodiment of the present disclosure.

In some embodiments, the capacitor 215 is connected to the first active region 201 (e.g., source or drain); the contact structure is connected to the second active region 202 or the second gate.

In some embodiments, the semiconductor device 200 further includes: a plurality of first interconnect structures in the third insulating structure, the first interconnect structures including first interconnect pillars 207 and first interconnect layers 208, the first interconnect pillars 207 being located between the substrate and the first interconnect layers 208. The material of the first interconnect structure includes a conductive material, for example, at least one of polysilicon, doped polysilicon, titanium nitride, tungsten nitride, tantalum nitride, tungsten, platinum, titanium, or aluminum.

In some embodiments, the first interconnect structure comprises: a first sub-interconnect structure and a second sub-interconnect structure; wherein a first sub-interconnect structure is located between the substrate of the array region and the capacitor 215, the first sub-interconnect structure being connected to the first transistor and the lower electrode, respectively; a second sub-interconnect structure is located between the substrate of the peripheral region and the second contact pillars 216, the second sub-interconnect structure being connected to the second transistor and the second contact pillars 216, respectively.

In one embodiment, the lower electrode of the capacitor 215 is connected to the first active region 201 through a first sub-interconnect structure. For example, the first interconnect column 207 located in the array region is connected to the first active region 201, and the first interconnect layer 208 located in the array region is connected to the lower electrode. Here, the plurality of capacitors 215 located in the array region 200a constitute a capacitance array. It is emphasized that for ease of illustration, the insulating layer between the first interconnect pillars 207 and the bit lines 206 is not shown in fig. 2.

The first contact stud 219 is connected to the upper electrode, and an electrical signal can be applied to the lower electrode and the upper electrode through the first transistor and the first contact stud 219, respectively, to charge or discharge the capacitor 215, thereby writing a logic "1" or "0" to the memory cell.

In a specific embodiment, the second contact pillar 216 is connected to the second transistor through a second sub-interconnect structure. For example, the first interconnect pillars 207 located in the peripheral region are connected to the second active region 202, and the first interconnect layer 208 located in the peripheral region is connected to the second contact pillars 216. The third contact stud 220 is connected to the second contact stud 216 and forms a contact structure through which an electrical signal can be applied to the second transistor to drive the peripheral circuitry to perform a corresponding logic operation.

The material of the first contact stud 219, the second contact stud 216, and the third contact stud 220 includes a conductive material, for example, at least one of polysilicon, doped polysilicon, titanium nitride, tungsten nitride, tantalum nitride, tungsten, platinum, titanium, or aluminum.

In some embodiments, the second contact pillars 216 and the capacitors 215 are formed in the same process step, and the height of the second contact pillars 216 and the height of the capacitors 215 are substantially the same. Here, the materials of the second contact pillars 216 and the capacitors 215 may be the same, thereby balancing the stress of the array region and the peripheral region, protecting the memory cell array.

In some embodiments, the third contact pillars 220 and the first contact pillars 219 are formed in the same process step, and the height of the third contact pillars 220 is greater than or equal to the height of the first contact pillars 219. Here, the materials of the third contact pillars 220 and the first contact pillars 219 may be the same, thereby balancing the stress of the array region and the peripheral region, protecting the memory cell array. In other embodiments, the third contact stud 220 and the first contact stud 219 may be fabricated separately and formed in different processes.

It should be noted that the number of contact structures and first contact pillars 219 may be one or more. As used in this disclosure, "height" refers to a dimension along the stacking direction of the first insulating structure and the substrate (i.e., the direction perpendicular to the plane of the substrate); "substantially identical" means that the two are identical or have a deviation that is within an allowable error range.

In some embodiments, the semiconductor device 200 further includes: a first insulating structure 214; wherein the second contact pillars 216 penetrate the first insulating structure 214; the first insulating structure 214 includes: a first support layer 211 on and covering the substrate; a second supporting layer 213 on the first supporting layer 211 and covering the first supporting layer 211; a first sacrificial layer 210 located in the peripheral region 200b and between the substrate and the first support layer 211; the second sacrificial layer 212 is located in the peripheral region 200b and between the first support layer 211 and the second support layer 213.

In some embodiments, the etch selectivity of the first sacrificial layer 210 and the second sacrificial layer 212 is greater than the etch selectivity of the first support layer 211 and the second support layer 213, thereby ensuring that the first support layer 211 and the second support layer 213 are not removed or are removed very little, and are almost negligible, when the first sacrificial layer 210 and the second sacrificial layer 212 of the array region are removed.

In some embodiments, the etch selectivity of the first sacrificial layer 210 is greater than the etch selectivity of the second sacrificial layer 212. With the increase of the depth-to-width ratio, the difficulty of etching the deep hole downwards increases, and the etching selection ratio of the first sacrificial layer 210 is larger than that of the second sacrificial layer 212, so that the uniformity of the upper dimension and the lower dimension of the deep hole can be regulated and controlled, and the uniformity of the finally formed capacitor 215 and the second contact post 216 is guaranteed to be better.

The materials of the first support layer 211 and the second support layer 213 include silicon nitride, and the first support layer 211 and the second support layer 213 are exemplified as silicon nitride in the embodiment of the present disclosure.

The materials of the first sacrificial layer 210 and the second sacrificial layer 212 include silicon oxide, and in the embodiment of the present disclosure, the first sacrificial layer 210 is borophosphosilicate glass (BPSG) and the second sacrificial layer 212 is silicon oxide.

In the embodiment of the disclosure, by arranging the composite first insulating structure and reserving the first sacrificial layer and the second sacrificial layer of the peripheral area, the capacitor manufacturing process is utilized to simultaneously finish the manufacturing of the capacitor and the contact structure, the uniformity of the whole wafer is improved, good protection is achieved for the capacitor array with high aspect ratio of the array area, in addition, the stress of the peripheral area and the array area is balanced, the probability of warping and even cracking of the semiconductor device is reduced, and the yield of the semiconductor device is improved.

In some embodiments, the first insulating structure 214 further comprises: an etch stop layer 209 is located between the first sacrificial layer 210 and the first interconnect structure. The material of the etching stopper 209 includes silicon nitride, and in the embodiment of the present disclosure, the etching stopper 209 is exemplified as silicon nitride. The etching barrier layer is used for preventing damage to the formed first interconnection structure in the deep hole etching process.

In some embodiments, the semiconductor device 200 further includes: a second insulating structure 221 covering the first insulating structure 214; the second insulation structure 221 includes: a first portion 221a located in the array region 200a; wherein the first contact pillars 219 extend through the first portion 221a; a second portion 221b located in the peripheral region 200b; wherein a surface of the second portion 221b remote from the first insulating structure 214 is substantially flush with a surface of the first portion 221a remote from the first insulating structure 214; the second portion 221b has a larger dimension than the first portion 221a in a direction perpendicular to the plane of the substrate; the third contact stud 220 extends through the second portion 221b.

In one specific implementation, the capacitor 215 is a double sided cylindrical capacitor, including: a lower electrode, an upper electrode on opposite sides (e.g., inner and outer sides) of the lower electrode, a capacitive dielectric layer between the lower electrode and the upper electrode, and an electrode contact layer 218 filled between the upper electrodes, which forms a part of the upper electrode; a portion of the electrode contact layer 218 is located between the first insulating structure 214 and the first portion 221a and is connected to the upper electrode located on the inner side of the lower electrode; another portion of the electrode contact layer 218 is located in the first insulating structure 214 and is connected to the upper electrode located on the outer side of the lower electrode. In this example, the capacitance of the capacitor can be increased by providing a double-sided cylindrical capacitor.

Here, the electrode contact layer 218 is located in the array region and covers the capacitor array, and the upper electrode of the capacitor array shares the electrode contact layer, so that the height of the first portion 221a is smaller than the height of the second portion 221 b. The sum of the size of the electrode contact layer 218 between the first insulating structure 214 and the first portion 221a and the size of the first contact pillars 219 in a direction perpendicular to the substrate plane is equal to the size of the third contact pillars 220, i.e. the height of the first contact pillars 219 is smaller than the height of the third contact pillars 220. Of course, in other embodiments, the height of the first contact beams 219 is equal to the height of the third contact beams 220, which is not particularly limited by the present disclosure.

The material of the electrode contact layer 218 includes polysilicon, silicon germanium, doped polysilicon, doped silicon germanium, or the like.

In some embodiments, the difference between the characteristic dimension W1 'at the top of the second contact pillars 216 and the characteristic dimension W2' at the bottom of the second contact pillars 216 is less than 10 nanometers. Here, the difference between W1 'and W2' is greater than or equal to 0. In one embodiment, the difference between the feature size at the top of the second contact pillars 216 and the feature size at the bottom of the second contact pillars 216 is 3nm.

In some embodiments, the difference between the feature size at the top of the capacitor 215 and the feature size at the bottom of the capacitor 215 is less than 10 nanometers. In one embodiment, the difference between the feature size at the top of the capacitor 215 and the feature size at the bottom of the capacitor 215 is 2nm.

In some embodiments, the second contact pillars 216 and the capacitors 215 are formed in the same process, the second contact pillars 216 and the capacitors 215 of the contact structure are fabricated together by using a capacitance fabrication process, and the problem of non-uniformity in holes of the contact pillars and non-controllability in on-chip uniformity is solved by using good verticality and uniformity of etching in the capacitance process.

In the embodiment of the disclosure, by synchronously manufacturing the second contact pillars of the peripheral region and the capacitor of the array region, the difference between the characteristic dimension of the top of the second contact pillars and the characteristic dimension of the bottom of the second contact pillars can be controlled to be less than 10 nanometers, the uniformity of the top dimension and the bottom dimension of the second contact pillars is improved, and no additional processing steps are required.

In some embodiments, the semiconductor device 200 further includes: a support structure 217 on the substrate of the array region and disposed around the capacitor 215; wherein the dimensions of the support structure 217 and the dimensions of the capacitor 215 are substantially the same in a direction perpendicular to the plane of the substrate. For example, the plurality of capacitors 215 may be located within an annular region defined by the support structure 217. The support structure 217 serves to provide support and protection against collapse of the semiconductor device and to protect the devices of the array region. For example, the support structure 217 may provide support when removing the sacrificial layer of the array region.

In some embodiments, the support structure 217 and the capacitor 215 are formed in the same process step, with the height of the support structure 217 and the height of the capacitor 215 being substantially the same. Here, the materials of the support structure 217 and the capacitor 215 may be the same, so that stress of each region of the semiconductor device protects the memory cell array. In other embodiments, the materials of support structure 217 and capacitor 215 may be different.

In some embodiments, the height of the support structure 217 is greater than the height of the capacitor 215, thereby providing better support.

In the embodiment of the disclosure, the support structure surrounding the capacitor array is arranged, so that the support structure can provide stable support and protection in the preparation and use processes of the capacitor, and is beneficial to improving the stability and reliability of the capacitor in the preparation and use processes of the capacitor, thereby improving the preparation yield and the service life of the semiconductor device.

In some embodiments, the semiconductor device 200 further includes: the second interconnect structure 227 is located in the fourth insulating structure, and the second interconnect structure 227 includes a first conductive layer 222, a first conductive post 223, a second conductive layer 224, a second conductive post 225, and a third conductive layer 226, which are sequentially connected. It should be noted that the number of the second interconnection structures 227 may be one or more.

In some embodiments, the second interconnect structure comprises: a third sub-interconnect structure and a fourth sub-interconnect structure; wherein the third sub-interconnect structure is located over and connected to the first contact pillars; the fourth sub-interconnect structure is located over and connected to the contact structure.

The materials of the first conductive layer 222, the first conductive post 223, the second conductive layer 224, the second conductive post 225, and the third conductive layer 226 include conductive materials, and in the embodiment of the disclosure, the materials of the first conductive layer 222, the first conductive post 223, the second conductive layer 224, and the second conductive post 225 are copper, and the materials of the third conductive layer 226 are aluminum.

Fig. 3a is a schematic view of one contact structure shown according to an embodiment of the present disclosure, and fig. 3b is a schematic view of another contact structure shown according to an embodiment of the present disclosure. The contact structure in the embodiments of the present disclosure will be further described with reference to fig. 2, 3a and 3 b.

In some embodiments, referring to fig. 2 and 3a, the third contact beam 220 wraps around a portion of the sidewall of the second contact beam 216, and the orthographic projection of the second contact beam 216 is located within the orthographic projection of the third contact beam 220. For example, the third contact stud 220 also extends through a portion of the first insulating structure 214, thereby increasing the contact area of the third contact stud 220 and the second contact stud 216, which is beneficial for reducing contact resistance.

In some embodiments, referring to fig. 2 and 3b, the second contact beam 216 wraps around a portion of the sidewall of the third contact beam 220, and the orthographic projection of the third contact beam 220 is located within the orthographic projection of the second contact beam 216. For example, the bottom of the third contact beam 220 is positioned in the second contact beam 216, thereby increasing the contact area of the third contact beam 220 and the second contact beam 216, which is beneficial for reducing contact resistance.

Fig. 4 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Referring to fig. 4, the method comprises at least the steps of:

s310: providing a substrate; the substrate comprises an array area and a peripheral area, wherein the array area is provided with a first transistor, and the peripheral area is provided with a second transistor;

s320: forming a capacitor on the substrate of the array region; wherein the lower electrode of the capacitor is connected with the first transistor;

s330: forming a second contact pillar on the substrate in the peripheral region; wherein the second contact pillar is connected with the second transistor; the second contact post has a size substantially the same as the size of the capacitor along a direction perpendicular to the plane of the substrate;

s340: forming a first contact stud over the capacitor; the first contact column is connected with the upper electrode of the capacitor;

S350: forming a third contact stud on the second contact stud; the third contact post is contacted with the second contact post, and the second contact post and the third contact post form a contact structure.

It should be noted that the steps shown in fig. 4 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations; the steps shown in fig. 4 can be sequentially adjusted according to actual requirements.

Fig. 5 to 17 are schematic views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present disclosure. The method of manufacturing the semiconductor device provided in the embodiments of the present disclosure will be described in detail with reference to fig. 4 and 5 to 17.

In step S310, a substrate is provided; the substrate comprises an array area and a peripheral area, wherein the array area is provided with a first transistor, and the peripheral area is provided with a second transistor. The material of the substrate comprises: elemental semiconductor materials (e.g., silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

In some embodiments, the above preparation method further comprises: doping treatment is carried out on the substrate to form an active region; shallow trench isolation is formed between two adjacent active regions. For example, the first active region 401 and the second active region 402 may be formed in the substrate by an ion implantation process or an ion diffusion process, the first active region 401 being located in the array region 400a, and the second active region 402 being located in the peripheral region 400b; shallow trench isolation 403 may be formed between the first active region 401 and the second active region 402 by a photolithography process, an etching process, and a thin film deposition process, as shown in fig. 5.

The materials of the shallow trench isolation 403 include: at least one of silicon oxide, silicon nitride or silicon oxynitride is exemplified by the shallow trench isolation 403 being a silicon oxide-silicon nitride-silicon oxide composite film in the embodiments of the present disclosure.

In some embodiments, referring to fig. 5, the preparation method further includes: forming a word line 404 connected to a first gate of the first transistor, the word line 404 being located in the substrate; forming a third insulating structure (not shown) covering the substrate; in the third insulating structure, a bit line 406 is formed, the bit line 406 is connected to the first active region 401, and the extending direction of the word line 404 and the extending direction of the bit line 406 are both parallel to and intersect the plane in which the substrate is located. In this example, word line 404 is a buried word line and bit line 406 is connected to first active region 401 through bit line contact 405. Here, the first active region 401, the first gate electrode, and the first gate dielectric layer between the first active region and the first gate electrode constitute a first transistor.

In other embodiments, the word line may be formed over the substrate, e.g., in a third insulating structure; the bit line contact 405 may be omitted, i.e., the bit line 406 is directly connected to the first active region 401, which is not particularly limited by the present disclosure.

The material of the bit line contact 405 includes a conductive material, such as polysilicon or doped polysilicon.

In some embodiments, referring to fig. 5, the preparation method further includes: a plurality of first interconnect structures are formed in the third insulating structure, the first interconnect structures including first interconnect pillars 407 and first interconnect layers 408, the first interconnect pillars 407 being located between the substrate and the first interconnect layers 408. Here, the first interconnection structure located at the array region 400a is connected to the first active region 401. The first interconnect structure located in the peripheral region 400b is connected to the second active region 402 or the second gate of the second transistor; the second active region 402, the second gate, and a second gate dielectric layer between the second active region and the second gate constitute a second transistor.

In some embodiments, the first interconnect structure comprises: a first sub-interconnect structure and a second sub-interconnect structure; the first sub-interconnection structure is positioned in the array area and connected with the first transistor; the second sub-interconnection structure is located in the peripheral region and is connected with the second transistor.

It is emphasized that for ease of illustration, the insulating layer between the first interconnect post 407 and the bit line 406 is not shown in fig. 5.

In steps S320 and S330, as shown with reference to fig. 5 to 14, a capacitor 415 is formed on the substrate of the array region; wherein the lower electrode of the capacitor 415 is connected to the first transistor; forming a second contact pillar 416 on the substrate in the peripheral region; wherein the second contact post 416 is connected to a second transistor; the dimensions of the second contact stud 416 and the dimensions of the capacitor 415 are substantially the same in a direction perpendicular to the plane of the substrate. Here, the lower electrode of the capacitor 415 may be connected to the first transistor through a first sub-interconnect structure, and the second contact pillar 416 may be connected to the second transistor through a second sub-interconnect structure.

In some embodiments, the above preparation method further comprises: forming a first insulating structure material layer covering the substrate; the first insulating structure material layer comprises a first sacrificial material layer, a first supporting material layer, a second sacrificial material layer and a second supporting material layer which are sequentially stacked; forming a first through hole and a second through hole penetrating the first insulating structure material layer; the first through holes are positioned in the array area, and the second through holes are positioned in the peripheral area.

The step S320 includes: forming a lower electrode covering the sidewall and the bottom of the first via hole; forming a capacitance dielectric layer covering the lower electrode; and forming an upper electrode covering the capacitor dielectric layer.

The step S330 includes: and forming a second contact post in the second through hole.

Referring to fig. 5, a first insulating structure material layer 414 'covering the third insulating structure is formed, and the first insulating structure material layer 414' includes a first sacrificial material layer 410', a first supporting material layer 411', a second sacrificial material layer 412', and a second supporting material layer 413' stacked in this order. Here, the first insulating structure material layer 414' is used to form the first insulating structure 414 in a subsequent process.

The materials of the first sacrificial material layer 410 'and the second sacrificial material layer 412' include silicon oxide, and in the embodiment of the present disclosure, the first sacrificial material layer 410 'is borophosphosilicate glass (BPSG) and the second sacrificial material layer 412' is silicon oxide.

The materials of the first support material layer 411 'and the second support material layer 413' include silicon nitride, and in the embodiment of the present disclosure, the first support material layer 411 'and the second support material layer 413' are exemplified by silicon nitride. Here, the first and second support material layers 411 'and 413' serve to provide support to prevent the semiconductor device from collapsing when the first and second sacrificial material layers 410 'and 412' are subsequently removed.

In some embodiments, the first insulating structural material layer 414' further comprises: the etching stop material layer 409', the etching stop material layer 409' can be used as an etching stop layer to prevent damage to the formed first interconnection structure in the subsequent deep hole etching process. The material of the etching stopper material layer 409 'includes silicon nitride, and in the embodiment of the present disclosure, the etching stopper material layer 409' is exemplified as silicon nitride.

Referring to fig. 5, a mask structure is formed overlying the first insulating structure material layer 414'. The mask structure may be a single film or a composite film. The material of the mask structure comprises one or any combination of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, or spin-on carbon. In one embodiment, the mask structure includes a first mask layer 4141, a second mask layer 4142, and a third mask layer 4143 stacked in sequence. Further, the mask pattern 4144 may be formed in the mask structure by a self-aligned process, including self-aligned double patterning or self-aligned quad patterning, etc.

Referring to fig. 6, a first photoresist layer 4145 covering the mask structure is formed, and the first photoresist layer 4145 includes a plurality of photolithography patterns, for example, a photolithography pattern 4145a and a photolithography pattern 4145b in the array region 400a, and a photolithography pattern 4145c in the peripheral region 400 b. Fig. 7 shows a top view of the structure shown in fig. 6, with the lithographic patterns 4145a, 4145b, 4145c being used to form the capacitor 415, the support structure 417, the second contact stud 416, respectively, in a subsequent process.

Etching the first insulation structure material layer 414' downward according to the photolithography pattern 4145a and the mask pattern 4144 to form a first via (not shown) in the array region 400a, the bottom of the first via exposing the first sub-interconnect structure; the first insulating structure material layer 414' is etched downward according to the photolithography pattern 4145c to form a second via (not shown) in the peripheral region 400b, the bottom of which exposes the second sub-interconnect structure. Here, the number of the first through holes and the second through holes may be one or more.

A first electrode material layer is formed to cover the first via sidewall and the bottom, and the first electrode material layer covers both the second via sidewall and the bottom, as shown in fig. 8. In this example, a first via and a second via are simultaneously deposited with a first electrode material layer in the first via for forming the lower electrode 415a of the capacitor and a first electrode material layer in the second via for forming a portion (denoted 416 a) of the second contact stud 416.

In the embodiment of the disclosure, the etching of the capacitor hole (i.e., the first through hole) of the array region and the etching of the contact hole (i.e., the second through hole) of the peripheral region are simultaneously completed by utilizing the multilayer hard mask and the better vertical etching technology of the capacitor array process, so that the uniformity of the second contact pillars of the peripheral region and the uniformity among a plurality of the second contact pillars can be improved, the dimensional accuracy of the second contact pillars can be improved, additional process steps are not required, and the reliability of the capacitor structure is improved while the CT is manufactured with high accuracy.

In some embodiments, the first via and the second via are etched or deposited simultaneously. Compared with separate etching or deposition, the simultaneous etching or deposition is beneficial to reducing the process and saving the cost.

The capacitor 415 includes a lower electrode 415a, an upper electrode, and a capacitive dielectric layer between the lower electrode 415a and the upper electrode, the lower electrode 415a being connected to the first interconnect layer 408 in the array region 400 a; the first transistor and a capacitor 415 connected to the first transistor constitute a memory cell.

In some embodiments, referring to fig. 6 to 14, the preparation method further includes: forming a support structure 417 surrounding the capacitor 415 on the substrate of the array region; wherein the dimensions of the support structure 417 and the dimensions of the capacitor 415 are substantially the same in a direction perpendicular to the plane of the substrate.

Etching the first insulating structure material layer 414' downward according to the photolithography pattern 4145b to form a support hole (not shown) in the array region, the bottom of the support hole exposing the third insulating structure; here, the support hole may deposit a first electrode material layer simultaneously with the first through hole, the first electrode material layer covering the support hole sidewall and bottom, as shown in fig. 8. The first electrode material layer in the support holes is used to form part of the support structure 417 (denoted 417 a).

In some embodiments, the support hole, the first via hole, and the second via hole are etched or deposited simultaneously.

In some embodiments, the above preparation method further comprises: forming a patterned mask layer on the lower electrode and the first via hole; the mask layer is provided with an opening, and the opening exposes the lower electrode and part of the first insulating structure material layer; removing the first sacrificial material layer and the second sacrificial material layer which are positioned in the array area according to the opening to form a gap; wherein the gap exposes the lower electrode; the remaining first sacrificial material layer forms a first sacrificial layer, the remaining first support material layer forms a first support layer, the remaining second sacrificial material layer forms a second sacrificial layer, and the remaining second support material layer forms a second support layer; the first sacrificial layer, the first supporting layer, the second sacrificial layer and the second supporting layer form a first insulating structure. According to the embodiment of the disclosure, the whole substrate with the structure is covered with 2 sacrificial layers, and the two additional sacrificial layers in the peripheral area do not need to be removed, so that the uniformity of the whole substrate is improved, and the capacitor with the array area and the high aspect ratio is well protected.

Referring to fig. 9, a second photoresist layer 4146 is formed to cover the first insulating structure material layer 414 'and the first electrode material layer, a plurality of openings are formed in the second photoresist layer 4146 through a photolithography process, and the openings expose the lower electrode 415a and a portion of the first insulating structure material layer 414' between two adjacent lower electrodes 415 a; the exposed first insulating structure material layer 414 'is removed through the opening, at which time the first insulating structure material layer 414' under the second photoresist layer 4146 remains, as shown in fig. 10; the second photoresist layer 4146 in the array region 400a is then removed, exposing the remaining first insulating structure material layer 414' in the array region, and then the first sacrificial material layer 410' and the second sacrificial material layer 412' in the array region 400a are removed to form voids 4147, as shown in fig. 11.

Here, the remaining first sacrificial material layer 410 'constitutes the first sacrificial layer 410, the remaining first support material layer 411' constitutes the first support layer 411, the remaining second sacrificial material layer 412 'constitutes the second sacrificial layer 412, and the remaining second support material layer 413' constitutes the second support layer 413; the first insulating structure 414 includes a first sacrificial layer 410, a first support layer 411, a second sacrificial layer 412, and a second support layer 413. The materials of the first insulating structure 414 include: silicon oxide, silicon nitride, or silicon oxynitride, etc.

After the void 4147 is formed, the remaining second photoresist layer 4146 is removed, as shown in fig. 12; and sequentially forming a capacitor dielectric material layer and a second electrode material layer which cover the first electrode material layer. Here, the capacitor dielectric material layer covers the exposed surface of the first electrode material layer (e.g., the exposed outer side of the void and the exposed inner side of the first via hole), and the second electrode material layer covers the exposed surface of the capacitor dielectric material layer, so that a double-sided cylindrical capacitor may be formed to increase the capacitance of the capacitor 415. The remaining voids and vias are filled with electrode contact material layer 418', as shown in fig. 13.

It should be noted that the second electrode material layer located in the first through hole and the gap is used to form the upper electrode of the capacitor, the capacitance dielectric material layer located in the first through hole and the gap is used to form the capacitance dielectric layer of the capacitor, the first electrode material layer, the second electrode material layer and the capacitance dielectric material layer located in the second through hole form the second contact pillar 416, and the first electrode material layer, the second electrode material layer and the capacitance dielectric material layer located in the supporting hole form the supporting structure 417. In this example, the second electrode material layer and the capacitive dielectric material layer are continuous film layers. In other embodiments, the second electrode material layer and the capacitive dielectric material layer may be discontinuous film layers.

A third photoresist layer 4148 is formed to cover the electrode contact material layer 418', and portions of the electrode contact material layer 418', the second electrode material layer, and the capacitor dielectric material layer in the peripheral region are removed by photolithography and etching processes to form the electrode contact layer 418 and the capacitor, and the electrode contact layer 418 covers the capacitor array, as shown in fig. 14. The electrode contact layer 418 is connected to the upper electrode and the first contact pillar 419 formed later, respectively. Fig. 15 shows a top view of the structure shown in fig. 14, with a plurality of capacitors 415 located within an annular region defined by a support structure 417, and an electrode contact layer 418 surrounding the upper electrode of the capacitors 415. After the electrode contact layer 418 is formed, the remaining third photoresist layer 4148 is removed.

In steps S340 and S350, referring to fig. 16, first contact pillars 419 are formed on the capacitor 415; wherein the first contact stud 419 is connected to an upper electrode of the capacitor, such as electrode contact layer 418; forming a third contact post 420 on the second contact post 416; wherein the third contact beam 420 is in contact with the second contact beam 416, the second contact beam 416 and the third contact beam 420 form a contact structure.

The material of the first contact pillars 419, the second contact pillars 416, and the third contact pillars 420 comprises a conductive material, e.g., at least one of polysilicon, doped polysilicon, titanium nitride, tungsten nitride, tantalum nitride, tungsten, platinum, titanium, or aluminum.

In some embodiments, the above preparation method further comprises: forming a second insulating structure material layer covering the electrode contact layer 418, the first insulating structure 414 and the second contact post 416 in the peripheral region 400b, and performing planarization treatment on the second insulating structure material layer to form a second insulating structure 421, as shown in fig. 16; wherein the second insulating structure 421 includes a first portion 421a located in the array region 400a and a second portion 421b located in the peripheral region 400 b; the surface of the second portion 421b remote from the first insulating structure 414 is substantially flush with the surface of the first portion 421a remote from the first insulating structure 414; the second portion 421b has a dimension greater than the dimension of the first portion 421a in a direction perpendicular to the plane of the substrate.

In some embodiments, the above preparation method further comprises: forming a third through hole penetrating the first portion; wherein the bottom of the third through hole exposes the electrode contact layer; forming a fourth through hole penetrating the second portion; wherein the bottom of the fourth through hole exposes the second contact post;

the step S340 includes: forming a first contact stud in the third via;

the step S350 includes: and forming a third contact post in the fourth through hole.

For example, a fourth photoresist layer (not shown) covering the second insulating structure 421 is formed, and the first contact pattern and the second contact pattern (not shown) are formed in the fourth photoresist layer through an exposure and development process; etching the first portion 421a downward according to the first contact pattern to form a third via (not shown) in the array region 400a, the bottom of the third via exposing the electrode contact layer 418; filling the third via to form a first contact pillar 419 in the third via, as shown in fig. 16; etching the second portion 421b downward according to the second contact pattern to form a fourth via (not shown) in the peripheral region 400b, the bottom of the fourth via exposing the second contact stud 416; the fourth via is filled to form a third contact stud 420 in the fourth via, as shown in fig. 16. Here, the number of the third through holes and the fourth through holes may be one or more.

In some embodiments, the third via and the fourth via are etched or filled simultaneously. In other embodiments, the third via and the fourth via are etched or filled separately. Compared with separate etching or filling, the simultaneous etching or filling is beneficial to reducing the manufacturing process and saving the cost.

In some embodiments, the fourth via also penetrates a portion of the first insulating structure 414 and exposes a portion of the sidewall of the second contact stud 416. Here, by providing a fourth via also penetrating a portion of the first insulating structure 414, a third contact stud 420 surrounding a portion of the sidewall of the second contact stud 416 may be subsequently formed.

In some embodiments, the bottom of the fourth via is located in the second contact stud 416, i.e., the fourth via also extends through a portion of the second contact stud 416. Here, by providing the bottom of the fourth via in the second contact stud 416, the second contact stud 416 may subsequently be made to wrap around a portion of the sidewall of the third contact stud 420.

In some embodiments, the above preparation method further comprises: forming a fourth insulating structure (not shown) covering the second insulating structure 421, the first contact pillars 419 and the third contact pillars 420; a second interconnect structure 427 is formed in the fourth insulating structure.

Referring to fig. 16, the second interconnection structure 427 includes a first conductive layer 422, a first conductive post 423, a second conductive layer 424, a second conductive post 425, and a third conductive layer 426, which are sequentially connected. It should be noted that the number of the second interconnection structures 427 may be one or more.

The materials of the first conductive layer 422, the first conductive pillar 423, the second conductive layer 424, the second conductive pillar 425, and the third conductive layer 426 include conductive materials, and in the embodiment of the disclosure, the materials of the first conductive layer 422, the first conductive pillar 423, the second conductive layer 424, and the second conductive pillar 425 are copper, and the materials of the third conductive layer 426 are aluminum.

In some embodiments, the above preparation method further comprises: the first via hole, the second via hole and the supporting hole are filled with the first electrode material layer, and steps similar to those shown in fig. 9 to 14 are performed, so that the structure shown in fig. 17 may be formed, and the disclosure will not be repeated here. In this example, a pillar (pilar) capacitor 415 'may be formed, the height of the second contact pillar 416, the height of the support structure 417, and the height of the pillar capacitor 415' being substantially the same.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Claims

1. A semiconductor device, comprising:

a contact structure on the substrate in the peripheral region, comprising: a second contact column and a third contact column stacked in sequence; wherein the second contact stud is connected to the second transistor and the third contact stud is in contact with the second contact stud; the second contact post has a size substantially the same as the capacitor in a direction perpendicular to the plane of the substrate; the second contact stud and the capacitor are at the same level.

2. The semiconductor device according to claim 1, wherein,

the third contact stud wraps part of the side wall of the second contact stud;

or,

the second contact stud wraps a portion of a sidewall of the third contact stud.

3. The semiconductor device according to claim 1 or 2, characterized in that the semiconductor device further comprises: a first insulating structure; wherein the second contact stud penetrates the first insulating structure; the first insulating structure includes:

a first support layer on the substrate and covering the substrate;

the second supporting layer is positioned on the first supporting layer and covers the first supporting layer;

a first sacrificial layer located in the peripheral region and between the substrate and the first support layer;

and the second sacrificial layer is positioned in the peripheral area and between the first supporting layer and the second supporting layer.

4. The semiconductor device according to claim 3, wherein the semiconductor device further comprises: a second insulating structure covering the first insulating structure; the second insulating structure includes:

a first portion located in the array region; wherein the first contact stud extends through the first portion;

a second portion located in the peripheral region; wherein a surface of the second portion remote from the first insulating structure is substantially flush with a surface of the first portion remote from the first insulating structure; the second portion has a dimension greater than the dimension of the first portion in a direction perpendicular to the plane of the substrate; the third contact stud extends through the second portion.

5. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:

a support structure on the substrate of the array region and disposed around the capacitor; wherein the dimensions of the support structure and the dimensions of the capacitor are substantially the same along a direction perpendicular to the plane of the substrate.

6. The semiconductor device of claim 1, wherein a difference between a characteristic dimension of a top portion of the second contact pillar and a characteristic dimension of a bottom portion of the second contact pillar is less than 10 nanometers.

7. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:

a first interconnect structure comprising: a first sub-interconnect structure and a second sub-interconnect structure; the first sub-interconnection structure is positioned between the substrate of the array region and the capacitor, and is respectively connected with the first transistor and the lower electrode; the second sub-interconnection structure is positioned between the substrate of the peripheral area and the second contact post, and is respectively connected with the second transistor and the second contact post;

A second interconnect structure, comprising: a third sub-interconnect structure and a fourth sub-interconnect structure; wherein the third sub-interconnect structure is located over and connected to the first contact pillars; the fourth sub-interconnect structure is located over and connected with the contact structure.

8. A method of manufacturing a semiconductor device, comprising:

forming a second contact post on the substrate of the peripheral region; wherein the second contact stud is connected with the second transistor; the second contact pillar and the capacitor are formed in the same process procedure and are at the same level; the second contact post has a size substantially the same as the capacitor in a direction perpendicular to the plane of the substrate;

9. The method of manufacturing according to claim 8, further comprising:

forming a first insulating structure material layer covering the substrate; the first insulating structure material layer comprises a first sacrificial material layer, a first supporting material layer, a second sacrificial material layer and a second supporting material layer which are sequentially stacked;

forming a first through hole and a second through hole penetrating the first insulating structure material layer; wherein the first through hole is positioned in the array area; the second through hole is positioned in the peripheral area;

the forming a capacitor on the substrate of the array region comprises:

forming the lower electrode covering the sidewall and the bottom of the first via hole;

forming a capacitance dielectric layer covering the lower electrode;

forming the upper electrode covering the capacitance medium layer;

the forming a second contact pillar on the substrate of the peripheral region comprises:

and forming the second contact pillars in the second through holes.

10. The method of manufacturing according to claim 9, wherein after forming the lower electrode and before forming the capacitor dielectric layer, the method of manufacturing further comprises:

forming a patterned mask layer on the lower electrode and the first via hole; the mask layer is provided with an opening, and the opening exposes the lower electrode and part of the first insulating structure material layer;

removing the first sacrificial material layer and the second sacrificial material layer which are positioned in the array area according to the opening to form a gap; wherein the gap exposes the lower electrode; the rest of the first sacrificial material layers form first sacrificial layers, the rest of the first supporting material layers form first supporting layers, the rest of the second sacrificial material layers form second sacrificial layers, and the rest of the second supporting material layers form second supporting layers; the first sacrificial layer, the first support layer, the second sacrificial layer and the second support layer form a first insulating structure.

11. The method of manufacturing according to claim 10, further comprising:

forming a second insulating structure material layer covering the array region, the first insulating structure and the second contact pillars in the peripheral region,

Performing planarization treatment on the second insulating structure material layer to form a second insulating structure; wherein the second insulating structure comprises a first portion located in the array region and a second portion located in the peripheral region; a surface of the second portion remote from the first insulating structure is substantially flush with a surface of the first portion remote from the first insulating structure; the second portion has a dimension greater than the dimension of the first portion in a direction perpendicular to the plane of the substrate;

forming a third through hole penetrating the first portion; wherein the bottom of the third through hole exposes the electrode contact layer;

forming a fourth through hole through the second portion; wherein the bottom of the fourth through hole exposes the second contact post;

the forming a first contact stud on the capacitor includes:

forming the first contact pillars in the third via holes;

forming a third contact stud on the second contact stud, comprising:

and forming the third contact pillars in the fourth through holes.

12. The method of manufacturing of claim 11, wherein the fourth via further penetrates a portion of the first insulating structure and exposes a portion of a sidewall of the second contact stud; or, the bottom of the fourth through hole is positioned in the second contact column.

13. The method of manufacturing according to claim 8, further comprising:

forming a support structure surrounding the capacitor on a substrate of the array region; wherein the dimensions of the support structure and the dimensions of the capacitor are substantially the same along a direction perpendicular to the plane of the substrate.