WO2022042411A1

WO2022042411A1 - Method for manufacturing fcob storage device, and capacitor thereof

Info

Publication number: WO2022042411A1
Application number: PCT/CN2021/113445
Authority: WO
Inventors: 华文宇; 陶谦; 刘藩东; 夏季
Original assignee: 无锡拍字节科技有限公司
Priority date: 2020-08-26
Filing date: 2021-08-19
Publication date: 2022-03-03
Also published as: CN111968981A; TW202209639A; CN111968981B

Abstract

Disclosed is a method for manufacturing a storage device, comprising: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a conductive pillar on the first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a conductive interconnect and a metal bit line on the second dielectric layer; forming a third dielectric layer on the second dielectric layer; forming a capacitor contact pad on the third dielectric layer; forming a fourth dielectric layer on the third dielectric layer; forming a ferroelectric capacitor on the fourth dielectric layer; forming a fifth dielectric layer on the fourth dielectric layer; forming on the fifth dielectric layer a metal plate line connected to the upper electrode of the capacitor.

Description

A kind of manufacturing method of FCOB memory device and capacitor thereof

technical field

The present invention relates to the field of manufacturing of memories. Specifically, the present invention relates to a manufacturing method of an FCOB (Ferroelectric Capacitor Over Bitline) storage device and a capacitor thereof.

Background technique

Ferroelectric memory is a special process of non-volatile memory. When an electric field is applied to the iron transistor, the central atom follows the electric field and stops at the first low-energy state position, and when an electric field inversion is applied to the same iron transistor, the central atom moves in the crystal in the direction of the electric field and stops at The second lowest energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarized charges under the action of an electric field. The polarization charge formed by the reversal of the ferroelectric domain under the electric field is higher, and the polarization charge formed by the ferroelectric domain without reversal under the electric field is lower. memory.

When the electric field is removed, the central atom remains in a low-energy state, and the state of the memory is also preserved and will not disappear. Therefore, the ferroelectric domain can be used to invert under the electric field to form high-polarization charges, or no inversion to form low-polarity charges. The electric charge is used to determine whether the memory cell is in the "1" or "0" state. The inversion of the ferroelectric domain does not require a high electric field, and only the general working voltage can change the state of the memory cell to be in "1" or "0"; it also does not require a charge pump to generate high-voltage data erasure, so there is no erasure Write delay phenomenon. This feature enables the ferroelectric memory to continue to save data after power failure, with fast writing speed and unlimited write life, and it is not easy to write bad. And, compared with existing non-volatile memory technologies, ferroelectric memory has higher write speed and longer read and write life.

FIG. 1 shows a schematic circuit diagram of an exemplary ferroelectric memory cell 100 . The ferroelectric memory cell 100 is a memory element of a ferroelectric memory device, and may include various designs and configurations. As shown in FIG. 1 , ferroelectric memory cell 100 is a “1T-1C” cell that includes capacitor 12 and transistor 14 . Transistor 14 is an NMOS transistor. The source S of the transistor 14 is electrically connected to the bit line BL. The gate of transistor 14 is electrically connected to word line WL. The drain D of the transistor 14 is electrically connected to the lower electrode 18 of the capacitor 12 . The upper electrode 16 of the capacitor 12 is connected to the plate line PL.

FIG. 2 shows a schematic perspective view of an exemplary ferroelectric memory cell 100 . In order to ensure that a strong signal can be obtained when the polarization of the ferroelectric capacitor of the ferroelectric memory cell 100 changes, the area of the ferroelectric capacitor needs to be large enough. As shown in FIG. 2 , the area occupied by the existing planar ferroelectric capacitor 12 is relatively large, which limits the integration degree of the ferroelectric memory unit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for manufacturing a storage device and a capacitor thereof, and the method for manufacturing a storage device and a capacitor thereof according to the present invention can improve the integration degree of the ferroelectric memory and reduce the cost of the ferroelectric memory chip.

According to an embodiment of the present invention, a method for manufacturing a memory device is provided, including:

a semiconductor substrate is provided, the semiconductor substrate includes a ferroelectric memory cell region, the ferroelectric memory cell region has a source region, a drain region, a gate region, an isolation region, electrodes and interconnecting metal lines above each functional region;

A first interconnect structure is formed that includes capacitor conductive pillars, bit line conductive pillars, capacitor conductive interconnects on top of the capacitor conductive pillars, metal bit lines on top of the bit line conductive pillars, and between them. the first dielectric layer;

forming a capacitor contact pad, the capacitor contact pad comprising a metal conductive post electrically connected to the capacitor conductive post, a contact pad on top of the metal conductive post, and a second dielectric layer therebetween;

forming a third dielectric layer and a hard mask layer in sequence;

The hard mask layer is patterned through photolithography and etching processes, and the patterned hard mask layer is used as a mask for etching to form deep holes in the third dielectric layer, and then the hard mask layer is removed. the bottom of the deep hole exposes the capacitor contact pad;

forming a first electrode layer;

forming a high-K ferroelectric oxide layer and a second electrode layer;

Form metal interconnects and board wires.

In an embodiment of the present invention, forming the first electrode layer includes: depositing the protective layer and the first electrode layer in sequence;

The protective layer and the first electrode layer on the top surface of the third dielectric layer are removed, and only the protective layer and the first electrode layer on the bottom and sides of the deep hole are retained.

In one embodiment of the present invention, the method for manufacturing a memory device further includes: after forming the high-K ferroelectric oxide layer and the second electrode layer, depositing a protective layer and a filling metal, and then removing the third dielectric layer by chemical equipment grinding The conductive metal, the high-K ferroelectric oxide layer and the second electrode layer on the top surface, only the protective layer, the conductive metal, the high-K ferroelectric oxide layer and the second electrode layer in the deep hole remain.

In one embodiment of the present invention, forming the metal interconnection and the plate wire includes: forming a fourth dielectric layer on the top surface of the third dielectric layer; drilling holes on the fourth dielectric layer and forming the metal interconnection, the metal interconnection The connection is electrically connected to the second electrode layer; a plate line is formed over the metal interconnection.

In one embodiment of the present invention, the method for manufacturing a memory device further includes: after forming the high-K ferroelectric oxide layer and the second electrode layer, removing part of the first electrode layer on the top surface through a process such as photolithography and etching , the high-K ferroelectric oxide layer and the second electrode layer, only the first electrode layer, the high-K ferroelectric oxide layer and the second electrode layer around the sidewall, bottom and top of the deep hole are retained, so that each capacitor is mutually separate.

In one embodiment of the present invention, forming the metal interconnection and the plate wire includes: forming a fourth dielectric layer on the top surface of the third dielectric layer; drilling holes on the fourth dielectric layer and forming the metal interconnection, the metal interconnection is electrically connected to the second electrode layer, wherein the metal interconnection extends from the second electrode layer at the bottom of the deep hole to the top of the fourth dielectric layer, or the metal interconnection extends from the second electrode layer around the top of the deep hole to the top of the fourth dielectric layer A top of the fourth dielectric layer; a plate line is formed over the metal interconnect.

In one embodiment of the present invention, the method for manufacturing a memory device further includes: after forming the first electrode layer, reaming the top of the deep hole to form a reaming structure, wherein the reaming structure is located at the top of the deep hole and has a cross section. The area is larger than the cross-sectional area of the deep hole.

In an embodiment of the present invention, the third dielectric layer is formed by laminating at least two different insulating materials,

The method further includes, after forming the deep hole and removing the hard mask layer, processing the sidewall of the deep hole by wet etching, the wet etching having different etching rates for the at least two different insulating materials , thereby forming one or more protrusions on the sidewall of the deep hole.

According to another embodiment of the present invention, there is provided a capacitor for a memory device, comprising:

a semiconductor substrate, the semiconductor substrate includes a ferroelectric memory cell region, the ferroelectric memory cell region has a source region, a drain region, a gate region, an isolation region, electrodes and interconnecting metal lines above each functional region;

a first interconnect structure comprising capacitor conductive pillars, bit line conductive pillars, capacitor conductive interconnects on top of the capacitor conductive pillars, metal bit lines on top of the bit line conductive pillars, and a first dielectric therebetween Floor;

a capacitor contact pad, the capacitor contact pad comprising a metal conductive post electrically connected to the capacitor conductive post, a contact pad on top of the metal conductive post, and a second dielectric layer therebetween;

a third dielectric layer stacked on the second dielectric layer;

a deep hole formed in the third dielectric layer, the bottom of the deep hole exposing the capacitor contact pad;

depositing a first electrode layer, a high-K ferroelectric oxide layer and a second electrode layer on the sidewall and bottom of the deep hole in sequence;

a plate wire connected to the second electrode layer by a metal interconnect.

In another embodiment of the present invention, the third dielectric layer is formed by stacking at least two different insulating materials, and the sidewall of the deep hole has one or more protrusions.

In another embodiment of the present invention, the capacitor of the memory device further includes a reaming structure formed by etching the top of the deep hole, the reaming structure is located at the top of the deep hole and the cross-sectional area is larger than that of the deep hole structure , the first electrode layer is only provided on the bottom and side of the deep hole below the hole-reaming structure, and the high-K ferroelectric oxide layer and the second electrode layer are formed on the sidewall and bottom of the deep hole and the hole-reaming structure.

In the ferroelectric capacitor and the manufacturing method thereof provided by the present invention, a bit line is formed, a plurality of deep hole structures are formed on the bit line, and a lower electrode, a ferroelectric material layer and an upper electrode of the capacitor are sequentially formed in the deep hole structure. , realizes a three-dimensional ferroelectric capacitor structure, therefore, this structure of the present invention is also called FCOB (Ferroelectric Capacitor Over Bitline). The use of the bottom electrode and the top electrode of the deep hole structure can significantly improve the equivalent remanent polarization of the ferroelectric capacitor under the same face-to-face area, so that the ferroelectric memory can continue to be proportionally reduced and still provide a large enough voltage Window, below the 130nm process node, three-dimensional ferroelectric capacitors can be realized, and the storage density is high.

The preparation method of the three-dimensional ferroelectric capacitor of the present invention is completely compatible with the CMOS process, which is convenient for integration and reduces the manufacturing cost.

Description of drawings

In order to further clarify the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is understood that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar numerals for clarity.

FIG. 1 shows a schematic circuit diagram of an exemplary ferroelectric memory cell 100 .

FIG. 2 shows a schematic perspective view of an exemplary ferroelectric memory cell 100 .

3A-3K illustrate cross-sectional views of a process of forming a capacitor of a ferroelectric memory cell according to one embodiment of the present invention.

Figure 4 shows a flow diagram of forming a capacitor for a ferroelectric memory cell according to one embodiment of the present invention.

FIG. 5 shows a schematic cross-sectional view of a planarization process for a capacitor according to an embodiment of the present invention.

Figure 6 shows a flow diagram of forming a capacitor of a ferroelectric memory cell according to one embodiment of the present invention.

7A-7E illustrate cross-sectional views of a process of forming a capacitor of a ferroelectric memory cell according to one embodiment of the present invention.

Figure 8 shows a schematic perspective view of a spaced capacitor cell according to one embodiment of the present invention.

9 shows a flow diagram of forming a capacitor for a ferroelectric memory cell according to one embodiment of the present invention.

10 shows a cross-sectional view of a capacitor forming a ferroelectric memory cell in accordance with one embodiment of the present invention.

11A shows a schematic cross-sectional view of the capacitor deep hole portion after forming the capacitor deep hole through an etching process and removing the carbon layer and the silicon oxynitride layer according to an embodiment of the present invention.

FIG. 11B shows a schematic cross-sectional view of a capacitor deep hole portion having a sidewall with protrusions according to an embodiment of the present invention.

detailed description

In the following description, the invention is described with reference to various embodiments. However, one skilled in the art will recognize that the various embodiments may be practiced without one or more of the specific details or with other alternative and/or additional methods, materials or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the various embodiments of the invention. Similarly, for purposes of explanation, specific quantities, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the present invention may be practiced without the specific details. Furthermore, it is to be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

In general, terms are to be understood, at least in part, from the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or a combination of features, structures or characteristics in the plural depending at least in part on context. Similarly, terms such as "a," "an," or "the" may in turn be construed to express singular usage or to express plural usage, depending at least in part on the context.

It can be easily understood that the meanings of "on", "on", and "over" in the present invention should be interpreted in the broadest manner such that "on" Not only means being directly on something, but can also include being on something with intervening features or layers in between, and "on", or "over" not only Means being on or over something, and can also include being over or over something (ie, directly over something) without intervening features or layers in between.

Additionally, spatially relative terms such as "below", "under", "lower", "above", "upper", etc. may be used herein to facilitate the description of an element or feature relative to relationship to another element or feature as shown in the drawings. Spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation of the device as depicted in the figures. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptions used herein interpreted accordingly as well.

The term "substrate" as used herein refers to the material to which subsequent layers of material are added. The substrate itself can be patterned. The material added over the substrate may be patterned, or may remain unpatterned. Additionally, the substrate may comprise a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can also be made of an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

The term "layer" as used herein refers to a site of material that includes a region of thickness. A layer may extend over all of the underlying or overlying structure, or may have less extension than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, the region having a thickness that is less than the thickness of the continuous structure. For example, layers may be located between any pair of horizontal planes, or at the top or bottom surface of the continuous structure. The layers may extend horizontally, vertically, and/or along tapered surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers above and/or one or more layers below. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

3A-3K illustrate cross-sectional views of a process of forming a capacitor of a ferroelectric memory cell according to one embodiment of the present invention. Figure 4 shows a flow diagram of forming a capacitor for a ferroelectric memory cell according to one embodiment of the present invention. A process of forming a capacitor of a ferroelectric memory cell is described in conjunction with FIGS. 3A-3K and FIG. 4 .

First, at step 410, a semiconductor substrate 310 is provided, as shown in FIG. 3A. The substrate 310 may have completed the fabrication process of the functional regions. For example, the substrate 310 includes a circuit region 311 and a ferroelectric memory cell region 312 . The circuit region 311 and the ferroelectric memory cell region 312 have been formed with source regions, drain regions (not shown in the figure), gate regions 313, inter-device isolation regions 314, electrodes and interconnecting metal lines above the respective functional regions (not shown in the figure). In order to clarify and simplify the description of the present invention, in FIG. 3A , only part of the circuit region 311 and the ferroelectric memory cell region 312 are shown. The circuit area 311 may be used to control the ferroelectric memory cell area 312 .

Next, at step 420 , a first interconnect structure is formed on the substrate 310 . In one embodiment of the present invention, forming the first interconnection structure may include: forming a dielectric layer 321 on the surface of the substrate; The external electrodes of each functional area on the substrate 310 are removed; the adhesive layer and the tungsten metal layer are sequentially deposited to fill the through hole; the chemical mechanical polishing process is performed to remove the excess dielectric layer 321, the adhesive layer and the tungsten metal layer to form a secondary layer from the substrate 310 The surface electrode extends to a plurality of tungsten

conductive pillars

323, 324, 325 on the top surface of the dielectric layer 321, as shown in FIG. 3B, and then a dielectric layer 329 and a first metal layer are formed on the plurality of tungsten conductive pillars, as shown in FIG. 3C Show. In other embodiments of the present invention, other metals may be used as materials for forming the conductive pillars. In the specific embodiment shown in FIG. 3B , titanium nitride can be formed as an adhesive layer (not shown in the figure) between the tungsten conductive pillars and the surface electrodes of the substrate 310 and between the tungsten conductive pillars and the dielectric layer. The plurality of tungsten conductive pillars may include circuit conductive pillars 323, capacitor conductive pillars 324, bit line conductive pillars 325, and the like. The circuit conductive column 323 is connected to the surface electrode of the circuit region 311, the capacitor conductive column 324 is used to electrically connect the doped region (source or drain) of the transistor in the ferroelectric memory cell region 312 with the capacitor, and the bit line conductive column 325 is used for The other doped region (source or drain) of the transistor in the ferroelectric memory cell region 312 is electrically connected to the bit line. In the specific embodiment shown in FIG. 3C , the first metal layer is a metal copper layer, which may include circuit lines 326 , capacitor conductive interconnects 327 , and metal bit lines 328 . The circuit line 326 is electrically connected to the circuit conductive post 323 , the capacitor conductive interconnect 327 is electrically connected to the capacitor conductive post 324 , and the metal bit line 328 is electrically connected to the bit line conductive post 325 . The capacitor conductive interconnect 327 is a square when viewed from the top surface, and the metal bit line 328 is a metal line perpendicular to the paper surface.

Those skilled in the art should understand that the formation method of the first interconnect structure is not limited to the above specific examples. In addition, other processes may also be performed before or after the formation of the first interconnect structure, eg, to form one or more other conductive interconnect structures.

Then, at step 430, capacitor contact pads 330 are formed, as shown in Figure 3D. In one embodiment of the present invention, forming the capacitor contact pad may include forming a dielectric layer 331 on the surface of the first metal layer; forming a through hole in the dielectric layer 331 through processes such as photolithography and etching, the window exposing the capacitor conductive interconnection Part of the top surface of the connection 327; depositing a metal layer to fill the via hole, in this embodiment the metal layer is metal copper; removing the excess metal layer to form a conductive layer extending from the top surface of the capacitor conductive interconnect 327 to the top surface of the dielectric layer 331 pillars 334 ; a dielectric layer 333 and a capacitor contact pad 330 are formed on the top surfaces of the conductive pillars 334 . At the same time as the above-mentioned forming process of the capacitor contact pad 330 , the conductive pillars 335 and the circuit lines 332 electrically connected to the circuit lines 326 may be formed above the circuit region 311 , so that the circuit conductive pillars 323 extend to the top surface of the dielectric layer. In this embodiment, the conductive pillars 335 and the circuit lines 332 are both copper metal. In this embodiment, the conductive pillars and the circuit lines are respectively etched and filled in two steps. In other embodiments, they can also be unified first. The conductive pillars and the through holes of the circuit lines are etched and then filled with metal at one time to form the conductive pillars and the circuit lines. Similarly, in this embodiment, the conductive pillars 334 and the capacitor contact pads 330 in the memory cell area are respectively made through holes in two steps. For etching and filling, in other embodiments, the conductive pillars and the through-holes of the capacitor contact pads may be uniformly etched first, and then metal is filled at one time to form the conductive pillars and the capacitor contact pads at the same time. The area of the capacitor contact pad 330 is larger than the bottom area of the subsequently formed deep hole, so the capacitor contact pad 330 can be used as an etch stop layer for deep hole etching.

In the embodiment of the present invention, the

dielectric layers

331 and 333 may be of the same material as the

dielectric layers

321 and 329 , or may be of different materials from the

dielectric layers

321 and 329 .

In actual operation, the steps of forming circuit conductive pillars and circuit lines can be repeated in the circuit area for many times, as shown in FIG. 3E , thereby forming circuit conductive pillars and circuit line structures with required heights. In the example shown in FIG. 3E, the circuit conductive pillars and circuit lines have five layers of circuit conductive pillars and circuit line structures, however, those skilled in the art should understand that in other embodiments of the present invention, the circuit area may have more or Fewer conductive posts and circuit trace structures. The dielectric materials and metal materials used in the conductive pillars and circuit structures of each layer may be the same or different.

In the above steps and subsequent steps, suitable metals can be selected for the conductive pillars and lines according to actual process requirements. For example, the conductive pillars can be tungsten metal conductive pillars and the lines can be copper. Likewise, the multiple dielectric layers (eg, the

dielectric layers

331, 333, etc.) between the conductive pillars and the lines may be a single material layer or a composite material layer formed by stacking multiple layers of materials individually or in combination. In the embodiment of the present invention, the dielectric layer may be silicon oxide, silicon oxynitride, borosilicate glass, phosphorous silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated glass silicate glass (FSG), low-K medium and other inorganic materials; can also be polyimide, photosensitive epoxy resin, solder resist ink, green paint, dry film, photosensitive build-up material, BCB (bisphenylcyclobutene resin) ) or organic materials such as PBO (phenylbenzobisoxazole resin). The dielectric layer can be fabricated by chemical vapor deposition, rolling, spin coating, spray coating, printing, non-spin coating, hot pressing, vacuum pressing, soaking, pressure bonding and the like.

Next, in step 440, multilayer dielectric layers 336, 337 are formed, and capacitor deep holes 361 are formed in the

dielectric layers

336, 337 through an etching process, as shown in FIG. 3F. Similar to the aforementioned dielectric layers 331 and 333 , in this embodiment, the

dielectric layers

336 and 337 may be a multi-layer structure or a single material layer. In an embodiment of the present invention, forming the capacitor deep hole 361 through an etching process may include forming a mask layer, forming a window in the mask layer through a photolithography process to expose the underlying dielectric layer, and etching the dielectric layer until the capacitor is exposed The top of the pad is contacted and the mask layer is finally removed. The capacitor contact pad can be used as an etch stop layer for the deep hole etch process. The area of the capacitor contact pad is larger than the bottom area of the deep hole 361 .

At step 450, a first electrode layer 371 is formed on the bottom and sidewalls of the deep hole 361, as shown in FIG. 3G. The first electrode layer 371 is an electrode layer of the capacitor, for example, can be one or more of the following materials: TiNx, TaNx, TiAlNx, TiCNx, TaAlNx, TaCNx, AlNx, Ru, RuOx, Ir, IrOx, W, WCNx, Wsix, Pt, Au, Ni, Mo or a combination of these materials. The first electrode may be deposited by one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam Ebeam deposition, molecular beam epitaxy MBE deposition, pulsed laser deposition (PLD), and similar deposition processes layer 371 , and then remove the material layer on the top surface of the dielectric layer, leaving only the material layer on the bottom and side surfaces of the deep hole 361 . In a specific embodiment of the present invention, if the capacitor contact pad is a copper pad, in order to prevent copper migration, a protective layer 372 is deposited before the first electrode layer 371 is deposited; if the capacitor contact pad is a tungsten pad, it can be omitted Deposition step of protective layer 372 . The protective layer 372 may be tantalum nitride (TaN), tungsten nitride (WNx), or the like.

At step 460, a ferroelectric material layer and a second electrode layer 382 are formed, which in this embodiment is a high-K ferroelectric oxide layer 381, as shown in FIG. 3H. The high-K ferroelectric oxide layer 381 is the dielectric layer of the capacitor, for example, can be one or more of the following materials _: HfOx, _AlOx , _ZrOx , _LaOx , _TaOx , _NbOx , _GdOx , YO _x , _SiOx , SrOx or a composite of these materials. High-K iron can be deposited by one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam Ebeam deposition, molecular beam epitaxy MBE deposition, pulsed laser deposition (PLD), and similar deposition processes electrical oxide layer. The second electrode layer 382 is another electrode layer of the capacitor, for example, can be one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), titanium nitride Aluminum (TiAlNx), Titanium Carbonitride (TiCNx), Tantalum Nitride (TaNx), Tantalum Silicon Nitride (TaSiNx), Tantalum Aluminum Nitride (TaAlNx), Tungsten Nitride (WNx), Tungsten Silicide (WSix), Carbon Tungsten nitride (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), doped polysilicon, transparent conductive oxide (TCO) or iridium oxide (IrOx) or a composite of these materials. The second electrode may be deposited by one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam Ebeam deposition, molecular beam epitaxy MBE deposition, pulsed laser deposition (PLD), and similar deposition processes Layer 382.

In step 470, a protective layer 391 and a filling metal 392 are formed, as shown in FIG. 3I, and then the protective layer 391 and the filling metal 392 on the top surface of the dielectric layer, the high-K ferroelectric oxide layer 381 and the second electrode are removed by chemical equipment grinding Layer 382, as shown in FIG. 3J, only the protective layer 391 and the contact layer 392, the high-K ferroelectric oxide layer 381 and the second electrode layer 382 in the deep hole 361 remain. In an embodiment of the present invention, the protective layer 391 is similar to the protective layer 372, and may be, but not limited to, TaN or tungsten nitride. Fill metal 392 is similar to the contact pads and can be, but not limited to, copper.

Next, at step 480, metal interconnects and board lines are formed. In one embodiment of the present invention, forming metal interconnects and board lines may include: firstly forming a dielectric layer 393; drilling holes on the dielectric layer 393 and depositing metal in the holes, wherein the deposited metal layer is formed in the circuit area Conductive pillars 395 connected to the underlying conductive lines and conductive pillars, then a circuit line 397 is formed on the conductive pillars, and a conductive pillar 396 connected to the filling metal 392 deposited on the upper electrode of the capacitor is formed in the memory cell area, and then on the conductive pillars 396 A metal plate wire 394 is formed thereon as shown in FIG. 3K , wherein the metal plate wire 394 is a metal wire extending perpendicular to the paper surface. In this embodiment, the conductive pillars and the circuit lines are etched and filled in two steps, respectively. In other embodiments, the conductive pillars and the through holes of the circuit lines can also be etched uniformly, and then filled with metal at one time. Conductive pillars and circuit lines. In this embodiment, the conductive pillars and the metal plate lines are etched and filled in two steps, respectively. The holes are then filled with metal in one go while forming conductive pillars and sheet metal lines. So far, the ferroelectric capacitors and plate lines of the memory are formed, and then structures such as dielectric layers, metal interconnections, and other metal layers are formed on the plate lines to form external connections, which will not be described in detail here.

The dielectric layer 392 may be of the same material as the dielectric layer 321 , or may be of a different material from the dielectric layer 321 . In the foregoing embodiments, when copper metal is used as the conductive pillars and metal lines, a protective layer of tantalum nitride or tungsten nitride can be deposited outside the copper metal layer to prevent the diffusion of metal copper.

In the foregoing embodiments, the dielectric layer 321 forming the first interconnect structure may be referred to as the first dielectric layer, the dielectric layer 329 forming the metal bit lines may be referred to as the second dielectric layer, and the

dielectric layers

331 and 333 forming the capacitor contact pads It may be referred to as the third dielectric layer, the

dielectric layers

336 and 337 forming the ferroelectric capacitor may be collectively referred to as the fourth dielectric layer, and the dielectric layer 393 covering the ferroelectric capacitor may be referred to as the fifth dielectric layer.

In the above embodiment, the metal interconnection process of the peripheral circuit region 311 is combined with the capacitor and metal interconnection process of the ferroelectric memory cell region 312, so that the peripheral circuit region 311 and the ferroelectric memory cell are completed at the same time as the capacitor is formed. The metal interconnection and lead-out of the region 312 is beneficial to simplify the process steps and reduce the manufacturing cost.

In the embodiment of the present invention, the structure of the capacitor unit is a stacked structure of the capacitor contact pad-protective layer-first electrode layer-high-K ferroelectric oxide layer-second electrode layer-protective layer-filling metal. The bit line is formed and the contact pad is formed on the bit line before the capacitor cell is formed, and the capacitor cell is formed on the metal bit line, so this structure of the present invention is also called FCOB (Ferroelectric Capacitor Over Bitline (Ferroelectric Capacitor Over Bitline) ). The use of the bottom electrode and the top electrode of the deep hole structure can significantly improve the equivalent remanent polarization of the ferroelectric capacitor under the same face-to-face area, so that the ferroelectric memory can continue to be proportionally reduced and still provide a large enough voltage Window, below the 130nm process node, three-dimensional ferroelectric capacitors can be realized, and the storage density is large.

The preparation method of the three-dimensional ferroelectric capacitor of the present invention is completely compatible with the CMOS process, is convenient for integration, and reduces the manufacturing cost

After the MIM structure film of the ferroelectric capacitor is deposited, it will be planarized by a chemical mechanical polishing process, and the MIM film outside the deep hole structure will be ground off to form an independent ferroelectric capacitor structure, as shown in Figure 5, through the planarization process , metal ion residues are likely to appear at the circle marks in FIG. 5, resulting in leakage of the upper and lower electrodes. If the lithography alignment deviation occurs on the upper electrode 4, it is easy to cause a direct short circuit of the upper and lower electrodes; therefore, the embodiments of FIGS. 6 to 8 are aimed at the above problem, a new solution was proposed.

Figure 6 shows a flow diagram of forming a capacitor of a ferroelectric memory cell according to one embodiment of the present invention. In the embodiment shown in FIG. 6 , steps 610 to 640 are similar to steps 410 to 440 shown in FIG. 4 above. To simplify the description, detailed descriptions of steps 610 to 640 are omitted.

In step 650, a first electrode layer 711, a high-K ferroelectric oxide layer 712 and a second electrode layer 713 are sequentially formed, as shown in FIG. 7A. The materials and formation processes of the first electrode layer 711, the high-K ferroelectric oxide layer 712 and the second electrode layer 713 are similar to the materials and formation processes of the above-mentioned first electrode layer, the high-K ferroelectric oxide layer and the second electrode layer, Similarly, a protective layer (not numbered in the figure) for preventing copper diffusion is formed between the copper metal contact pad and the lower electrode 711 of the ferroelectric capacitor, which will not be described in detail here.

In step 660, the dielectric layer is filled, and then a part of the first electrode layer 711, the high-K ferroelectric oxide layer 712 and the second electrode layer 713 on the top surface are removed through photolithography, etching and other processes, and only the sidewalls of the deep hole 714 are left. , the first electrode layer 711, the high-K ferroelectric oxide layer 712, and the second electrode layer 713 at the bottom and the periphery, so that each capacitor is separated from each other, as shown in FIG. 7B. FIG. 8 shows a schematic perspective view of a capacitor unit separated after photolithography and etching in step 660 according to an embodiment of the present invention, wherein the schematic diagram of the protective layer is omitted, which is different from the conventional planar capacitor as shown in the figure , the capacitor has a three-dimensional structure.

Next, at step 670, metal interconnects and board lines are formed. In an embodiment of the present invention, forming metal interconnects and board lines may include forming a dielectric layer 715, drilling holes in the dielectric layer 715, and forming a plurality of

conductive pillars

731, 732, which are respectively connected to the second Electrode layer 713, circuit conductive pillars 716, next, a dielectric layer is formed above the capacitive conductive pillars 731, and metal is formed by opening holes to form metal plate lines 733 connected to the conductive pillars 731, and holes are deposited in the circuit area to form a conductive circuit with the circuit. The metal lines 734 connected to the posts 716 are shown in FIG. 7C. In the embodiment shown in FIG. 7C , the conductive pillars 731 extend from the bottom of the capacitor deep hole to the top of the dielectric layer 715 . In another embodiment of the present invention, the conductive pillars 731 may be provided at the top edge of the capacitor deep hole, as shown in Figure 7D. In yet another embodiment of the present invention, conductive metal is filled in the deep hole, and then conductive pillars 731 are formed on top of the conductive metal, as shown in FIG. 7E .

9 shows a flow diagram of forming a capacitor for a ferroelectric memory cell according to one embodiment of the present invention. In the embodiment shown in FIG. 9 , steps 910 to 940 are similar to steps 410 to 440 shown in FIG. 4 above. To simplify the description, detailed descriptions of steps 910 to 940 are omitted.

Different from the previous embodiments, after the capacitor deep hole is formed in step 940, in step 951, the top of the deep hole structure 101 is reamed, as shown in FIG. 10A. Specifically, reaming can be performed on the top of the deep hole by dry etching to form the reaming structure 102 . The reaming structure 102 is located at the top of the deep hole and has a cross-sectional area larger than that of the deep hole structure.

At step 950, a first electrode layer 103 is formed, as shown in FIG. 10B. The first electrode layer 103 is the bottom electrode layer of the capacitor. Then, the material layers on the top surface of the dielectric layer, the sidewalls and the bottom of the hole reaming structure are removed, and only the material layers on the bottom and side surfaces of the deep hole 101 below the hole reaming structure are retained, as shown in FIG. 10C .

In step 960, a high-K ferroelectric oxide layer 104 and a second electrode layer 105 are formed, wherein the high-K ferroelectric oxide layer 104 completely covers the first electrode layer of the deep hole and the inner surface of the expanded hole structure, as shown in FIG. 10D Show. The second electrode layer 105 completely fills the deep hole 101 and the hole reaming structure 102 .

In step 970 , the excess high-K ferroelectric oxide layer 104 and the second electrode layer 105 on the surface of the crystal substrate are ground off by chemical mechanical grinding to form a ferroelectric capacitor structure, as shown in FIG. 10E .

In step 980, a dielectric layer 106 is formed above the ferroelectric capacitor, through holes are formed on the dielectric layer 106, and conductive pillars 107 connected to the upper electrodes of the ferroelectric capacitor are formed in the through holes. Then, metal interconnects, plate lines and bit lines are formed over the dielectric layer 106, as shown in FIG. 10F. For specific steps of forming metal interconnections, plate lines and bit lines, reference may be made to FIG. 3K in conjunction with the description of step 480 in the foregoing embodiment to form metal interconnections, plate lines, and bit lines.

11A and 11B show another embodiment of the present invention, which provides a method of forming a capacitor for a ferroelectric memory cell. In this embodiment, the method of forming the capacitor of the ferroelectric memory cell may be similar to the processes shown in FIGS. 4 , 6 and 9 above. The main difference of this embodiment is that in the aforementioned embodiment shown in FIG. 3K , one or more

dielectric layers

336 and 337 are collectively referred to as the fourth dielectric layer, wherein the

dielectric layers

336 and 337 are formed by laminating at least two different insulating materials. And after steps 440 , 640 and 940 , the sidewalls of the capacitor deep holes are processed by wet etching, and one or more protrusions are formed on the sidewalls of the deep holes. 11A shows a schematic cross-sectional view of the capacitor deep hole portion after forming the capacitor deep hole through an etching process and removing the carbon layer and the silicon oxynitride layer according to an embodiment of the present invention. As shown in FIG. 11A , the fourth dielectric layer may include three layers of the first insulating material 111 and two layers of the second insulating material 112 , and each layer of the first insulating material and the second insulating material are alternately stacked in sequence. When forming the deep hole structure of the ferroelectric capacitor, the deep hole structure 113 with flush sidewalls as shown in FIG. 11A is first formed, and after the structure of FIG. 11A is formed by etching, the structure formed in FIG. 11A is then wet-etched Etching, through the wet etching process, the etching rates of different insulating materials in the dielectric layer are different to form different etching depths, thereby forming different degrees of sidewall depression between different layers, forming a protruding structure between different layers. 114. For example, the etching rate of the first insulating material layer 111 is lower than the etching rate of the second insulating material layer 112, and after a certain time, the first insulating material layer 111 protrudes from the second insulating material layer 112, as shown in FIG. 11B Therefore, the area of the capacitor can be increased under the same aperture, and the ferroelectric performance can be improved. Then, the bottom electrode layer, the ferroelectric material layer and the top electrode layer for forming the ferroelectric capacitor are deposited in the deep hole 114 with the protruding structure of different layers. For the specific steps, please refer to the aforementioned 460-480, 660-670 and 960 -980 Step description. Those skilled in the art should understand that the fourth dielectric layer used to form the deep hole structure of the ferroelectric capacitor is not limited to the alternately stacked structure of three layers of the first insulating material 111 and two layers of the second insulating material 112 shown in FIG. 11A . The fourth dielectric layer forming the ferroelectric capacitor deep hole structure may include a stacked structure of three or more insulating materials, and the thickness and position of each insulating material may be set according to actual needs.

The material used to form the second dielectric layer of the ferroelectric capacitor deep hole structure can be selected from: silicon oxide, silicon oxynitride, borosilicate glass, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) , fluorinated glass silicate glass (FSG), low-K medium and other inorganic materials; can also be polyimide, photosensitive epoxy resin, solder resist ink, green paint, dry film, photosensitive build-up material, Organic materials such as BCB (bisphenylcyclobutene resin) or PBO (phenylbenzobisoxazole resin), or a combination thereof. The wet etching process may be etched with an acidic solution such as hydrochloric acid, phosphoric acid, and hydrofluoric acid.

Although the foregoing embodiments respectively introduce the steps of several embodiments, the steps described in the foregoing different embodiments are not completely inseparable, and the specific steps and structures of the various embodiments can also be replaced or combined with each other, and no one will be described here. An example.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications and changes can be made therein without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the above-disclosed exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalents.

Claims

A method of manufacturing a memory device, comprising:

a semiconductor substrate is provided, the semiconductor substrate includes a ferroelectric memory cell region, the ferroelectric memory cell region has a source region, a drain region, a gate region, an isolation region, electrodes and interconnecting metal lines above each functional region;

A first interconnect structure is formed, the first interconnect structure including a capacitor conductive pillar, a bit line conductive pillar, a capacitor conductive interconnect on top of the capacitor conductive pillar, a metal bit line on top of the bit line conductive pillar, and a th a dielectric layer;

forming a capacitor contact pad, the capacitor contact pad comprising a metal conductive post electrically connected to the capacitor conductive post, a contact pad on top of the metal conductive post, and a second dielectric layer therebetween;

forming a third dielectric layer and a hard mask layer in sequence;

The hard mask layer is patterned through photolithography and etching processes, and the patterned hard mask layer is used as a mask for etching to form deep holes in the third dielectric layer, and then the hard mask layer is removed. the bottom of the deep hole exposes the capacitor contact pad;

forming a first electrode layer;

forming a high-K ferroelectric oxide layer and a second electrode layer;

Form metal interconnects and board wires.
The method for manufacturing a memory device according to claim 1, wherein forming the first electrode layer comprises: depositing the protective layer and the first electrode layer in sequence;

The protective layer and the first electrode layer on the top surface of the third dielectric layer are removed, and only the protective layer and the first electrode layer on the bottom and sides of the deep hole are retained.
The method for manufacturing a memory device according to claim 1, further comprising: after forming the high-K ferroelectric oxide layer and the second electrode layer, depositing a protective layer and a filling metal, and then removing the first The conductive metal, the high-K ferroelectric oxide layer and the second electrode layer on the top surface of the three dielectric layers only retain the protective layer, the conductive metal, the high-K ferroelectric oxide layer and the second electrode layer in the deep hole.
The method for manufacturing a memory device according to claim 1, wherein forming the metal interconnection and the plate line comprises: forming a fourth dielectric layer on the top surface of the third dielectric layer; drilling holes on the fourth dielectric layer and forming a metal interconnection that is electrically connected to the second electrode layer; a plate line is formed over the metal interconnection.
The method for manufacturing a memory device according to claim 1, further comprising: after forming the high-K ferroelectric oxide layer and the second electrode layer, removing part of the top surface by photolithography, etching and other processes An electrode layer, a high-K ferroelectric oxide layer and a second electrode layer, only the first electrode layer, the high-K ferroelectric oxide layer and the second electrode layer around the sidewall, bottom and top of the deep hole are retained, so that each capacitors are separated from each other.
The method of manufacturing a memory device according to claim 5, wherein forming the metal interconnection and the plate line comprises: forming a fourth dielectric layer on the top surface of the third dielectric layer; drilling holes on the fourth dielectric layer and forming a metal interconnection electrically connected to the second electrode layer, wherein the metal interconnection extends from the second electrode layer at the bottom of the deep hole to the top of the fourth dielectric layer, or the metal interconnection extends from the top of the deep hole The surrounding second electrode layer extends to the top of the fourth dielectric layer; a plate line is formed over the metal interconnection.
The method for manufacturing a memory device according to claim 1, further comprising: after forming the first electrode layer, reaming the top of the deep hole to form a reaming structure, wherein the reaming structure is located at the bottom of the deep hole. the top and the cross-sectional area is larger than the cross-sectional area of the deep hole.
The method for manufacturing a memory device according to claim 1, wherein the third dielectric layer is formed by laminating at least two different insulating materials,

The method further includes, after forming the deep hole and removing the hard mask layer, processing the sidewall of the deep hole by wet etching, the wet etching having different etching rates for the at least two different insulating materials , thereby forming one or more protrusions on the sidewall of the deep hole.
A capacitor for a memory device, comprising:

a semiconductor substrate, the semiconductor substrate includes a ferroelectric memory cell region, the ferroelectric memory cell region has a source region, a drain region, a gate region, an isolation region, electrodes and interconnecting metal lines above each functional region;

a first interconnect structure comprising capacitor conductive pillars, bit line conductive pillars, capacitor conductive interconnects on top of the capacitor conductive pillars, metal bit lines on top of the bit line conductive pillars, and a first dielectric therebetween Floor;

a capacitor contact pad, the capacitor contact pad comprising a metal conductive post electrically connected to the capacitor conductive post, a contact pad on top of the metal conductive post, and a second dielectric layer therebetween;

a third dielectric layer stacked on the second dielectric layer;

a deep hole formed in the third dielectric layer, the bottom of the deep hole exposing the capacitor contact pad;

depositing a first electrode layer, a high-K ferroelectric oxide layer and a second electrode layer on the sidewall and bottom of the deep hole in sequence;

a plate wire connected to the second electrode layer by a metal interconnect.
The capacitor of the storage device according to claim 9, wherein the third dielectric layer is formed by stacking at least two different insulating materials, and the sidewall of the deep hole has one or more protrusions.
10. The capacitor of the storage device according to claim 9, further comprising a hole expansion structure formed by etching the top of the deep hole, wherein the hole expansion structure is located at the top of the deep hole and has a cross-sectional area larger than that of the deep hole structure. The cross-sectional area, the first electrode layer is only provided on the bottom and side of the deep hole under the reaming structure, the high-K ferroelectric oxide layer and the second electrode layer are formed on the sidewall and bottom of the deep hole and the reaming structure .
A method of manufacturing a memory device, comprising:

forming a memory cell region and a peripheral circuit region on a semiconductor substrate, wherein a transistor is formed on the substrate of the memory cell region, and the transistor includes a source electrode, a drain electrode and a gate electrode;

A first dielectric layer is deposited on the transistor layer of the substrate in the memory cell area and the peripheral circuit area, a through hole corresponding to the source or drain of the transistor is formed in the first dielectric layer, and a bit line conductive column and a capacitor are formed in the through hole conductive column;

forming a second dielectric layer on the first dielectric layer, forming a capacitor conductive interconnection connected to the capacitor conductive column on the second dielectric layer, and forming a metal bit line connected to the bit line conductive column on the second dielectric layer;

forming a third dielectric layer on the second dielectric layer, and forming a capacitor contact pad connected to the conductive interconnection of the capacitor on the third dielectric layer;

A fourth dielectric layer is formed on the third dielectric layer, a deep hole is formed by etching at the position corresponding to the aforementioned capacitor contact pad, and the capacitor contact pad is exposed, and a lower electrode layer and a ferroelectric material layer are sequentially deposited in the deep hole and the upper electrode layer to form a ferroelectric capacitor structure;

A fifth dielectric layer is formed above the ferroelectric capacitor, and a metal plate line connected to the upper electrode of the ferroelectric capacitor is formed on the fifth dielectric layer.
13. The method of claim 12, wherein the capacitor conductive interconnects, metal bit lines, metal plate lines are copper metal.
13. The method of claim 12, wherein the ferroelectric capacitor structure further comprises a copper diffusion protection layer formed between the lower electrode and the capacitor contact pad, and a copper diffusion protection layer is formed on the upper electrode.
The method of claim 12 , wherein the bottom area of the ferroelectric capacitor is smaller than the area of the capacitor contact pad, and when the deep hole is formed by etching, the capacitor contact pad forms a deep hole etching barrier.
13. The method of claim 12, wherein the step of forming the ferroelectric capacitor structure further comprises grinding and removing the upper electrode, the ferroelectric material layer and the lower electrode of the capacitor outside the deep hole by a chemical mechanical polishing process, leaving only the capacitor in the deep hole The steps of upper electrode, ferroelectric material layer and lower electrode.
The method of claim 12, wherein the step of forming the ferroelectric capacitor further comprises depositing a metal layer on the upper electrode of the capacitor in the deep hole to fill the deep hole, and then grinding and removing the metal layer and the metal layer outside the deep hole by a chemical mechanical polishing process. For the upper electrode, ferroelectric material layer and lower electrode of the capacitor, only the metal layer in the deep hole and the steps of the upper electrode, ferroelectric material layer and lower electrode of the capacitor are retained.
18. The method of claim 17, wherein the step of forming a metal plate line connected to the upper electrode of the capacitor comprises forming a dielectric layer on the capacitor structure, and forming a dielectric layer at the center of the capacitor in communication with the filler metal layer on the upper electrode of the capacitor A dielectric layer is formed above the conductive interconnection, an opening is formed in the dielectric layer, and metal is deposited in the opening to form a metal plate wire.
13. The method of claim 12, wherein the step of forming a metal plate line connected to the upper electrode of the capacitor comprises forming a dielectric layer on the capacitor structure, forming a through hole in the dielectric layer at a central position of the capacitor structure, and forming a through hole in the through hole The conductive column is connected to the upper electrode of the capacitor, a dielectric layer is formed on the conductive column, an opening is formed in the dielectric layer, and metal is deposited in the opening to form a metal plate wire.
13. The method of claim 12, wherein the step of forming the capacitor structure comprises, after depositing the capacitor lower electrode, the ferroelectric material layer and the upper electrode in the deep hole, etching the ferroelectric capacitor lower electrode material at the edge of the deep hole through a photomask The layer, the ferroelectric material layer and the upper electrode material layer separate the adjacent ferroelectric capacitors and retain the lower electrode material layer, the ferroelectric material layer and the upper electrode material layer around the edge of the deep hole.
The method of claim 20, wherein the step of forming a metal plate wire connected to the upper electrode of the capacitor comprises forming a through hole in the edge portion of the deep hole of the ferroelectric capacitor, and forming a conductive column in the through hole to connect the upper electrode of the capacitor, A dielectric layer is formed on the conductive pillar, an opening is formed in the dielectric layer, and metal is deposited in the opening to form a metal plate line.
The method as claimed in claim 12, wherein the step of forming the deep hole further comprises the step of first etching to form a deep hole with a first cross-sectional size, and then etching over the deep hole to form a hole reaming structure, wherein the reaming structure is in the deep hole and the cross-sectional area is larger than the cross-sectional area of the deep hole structure.
The method of claim 22, wherein the step of forming the ferroelectric capacitor further comprises: forming a first electrode layer of the bottom electrode layer of the capacitor in the deep hole structure and the expanded hole structure, and then removing the top surface of the dielectric layer and the expanded hole structure The bottom electrode layer on the sidewall and the bottom, only the first electrode layer on the bottom and side of the deep hole below the hole reaming structure is retained;

A ferroelectric material layer and a second electrode layer on the ferroelectric material layer are formed on the bottom electrode layer, wherein the ferroelectric material layer completely covers the first electrode layer of the deep hole and the inner surface of the expanded hole structure, and the second electrode layer completely fills Deep hole and reaming structure;

A ferroelectric capacitor structure is formed by grinding off the ferroelectric material layer and the second electrode layer on the surface of the crystal substrate by means of chemical mechanical grinding.
The method of claim 12, wherein the fourth dielectric layer comprises a multi-layer structure, and the step of etching to form the deep hole further comprises etching the multi-layer structure to form a flush inner wall of the deep hole, and then performing a wet method Etching forms protruding structures between the different layers.
The method of claim 12, wherein the material of the upper electrode layer and the lower electrode layer of the ferroelectric capacitor comprises at least one of the following: titanium nitride (TiN), titanium silicon nitride (TiSiNx), nitride Titanium aluminum (TiAlNx), titanium carbonitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), Tungsten carbonitride (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), doped polysilicon, transparent conductive oxide (TCO) or iridium oxide (IrOx); the material of the ferroelectric material layer comprising oxygen and one or more ferroelectric metals including zirconium (Zr), hafnium (Hf), titanium (Ti), aluminium (Al), nickel (Ni) and/or iron (Fe), And the ferroelectric material can be doped with group II elements calcium (Ca), strontium (Sr) or barium (Ba) or group III elements scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga) and Indium (In) or lanthanide elements Lanthanum (La), Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium ( Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu).