TWI803792B - Random power-on protection circuit and its control chip and electronic device - Google Patents

Random power-on protection circuit and its control chip and electronic device Download PDF

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TWI803792B
TWI803792B TW109142244A TW109142244A TWI803792B TW I803792 B TWI803792 B TW I803792B TW 109142244 A TW109142244 A TW 109142244A TW 109142244 A TW109142244 A TW 109142244A TW I803792 B TWI803792 B TW I803792B
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supply voltage
power supply
coupled
switch circuit
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TW202224355A (en
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吳俊杰
陳天豪
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大陸商北京集創北方科技股份有限公司
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Abstract

一種隨機上電保護電路，用以在一控制晶片中依一供應電壓的準位決定是否讓外部電源電壓進入該控制晶片而提供輸入電源電壓，且其具有一第一開關電路及一第二開關電路；於操作時，在該供應電壓尚未到達一閾值電壓前，該第一開關電路及該第二開關電路均呈現斷開狀態；以及在該內部供應電壓到達該閾值電壓後，該第一開關電路及該第二開關電路均呈現導通狀態以依所述外部電源電壓產生所述輸入電源電壓。 A random power-on protection circuit is used in a control chip to determine whether to allow an external power supply voltage to enter the control chip to provide an input power supply voltage according to a supply voltage level, and it has a first switch circuit and a second switch circuit; during operation, before the supply voltage has not reached a threshold voltage, both the first switch circuit and the second switch circuit are in an off state; and after the internal supply voltage reaches the threshold voltage, the first switch Both the circuit and the second switch circuit are turned on to generate the input power supply voltage according to the external power supply voltage.

Description

隨機上電保護電路及利用其之控制晶片和電子裝置Random power-on protection circuit and its control chip and electronic device

本發明係有關一種隨機上電保護電路，尤指一種設於一控制晶片內部之外部電壓閘控電路，其可在該控制晶片之內部邏輯電路之供應電壓尚未建立之前阻止外部電壓進入該控制晶片。The present invention relates to a random power-on protection circuit, especially an external voltage gating circuit installed inside a control chip, which can prevent external voltage from entering the control chip before the supply voltage of the internal logic circuit of the control chip is established. .

一般的控制晶片的上電過程都是由一外部電源晶片直接提供電源。請參照圖1，其繪示以一電源晶片提供兩個電壓源給一習知控制晶片之電路圖。如圖1所示，一電源晶片10提供一正電壓V SP及一負電壓V SN給一習知控制晶片20。 In general, the power-on process of the control chip is directly provided by an external power chip. Please refer to FIG. 1 , which shows a circuit diagram for providing two voltage sources to a conventional control chip with a power chip. As shown in FIG. 1 , a power chip 10 provides a positive voltage V SP and a negative voltage V SN to a conventional control chip 20 .

然而，由於在習知控制晶片20內的邏輯電路的供應電壓尚未建立之前，該邏輯電路的操作係處於不確定狀態，若電源晶片10所提供的正電壓V SP及負電壓V SN在此時進入習知控制晶片20，習知控制晶片20很可能會因該邏輯電路之不確定狀態產生大電流或閂鎖(latch up)效應。 However, before the supply voltage of the logic circuit in the conventional control chip 20 is established, the operation of the logic circuit is in an uncertain state. If the positive voltage V SP and negative voltage V SN provided by the power chip 10 are at this time Entering the conventional control chip 20, the conventional control chip 20 is likely to generate a large current or a latch-up effect due to the uncertain state of the logic circuit.

為解決上述問題，本領域亟須一種新穎的上電保護電路。In order to solve the above problems, a novel power-on protection circuit is urgently needed in the field.

本發明之一目的在於提供一種用於一控制晶片中的上電保護電路，其可在該控制晶片的內部邏輯電路的供應電壓尚未建立前禁止外部電壓輸入，以避免該控制晶片產生閂鎖效應或在該邏輯電路處於不確定狀態時產生大電流，從而避免該控制晶片被損毀。One object of the present invention is to provide a power-on protection circuit used in a control chip, which can prohibit the input of external voltage before the supply voltage of the internal logic circuit of the control chip is established, so as to avoid the latch-up effect of the control chip Or generate a large current when the logic circuit is in an uncertain state, thereby preventing the control chip from being damaged.

本發明之另一目的在於提供一種控制晶片，其可在上電順序不受控時，利用內部的上電保護電路提供一自我防護機制，以降低被損毀的機率。Another object of the present invention is to provide a control chip, which can use an internal power-on protection circuit to provide a self-protection mechanism to reduce the probability of being damaged when the power-on sequence is out of control.

本發明之又一目的在於提供一種電子裝置，其可藉由採用上述的控制晶片而進一步提升其可靠度及工作壽命。Another object of the present invention is to provide an electronic device, which can further improve its reliability and working life by using the above-mentioned control chip.

為達到前述之目的，一種隨機上電保護電路乃被提出，其係用以設置在一控制晶片中以依該控制晶片內部之一供應電壓決定是否讓一外部正電源電壓及一外部負電源電壓進入該控制晶片而提供一正輸入電源電壓及一負輸入電源電壓，且其具有：In order to achieve the aforementioned purpose, a random power-on protection circuit is proposed, which is used to be arranged in a control chip to determine whether to allow an external positive power supply voltage and an external negative power supply voltage according to a supply voltage inside the control chip into the control chip to provide a positive input supply voltage and a negative input supply voltage, and it has:

一第一開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部正電源電壓，且該輸出端係用以提供該正輸入電源電壓；以及A first switch circuit has a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, the input terminal is coupled to the external positive power supply voltage, and the output terminal is used to provide the positive input supply voltage; and

一第二開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部負電源電壓，且該輸出端係用以提供該負輸入電源電壓；A second switch circuit has a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, the input terminal is coupled to the external negative power supply voltage, and the output terminal is used to provide the Negative input supply voltage;

於操作時，在該供應電壓尚未到達一閾值電壓前，該第一開關電路及該第二開關電路均呈現斷開狀態；以及在該內部供應電壓到達該閾值電壓後，該第一開關電路及該第二開關電路均呈現導通狀態以依該外部正電源電壓及該外部負電源電壓分別產生該正輸入電源電壓及該負輸入電源電壓。In operation, before the supply voltage reaches a threshold voltage, both the first switch circuit and the second switch circuit are turned off; and after the internal supply voltage reaches the threshold voltage, the first switch circuit and the second switch circuit Both the second switch circuits are turned on to generate the positive input power supply voltage and the negative input power supply voltage according to the external positive power supply voltage and the external negative power supply voltage respectively.

在一實施例中，該第一開關電路具有：In one embodiment, the first switch circuit has:

一第一電阻，耦接於該外部正電源電壓與一第一節點之間；a first resistor coupled between the external positive power supply voltage and a first node;

一第一NMOS電晶體，其閘極耦接該供應電壓，且其通道耦接於該第一節點與一參考地之間；以及a first NMOS transistor, the gate of which is coupled to the supply voltage, and the channel of which is coupled between the first node and a reference ground; and

一第一PMOS電晶體，其閘極耦接該第一節點，且其通道之一端耦接該外部正電源電壓，而該通道之另一端則係用以提供該正輸入電源電壓。A first PMOS transistor, the gate of which is coupled to the first node, and one end of its channel is coupled to the external positive power supply voltage, and the other end of the channel is used to provide the positive input power supply voltage.

在一實施例中，該第二開關電路具有：In one embodiment, the second switch circuit has:

一第二電阻，耦接於該外部負電源電壓與一第二節點之間；a second resistor coupled between the external negative power supply voltage and a second node;

一第二PMOS電晶體，其閘極耦接該參考地，且其通道耦接於該第二節點與該供應電壓之間；以及a second PMOS transistor, the gate of which is coupled to the reference ground, and the channel of which is coupled between the second node and the supply voltage; and

一第二NMOS電晶體，其閘極耦接該第二節點，且其通道之一端耦接該外部負電源電壓，而該通道之另一端則係用以提供該負輸入電源電壓。A second NMOS transistor, the gate of which is coupled to the second node, and one end of its channel is coupled to the external negative power supply voltage, and the other end of the channel is used to provide the negative input power supply voltage.

為達到上述目的，本發明進一步提出一種控制晶片，其具有一隨機上電保護電路以依該控制晶片內部之一供應電壓決定是否讓一外部正電源電壓及一外部負電源電壓進入該控制晶片而提供一正輸入電源電壓及一負輸入電源電壓，該隨機上電保護電路具有：To achieve the above object, the present invention further proposes a control chip, which has a random power-on protection circuit to determine whether to allow an external positive power supply voltage and an external negative power supply voltage to enter the control chip according to a supply voltage inside the control chip. Provide a positive input power supply voltage and a negative input power supply voltage, the random power-on protection circuit has:

一第一開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部正電源電壓，且該輸出端係用以提供該正輸入電源電壓；以及A first switch circuit has a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, the input terminal is coupled to the external positive power supply voltage, and the output terminal is used to provide the positive input supply voltage; and

一第二開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部負電源電壓，且該輸出端係用以提供該負輸入電源電壓；A second switch circuit has a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, the input terminal is coupled to the external negative power supply voltage, and the output terminal is used to provide the Negative input supply voltage;

於操作時，在該供應電壓尚未到達一閾值電壓前，該第一開關電路及該第二開關電路均呈現斷開狀態；以及在該內部供應電壓到達該閾值電壓後，該第一開關電路及該第二開關電路均呈現導通狀態以依該外部正電源電壓及該外部負電源電壓分別產生該正輸入電源電壓及該負輸入電源電壓。In operation, before the supply voltage reaches a threshold voltage, both the first switch circuit and the second switch circuit are turned off; and after the internal supply voltage reaches the threshold voltage, the first switch circuit and the second switch circuit Both the second switch circuits are turned on to generate the positive input power supply voltage and the negative input power supply voltage according to the external positive power supply voltage and the external negative power supply voltage respectively.

在一實施例中，該第一開關電路具有：In one embodiment, the first switch circuit has:

一第一電阻，耦接於該外部正電源電壓與一第一節點之間；a first resistor coupled between the external positive power supply voltage and a first node;

一第一NMOS電晶體，其閘極耦接該供應電壓，且其通道耦接於該第一節點與一參考地之間；以及a first NMOS transistor, the gate of which is coupled to the supply voltage, and the channel of which is coupled between the first node and a reference ground; and

一第一PMOS電晶體，其閘極耦接該第一節點，且其通道之一端耦接該外部正電源電壓，而該通道之另一端則係用以提供該正輸入電源電壓。A first PMOS transistor, the gate of which is coupled to the first node, and one end of its channel is coupled to the external positive power supply voltage, and the other end of the channel is used to provide the positive input power supply voltage.

在一實施例中，該第二開關電路具有：In one embodiment, the second switch circuit has:

一第二電阻，耦接於該外部負電源電壓與一第二節點之間；a second resistor coupled between the external negative power supply voltage and a second node;

一第二PMOS電晶體，其閘極耦接該參考地，且其通道耦接於該第二節點與該供應電壓之間；以及a second PMOS transistor, the gate of which is coupled to the reference ground, and the channel of which is coupled between the second node and the supply voltage; and

一第二NMOS電晶體，其閘極耦接該第二節點，且其通道之一端耦接該外部負電源電壓，而該通道之另一端則係用以提供該負輸入電源電壓。A second NMOS transistor, the gate of which is coupled to the second node, and one end of its channel is coupled to the external negative power supply voltage, and the other end of the channel is used to provide the negative input power supply voltage.

為達到上述目的，本發明進一步提出一種電子裝置，其具有一電源晶片及一控制晶片，該電源晶片係用以提供一外部正電源電壓及一外部負電源電壓給該控制晶片，該控制晶片具有一隨機上電保護電路以依該控制晶片內部之一供應電壓決定是否讓該外部正電源電壓及該外部負電源電壓進入該控制晶片而提供一正輸入電源電壓及一負輸入電源電壓，該隨機上電保護電路具有：To achieve the above object, the present invention further proposes an electronic device, which has a power chip and a control chip, the power chip is used to provide an external positive power supply voltage and an external negative power supply voltage to the control chip, the control chip has A random power-on protection circuit determines whether to allow the external positive power supply voltage and the external negative power supply voltage to enter the control chip according to a supply voltage inside the control chip to provide a positive input power supply voltage and a negative input power supply voltage. The power-on protection circuit has:

一第一開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部正電源電壓，且該輸出端係用以提供該正輸入電源電壓；以及A first switch circuit has a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, the input terminal is coupled to the external positive power supply voltage, and the output terminal is used to provide the positive input supply voltage; and

一第二開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部負電源電壓，且該輸出端係用以提供該負輸入電源電壓；A second switch circuit has a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, the input terminal is coupled to the external negative power supply voltage, and the output terminal is used to provide the Negative input supply voltage;

於操作時，在該供應電壓尚未到達一閾值電壓前，該第一開關電路及該第二開關電路均呈現斷開狀態；以及在該內部供應電壓到達該閾值電壓後，該第一開關電路及該第二開關電路均呈現導通狀態以依該外部正電源電壓及該外部負電源電壓分別產生該正輸入電源電壓及該負輸入電源電壓。In operation, before the supply voltage reaches a threshold voltage, both the first switch circuit and the second switch circuit are turned off; and after the internal supply voltage reaches the threshold voltage, the first switch circuit and the second switch circuit Both the second switch circuits are turned on to generate the positive input power supply voltage and the negative input power supply voltage according to the external positive power supply voltage and the external negative power supply voltage respectively.

在一實施例中，該第一開關電路具有：In one embodiment, the first switch circuit has:

一第一電阻，耦接於該外部正電源電壓與一第一節點之間；a first resistor coupled between the external positive power supply voltage and a first node;

一第一NMOS電晶體，其閘極耦接該供應電壓，且其通道耦接於該第一節點與一參考地之間；以及a first NMOS transistor, the gate of which is coupled to the supply voltage, and the channel of which is coupled between the first node and a reference ground; and

一第一PMOS電晶體，其閘極耦接該第一節點，且其通道之一端耦接該外部正電源電壓，而該通道之另一端則係用以提供該正輸入電源電壓。A first PMOS transistor, the gate of which is coupled to the first node, and one end of its channel is coupled to the external positive power supply voltage, and the other end of the channel is used to provide the positive input power supply voltage.

在一實施例中，該第二開關電路具有：In one embodiment, the second switch circuit has:

一第二電阻，耦接於該外部負電源電壓與一第二節點之間；a second resistor coupled between the external negative power supply voltage and a second node;

一第二PMOS電晶體，其閘極耦接該參考地，且其通道耦接於該第二節點與該供應電壓之間；以及a second PMOS transistor, the gate of which is coupled to the reference ground, and the channel of which is coupled between the second node and the supply voltage; and

一第二NMOS電晶體，其閘極耦接該第二節點，且其通道之一端耦接該外部負電源電壓，而該通道之另一端則係用以提供該負輸入電源電壓。A second NMOS transistor, the gate of which is coupled to the second node, and one end of its channel is coupled to the external negative power supply voltage, and the other end of the channel is used to provide the negative input power supply voltage.

在可能的實施例中，該電子裝置可為一顯示器、一攜帶型電腦或一智慧型手持裝置。In possible embodiments, the electronic device can be a display, a portable computer or a smart handheld device.

本發明的原理在於：Principle of the present invention is:

在一控制晶片的內部設置一第一開關電路及一第二開關電路以依一內部供應電壓是否建立完成分別閘控一外部正電壓及一外部負電壓，其中，該第一開關電路及該第二開關電路均係在該內部供應電壓尚未建立前呈現斷開狀態以禁止該外部正電壓及該外部負電壓輸入該控制晶片，以及在該內部供應電壓建立後呈現導通狀態以讓該外部正電壓及該外部負電壓輸入該控制晶片。A first switch circuit and a second switch circuit are arranged inside a control chip to respectively gate an external positive voltage and an external negative voltage according to whether an internal supply voltage is established, wherein the first switch circuit and the second switch circuit Both switch circuits are turned off before the internal supply voltage is established to prohibit the external positive voltage and the external negative voltage from being input to the control chip, and are turned on after the internal supply voltage is established to allow the external positive voltage And the external negative voltage is input to the control chip.

請一併參照圖2及圖3，其中，圖2繪示包含本發明之隨機上電保護電路之一控制晶片之一實施例的方塊圖；圖3繪示圖2所示之隨機上電保護電路之一實施例的電路圖。Please refer to FIG. 2 and FIG. 3 together, wherein FIG. 2 shows a block diagram of an embodiment of a control chip including a random power-on protection circuit of the present invention; FIG. 3 shows the random power-on protection shown in FIG. 2 Circuit diagram of one embodiment of the circuit.

如圖2所示，一控制晶片100具有一隨機上電保護電路110，隨機上電保護電路110係依控制晶片100的內部邏輯電路的一供應電壓V DD的控制，決定是否讓一電源晶片10輸出的一正電源電壓V SP及一負電源電壓V SN進入控制晶片100而提供一正輸入電源電壓V SPIN及一負輸入電源電壓V SNIN，其中，當供應電壓V DD尚未建立(到達一閾值電壓)前，隨機上電保護電路110會禁止正電源電壓V SP及負電源電壓V SN進入控制晶片100以避免控制晶片100因閂鎖效應或該內部邏輯電路處於不確定狀態而產生大電流；以及當供應電壓V DD建立完成(到達該閾值電壓)後，隨機上電保護電路110會讓正電源電壓V SP及負電源電壓V SN進入控制晶片100以使控制晶片100可正常工作。 As shown in Figure 2, a control chip 100 has a random power-on protection circuit 110, and the random power-on protection circuit 110 is controlled by a supply voltage V DD of the internal logic circuit of the control chip 100 to determine whether to allow a power chip 10 An output positive power supply voltage V SP and a negative power supply voltage V SN enter the control chip 100 to provide a positive input power supply voltage V SPIN and a negative input power supply voltage V SNIN , wherein, when the supply voltage V DD has not been established (reaching a threshold voltage), the random power-on protection circuit 110 will prohibit the positive power supply voltage V SP and the negative power supply voltage V SN from entering the control chip 100 to prevent the control chip 100 from generating a large current due to the latch-up effect or the internal logic circuit being in an uncertain state; And when the supply voltage V DD is established (reaches the threshold voltage), the random power-on protection circuit 110 allows the positive power supply voltage V SP and the negative power supply voltage V SN to enter the control chip 100 so that the control chip 100 can work normally.

另外，如圖3所示，隨機上電保護電路110具有一第一開關電路111及一第二開關電路112以依供應電壓V DD是否建立完成分別閘控正電源電壓V SP及負電源電壓V SN，其中，第一開關電路111具有一第一電阻111a、一第一NMOS電晶體111b及一第一PMOS電晶體111c，第二開關電路112具有一第二電阻112a、一第二PMOS電晶體112b及一第二NMOS電晶體112c，且第一PMOS電晶體111c及第二NMOS電晶體112c均係在供應電壓V DD尚未建立(到達一閾值電壓)前呈現斷開狀態以禁止正電源電壓V SP及負電源電壓V SN進入控制晶片100，以及在供應電壓V DD建立(到達一閾值電壓)後呈現導通狀態以讓正電源電壓V SP及負電源電壓V SN進入控制晶片100以提供正輸入電源電壓V SPIN及負輸入電源電壓V SNIN。 In addition, as shown in FIG. 3 , the random power-on protection circuit 110 has a first switch circuit 111 and a second switch circuit 112 to separately gate the positive power supply voltage V SP and the negative power supply voltage V according to whether the supply voltage V DD is established or not. SN , where the first switch circuit 111 has a first resistor 111a, a first NMOS transistor 111b, and a first PMOS transistor 111c, and the second switch circuit 112 has a second resistor 112a, a second PMOS transistor 112b and a second NMOS transistor 112c, and both the first PMOS transistor 111c and the second NMOS transistor 112c are turned off before the supply voltage V DD is established (reaching a threshold voltage) to prohibit the positive power supply voltage V SP and the negative power supply voltage V SN enter the control chip 100, and after the supply voltage V DD is established (reaching a threshold voltage), it assumes a conduction state to allow the positive power supply voltage V SP and the negative power supply voltage V SN to enter the control chip 100 to provide a positive input. The power supply voltage V SPIN and the negative input power supply voltage V SNIN .

詳細而言，在第一開關電路111中：第一電阻111a係耦接於正電源電壓V SP與一第一節點A之間；第一NMOS電晶體111b之閘極耦接供應電壓V DD，而其通道則耦接於第一節點A與一參考地GND之間；以及第一PMOS電晶體111c之閘極耦接第一節點A，第一PMOS電晶體111c之通道之一端耦接正電源電壓V SP，而該通道之另一端則係用以提供正輸入電源電壓V SPIN。於操作時，當供應電壓V DD尚未建立(到達一閾值電壓)前，第一NMOS電晶體111b的通道係呈現高阻抗狀態，致使第一節點A的電壓等於正電源電壓V SP，從而使第一PMOS電晶體111c之通道被斷開；當供應電壓V DD建立完成(到達該閾值電壓)後，第一NMOS電晶體111b的通道會被導通，致使第一節點A的電壓被下拉至參考地GND，從而使第一PMOS電晶體111c之通道被導通而提供正輸入電源電壓V SPIN。 Specifically, in the first switch circuit 111: the first resistor 111a is coupled between the positive power supply voltage V SP and a first node A; the gate of the first NMOS transistor 111b is coupled to the supply voltage V DD , And its channel is coupled between the first node A and a reference ground GND; and the gate of the first PMOS transistor 111c is coupled to the first node A, and one end of the channel of the first PMOS transistor 111c is coupled to the positive power supply voltage V SP , and the other end of the channel is used to provide the positive input power supply voltage V SPIN . In operation, before the supply voltage V DD is established (reaches a threshold voltage), the channel of the first NMOS transistor 111b is in a high impedance state, so that the voltage of the first node A is equal to the positive power supply voltage V SP , thereby making the first NMOS transistor 111b in a high impedance state. The channel of a PMOS transistor 111c is turned off; when the supply voltage V DD is established (reaching the threshold voltage), the channel of the first NMOS transistor 111b is turned on, so that the voltage of the first node A is pulled down to the reference ground GND, so that the channel of the first PMOS transistor 111c is turned on to provide a positive input power supply voltage V SPIN .

在第二開關電路112中：第二電阻112a係耦接於負電源電壓V SN與一第二節點B之間；第二PMOS電晶體112b之閘極耦接該參考地GND，而其通道則耦接於第二節點B與供應電壓V DD之間；以及第二NMOS電晶體112c之閘極耦接第二節點B，第二NMOS電晶體112c之通道之一端耦接負電源電壓V SN，而該通道之另一端則係用以提供負輸入電源電壓V SNIN。於操作時，當供應電壓V DD尚未建立(到達該閾值電壓)前，第二PMOS電晶體112b的通道係呈現高阻抗狀態，致使第二節點B的電壓等於負電源電壓V SN，從而使第二NMOS電晶體112c之通道被斷開；當供應電壓V DD建立完成(到達該閾值電壓)後，第二PMOS電晶體112b的通道會被導通，致使第二節點B的電壓被拉高至供應電壓V DD，從而使第二NMOS電晶體112c之通道被導通而提供負輸入電源電壓V SNIN。 In the second switch circuit 112: the second resistor 112a is coupled between the negative supply voltage V SN and a second node B; the gate of the second PMOS transistor 112b is coupled to the reference ground GND, and its channel is coupled between the second node B and the supply voltage V DD ; and the gate of the second NMOS transistor 112c is coupled to the second node B, and one end of the channel of the second NMOS transistor 112c is coupled to the negative supply voltage V SN , The other end of the channel is used to provide the negative input power supply voltage V SNIN . In operation, before the supply voltage V DD is established (reaching the threshold voltage), the channel of the second PMOS transistor 112b is in a high impedance state, so that the voltage of the second node B is equal to the negative supply voltage V SN , so that the first The channel of the two NMOS transistors 112c is turned off; when the supply voltage V DD is established (reaching the threshold voltage), the channel of the second PMOS transistor 112b will be turned on, so that the voltage of the second node B is pulled up to the supply voltage Voltage V DD , so that the channel of the second NMOS transistor 112c is turned on to provide a negative input power supply voltage V SNIN .

另外，本發明進一步提出一電子裝置。請參照圖4，其繪示本發明之電子裝置之一實施例的方塊圖。如圖4所示，一電子裝置200具有一電源晶片210及一控制晶片220，其中，電源晶片210係用以輸出一正電源電壓V SP及一負電源電壓V SN至控制晶片220，且控制晶片220係由前述之控制晶片100實現以有效避免控制晶片220因電源晶片210的隨機上電而被損毀。另外，電子裝置200可為一顯示器、一攜帶型電腦或一智慧型手持裝置。 In addition, the invention further provides an electronic device. Please refer to FIG. 4 , which shows a block diagram of an embodiment of the electronic device of the present invention. As shown in FIG. 4, an electronic device 200 has a power chip 210 and a control chip 220, wherein the power chip 210 is used to output a positive power supply voltage V SP and a negative power supply voltage V SN to the control chip 220, and control The chip 220 is implemented by the aforementioned control chip 100 to effectively prevent the control chip 220 from being damaged due to random power-on of the power chip 210 . In addition, the electronic device 200 can be a display, a portable computer or a smart handheld device.

依上述的說明可知，本發明可提供以下的優點：According to the above description, the present invention can provide the following advantages:

1.本發明的上電保護電路可在一控制晶片的內部邏輯電路的供應電壓尚未建立前禁止外部電壓輸入該控制晶片，以避免該控制晶片產生閂鎖效應或在該邏輯電路處於不確定狀態時產生大電流，從而有效避免該控制晶片被損毀。1. The power-on protection circuit of the present invention can prohibit the input of external voltage to the control chip before the supply voltage of the internal logic circuit of a control chip is established, so as to avoid the latch-up effect of the control chip or the logic circuit being in an uncertain state When a large current is generated, the control chip is effectively prevented from being damaged.

2.本發明的控制晶片可在上電順序不受控時，利用內部的上電保護電路提供一自我防護機制，以降低被損毀的機率。2. The control chip of the present invention can use the internal power-on protection circuit to provide a self-protection mechanism when the power-on sequence is out of control, so as to reduce the probability of being damaged.

3.本發明的電子裝置可藉由採用上述的控制晶片而進一步提升其可靠度及工作壽命。3. The electronic device of the present invention can further improve its reliability and working life by using the above-mentioned control chip.

本發明所揭示者，乃較佳實施例之一種，舉凡局部之變更或修飾而源於本發明之技術思想而為熟習該項技藝知人所易於推知者，俱不脫本發明之專利權範疇。What is disclosed in the present invention is one of the preferred embodiments. For example, all partial changes or modifications derived from the technical idea of the present invention and easily deduced by those skilled in the art do not depart from the scope of the patent right of the present invention.

綜上所陳，本案無論目的、手段與功效，皆顯示其迥異於習知技術，且其首先發明合於實用，確實符合發明之專利要件，懇請　貴審查委員明察，並早日賜予專利俾嘉惠社會，是為至禱。To sum up, regardless of the purpose, means and efficacy of this case, it shows that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. I implore your review committee to understand it clearly and grant a patent as soon as possible. Society is for the Most Prayer.

10:電源晶片 20:習知控制晶片 100:控制晶片 110:隨機上電保護電路 111:第一開關電路 111a:第一電阻 111b:第一NMOS電晶體 111c:第一PMOS電晶體 112:第二開關電路 112a:第二電阻 112b:第二PMOS電晶體 112c:第二NMOS電晶體 200:電子裝置 210:電源晶片 220:控制晶片 10: Power chip 20: Conventional control chip 100: control chip 110: random power-on protection circuit 111: the first switch circuit 111a: the first resistor 111b: the first NMOS transistor 111c: the first PMOS transistor 112: the second switch circuit 112a: the second resistance 112b: the second PMOS transistor 112c: the second NMOS transistor 200: electronic device 210: power chip 220: control chip

為進一步揭示本發明之具體技術內容，首先請參閱圖式，其中： 圖1繪示以一電源晶片提供兩個電壓源給一習知控制晶片之電路圖。 圖2繪示包含本發明之隨機上電保護電路之一控制晶片之一實施例的方塊圖。 圖3繪示圖2所示之隨機上電保護電路之一實施例的電路圖。 圖4繪示本發明之電子裝置之一實施例的方塊圖。 In order to further disclose the specific technical content of the present invention, first please refer to the drawings, wherein: FIG. 1 shows a circuit diagram of using a power chip to provide two voltage sources to a conventional control chip. FIG. 2 is a block diagram of an embodiment of a control chip including a random power-on protection circuit of the present invention. FIG. 3 is a circuit diagram of an embodiment of the random power-on protection circuit shown in FIG. 2 . FIG. 4 shows a block diagram of an embodiment of the electronic device of the present invention.

10:電源晶片 10: Power chip

100:控制晶片 100: control chip

110:隨機上電保護電路 110: random power-on protection circuit

Claims (7)

一種隨機上電保護電路，用以設置在一控制晶片中以依該控制晶片內部之一供應電壓決定是否讓一外部正電源電壓及一外部負電源電壓進入該控制晶片而提供一正輸入電源電壓及一負輸入電源電壓，其具有：一第一開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部正電源電壓，且該輸出端係用以提供該正輸入電源電壓；以及一第二開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部負電源電壓，且該輸出端係用以提供該負輸入電源電壓；於操作時，在該供應電壓尚未到達一閾值電壓前，該第一開關電路及該第二開關電路均呈現斷開狀態；以及在該供應電壓到達該閾值電壓後，該第一開關電路及該第二開關電路均呈現導通狀態以依該外部正電源電壓及該外部負電源電壓分別產生該正輸入電源電壓及該負輸入電源電壓；其中該第一開關電路具有：一第一電阻，耦接於該外部正電源電壓與一第一節點之間；一第一NMOS電晶體，其閘極耦接該供應電壓，且其通道耦接於該第一節點與一參考地之間；以及一第一PMOS電晶體，其閘極耦接該第一節點，且其通道之一端耦接該外部正電源電壓，而該通道之另一端則係用以提供該正輸入電源電壓。 A random power-on protection circuit, which is used to set in a control chip to determine whether to allow an external positive power supply voltage and an external negative power supply voltage to enter the control chip according to a supply voltage inside the control chip to provide a positive input power supply voltage and a negative input power supply voltage, which has: a first switch circuit with a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, and the input terminal is coupled to the external positive power supply voltage , and the output terminal is used to provide the positive input power supply voltage; and a second switch circuit has a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, and the input terminal is coupled to connected to the external negative power supply voltage, and the output terminal is used to provide the negative input power supply voltage; during operation, before the supply voltage reaches a threshold voltage, both the first switch circuit and the second switch circuit are turned off an open state; and after the supply voltage reaches the threshold voltage, both the first switch circuit and the second switch circuit are in a conduction state to generate the positive input power supply voltage and the external negative power supply voltage respectively according to the external positive power supply voltage and the external negative power supply voltage The negative input power supply voltage; wherein the first switch circuit has: a first resistor coupled between the external positive power supply voltage and a first node; a first NMOS transistor whose gate is coupled to the supply voltage , and its channel is coupled between the first node and a reference ground; and a first PMOS transistor, its gate is coupled to the first node, and one end of its channel is coupled to the external positive power supply voltage, and The other end of the channel is used to provide the positive input power supply voltage. 如申請專利範圍第1項所述之隨機上電保護電路，其中該第二開關電路具有：一第二電阻，耦接於該外部負電源電壓與一第二節點之間；一第二PMOS電晶體，其閘極耦接該參考地，且其通道耦接於該第二節點與該供應電壓之間；以及一第二NMOS電晶體，其閘極耦接該第二節點，且其通道之一端耦接該外部負電源電壓，而該通道之另一端則係用以提供該負輸入電源電壓。 The random power-on protection circuit described in Item 1 of the scope of the patent application, wherein the second switch circuit has: a second resistor coupled between the external negative power supply voltage and a second node; a second PMOS circuit a crystal whose gate is coupled to the reference ground and whose channel is coupled between the second node and the supply voltage; and a second NMOS transistor whose gate is coupled to the second node and whose channel One end is coupled to the external negative power supply voltage, and the other end of the channel is used to provide the negative input power supply voltage. 一種控制晶片，其具有一隨機上電保護電路以依該控制晶片內部之一供應電壓決定是否讓一外部正電源電壓及一外部負電源電壓進入該控制晶片而提供一正輸入電源電壓及一負輸入電源電壓，該隨機上電保護電路具有：一第一開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部正電源電壓，且該輸出端係用以提供該正輸入電源電壓；以及一第二開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部負電源電壓，且該輸出端係用以提供該負輸入電源電壓；於操作時，在該供應電壓尚未到達一閾值電壓前，該第一開關電路及該第二開關電路均呈現斷開狀態；以及在該內部供應電壓到達該閾值電壓後，該第一開關電路及該第二開關電路均呈現導通狀態以依該外部正電源電壓及該外部負電源電壓分別產生該正輸入電源電壓及該負輸入電源電壓；其中該第一開關電路具有：一第一電阻，耦接於該外部正電源電壓與一第一節點之間；一第一NMOS電晶體，其閘極耦接該供應電壓，且其通道耦接於該第一節點與一參考地之間；以及一第一PMOS電晶體，其閘極耦接該第一節點，且其通道之一端耦接該外部正電源電壓，而該通道之另一端則係用以提供該正輸入電源電壓。 A control chip, which has a random power-on protection circuit to determine whether to allow an external positive power supply voltage and an external negative power supply voltage to enter the control chip according to a supply voltage inside the control chip to provide a positive input power supply voltage and a negative power supply voltage. Input power supply voltage, the random power-on protection circuit has: a first switch circuit with a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, and the input terminal is coupled to the external positive power supply voltage, and the output terminal is used to provide the positive input power supply voltage; and a second switch circuit has a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, the input The terminal is coupled to the external negative power supply voltage, and the output terminal is used to provide the negative input power supply voltage; during operation, before the supply voltage reaches a threshold voltage, both the first switch circuit and the second switch circuit exhibiting an off state; and after the internal supply voltage reaches the threshold voltage, both the first switch circuit and the second switch circuit exhibit an on state to generate the positive input according to the external positive power supply voltage and the external negative power supply voltage respectively power supply voltage and the negative input power supply voltage; wherein the first switch circuit has: a first resistor coupled between the external positive power supply voltage and a first node; a first NMOS transistor whose gate is coupled the supply voltage, and its channel is coupled between the first node and a reference ground; and a first PMOS transistor, its gate is coupled to the first node, and one end of its channel is coupled to the external positive power supply voltage, while the other end of the channel is used to provide the positive input supply voltage. 如申請專利範圍第4項所述之控制晶片，其中該第二開關電路具有：一第二電阻，耦接於該外部負電源電壓與一第二節點之間；一第二PMOS電晶體，其閘極耦接該參考地，且其通道耦接於該第二節點與該供應電壓之間；以及一第二NMOS電晶體，其閘極耦接該第二節點，且其通道之一端耦接該外部負電源電壓，而該通道之另一端則係用以提供該負輸入電源電壓。 The control chip as described in item 4 of the scope of the patent application, wherein the second switch circuit has: a second resistor coupled between the external negative power supply voltage and a second node; a second PMOS transistor, which the gate is coupled to the reference ground, and its channel is coupled between the second node and the supply voltage; and a second NMOS transistor, its gate is coupled to the second node, and one end of its channel is coupled to The external negative power supply voltage, and the other end of the channel is used to provide the negative input power supply voltage. 一種電子裝置，其具有一電源晶片及一控制晶片，該電源晶片係用以提供一外部正電源電壓及一外部負電源電壓給該控制晶片，該控制晶片具有一隨機上電保護電路以依該控制晶片內部之一供應電壓決定是否讓該外部正電源電壓及該外部負電源電壓進入該控制晶片而提供一正輸入電源電壓及一負輸入電源電壓，該隨機上電保護電路具有：一第一開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部正電源電壓，且該輸出端係用以提供該正輸入電源電壓；以及一第二開關電路，具有一控制端、一輸入端及一輸出端，其中，該控制端耦接該供應電壓，該輸入端耦接該外部負電源電壓，且該輸出端係用以提供該負輸入電源電壓；於操作時，在該供應電壓尚未到達一閾值電壓前，該第一開關電路及該第二開關電路均呈現斷開狀態；以及在該內部供應電壓到達該閾值電壓後，該第一開關電路及該第二開關電路均呈現導通狀態以依該外部正電源電壓及該外部負電源電壓分別產生該正輸入電源電壓及該負輸入電源電壓；其中該第一開關電路具有：一第一電阻，耦接於該外部正電源電壓與一第一節點之間；一第一NMOS電晶體，其閘極耦接該供應電壓，且其通道耦接於該第一節點與一參考地之間；以及一第一PMOS電晶體，其閘極耦接該第一節點，且其通道之一端耦接該外部正電源電壓，而該通道之另一端則係用以提供該正輸入電源電壓。 An electronic device, which has a power chip and a control chip, the power chip is used to provide an external positive power supply voltage and an external negative power supply voltage to the control chip, the control chip has a random power-on protection circuit according to the A supply voltage inside the control chip determines whether to allow the external positive power supply voltage and the external negative power supply voltage to enter the control chip to provide a positive input power supply voltage and a negative input power supply voltage. The random power-on protection circuit has: a first The switch circuit has a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, the input terminal is coupled to the external positive power supply voltage, and the output terminal is used to provide the positive input power supply voltage; and a second switch circuit having a control terminal, an input terminal and an output terminal, wherein the control terminal is coupled to the supply voltage, the input terminal is coupled to the external negative power supply voltage, and the output terminal is used for to provide the negative input power supply voltage; during operation, before the supply voltage reaches a threshold voltage, both the first switch circuit and the second switch circuit are turned off; and when the internal supply voltage reaches the threshold voltage Afterwards, both the first switch circuit and the second switch circuit are turned on to generate the positive input power supply voltage and the negative input power supply voltage respectively according to the external positive power supply voltage and the external negative power supply voltage; wherein the first switch circuit It has: a first resistor, coupled between the external positive power supply voltage and a first node; a first NMOS transistor, whose gate is coupled to the supply voltage, and whose channel is coupled between the first node and a first node between a reference ground; and a first PMOS transistor, the gate of which is coupled to the first node, and one end of its channel is coupled to the external positive power supply voltage, and the other end of the channel is used to provide the positive Input supply voltage. 如申請專利範圍第5項所述之電子裝置，其中該第二開關電路具有：一第二電阻，耦接於該外部負電源電壓與一第二節點之間；一第二PMOS電晶體，其閘極耦接該參考地，且其通道耦接於該第二節點與該供應電壓之間；以及一第二NMOS電晶體，其閘極耦接該第二節點，且其通道之一端耦接該外部負電源電壓，而該通道之另一端則係用以提供該負輸入電源電壓。 The electronic device as described in item 5 of the scope of the patent application, wherein the second switch circuit has: a second resistor, coupled between the external negative power supply voltage and a second node; a second PMOS transistor, which the gate is coupled to the reference ground, and its channel is coupled between the second node and the supply voltage; and a second NMOS transistor, its gate is coupled to the second node, and one end of its channel is coupled to The external negative power supply voltage, and the other end of the channel is used to provide the negative input power supply voltage. 如申請專利範圍第5項所述之電子裝置，其係由顯示器、攜帶型電腦和智慧型手持裝置所組成群組所選擇的一種裝置。 The electronic device described in item 5 of the scope of the patent application is a device selected from the group consisting of a display, a portable computer and a smart handheld device.
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