TWI795739B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate and an oxide layer. The substrate has at least two isolation structures and an active region located between the at least two isolation structures. Each isolation structure includes a first oxide material layer and a second oxide material layer, and the second oxide material layer is disposed on the first oxide material layer. The oxide layer is disposed on the active area, wherein the orthographic projection of the oxide layer on the substrate overlaps with at least two isolation structures. A manufacturing method of the semiconductor device is also provided

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a device and its manufacturing method, and in particular to a semiconductor device and its manufacturing method.

Generally speaking, isolation structures are often used in semiconductor devices to separate active regions of semiconductor devices. However, during the manufacturing process, a depression (divot) is easily formed around the isolation structure. In this way, when an oxide layer is subsequently formed on the active region, the oxidation rate will be affected by the depression around the isolation structure. The thickness of the oxide layer formed around it will be thinner than the thickness of the oxide layer formed in the active area, resulting in the problem of uneven thickness thinning, and the formation of the oxide layer will often produce a lot of stress Derived problems, and the above problems will reduce the yield of the product.

The invention provides a semiconductor device and a manufacturing method thereof, which can improve the yield of products.

A semiconductor device of the present invention includes a substrate and an oxide layer. The substrate has at least two isolation structures and an active area between the at least two isolation structures. Each isolation structure includes a first oxide material layer and a second oxide material layer, and the second oxide material layer is disposed on the first oxide material layer. The oxide layer is disposed on the active area, wherein the orthographic projection of the oxide layer on the substrate overlaps with at least two isolation structures.

In an embodiment of the present invention, the above-mentioned active region is a high voltage region.

In an embodiment of the present invention, the material of the above-mentioned first oxide material layer is different from the material of the second oxide material layer.

In an embodiment of the present invention, the aforementioned partial oxide layer is embedded in at least two isolation structures.

In an embodiment of the present invention, the top surface of the second oxide material layer is higher than the top surface of the first oxide material layer.

In an embodiment of the present invention, the above-mentioned oxide layer directly contacts the first oxide material layer and the second oxide material layer.

A method of manufacturing a semiconductor device includes at least the following steps. At least two trenches are formed in the substrate to define at least one active area. A first oxide material layer is formed on the substrate. A second oxide material layer is formed on the first oxide material layer. A portion of the first oxide material layer and a portion of the second oxide material layer are removed to form an opening between the second oxide material layer and the substrate, wherein the opening exposes a top surface of the first oxide material layer.

In an embodiment of the present invention, the above manufacturing method uses an etching process to remove part of the first oxide material layer and part of the second oxide material layer.

In an embodiment of the present invention, the etching rate of the first oxide material layer is greater than the etching rate of the second oxide material layer.

In an embodiment of the present invention, the above-mentioned at least one active region is a high voltage region, the substrate includes a low voltage region on one side of the high voltage region, the mask layer exposes the high voltage region, and the mask layer covers the low voltage region. district.

Based on the above, the semiconductor device of the present invention removes a portion of the first oxide material layer and a portion of the second oxide material layer to form an exposed first oxide layer between the second oxide material layer and the substrate in the trench. The manufacturing method of the opening on the top surface of the object material layer can make the oxide layer formed on the active region subsequently fill in the aforementioned opening. The oxide material layer and the isolation structure of the second oxide material layer are overlapped to improve the thinning problem of uneven thickness around the isolation structure and the problem caused by stress when forming the oxide layer, so that the yield of products can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Directional terms (eg, up, down, right, left, front, back, top, bottom) as used herein are used pictorially for reference only and are not intended to imply absolute orientation.

Any method described herein is in no way intended to be construed as requiring performance of its steps in a particular order, unless expressly stated otherwise.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or magnitude of layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1I are partial cross-sectional schematic diagrams of a part of a manufacturing method of a semiconductor device according to an embodiment of the present invention. In this embodiment, the manufacturing method of the semiconductor device 100 may include the following steps. It should be noted that only a partial schematic cross-sectional view of the semiconductor device is shown in the drawings, and other unshown areas may be determined according to actual design requirements.

Referring to FIG. 1A , a substrate 110 is provided. The substrate 110 may be a semiconductor substrate. For example, the substrate 110 is a silicon substrate, but the invention is not limited thereto. Further, in this embodiment, at least two trenches 112 (a trench 112a, a trench 112b and a trench 112c are schematically shown in FIG. 1A ) can be formed in the substrate 110 to define at least one active region. 114 (the active region 114a and the active region 114b are schematically depicted in FIG. 1A ), wherein at least two trenches 112 are formed by removing part of the substrate 110, for example, by an etching process, but the present invention is not limited thereto, at least two trenches 112 can be formed by other suitable methods.

The following is a clear statement, and the trench 112a, the trench 112b and the trench 112c and the active region 114a and the active region 114b sandwiched therebetween will be described directly, but the present invention is not limited thereto, the trench 112 and the active The number of regions 114 can be determined according to actual design requirements.

In this embodiment, the substrate 110 may include a high voltage region and a low voltage region located on one side of the high voltage region, wherein the high voltage region may be the active region 114a between the trench 112a and the trench 112b, and the low voltage region It can be the active region 114b between the trench 112b and the trench 112c, so semiconductor elements with different operating voltage requirements can be formed thereon, but the present invention is not limited thereto, and the active region 114 can be determined according to the actual design. The corresponding semiconductor components are produced according to the requirements.

On the other hand, as shown in FIG. 1A , the pad layer 10 and the mask layer 20 can also be sequentially formed on the substrate 110 . For example, the pad layer 10 and the mask layer 20 may be formed only on the active region 114 a and the active region 114 b of the substrate 110 . The material of the cushion layer 10 is, for example, silicon oxide, and its formation method is, for example, thermal oxidation or chemical vapor deposition. The material of the mask layer 20 is, for example, silicon nitride, and its formation method is, for example, chemical vapor deposition, but the invention is not limited thereto.

In one embodiment, the cushion layer 10 and the mask layer 20 may have the same size and overlap the edges of the trench 112a, the trench 112b, and the trench 112c. In other words, the edges of the cushion layer 10 and the mask layer 20 are substantially The upper cut does not extend into the groove 112a, the groove 112b, and the groove 112c, but the invention is not limited thereto.

Referring to FIG. 1B , optionally, a liner layer 120 may be formed on the substrate 110 . For example, the liner 120 may be formed in the trench 112a, the trench 112b and the trench 112c. The material of the lining layer 120 includes silicon oxide, and can be formed on the sidewalls of the trench 112a, the trench 112b, and the trench 112c through a thermal oxidation process, but the present invention is not limited thereto, and the lining layer 120 can use any suitable material and method formed. Optionally, no lining layer may be formed on the substrate 110 , in other words, no lining layer may be formed in the trench 112 a , the trench 112 b and the trench 112 c .

In this embodiment, the liner 120 is conformally formed on the substrate 110 . For example, the liner 120 is conformally formed on the sidewalls of the trench 112a, the trench 112b, and the trench 112c. Therefore, the spaces in the trench 112a, the trench 112b, and the trench 112c are not completely filled, and may Continue to fill in other material layers, but the present invention is not limited thereto.

In addition, the top surface 120t of the liner 120 may be substantially coplanar with the top surface 110t of the substrate 110 , in other words, the top surface 120t of the liner 120 may be substantially coplanar with the bottom surface of the pad layer 10 . On the other hand, the lining layer 120 may not be in direct contact with the mask layer 20, but the invention is not limited thereto.

Referring to FIG. 1C, the first oxide material layer 130 is fully formed on the substrate 110 (for example, simultaneously formed in the active region 114a and the active region 114b), so the first oxide material layer 130 can cover the pad layer 10, the mask layer 20 and lining 120. Further, the first oxide material layer 130 may be an oxide formed by a sub-atmospheric chemical vapor deposition (SA-CVD) deposition process using a TEOS precursor, but the present invention is not limited thereto .

In this embodiment, the first oxide material layer 130 may be conformally formed on the substrate 110 . For example, the first oxide material layer 130 may be formed on the surface 110t of the substrate 110 and extend to the sidewalls of the trench 112a, the trench 112b, and the trench 112c. Therefore, the trench 112a, the trench 112b, and the trench The space in 112c is not completely filled, and other material layers can be continuously filled in, but the present invention is not limited thereto.

Referring to FIG. 1D , the second oxide material layer 140 is fully formed on the first oxide material layer 130 (for example, formed simultaneously in the active region 114 a and the active region 114 b ). In this embodiment, the second oxide material layer 140 may be formed on the surface 110t of the substrate 110 and fill up the trenches 112a, 112b and 112c.

Further, the material of the first oxide material layer 130 and the material of the second oxide material layer 140 can be different, so that the etching rate of the first oxide material layer 130 can be the same as the etching rate of the second oxide material layer 140 Different, for example, the etching rate of the first oxide material layer 130 may be greater than the etching rate of the second oxide material layer 140, so the subsequent etching process can utilize the first oxide material layer 130 and the second oxide material layer 140 The etch rate difference forms the desired opening OP (as shown in FIG. 1H ). For example, the second oxide material layer 140 is, for example, an oxide formed by high-density plasma (HDP) chemical vapor deposition, but the present invention is not limited thereto, and the second oxide material layer 140 can be formed by other Appropriate methods and materials are made.

Referring to FIG. 1E , part of the first oxide material layer 130 and part of the second oxide material layer 140 are removed, so that the top surface 20t of the mask layer 20 is substantially in contact with the top surface 130t of the first oxide material layer 130 and The top surface 140t of the second oxide material layer 140 is coplanar. For example, a planarization process may be performed on the first oxide material layer 130 and the second oxide material layer 140 through the mask layer 20, wherein the planarization process is, for example, a chemical-mechanical polishing (CMP) process. , mechanical grinding process, etching process or other suitable processes.

Referring to FIG. 1F , after removing part of the first oxide material layer 130 and part of the second oxide material layer 140 , the mask layer 20 may be removed through a suitable process to expose the top surface 10t of the pad layer 10 . In this embodiment, the top surface 10t of the pad layer 10 may be lower than the top surface 140t of the second oxide material layer 140 and the top surface 130t of the first oxide material layer 130 , but the invention is not limited thereto.

Please refer to FIG. 1G. Optionally, when an etching process needs to be performed subsequently, a mask layer 30 can be formed on the substrate 110, wherein the mask layer 30 can only expose the opening OP to be formed by a lithographic etching process (as shown in FIG. 1H) and cover the area where the opening OP does not need to be formed, for example, the mask layer 30 may only expose the active region 114a and cover the active region 114b. Furthermore, when the active region 114a is a high-voltage region and the active region 114b is a low-voltage region, the mask layer 30 can only expose the high-voltage region and cover the low-voltage region, so the opening OP can only be formed in the high-voltage region. area, but the present invention is not limited thereto.

1H, in order to form a buffer space for the subsequent oxide layer 150 (as shown in FIG. An opening OP is formed between the base 140 and the substrate 110, wherein the opening OP exposes the top surface 130t of the first oxide material layer 130 to form at least two isolation structures S (the first isolation structure S1, the second isolation structure S are schematically shown in FIG. Two isolation structures S2 and a third isolation structure S3), wherein each isolation structure S includes a liner 120, a first oxide material layer 130, and a second oxide material layer 140, and the first isolation structure S1, the second isolation structure The S2 and the third isolation structure S3 are, for example, respectively formed in the trench 112a, the trench 112b and the trench 112c.

In one embodiment, when the material of the first oxide material layer 130 is different from that of the second oxide material layer 140, and the etching rate of the first oxide material layer 130 is greater than the etching rate of the second oxide material layer 140 At this time, an etching process may be performed through the mask layer 30 to form the opening OP between the second oxide material layer 140 and the substrate 110 . Further, when performing the etching process, the difference in etching rates between the first oxide material layer 130 and the second oxide material layer 140 can be used to make the removal amount of the first oxide material layer 130 larger than that of the second oxide material layer 140. In other words, the first oxide material layer 130 will gradually shrink during the etching process, so that the top surface 130t of the first oxide material layer 130 is lower than the second oxide material layer. 140 to form the opening OP, but the present invention is not limited thereto.

In one embodiment, the above etching process may be performed by an acid etchant having an etching selectivity between the material of the first oxide material layer 130 and the second oxide material layer 140 , but the invention is not limited thereto.

Referring to FIG. 1I, an oxide layer 150 is formed on the active region 114a of the substrate 110 and partially fills the opening OP, wherein the oxide layer 150 can be formed by any suitable material and method, and the present invention is not limited thereto. After the above process, the fabrication of the semiconductor device 100 of this embodiment can be substantially completed. The semiconductor device 100 includes a substrate 110 and an oxide layer 150 . The substrate 110 has at least two isolation structures S and an active region 114 between the at least two isolation structures S, wherein each isolation structure S includes a first oxide material layer 130 and a second oxide material layer 140, the second oxide material Layer 140 is disposed on first oxide material layer 130 . The oxide layer 150 is disposed on the active region 114, wherein the orthographic projection of the oxide layer 150 on the substrate 110 overlaps with at least two isolation structures S. Accordingly, the semiconductor device 100 of this embodiment removes part of the first oxide material layer 130 and part of the second oxide material layer 140 to form an opening OP exposing the top surface 130t of the first oxide material layer 130 between the second oxide material layer 140 in the trench 112 and the substrate 110 , the oxide layer 150 subsequently formed on the active region 114 can be filled into the opening OP, so that, on the one hand, the buffer space formed by the opening OP can increase the ratio of contact with oxygen around the isolation structure S, and increase the oxide layer 150 The thickness around the isolation structure S can improve the thinning problem of uneven thickness around the isolation structure S when the oxide layer 150 is formed. On the other hand, the buffer space formed by the opening OP can also effectively relieve stress and improve the formation of the oxide layer. Problems caused by stress at 150, therefore, can improve the yield of products.

For example, according to the Raman shift (Raman shift) display of the semiconductor device 100, it can be known that the surroundings of the isolation structure S may have a smaller displacement than the conventional structures, that is, the surroundings of the isolation structure S can bear a smaller displacement than the conventional structures. The stress is small, so the yield of the product can be increased from about 39% to 80%, and the yield is significantly improved, but the present invention is not limited thereto.

In one embodiment, the oxide layer 150 is closely combined with the isolation structure S. In other words, the oxide layer 150 completely fills the second oxide material layer 140 of the isolation structure S1 in FIG. 1I and the second oxide layer of the isolation structure S2. The region between the oxide material layers 140 is used so that the two side edges of the oxide layer 150 can directly contact the isolation structure S1 and the isolation structure S2, but the invention is not limited thereto.

In one embodiment, the active region 114a where the oxide layer 150 is formed is a high-voltage region, so the oxide layer 150 can be regarded as a high-voltage oxide layer (HVOX) for making subsequent high-voltage semiconductor devices, but the present invention is not limited thereto .

It should be noted that the mask layer 30 can be further removed and other semiconductor elements, such as low-voltage semiconductor elements (not shown), can be formed on the active region 114b, but the present invention is not limited thereto, and the subsequent process can be based on the actual design depends on your needs.

In summary, the semiconductor device of the present invention forms an exposed layer between the second oxide material layer and the substrate in the trench by removing part of the first oxide material layer and part of the second oxide material layer. The manufacturing method of the opening on the top surface of the first oxide material layer can make the oxide layer formed on the active region subsequently fill in the aforementioned opening, in other words, the orthographic projection and isolation of the oxide layer on the substrate can be made The structure (including the first oxide material layer and the second oxide material layer) overlaps, so that the buffer space formed by the opening can increase the proportion of oxygen contact around the isolation structure and increase the oxide layer around the isolation structure. Therefore, it can improve the thinning problem of uneven thickness around the isolation structure when forming the oxide layer. On the other hand, the buffer space formed by the opening can also effectively relieve stress and improve the stress-derived problems when forming the oxide layer. Therefore, , can increase the product yield.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10: Cushion 20, 30: mask layer 100: Semiconductor device 110: base 10t, 20t, 110t, 120t, 130t, 140t: top surface 112, 112a, 112b, 112c: grooves 114, 114a, 114b: active area 120: lining 130: the first oxide material layer 140: second oxide material layer 150: oxide layer OP: opening S, S1, S2, S3: isolation structure

1A to 1I are partial cross-sectional schematic diagrams of a part of a manufacturing method of a semiconductor device according to an embodiment of the present invention.

10: Cushion

30: mask layer

100: Semiconductor device

110: base

112, 112a, 112b, 112c: grooves

114, 114a, 114b: active area

120: lining

130: the first oxide material layer

140: second oxide material layer

150: oxide layer

S, S1, S2, S3: isolation structure

Claims (9)

A semiconductor device, comprising: a substrate having at least two isolation structures and an active region between the at least two isolation structures, wherein each isolation structure includes a first oxide material layer and a second oxide material layer, and The second oxide material layer is disposed on the first oxide material layer; and an oxide layer is disposed on the active region, wherein the orthographic projection of the oxide layer on the substrate is the same as that of the at least two The isolation structures overlap, and part of the oxide layer is embedded in the at least two isolation structures. The semiconductor device according to claim 1, wherein the active region is a high voltage region. The semiconductor device according to claim 1, wherein a material of the first oxide material layer is different from a material of the second oxide material layer. The semiconductor device according to claim 1, wherein the top surface of the second oxide material layer is higher than the top surface of the first oxide material layer. The semiconductor device according to claim 1, wherein the oxide layer directly contacts the first oxide material layer and the second oxide material layer. A method of manufacturing a semiconductor device, comprising: forming at least two trenches in a substrate to define at least one active region; forming a first oxide material layer on the substrate; forming a second oxide material layer on the first On an oxide material layer; removing part of the first oxide material layer and part of the second oxide material layer to form an opening between the second oxide material layer and the substrate, wherein the opening exposes a top surface of the first oxide material layer; and an oxide layer is formed on the active region and Partially fill the opening. The method of manufacturing a semiconductor device according to claim 6, wherein part of the first oxide material layer and part of the second oxide material layer are removed by an etching process. The method of manufacturing a semiconductor device according to claim 7, wherein the etching rate of the first oxide material layer is greater than the etching rate of the second oxide material layer. The method for manufacturing a semiconductor device according to claim 7, wherein the at least one active region is a high-voltage region, the substrate includes a low-voltage region on one side of the high-voltage region, and when performing the etching process, A mask layer is formed on the base, the mask layer exposes the high voltage area, and the mask layer covers the low voltage area.

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