CN114242657A - Forming method of semiconductor structure and manufacturing method of CMOS (complementary Metal oxide semiconductor) device - Google Patents

Forming method of semiconductor structure and manufacturing method of CMOS (complementary Metal oxide semiconductor) device Download PDF

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CN114242657A
CN114242657A CN202111385900.9A CN202111385900A CN114242657A CN 114242657 A CN114242657 A CN 114242657A CN 202111385900 A CN202111385900 A CN 202111385900A CN 114242657 A CN114242657 A CN 114242657A
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voltage device
layer
low
device area
forming
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邢彦召
陈洁
艾义明
张权
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses a method for forming a semiconductor structure and a method for manufacturing a CMOS device, wherein the method for forming the semiconductor structure comprises the following steps: providing a substrate comprising a high-voltage device area and a low-voltage device area; the high-voltage device area comprises an isolation structure formed in the substrate, and a gate oxide layer and a mask layer which are formed on the substrate; the low-voltage device area comprises an isolation structure formed in the substrate, and a liner oxide layer and a mask layer which are formed on the substrate; forming a protective layer on the mask layer of the high-voltage device area; the protective layer comprises a polycrystalline silicon layer and a dielectric layer; etching back the isolation structure of part of the low-voltage device area by adopting a Certas etching process; and removing the protective layer in the high-voltage device area. According to the forming method, the protective layer is formed on the high-voltage device area, so that the mask layer and the gate oxide layer of the high-voltage device area are prevented from being damaged when the barrier structure of the low-voltage device area is etched back by adopting a Certas etching process, and the quality of the gate oxide layer of the high-voltage device area is guaranteed.

Description

Forming method of semiconductor structure and manufacturing method of CMOS (complementary Metal oxide semiconductor) device
Technical Field
The embodiment of the application relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure and a manufacturing method of a CMOS device.
Background
With the continuous reduction of the characteristic size of semiconductor integrated circuit devices, the thickness of a gate oxide layer is correspondingly and continuously reduced according to the principle of equal-scale reduction. Devices with different operating voltages are often required to be integrated on a semiconductor structure, a gate oxide layer corresponding to a high-voltage Complementary Metal Oxide Semiconductor (CMOS) device is thicker, and a gate oxide layer corresponding to a low-voltage CMOS device is thinner.
Among them, the gate oxide layer is an important structure in the semiconductor device, and if there is a defect on the gate oxide layer, the reliability of the semiconductor device is reduced. Therefore, how to improve the quality of the gate oxide layer in the semiconductor device is a problem to be solved.
Disclosure of Invention
The embodiment of the application provides a forming method of a semiconductor structure and a manufacturing method of a CMOS device.
In a first aspect, an embodiment of the present application provides a method for forming a semiconductor structure, where the method includes:
providing a substrate comprising a high-voltage device area and a low-voltage device area; the high-voltage device area comprises an isolation structure formed in the substrate, and a gate oxide layer and a mask layer which are formed on the substrate; the low-voltage device area comprises an isolation structure formed in the substrate, and a pad oxide layer and a mask layer which are formed on the substrate;
forming a protective layer on the mask layer of the high-voltage device area; the protective layer comprises a polycrystalline silicon layer and a dielectric layer;
etching back part of the isolation structure of the low-voltage device area by adopting a Certas etching process;
and removing the protective layer of the high-voltage device area.
According to one embodiment of the present application, the dielectric layer includes a silicon oxide layer and/or a silicon nitride layer.
According to an embodiment of the present application, before the etching back the isolation structure of the low-voltage device region by using the Certas etching process, the method further includes:
and removing the liner oxide layer and the mask layer in the low-voltage device area.
According to an embodiment of the present application, the forming a protection layer on the mask layer in the high voltage device region includes:
forming a protective layer on the mask layer;
forming a patterned photoresist layer on the protective layer, the patterned photoresist layer exposing the low-voltage device region;
and etching through the patterned photoresist layer to remove the protective layer in the low-voltage device area.
According to an embodiment of the present application, the removing a portion of the isolation structure in the low voltage device region by etching back using a Certas etching process includes:
and etching back part of the isolation structure of the low-voltage device area by adopting a Certas etching process, and removing the dielectric layer of the high-voltage device area.
According to an embodiment of the present application, the removing the protection layer of the high voltage device region includes:
removing the polycrystalline silicon layer in the high-voltage device area through etching gas;
the selection ratio of the etching gas to the material of the polycrystalline silicon layer is larger than the selection ratio of the etching gas to the material of the substrate.
According to one embodiment of the present application, the etching gas includes hydrogen chloride gas.
According to one embodiment of the present application, a selectivity ratio of the polysilicon layer to the substrate is greater than 20: 1.
According to an embodiment of the present application, after removing the protection layer of the high voltage device region, the method further includes:
and removing the mask layer in the high-voltage device area to expose the gate oxide layer.
According to an embodiment of the application, the method further comprises:
and forming CMOS devices in the high-voltage device area and the low-voltage device area respectively.
According to one embodiment of the present application, the low voltage device region includes a first low voltage device region and a second low voltage device region; the working voltage of the CMOS device formed in the first low-voltage device area is higher than that of the CMOS device formed in the second low-voltage device area.
In a second aspect, embodiments of the present application provide a method for fabricating a CMOS device, including a method for forming a semiconductor structure as described in the first aspect of the present application.
The embodiment of the application provides a method for forming a semiconductor structure and a method for manufacturing a CMOS device, wherein the method for forming the semiconductor structure comprises the following steps: providing a substrate comprising a high-voltage device area and a low-voltage device area; the high-voltage device area comprises an isolation structure formed in the substrate, and a gate oxide layer and a mask layer which are formed on the substrate; the low-voltage device area comprises an isolation structure formed in the substrate, and a pad oxide layer and a mask layer which are formed on the substrate; forming a protective layer on the mask layer of the high-voltage device area; the protective layer comprises a polycrystalline silicon layer and a dielectric layer; etching back part of the isolation structure of the low-voltage device area by adopting a Certas etching process; and removing the protective layer of the high-voltage device area. According to the forming method of the semiconductor structure, the protective layer is formed on the mask layer of the high-voltage device area, so that the mask layer and the gate oxide layer of the high-voltage device area are prevented from being damaged when a Certas etching process is adopted to etch back part of the isolation structure of the low-voltage device area, and the quality of the gate oxide layer of the high-voltage device area is guaranteed.
Drawings
Fig. 1-10 are simplified cross-sectional views of semiconductor structures formed in accordance with embodiments of the present disclosure;
FIG. 11 is an electron microscope image of a gate oxide layer according to the related art;
fig. 12 is a flowchart of a method of forming a semiconductor structure according to an embodiment of the present disclosure;
the figure includes: 100-a substrate; 101 a-a first active region; 102 a-a second active region; 103 a-a third active region; 200-a low voltage device region; 201-a first low voltage device region; 202-a second low voltage device region; 300-a high voltage device region; 400-isolation trenches; 500-an isolation structure; 601-a gate oxide layer; 601 a-the upper surface of the gate oxide layer; 602-a liner oxide layer; 602 a-upper surface of liner oxide layer; 700-mask layer; 800-a protective layer; 801-a polysilicon layer; 802-a dielectric layer; 900-patterned photoresist layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the embodiments of the present application and the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.
With the continuous reduction of the characteristic size of semiconductor integrated circuit devices, the thickness of a gate oxide layer is correspondingly and continuously reduced according to the principle of equal-scale reduction. Devices with different working voltages are often required to be integrated on a semiconductor structure, the thickness of a gate oxide layer corresponding to a high-voltage CMOS device is larger, and the thickness of a gate oxide layer corresponding to a low-voltage CMOS device is smaller.
Fig. 1-10 illustrate simplified cross-sectional views of forming a semiconductor structure provided by an embodiment of the present application.
As shown in fig. 1, a substrate 100 including a high voltage device region 300 and a low voltage device region 200 is provided. The substrate may be an elemental semiconductor material substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, or the like; or a composite semiconductor material substrate, such as a silicon germanium substrate or the like; but may also be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or the like.
With continued reference to fig. 1, the substrate 100 includes a high voltage device region 300 and a low voltage device region 200, and the operating voltage of the CMOS device formed in the high voltage device region 300 is higher than the operating voltage of the CMOS device formed in the low voltage device region 200. For example, the operating voltage of the CMOS device formed in the High Voltage (HV) device region is greater than 10V, and the operating voltage of the CMOS device formed in the Low Voltage (LV) device region is less than 10V.
Still referring to fig. 1, the low voltage device region 200 may include a first low voltage device region 201 and a second low voltage device region 202, wherein an operating voltage of a CMOS device formed by the first low voltage device region 201 is higher than an operating voltage of a CMOS device formed by the second low voltage device region 202. For example, the operating voltages of the CMOS device formed in the first low-voltage device region and the CMOS device formed in the second low-voltage device region are both less than 10V, where the operating voltage range of the CMOS device formed in the first low-voltage device region may be 3-10V, the operating voltage range of the CMOS device formed in the second low-voltage device region may be 1-3V, and at this time, the second low-voltage device region is also referred to as a low-voltage (LLV) device region.
As shown in fig. 1, a gate oxide 601 is formed on the substrate 100 corresponding to the high-voltage device region 300, and a pad oxide 602 is formed on the substrate 100 corresponding to the low-voltage device region 200, wherein an upper surface 601a of the gate oxide is higher than an upper surface 602a of the pad oxide. The Gate Oxide (GOX) may be, for example, silicon oxide, and the thickness of the gate oxide in the high-voltage device region is relatively large, specifically, the thickness of the gate oxide may be even greater than 1000 angstroms, for example, the thickness of the gate oxide corresponding to the high-voltage device region may be 1200 angstroms. The material of the pad oxide layer may be, for example, silicon oxide, and the thickness of the pad oxide layer corresponding to the low-voltage device region is smaller than that of the gate oxide layer, specifically, the thickness of the pad oxide layer may be in a range of 50 to 200 angstroms, for example, the thickness of the pad oxide layer of the low-voltage device region may be 150 angstroms. The pad oxide layer can be used as a transition layer and a buffer layer between a mask layer and a substrate which are formed subsequently, and can protect an active region between the isolation structures from being polluted in the etching process.
Still referring to fig. 1, a mask layer 700 is formed on the gate oxide 601 and the pad oxide 602, and a Chemical Mechanical Polishing (CMP) process may be used to planarize the surface of the mask layer 700 after the mask layer 700 is formed, where the mask layer 700 shown in fig. 1 is the planarized mask layer 700. At this time, the thickness of the mask layer located in the high-voltage device region is different from the thickness of the mask layer located in the low-voltage device region, and more specifically, the thickness of the mask layer located in the high-voltage device region is smaller than the thickness of the mask layer located in the low-voltage device region. The material of the mask layer may be, for example, silicon nitride. The silicon nitride is used as a material of the mask layer, so that an active region between the isolation structures can be protected, and the silicon nitride can also serve as a polishing barrier material in the subsequent polishing process. The material of the mask layer may also be, for example, silicon oxynitride.
To form the above-described gate oxide, liner oxide, and mask layers, one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof may be used.
Subsequently, a photoresist layer (not shown in fig. 1) may be coated on the surface of the mask layer and a photolithography process such as exposure and development may be performed to form a photoresist pattern having an opening for defining the location of the isolation trench.
As shown in fig. 2, the mask layer is etched using the opening of the photoresist layer to form a mask layer defining the location of the isolation trench and having an opening, after the photoresist layer is removed, the pad oxide layer 602 and the substrate 100 are etched through the mask layer 700 having an opening to form the isolation trench 400 in the low voltage device region 200, and the gate oxide layer 601 and the substrate 100 are etched through the mask layer 700 having an opening to form the isolation trench 400 in the high voltage device region 300. The mask layer can be etched through the opening of the photoresist layer by utilizing a plasma etching process to form the mask layer with the opening, then the liner oxide layer and the substrate are etched through the mask layer with the opening by utilizing fluorine-containing etching gas, and the gate oxide layer and the substrate are etched through the mask layer with the opening to form the isolation trench.
Still referring to fig. 2, oxide layers (not shown in fig. 2) may be formed on the sidewalls and bottom of the isolation trench 400, respectively. The oxide layer, which may have a thickness of 150 angstroms, may be used to improve the interfacial characteristics between the substrate and the filling material of the isolation trench.
As shown in fig. 3, the isolation trenches 400 are filled with an isolation material, respectively, to form an isolation structure 500. Wherein the isolation material may be silicon oxide. Fig. 3 shows only three isolation structures, which are located in the first low voltage device region, the second low voltage device region, and the high voltage device region, respectively. The isolation structure is a Shallow Trench Isolation (STI).
As shown in fig. 4, a CMP process may be employed to planarize the upper surface of the isolation structure and expose the upper surface of the mask layer, i.e., the upper surface of the isolation structure is flush with the upper surface of the mask layer.
As shown in fig. 4, here, the Area between the isolation structures is defined as an Active Area (AA), and referring to fig. 4 again, the Active Area includes a first Active Area 101a, a second Active Area 102a, and a third Active Area 103a, and the first Active Area 101a is located in the first low voltage device region; the second active region 102a is located in the second low voltage device region; the third active region 103a is located within the high voltage device region. The first active region 101a, the second active region 102a, and the third active region 103a are divided based on a device region where the active regions are located.
In the above technical solution, a part of the isolation structure of the low voltage device region needs to be further etched back, and plasma (plasma) in the etching back process may damage the mask layer of the high voltage device region and the gate oxide layer located below the mask layer (damage). The plasma in the back etching process can even cause holes in the mask layer and the gate oxide layer of the high-voltage device area, thereby influencing the breakdown voltage of the gate oxide layer.
Referring to fig. 11, fig. 11 is an electron microscope image of a gate oxide layer according to the related art. As shown in fig. 11, during the back etching process, the gate oxide layer in the high-voltage device region is damaged, and specifically, the gate oxide layer has a hole (punch) defect.
It will be appreciated that the gate oxide is an important structure in semiconductor devices, which may lead to a reduced reliability of the semiconductor device if, for example, a void defect is present in the gate oxide. Therefore, how to improve the quality of the gate oxide layer in the semiconductor device is a problem to be solved.
In view of this, an embodiment of the present application provides a method for forming a semiconductor structure, and fig. 12 shows a flowchart of the method for forming a semiconductor structure provided by the embodiment of the present application, and as shown in fig. 12, the method for forming a semiconductor structure includes:
s1201, providing a substrate comprising a high-voltage device area and a low-voltage device area; the high-voltage device area comprises an isolation structure formed in the substrate, and a gate oxide layer and a mask layer which are formed on the substrate; the low-voltage device area comprises an isolation structure formed in the substrate, and a pad oxide layer and a mask layer formed on the substrate.
As shown in fig. 5, the substrate 100 includes a high voltage device region 300 and a low voltage device region 200, the high voltage device region 300 includes an isolation structure 500 formed in the substrate 100, and the high voltage device region 300 may include a gate oxide layer 601 and a mask layer 700 sequentially formed on the substrate 100; the low-voltage device region 200 includes an isolation structure 500 formed within the substrate 100, and the low-voltage device region 200 may include a pad oxide layer 602 and a mask layer 700 sequentially formed on the substrate 100.
In some embodiments of the present application, CMOS devices are formed in the high voltage device region and the low voltage device region, respectively. The CMOS device formed in the high-voltage device area has a higher operating voltage than the CMOS device formed in the low-voltage device area.
In some embodiments of the present application, a surface of the gate oxide layer is higher than a surface of the pad oxide layer. The thickness of the gate oxide layer in the high-voltage device area is larger than that of the liner oxide layer in the low-voltage device area.
In some embodiments of the present application, the low voltage device region includes a first low voltage device region and a second low voltage device region; the working voltage of the CMOS device formed in the first low-voltage device area is higher than that of the CMOS device formed in the second low-voltage device area.
Still referring to fig. 5, the low voltage device region 200 includes a first low voltage device region 201 and a second low voltage device region 202; the operating voltage of the CMOS device formed in the first low-voltage device region 201 is higher than the operating voltage of the CMOS device formed in the second low-voltage device region 202.
S1202, forming a protective layer on the mask layer of the high-voltage device area; the protective layer comprises a polysilicon layer and a dielectric layer.
In some embodiments of the present application, the forming a protection layer on the mask layer in the high voltage device region includes: forming a protective layer on the mask layer; forming a patterned photoresist layer on the protective layer, the patterned photoresist layer exposing the low-voltage device region; and etching through the patterned photoresist layer to remove the protective layer in the low-voltage device area.
With continued reference to fig. 5, a protection layer 800 is formed on the substrate 100, the protection layer 800 completely covers the mask layer 700 and the upper surface of the isolation structure 500, a patterned photoresist layer 900 is formed on the protection layer 800, the patterned photoresist layer 900 exposes the low-voltage device region 200, and etching is performed through the patterned photoresist layer 900 to remove the protection layer 800 located above the low-voltage device region 200.
With further reference to fig. 6, fig. 6 illustrates a protective layer 800 covering only the upper surfaces of the mask layer 700 and the isolation structure 500 over the high voltage device region 300.
In some embodiments of the present application, the protective layer includes a polysilicon layer and a dielectric layer.
Still referring to fig. 5, a polysilicon film 801 is first formed on the upper surfaces of the mask layer 700 and the isolation structure 500 as a cap layer; then, a dielectric layer 802 is formed on the polysilicon layer 801; a patterned photoresist layer 900 is formed on the dielectric layer 802, the patterned photoresist layer 900 exposes the low voltage device region 200, and etching is performed through the patterned photoresist layer 900 to remove the dielectric layer 802 and the polysilicon layer 801 located above the low voltage device region 200.
To form the polysilicon layer and the dielectric layer in the protective layer described above, one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof may be used.
In some embodiments of the present application, the dielectric layer comprises a silicon oxide layer and/or a silicon nitride layer. The dielectric layer may be a silicon oxide layer, and for example, the thickness of the dielectric layer may be 80 angstroms.
In some embodiments of the present application, the method of forming a semiconductor structure further comprises: and removing the liner oxide layer and the mask layer in the low-voltage device area.
As shown in fig. 7, removing the pad oxide layer and the mask layer over the low voltage device region 200 specifically includes removing the mask layer over the first low voltage device region 201 and the mask layer over the second low voltage device region 202 to expose a portion of the sidewall of the isolation structure 500 in the first low voltage device region 201 and the second low voltage device region 202. At this time, the upper surface of the isolation structure 500 is higher than the upper surface of the substrate 100.
And S1203, etching back a part of the isolation structure of the low-voltage device area by adopting a Certas etching process.
In some embodiments of the present application, the removing, by using a Certas etching process, a portion of the isolation structure in the low voltage device region includes:
and etching back part of the isolation structure of the low-voltage device area by adopting a Certas etching process, and removing the dielectric layer of the high-voltage device area.
As shown in fig. 8, a Certas etch process may be used to etch back portions of the isolation structure 500 of the low voltage device region 200 and to remove the dielectric layer in the protective layer over the high voltage device region. At this time, the upper surface of the isolation structure 500 is lower than the upper surface of the substrate 100, and thus, the upper surface of the isolation structure 500 and the upper surface of the substrate 100 form a recess region (receive).
Specifically, the machine used in the etch-back process is a Certas (chemical gas etching) machine, and the isolation structure of the low-voltage device region in the semiconductor structure can be etched by using a Certas dry etching process. A first air inlet pipe and a second air inlet pipe are respectively arranged at two sides of the reaction chamber of the machine platform, and ammonia (NH) is respectively introduced into the reaction chamber through the first air inlet pipe and the second air inlet pipe3) And Hydrogen Fluoride (HF) gas is conveyed into the reaction chamber of the machine table to form plasma so as to etch the isolation structure.
And S1204, removing the protective layer of the high-voltage device area.
In some embodiments of the present application, the removing the protection layer of the high voltage device region includes:
removing the polycrystalline silicon layer in the high-voltage device area through etching gas;
the selection ratio of the etching gas to the material of the polycrystalline silicon layer is larger than the selection ratio of the etching gas to the material of the substrate.
As shown in fig. 9, the polysilicon layer of the high voltage device region 300 may be removed by an etching gas, and since the selectivity of the etching gas to the material of the polysilicon layer is greater than the selectivity of the etching gas to the material of the substrate, the etching gas may etch only the polysilicon layer without causing damage to the substrate exposed by the low voltage device region.
In some embodiments of the present application, a selectivity ratio of the polysilicon layer relative to the substrate is greater than 20: 1.
As shown in table 1, the etching gas may be, for example, hydrogen chloride (HCl) gas, and the hydrogen chloride gas etches polysilicon material at a rate of 45 a/min at a temperature of 660 ℃, whereas the hydrogen chloride gas etches substrate material, for example, epi-si, at a rate of 2.1 a/min, and thus analysis shows that the selectivity of hydrogen chloride etching polysilicon to epi-si is 21.4.
TABLE 1 etch selectivity of etch gas to polysilicon and epitaxial silicon
Figure BDA0003367004900000111
According to the forming method of the semiconductor structure, the protective layer comprising the polycrystalline silicon layer and the dielectric layer is formed on the mask layer of the high-voltage device area, so that the mask layer of the high-voltage device area and the gate oxide layer located below the mask layer are prevented from being damaged when the Certas process etches back part of the isolation structure of the low-voltage device area, and therefore the quality of the gate oxide layer of the high-voltage device area is ensured. And after the back etching process is finished, the high selection ratio of hydrogen chloride gas to the polysilicon layer and the substrate material can be used, so that the substrate material in the low-voltage device area can not be damaged while the polysilicon layer is removed.
In some embodiments of the present application, after the removing the protective layer of the high voltage device region, the method further comprises:
and removing the mask layer in the high-voltage device area to expose the gate oxide layer.
As shown in fig. 10, the mask layer in the high voltage device region is removed, where the material of the mask layer may be silicon nitride. In other words, the Hard Mask (HM) of the high voltage device region is removed to expose the gate oxide 601 of the high voltage device region.
The embodiment of the application also provides a manufacturing method of the CMOS device, which comprises the forming method of the semiconductor structure in the technical scheme.
The embodiment of the application provides a method for forming a semiconductor structure and a method for manufacturing a CMOS device, wherein the method for forming the semiconductor structure comprises the following steps: providing a substrate comprising a high-voltage device area and a low-voltage device area; the high-voltage device area comprises an isolation structure formed in the substrate, and a gate oxide layer and a mask layer which are formed on the substrate; the low-voltage device area comprises an isolation structure formed in the substrate, and a pad oxide layer and a mask layer which are formed on the substrate; forming a protective layer on the mask layer of the high-voltage device area; the protective layer comprises a polycrystalline silicon layer and a dielectric layer; etching back part of the isolation structure of the low-voltage device area by adopting a Certas etching process; and removing the protective layer of the high-voltage device area. According to the forming method of the semiconductor structure, the protective layer is formed on the mask layer of the high-voltage device area, so that the mask layer of the high-voltage device area and the gate oxide layer located below the mask layer are prevented from being damaged when a Certas etching process is adopted to etch back part of the isolation structure of the low-voltage device area, and the quality of the gate oxide layer of the high-voltage device area is guaranteed.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that are included in the present application, which are made by the present specification and the accompanying drawings, or are directly/indirectly applied to other related technical fields, are included in the scope of the present application.

Claims (12)

1. A method of forming a semiconductor structure, the method comprising:
providing a substrate comprising a high-voltage device area and a low-voltage device area; the high-voltage device area comprises an isolation structure formed in the substrate, and a gate oxide layer and a mask layer which are formed on the substrate; the low-voltage device area comprises an isolation structure formed in the substrate, and a pad oxide layer and a mask layer which are formed on the substrate;
forming a protective layer on the mask layer of the high-voltage device area; the protective layer comprises a polycrystalline silicon layer and a dielectric layer;
etching back part of the isolation structure of the low-voltage device area by adopting a Certas etching process;
and removing the protective layer of the high-voltage device area.
2. The method of forming a semiconductor structure of claim 1, wherein the dielectric layer comprises a silicon oxide layer and/or a silicon nitride layer.
3. The method of claim 1, wherein before the etching back the isolation structure of the low-voltage device region using the Certas etching process, the method further comprises:
and removing the liner oxide layer and the mask layer in the low-voltage device area.
4. The method of forming a semiconductor structure of claim 1, wherein said forming a protective layer on said mask layer in said high voltage device region comprises:
forming a protective layer on the mask layer;
forming a patterned photoresist layer on the protective layer, the patterned photoresist layer exposing the low-voltage device region;
and etching through the patterned photoresist layer to remove the protective layer in the low-voltage device area.
5. The method of claim 1, wherein the removing the isolation structures of the low voltage device region by etching back using a Certas etching process comprises:
and etching back part of the isolation structure of the low-voltage device area by adopting a Certas etching process, and removing the dielectric layer of the high-voltage device area.
6. The method of forming a semiconductor structure of claim 5, wherein the removing the protective layer of the high voltage device region comprises:
removing the polycrystalline silicon layer in the high-voltage device area through etching gas;
the selection ratio of the etching gas to the material of the polycrystalline silicon layer is larger than the selection ratio of the etching gas to the material of the substrate.
7. The method of forming a semiconductor structure of claim 6, wherein the etching gas comprises hydrogen chloride gas.
8. The method of forming a semiconductor structure of claim 1, wherein a selectivity ratio of the polysilicon layer to the substrate is greater than 20: 1.
9. The method of forming a semiconductor structure of claim 1, wherein after the removing the protective layer of the high voltage device region, the method further comprises:
and removing the mask layer in the high-voltage device area to expose the gate oxide layer.
10. The method of forming a semiconductor structure of claim 1 or 9, further comprising:
and forming CMOS devices in the high-voltage device area and the low-voltage device area respectively.
11. The method of forming a semiconductor structure of claim 10, wherein the low voltage device region comprises a first low voltage device region and a second low voltage device region; the working voltage of the CMOS device formed in the first low-voltage device area is higher than that of the CMOS device formed in the second low-voltage device area.
12. A method of fabricating a CMOS device comprising the method of forming a semiconductor structure according to any one of claims 1 to 11.
CN202111385900.9A 2021-11-22 2021-11-22 Forming method of semiconductor structure and manufacturing method of CMOS (complementary Metal oxide semiconductor) device Pending CN114242657A (en)

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