US11832437B2 - Semiconductor memory device with air gaps for reducing current leakage - Google Patents
Semiconductor memory device with air gaps for reducing current leakage Download PDFInfo
- Publication number
- US11832437B2 US11832437B2 US17/546,310 US202117546310A US11832437B2 US 11832437 B2 US11832437 B2 US 11832437B2 US 202117546310 A US202117546310 A US 202117546310A US 11832437 B2 US11832437 B2 US 11832437B2
- Authority
- US
- United States
- Prior art keywords
- bit line
- line structure
- sidewall
- substrate
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 230000001174 ascending effect Effects 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 230000002093 peripheral effect Effects 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 239000010453 quartz Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 80
- 238000000034 method Methods 0.000 description 44
- 125000006850 spacer group Chemical group 0.000 description 41
- 230000008569 process Effects 0.000 description 31
- 238000005530 etching Methods 0.000 description 26
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 14
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 14
- 229910019975 (NH4)2SiF6 Inorganic materials 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- -1 spacer nitride Chemical class 0.000 description 10
- 238000000059 patterning Methods 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 239000000126 substance Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 5
- 238000009834 vaporization Methods 0.000 description 5
- 230000008016 vaporization Effects 0.000 description 5
- 101150072179 ATP1 gene Proteins 0.000 description 4
- 101100003366 Arabidopsis thaliana ATPA gene Proteins 0.000 description 4
- 102100021649 Elongator complex protein 6 Human genes 0.000 description 4
- 101100065219 Homo sapiens ELP6 gene Proteins 0.000 description 4
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 4
- 238000003877 atomic layer epitaxy Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 101150105046 atpI gene Proteins 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910004014 SiF4 Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000001878 scanning electron micrograph Methods 0.000 description 3
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003638 chemical reducing agent Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- JYIFRKSFEGQVTG-UHFFFAOYSA-J tetrachlorotantalum Chemical compound Cl[Ta](Cl)(Cl)Cl JYIFRKSFEGQVTG-UHFFFAOYSA-J 0.000 description 1
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
Definitions
- the present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device with a bit line structure sandwiched by a pair of air gaps for reducing current leakage.
- Semiconductor devices are widely used in electronics industries. Semiconductor devices may have relatively small sizes, multi-functional characteristics, and relatively low manufacturing costs. Semiconductor devices include semiconductor memory devices for storing logical data, semiconductor logic devices for processing logical data (e.g., random-access memory (RAM) and read-only memory (ROM)), and hybrid semiconductor devices performing the functions of both the semiconductor memory devices and the semiconductor logic devices.
- semiconductor memory devices for storing logical data
- semiconductor logic devices for processing logical data e.g., random-access memory (RAM) and read-only memory (ROM)
- hybrid semiconductor devices performing the functions of both the semiconductor memory devices and the semiconductor logic devices.
- DRAM dynamic random-access memory
- bonding between silicon oxide in an interlayer insulating layer of a device and silicon near an interface between a semiconductor substrate of the device and the interlayer insulating layer, or between a gate dielectric layer and silicon near an interface between a semiconductor substrate of the device and the gate dielectric layer results in the existence of an interface energy level, which causes a leakage current to flow from a diffusion layer to the semiconductor substrate.
- Such leakage current reduces performance characteristics of the DRAM.
- a semiconductor memory device comprises a cell area and a periphery area.
- FIGS. 1 to 6 provide illustrative 3D-perspective views and cross-sectional views of a cell area of a semiconductor memory device 10 with air gaps manufactured according to a conventional method of the prior art.
- the semiconductor memory device 10 comprises a bit line structure 101 comprising a bit line tungsten 101 a and a bit line nitride 101 b , wherein the bit line structure 101 is disposed on and protrudes from a substrate of the semiconductor memory device 10 .
- the bit line structure 101 further includes sidewalls SW 1 and SW 2 and an ascending top portion ATP 1 , wherein the ascending top portion ATP 1 is connected to the sidewall SW 2 of the bit line structure 101 .
- the semiconductor memory device 10 further comprises a landing pad 103 , disposed over the ascending top portion ATP 1 and the sidewalls SW 1 and SW 2 of the bit line structure 101 , wherein the landing pad 103 includes an inclined surface IS 1 corresponding to the ascending top portion ATP 1 of the bit line structure 101 .
- the bit line structure 101 is sandwiched between a pair of spacers 105 a and 105 b .
- a spacer oxide 107 is disposed in each of the spacers 105 a and 105 b .
- a pair of air gaps AG 1 and AG 2 are formed within the spacers 105 b and 105 a , respectively (see FIG. 2 ).
- a size of an open area of the spacer oxide 107 determines a stability of the HF vapor etching process.
- open area refers to an area on a top of a laminated structure formed after being slightly etched. Please refer to FIGS. 2 and 3 .
- a smaller open area 109 in the spacer oxide 107 leads to a longer HF vapor etching time and an insufficient air gap depth H 1 .
- the longer HF vapor etching time results in loss of nitride from the spacers 105 a and 105 b and the bit line nitride 101 b in the cell area and a significant nitride loss from the nitride film in the periphery area.
- a larger spacer oxide open area 111 requires a longer dry-etching time for tungsten of the landing pad 103 , which results in a greater etching depth DP 1 .
- a greater height H 2 of the spacer oxide 107 would result in a larger open area of the spacer oxide 107 and a reduction of the HF vapor etching time.
- the greater height H 2 of the spacer oxide 107 would also cause the air gaps to be formed at a high position, which would lead to a shorter distance between a capacitor and an air gap and impact a process window of the capacitor due to a need to perform a dry-etching step for etching through the air gaps.
- metal nitride for the capacitor is deposited into the air gaps, and a current leakage between bit lines occurs.
- One aspect of the present disclosure provides a method of manufacturing a semiconductor memory device.
- the method comprises: receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area, wherein the first bit line structure sequentially comprises a bit line contact disposed on the surface of the cell area, a tungsten layer disposed on the bit line contact, and a nitride layer disposed on the tungsten layer, the first bit line structure includes a top surface away from the substrate and two sidewalls connecting the top surface of the first bit line structure to the substrate, and the first bit line structure is sandwiched by a pair of spacers, wherein each spacer comprises a spacer oxide layer sandwiched by two spacer nitride layers, and wherein a barrier layer conformally overlays the spacers adjacent to the sidewalls of the first bit line structure and the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing
- Another aspect of the present disclosure provides a method of manufacturing a semiconductor memory device.
- the method comprises: receiving a silicon substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area, wherein the first bit line structure sequentially comprises a bit line contact disposed on the surface of the cell area, a tungsten layer disposed on the bit line contact, and a nitride layer disposed on the tungsten layer, the first bit line structure has a top surface away from the substrate and two sidewalls connecting the top surface of the first bit line structure to the substrate, and the first bit line structure is sandwiched by a pair of spacers, wherein each spacer comprises a spacer oxide layer sandwiched by two spacer nitride layers, and wherein a barrier layer conformally overlays the spacers adjacent to the sidewalls of the first bit line structure and the cell area; performing an atomic layer deposition (ALD) to deposit a landing pad above the barrier layer and on the top surface of the first bit
- a further aspect of the present disclosure provides a semiconductor memory device.
- the semiconductor memory device comprises: a substrate including a cell area and a peripheral area; a first bit line structure, disposed on and protruding from a surface of the cell area, wherein the first bit line structure sequentially comprises a bit line contact disposed on the surface of the cell area, a tungsten layer disposed on the bit line contact, and a nitride layer disposed on the tungsten layer, wherein the first bit line structure has a sidewall and an ascending top portion, the sidewall of the first bit line structure connects the ascending top portion of the bit line structure to the surface of the cell area, the ascending top portion has a concavity facing the nitride layer of the first bit line structure, and the first bit line structure is sandwiched by a pair of air gaps; a barrier layer conformally overlaying the air gaps adjacent to the sidewalls of the first bit line structure and the cell area; and a landing pad, disposed over the ascending top portion and the
- (NH 4 ) 2 SiF 6(s) is deposited on a top opening of a spacer.
- This chemical substance begins to decompose and surrounds the nitride layer of the first bit line structure and the spacer nitride layer so that the etching rate is enhanced.
- a vaporization rate of (NH 4 ) 2 SiF 6(s) in a subsequent step of etching the spacer oxide layer a desired profile of an air gap can be obtained.
- problems encountered in the prior art such as difficulties associated with a size of an open area of a spacer oxide, HF vapor etching time, current leakage and other issues are addressed by the method of the present disclosure.
- FIG. 1 is a cross-sectional view showing a portion of a semiconductor memory device of the prior art prior to the formation of an air gap.
- FIG. 2 is a cross-sectional view showing a portion of a semiconductor memory device of the prior art after the formation of an air gap.
- FIG. 3 is an illustrative 3D-perspective view of a semiconductor memory device of the prior art, which has a relatively small spacer oxide open area.
- FIG. 4 is an illustrative 3D-perspective view of a semiconductor memory device of the prior art, which has a relatively large spacer oxide open area.
- FIG. 5 is a cross-sectional view showing a portion of a semiconductor memory device of the prior art, which comprises a spacer oxide with a relatively large height H 2 prior to the formation of an air gap.
- FIG. 6 is a cross-sectional view showing a portion of a semiconductor memory device of the prior art, which comprises a spacer oxide with a relatively large height H 2 after the formation of an air gap.
- FIG. 7 is a representative flow diagram illustrating a method 700 for manufacturing a semiconductor memory device 800 according to an embodiment of the present disclosure.
- FIG. 8 is a perspective view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure after performing of step S 101 in FIG. 7 .
- FIG. 9 is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure after performing of step S 103 in FIG. 7 .
- FIG. 10 is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure after performing of step S 105 in FIG. 7 .
- FIG. 11 is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure after performing of step S 107 in FIG. 7 .
- FIG. 12 is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure during an intermediate stage of step S 109 in FIG. 7 .
- FIG. 13 is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure after performing of step S 109 in FIG. 7 .
- FIG. 14 is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure after performing of step S 111 in FIG. 7 .
- FIG. 15 is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure after performing of step S 113 in FIG. 7 .
- FIG. 16 is an SEM image showing a portion of a semiconductor memory device according to an embodiment of the present disclosure after the performing of step S 113 in FIG. 7 .
- first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “over,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a patterning process is adopted to pattern an existing film or layer.
- the patterning process includes forming a mask on the existing film or layer and removing the unmasked film or layer with an etching or other removal process.
- the mask can be a photoresist or a hard mask.
- a patterning process is adopted to form a patterned layer directly on a surface.
- the patterning process includes forming a photosensitive film on the surface, conducting a photolithography process and performing a developing process. The remaining photosensitive film is retained and integrated into the semiconductor device.
- FIGS. 1 to 6 are illustrative 3D-perspective views and cross-sectional views of a cell area of a semiconductor memory device 10 with air gaps manufactured according to a conventional method.
- FIG. 7 is a flow diagram of a method 700 for manufacturing a semiconductor memory device of the present disclosure.
- FIGS. 8 to 16 are cross-sectional views and SEM images showing a portion of a semiconductor structure 801 during an intermediate stage or after performing steps of the method in accordance with some embodiments of the present disclosure.
- a substrate 801 including a cell area 801 a and a peripheral area 801 b is provided.
- the term “substrate” means and includes a base material or construction upon which materials are formed. It will be appreciated that the substrate may include a single material, a plurality of layers of different materials, a layer or layers having regions of different materials or different structures in them, or another similar arrangement. These materials may include semiconductors, insulators, conductors or combinations thereof.
- the substrate 801 may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a semiconductor substrate having one or more layers, structures or regions formed thereon.
- the substrate 801 may be a semiconductor wafer such as a silicon wafer.
- the substrate 801 may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials.
- the elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium and/or diamond.
- the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide.
- the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP.
- the substrate 801 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate, a silicon-on-insulator (SOI) substrate, or the like.
- the substrate 801 is a multi-layer structure including a polysilicon layer and a metal layer stacked on the substrate 801 in sequence.
- the substrate 801 comprises a metal layer.
- a first bit line structure 803 is formed on a surface 51 of the cell area 801 a , wherein the first bit line structure 803 sequentially comprises a bit line contact 803 a disposed on the surface 51 of the cell area 801 a , a tungsten layer 803 b disposed on the bit line contact 803 a , and a nitride layer 803 c disposed on the tungsten layer 803 b , the first bit line structure 803 has a top surface TS 1 away from the substrate 801 and two sidewalls SW 3 and SW 4 connecting the top surface TS 1 of the first bit line structure 803 to the substrate 801 , and the first bit line structure 803 is sandwiched by a pair of spacers 805 and 807 , wherein each spacer 805 or 807 comprises a spacer oxide layer 809 sandwiched by two spacer nitride layers 811 and 813 , and wherein a barrier layer 815
- the first bit line structure 803 is a pillar having a rounded top. In some embodiments, the first bit line structure 803 includes a sidewall, an ascending top portion, a top portion and a descending portion. In some embodiments, the ascending top portion, the top portion and the descending portion together form the rounded top.
- the semiconductor structure 800 further includes an adhesion layer (not shown in the figures) disposed over the substrate 801 between adjacent pairs of bit line structures 803 .
- the adhesion layer is for a purpose of increased adhesion between a landing pad 817 (to be formed in a later processing step) and the barrier layer 815 to prevent peeling off of the landing pad 817 .
- the barrier layer 815 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.
- silicon oxynitride refers to a substance which contains silicon, nitrogen and oxygen and in which a proportion of oxygen is greater than that of nitrogen.
- Silicon nitride oxide refers to a substance which contains silicon, oxygen and nitrogen and in which a proportion of nitrogen is greater than that of oxygen.
- a cleaning process using a reducing agent may be optionally performed to remove the defects from the substrate 801 .
- the reducing agent may be titanium tetrachloride, tantalum tetrachloride, or a combination thereof.
- a landing pad 817 is deposited above the barrier layer 815 and on the top surface TS 1 of the first bit line structure 803 .
- a process such as atomic layer deposition (ALD), atomic layer epitaxy (ALE), atomic layer chemical vapor deposition (ALCVD), spin-coating, sputtering or the like can be used to apply the landing pad 817 above the barrier layer 815 and on the top surface TS 1 of the first bit line structure 803 .
- the step of depositing the landing pad 817 above the barrier layer 815 and on the top surface TS 1 of the first bit line structure 803 is performed using ALD.
- a planarization process such as chemical mechanical polishing, may be performed after step S 105 .
- a top corner TC 1 of the landing pad 817 is removed to form an inclined surface IS 2 connecting a top surface TS 2 to a sidewall SW 5 of the landing pad 817 .
- a top opening O 1 of the spacer 805 or 807 is formed in the inclined surface IS 2 .
- the inclined surface IS 2 is a convex surface.
- an etching process such as an anisotropic dry etch process or a post reactive ion etching (RIE) process, may be performed to remove the top corner TC 1 of the landing pad 817 .
- RIE post reactive ion etching
- a spacer etching is performed to remove the top corner TC 1 of the landing pad 817 , and the inclined surface IS 2 is a convex surface.
- a directional etching is performed to remove the top corner TC 1 of the landing pad 817 in FIG. 11 .
- multiple etching operations are performed to achieve a desired configuration or a combined configuration of the inclined surface IS 2 of the landing pad 817 .
- a tilt dry-etching is performed to remove the top corner TC 1 of the landing pad 817 .
- step S 109 an etching process is performed on the nitride layer 803 c of the first bit line structure 803 and the spacer nitride layer 811 or 813 from the top opening O 1 using a hydrogen fluoride vapor to form a concavity 819 .
- the following reactions occur at the beginning of step S 109 to generate (NH 4 ) 2 SiF 6(s) : SiO 2(s) +4HF (g) ⁇ SiF 4(g) +2H 2(g) 1. SiF 4(g) +2HF (g) +2NH 3(g) ⁇ (NH 4 ) 2 SiF 6(s) 2. (NH 4 ) 2 SiF 6(s) ⁇ SiF 4(g) +2HF (g) +2NH 3(g) 3.
- (NH 4 ) 2 SiF 6(s) is generated on the top opening O 1 of the spacer 805 or 807 .
- This chemical substance begins to decompose and surrounds the nitride layer 803 c of the first bit line structure 803 and the spacer nitride layer 811 or 813 so that an etching rate is enhanced.
- a concavity 819 is formed after the performing of step S 109 .
- an etching process is performed on the spacer oxide layer 809 from the concavity 819 using a hydrogen fluoride vapor.
- An etching process such as an anisotropic dry etch process or a post reactive ion etching (RIE) process, may be performed in step S 111 .
- RIE post reactive ion etching
- a desired profile of an air gap AG 3 is obtained.
- air gap is used to denote a cavity which may be filled with air, with a gas other than air, or in particular with an inert gas such as argon, or which may otherwise be a vacuum.
- a silicon nitride layer 821 is deposited on the semiconductor memory device 800 to seal the air gap AG 4 .
- a process such as atomic layer deposition (ALD), atomic layer epitaxy (ALE), atomic layer chemical vapor deposition (ALCVD), spin-coating, sputtering or the like can be used to apply the silicon nitride layer 821 on the semiconductor memory device 800 to seal the air gap AG 3 .
- the step of depositing the silicon nitride layer 821 on the semiconductor memory device 800 is performed using ALD.
- a planarization process such as chemical mechanical polishing, may be performed after step S 113 .
- FIG. 16 is an SEM image showing a portion of a semiconductor memory device according to an embodiment of the present disclosure after the performing of step S 113 in FIG. 7 .
- a concavity is formed on the nitride layer of the first bit line structure and the spacer nitride layer.
- (NH 4 ) 2 SiF 6(s) is formed on a top opening of a spacer.
- This chemical substance begins to decompose and surrounds a nitride layer of a first bit line structure and a spacer nitride layer so that an etching rate is enhanced.
- a vaporization rate of (NH 4 ) 2 SiF 6(s) in a subsequent step of etching the spacer oxide layer By controlling a vaporization rate of (NH 4 ) 2 SiF 6(s) in a subsequent step of etching the spacer oxide layer, a desired profile of an air gap can be obtained.
- problems encountered in the prior art such as difficulties associated with a size of an open area of a spacer oxide and HF vapor etching time, current leakage and other issues are addressed by the method of the present disclosure.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
SiO2(s)+4HF(g)→SiF4(g)+
SiF4(g)+2HF(g)+2NH3(g)→(NH4)2
(NH4)2SiF6(s)→SiF4(g)+2HF(g)+
Claims (10)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/546,310 US11832437B2 (en) | 2021-12-09 | 2021-12-09 | Semiconductor memory device with air gaps for reducing current leakage |
TW111115024A TWI799237B (en) | 2021-12-09 | 2022-04-20 | Semiconductor memory device |
TW111115028A TWI855320B (en) | 2021-12-09 | 2022-04-20 | Method for manufacturing semiconductor memory device |
CN202210786157.6A CN116259646A (en) | 2021-12-09 | 2022-07-04 | Semiconductor memory device with reduced power consumption |
CN202210811620.8A CN116261325A (en) | 2021-12-09 | 2022-07-11 | Method for manufacturing semiconductor memory element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/546,310 US11832437B2 (en) | 2021-12-09 | 2021-12-09 | Semiconductor memory device with air gaps for reducing current leakage |
Publications (2)
Publication Number | Publication Date |
---|---|
US20230189500A1 US20230189500A1 (en) | 2023-06-15 |
US11832437B2 true US11832437B2 (en) | 2023-11-28 |
Family
ID=86694326
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/546,310 Active US11832437B2 (en) | 2021-12-09 | 2021-12-09 | Semiconductor memory device with air gaps for reducing current leakage |
Country Status (1)
Country | Link |
---|---|
US (1) | US11832437B2 (en) |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6010933A (en) * | 1998-07-17 | 2000-01-04 | Vanguard International Semiconductor | Method for making a planarized capacitor-over-bit-line structure for dynamic random access memory (DRAM) devices |
US20100255263A1 (en) * | 2006-08-29 | 2010-10-07 | Pioneer Corporation | Gas barrier film and process for preparation of the same |
US20190013321A1 (en) | 2017-07-07 | 2019-01-10 | United Microelectronics Corp. | Method of forming semiconductor memory device |
CN110718550A (en) | 2018-07-12 | 2020-01-21 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
US20200203354A1 (en) * | 2018-12-24 | 2020-06-25 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of fabricating the same |
TWI708372B (en) | 2019-07-24 | 2020-10-21 | 南亞科技股份有限公司 | Semiconductor memory structure and method of manufacturing the same |
US20200388620A1 (en) | 2019-06-07 | 2020-12-10 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US20210066304A1 (en) * | 2019-08-28 | 2021-03-04 | Samsung Electronics Co., Ltd. | Dram device including an air gap and a sealing layer |
CN112514069A (en) | 2018-08-22 | 2021-03-16 | 美光科技公司 | Method of forming a device including an air gap, related device and electronic system |
US20210296321A1 (en) | 2020-03-17 | 2021-09-23 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of fabricating same |
TW202141701A (en) | 2020-04-21 | 2021-11-01 | 力晶積成電子製造股份有限公司 | Sram device and manufacturing method thereof |
-
2021
- 2021-12-09 US US17/546,310 patent/US11832437B2/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6010933A (en) * | 1998-07-17 | 2000-01-04 | Vanguard International Semiconductor | Method for making a planarized capacitor-over-bit-line structure for dynamic random access memory (DRAM) devices |
US20100255263A1 (en) * | 2006-08-29 | 2010-10-07 | Pioneer Corporation | Gas barrier film and process for preparation of the same |
US20190013321A1 (en) | 2017-07-07 | 2019-01-10 | United Microelectronics Corp. | Method of forming semiconductor memory device |
CN110718550A (en) | 2018-07-12 | 2020-01-21 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
CN112514069A (en) | 2018-08-22 | 2021-03-16 | 美光科技公司 | Method of forming a device including an air gap, related device and electronic system |
US20200203354A1 (en) * | 2018-12-24 | 2020-06-25 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of fabricating the same |
US20200388620A1 (en) | 2019-06-07 | 2020-12-10 | Samsung Electronics Co., Ltd. | Semiconductor devices |
TWI708372B (en) | 2019-07-24 | 2020-10-21 | 南亞科技股份有限公司 | Semiconductor memory structure and method of manufacturing the same |
US20210066304A1 (en) * | 2019-08-28 | 2021-03-04 | Samsung Electronics Co., Ltd. | Dram device including an air gap and a sealing layer |
US20210296321A1 (en) | 2020-03-17 | 2021-09-23 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of fabricating same |
TW202141701A (en) | 2020-04-21 | 2021-11-01 | 力晶積成電子製造股份有限公司 | Sram device and manufacturing method thereof |
Non-Patent Citations (3)
Title |
---|
Office Action dated Apr. 14, 2023 related to Taiwanese Application No. 111115028. |
Office Action dated Nov. 3, 2022 related to Taiwanese Application No. 111115028. |
Office Action dated Nov. 8, 2022 related to Taiwanese Application No. 111115024. |
Also Published As
Publication number | Publication date |
---|---|
US20230189500A1 (en) | 2023-06-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10535532B2 (en) | Multiple patterning method using mask portions to etch semiconductor substrate | |
US11437384B1 (en) | Semiconductor memory device and method for manufacturing the same | |
US8105918B2 (en) | Semiconductor device and method of fabricating the same including forming pillar neck patterns | |
US11832437B2 (en) | Semiconductor memory device with air gaps for reducing current leakage | |
US11706913B2 (en) | Method for manufacturing semiconductor memory device | |
TWI845114B (en) | Semiconductor device and method of forming the same | |
US12034056B2 (en) | Semiconductor devices including gate structures with gate spacers | |
CN114975120A (en) | Semiconductor device with a plurality of semiconductor chips | |
KR102224831B1 (en) | Semiconductor finfet device and method | |
TWI799237B (en) | Semiconductor memory device | |
TWI855320B (en) | Method for manufacturing semiconductor memory device | |
TWI854433B (en) | Semiconductor device and method of forming the same | |
US20230352564A1 (en) | Semiconductor device and methods of formation | |
TWI848502B (en) | Semiconductor device and method of forming the same | |
US20230352593A1 (en) | Semiconductor device and methods of formation | |
US20230343834A1 (en) | Semiconductor gate and contact formation | |
CN221226228U (en) | Semiconductor device with a semiconductor device having a plurality of semiconductor chips | |
US20230282572A1 (en) | Method for manufacturing semiconductor device and semiconductor device | |
US12094782B2 (en) | Semiconductor devices and methods of manufacturing thereof | |
US11842929B2 (en) | Semiconductor devices and methods of manufacturing thereof | |
US20230299138A1 (en) | Semiconductor device and manufacturing methods thereof | |
US20230411453A1 (en) | Semiconductor device and methods of formation | |
US20230361191A1 (en) | Semiconductor device and methods of formation | |
US20230253258A1 (en) | Semiconductor device and methods of formation | |
WO2023240704A1 (en) | Semiconductor structure and forming method therefor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NANYA TECHNOLOGY CORPORATION, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LO, HAO-CHAN;WU, HSING-HAN;WANG, JR-CHIUAN;AND OTHERS;REEL/FRAME:058345/0986 Effective date: 20211208 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |