CN116261325A - Method for manufacturing semiconductor memory element - Google Patents

Method for manufacturing semiconductor memory element Download PDF

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Publication number
CN116261325A
CN116261325A CN202210811620.8A CN202210811620A CN116261325A CN 116261325 A CN116261325 A CN 116261325A CN 202210811620 A CN202210811620 A CN 202210811620A CN 116261325 A CN116261325 A CN 116261325A
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bit line
layer
line structure
substrate
spacer
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Inventor
罗浩展
吴星汉
王治权
赖振益
吴俊亨
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Nanya Technology Corp
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Nanya Technology Corp
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Priority claimed from US17/546,657 external-priority patent/US11706913B2/en
Priority claimed from US17/546,310 external-priority patent/US11832437B2/en
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Publication of CN116261325A publication Critical patent/CN116261325A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

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  • General Physics & Mathematics (AREA)
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Abstract

The present disclosure provides a method of manufacturing a semiconductor memory element. The preparation method comprises receiving a substrate having a cell region and a peripheral region; forming a first bit line structure on a surface of the cell region; depositing a landing pad on the barrier layer and on the upper surface of the first bit line structure; removing an upper corner of the landing pad to form an inclined surface connecting an upper surface of the landing pad to a sidewall of the landing pad; etching the nitride layer and the spacer nitride layer of the first bit line structure from the upper opening to form a concave surface; etching the spacer oxide layer from the concave surface to form an air gap; and depositing a silicon nitride layer to seal the air gap.

Description

Method for manufacturing semiconductor memory element
The priority of U.S. patent application No. 17/546,657 (i.e., priority date "2021, 12, 9") is claimed, the contents of which are incorporated herein by reference in their entirety.
Technical Field
The present disclosure relates to a method of manufacturing a memory element. And more particularly to a method of fabricating a memory device having a bit line structure sandwiched between a pair of air gaps.
Background
Semiconductor devices are widely used in the electronics industry. The semiconductor element may have a relatively small size, multi-functional characteristics, and relatively low manufacturing cost. The semiconductor element includes a semiconductor memory element for storing logic data, a semiconductor logic element for processing logic data, such as a Random Access Memory (RAM) and a Read Only Memory (ROM), and a hybrid semiconductor element that performs functions of the semiconductor memory element and the semiconductor logic element.
In Dynamic Random Access Memory (DRAM) devices, there are serious problems associated with leakage currents. The junction between silicon oxide in an interlayer isolation layer of a device and silicon near an interface between a semiconductor substrate of the device and the interlayer isolation layer, or between a gate dielectric layer and silicon near an interface between a semiconductor substrate of the device and the gate dielectric layer, results in the presence of an interface level that causes a leakage current to flow from a diffusion layer to the semiconductor substrate. This leakage current reduces the performance characteristics of the DRAM.
Generally, a semiconductor memory device includes a cell region and a peripheral region. Fig. 1-6 are schematic diagrams illustrating 3D perspective and cross-sectional views providing a cell region of a semiconductor memory device 10 having multiple air gaps fabricated according to a conventional method of the prior art. As shown in fig. 1, the semiconductor memory device 10 includes a bit line structure 101, and the bit line structure 101 includes a bit line tungsten 101a and a bit line nitride 101b, wherein the bit line structure 101 is disposed on a substrate of the semiconductor memory device 10 and protrudes from the substrate of the semiconductor memory device 10. The bit line structure 101 further includes sidewalls SW1 and SW2 and an upwardly sloped upper ATP1, wherein the upwardly sloped upper ATP1 is connected to the sidewall SW2 of the bit line structure 101. The semiconductor memory device 10 further includes a landing pad 103 disposed on the upwardly inclined upper portion ATP1 and the sidewalls SW1 and SW2 of the bit line structure 101, wherein the landing pad 103 has an inclined surface IS1 corresponding to the upwardly inclined upper portion ATP1 of the bit line structure 101. The bit line structure 101 is sandwiched between a pair of spacers 105a and 105 b. After an etching step using a chemical etchant such as HF (hydrogen fluoride) vapor, a pair of air gaps AG1 and AG2 are formed in the spacers 105b and 105a, respectively (refer to fig. 2). The spacer oxide 107 determines a stability of the HF vapor etch process.
As used herein, the term "open area" refers to the area on top of a laminate structure that is formed after being slightly etched. Please refer to fig. 2 and 3. A smaller opening 109 in the spacer oxide 107 results in a longer HF vapor etch time and an insufficient air gap depth H1. Longer HF vapor etch times result in nitride loss from the spacers 105a and 105b in the cell region and the bit line nitride 101b and a significant nitride loss from the nitride film in the surrounding regions.
Please refer to fig. 1 and fig. 4. A larger spacer oxide opening 111 requires a longer dry etch time for the tungsten of landing pad 103, which results in a larger etch depth DP1. A significant nitride loss in the nitride film of the cell region and the surrounding region results in a sealed nitride profile in both regions.
Please refer to fig. 1, 5 and 6. A larger height H2 of the spacer oxide 107 will result in a larger opening area of the spacer oxide 107 and a reduction in HF vapor etch time. However, the larger height H2 of the spacer oxide 107 also results in a plurality of air gaps being formed at a higher location, which results in a shorter distance between a capacitor and an air gap, and affects a process window (process window) of the capacitor due to the need to perform a dry etching step to etch through the plurality of air gaps. Thus, metal nitride for the capacitor is deposited in the plurality of the air gaps, and a leakage current occurs between the plurality of the bit lines. Furthermore, a larger air gap depth results in a larger loss of nitride, which results in a sealed nitride profile in both the cell region and the surrounding region. Thus, these problems require an additional patterning process to form the individual cells and surrounding areas.
The above description of "prior art" merely provides background art, and it is not admitted that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as any part of the present disclosure.
Disclosure of Invention
An embodiment of the present disclosure provides a method for manufacturing a semiconductor memory device. The preparation method comprises receiving a substrate having a cell region and a peripheral region; forming a first bit line structure on a surface of the cell region, wherein the first bit line structure comprises a bit line contact, a tungsten layer and a nitride layer in sequence, the bit line contact is disposed on the surface of the cell region, the tungsten layer is disposed on the bit line contact, the nitride layer is disposed on the tungsten layer, the first bit line structure has an upper surface and two sidewalls, the upper surface is far away from the substrate, the two sidewalls connect the upper surface to the substrate, the first bit line structure is sandwiched between a pair of spacers, wherein each spacer comprises a spacer oxide layer sandwiched between two spacer nitride layers, wherein a barrier layer conformally covers a plurality of the sidewalls adjacent to the first bit line structure and a plurality of the spacers of the cell region; depositing a landing pad on the barrier layer and on the upper surface of the first bit line structure; removing an upper corner of the landing pad to form an inclined surface connecting an upper surface of the landing pad to a sidewall of the landing pad, wherein an upper opening of the spacer is formed in the inclined surface; using hydrogen fluoride vapor (hydrogen fluoride vapor) to produce (NH) 4 ) 2 SiF 6(s) Etching the nitride layer and the spacer nitride layer of the first bit line structure from the upper opening to form a concave surface; by using hydrogen fluoride vapourOver-control (NH) 4 ) 2 SiF 6(s) Etching the spacer oxide layer from the concave surface to form an air gap; and depositing a silicon nitride layer to seal the air gap.
Another embodiment of the present disclosure provides a method of manufacturing a semiconductor memory element. The preparation method comprises receiving a silicon substrate having a cell region and a peripheral region; forming a first bit line structure on a surface of the cell region, wherein the first bit line structure sequentially comprises a bit line contact, a tungsten layer and a nitride layer, the bit line contact is disposed on the surface of the cell region, the tungsten layer is disposed on the bit line contact, the nitride layer is disposed on the tungsten layer, the first bit line structure comprises an upper surface and two sidewalls, the upper surface is away from the substrate, the two sidewalls connect the upper surface to the substrate, the first bit line structure is sandwiched between a pair of spacers, wherein each spacer comprises a spacer oxide layer sandwiched between two spacer nitride layers, wherein a barrier layer conformally covers a plurality of the sidewalls adjacent to the first bit line structure and a plurality of the spacers of the cell region; performing an Atomic Layer Deposition (ALD) to deposit a landing pad on the barrier layer and on the upper surface of the first bit line structure; performing a directional etching to remove an upper corner of the landing pad to form a concave surface having an upper opening of the spacer, the upper opening being formed in the concave surface; using hydrogen fluoride vapor (hydrogen fluoride vapor) to produce (NH) 4 ) 2 SiF 6(s) Performing an anisotropic dry etching process to etch the nitride layer and the spacer nitride layer of the first bit line structure from the opening so as to form a concave surface; by controlling (NH) using hydrogen fluoride vapor 4 ) 2 SiF 6(s) Etching the spacer oxide layer from the concave surface to form an air gap; and depositing a silicon nitride layer to seal the air gap.
Yet another embodiment of the present disclosure provides a semiconductor memory element. The semiconductor memory device includes a substrate having a cell region and a peripheral region; a first bit line structure disposed on and protruding from a surface of the cell region, wherein the first bit line structure sequentially comprises a bit line contact disposed on the surface of the cell region, a tungsten layer disposed on the bit line contact, and a nitride layer disposed on the tungsten layer, wherein the first bit line structure has a sidewall and an upwardly inclined upper portion, the sidewall of the first bit line structure connects the upwardly inclined upper portion of the first bit line structure to the surface of the cell region, and the upwardly inclined upper portion has a concave surface facing the nitride layer of the first bit line, wherein the first bit line structure is sandwiched between a pair of air gaps; a barrier layer conformally covering a plurality of the sidewalls adjacent to the first bit line structure and a plurality of the air gaps of the cell region; and a landing pad disposed on the upwardly inclined upper portion and the sidewalls of the first bit line structure, wherein the landing pad has an inclined surface corresponding to the upwardly inclined upper portion of the first bit line structure.
Due to the design of this preparation method of the present disclosure, (NH 4 ) 2 SiF 6(s) Is deposited over an upper opening of a spacer. This chemical species begins to decompose and surround the nitride layer and a spacer nitride layer of the first bit line structure to increase the etch rate. By controlling (NH) in a subsequent step of etching the spacer oxide layer 4 ) 2 SiF 6(s) A desired profile of an air gap can be obtained. Thus, the methods of preparation of the present disclosure address problems encountered in the prior art, such as difficulties associated with a size dimension of an opening region of a spacer oxide, associated with HF vapor etch time, associated with leakage current, and other problems. Furthermore, for the fabrication methods of the present disclosure, an additional patterning process is not required to form the separate cells and surrounding regions.
The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure are described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
Drawings
The disclosure may be more completely understood in consideration of the following description in conjunction with the accompanying drawings, in which like reference numerals refer to like elements.
FIG. 1 is a schematic cross-sectional view illustrating a portion of a semiconductor memory device of the prior art prior to the preparation of an air gap.
Fig. 2 is a schematic cross-sectional view illustrating a portion of a semiconductor memory device of the prior art after preparing an air gap.
FIG. 3 is a 3D schematic diagram illustrating a conventional semiconductor memory device having a relatively small spacer oxide open area.
Fig. 4 is a 3D schematic diagram illustrating a semiconductor memory device of the prior art having a relatively large spacer oxide open area.
FIG. 5 is a schematic cross-sectional view illustrating a portion of a semiconductor memory device of the prior art including a spacer oxide having a relatively large height prior to preparing an air gap.
Fig. 6 is a schematic cross-sectional view illustrating a portion of a semiconductor memory device of the prior art including a spacer oxide having a relatively large height after preparing an air gap.
Fig. 7 is a schematic flow chart illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.
Fig. 8 is a schematic perspective view illustrating a portion of the semiconductor memory element of an embodiment of the present disclosure after performing step S101 in fig. 7.
Fig. 9 is a schematic cross-sectional view illustrating a portion of the semiconductor memory element of an embodiment of the present disclosure after performing step S103 in fig. 7.
Fig. 10 is a schematic sectional view illustrating a portion of the semiconductor memory element of an embodiment of the present disclosure after performing step S105 in fig. 7.
Fig. 11 is a schematic sectional view illustrating a portion of the semiconductor memory element of an embodiment of the present disclosure after performing step S107 in fig. 7.
Fig. 12 is a schematic cross-sectional view illustrating a portion of a semiconductor memory element during an intermediate stage of performing step S103 in fig. 7 according to an embodiment of the present disclosure.
Fig. 13 is a schematic cross-sectional view illustrating a portion of the semiconductor memory element of an embodiment of the present disclosure after performing step S109 in fig. 7.
Fig. 14 is a schematic cross-sectional view illustrating a portion of the semiconductor memory element of an embodiment of the present disclosure after performing step S111 in fig. 7.
Fig. 15 is a schematic cross-sectional view illustrating a portion of the semiconductor memory element of an embodiment of the present disclosure after performing step S113 in fig. 7.
Fig. 16 is an SEM image view illustrating a portion of the semiconductor memory device after performing step S113 in fig. 7 according to an embodiment of the present disclosure.
The reference numerals are as follows:
10 semiconductor memory element
101 bit line structure
101a bit line tungsten
101b bit line nitride
103 landing pad
105a spacer
105b spacer
107 spacer oxide
109 open area
111 spacer oxide opening region
700 preparation method
800 semiconductor memory element
801 substrate
801a cell region
801b peripheral zone
803 first bit line structure
803a bit line contact
803b tungsten layer
803c nitride layer
805 spacer
807 spacer(s)
809 a spacer oxide layer
811 spacer nitride layer
813 spacer nitride layer
815 barrier layer
817 landing pad
819 concave surface
821 silicon nitride layer
AG1 air gap
AG2 air gap
AG3 air gap
AG4 air gap
ATP1 upward tilting of the upper part
DP1 etch depth
H1 depth
H2 depth
IS1 inclined surface
IS2 inclined surface
O1 upper opening
S1 surface
S101, step
S103 step
S105 step
S107 step
S109 step
S111 step
S113 step
SW1 side wall
SW2 side wall
SW3 side wall
SW4 side wall
SW5 side wall
TC1 upper corner
TS1 upper surface
TS2 upper surface
Detailed Description
The particulars shown herein are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of various embodiments. No attempt is made in this respect to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings and/or the examples should be taken to make apparent to those skilled in the art how the several forms of the invention may be embodied in practice. Thus, before the disclosed processes and elements are described, it is to be understood that the aspects described herein are not limited to particular embodiments, devices, or configurations, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only, and is not intended to be limiting unless specifically defined herein.
The embodiments or examples of the present disclosure shown in the drawings will now be described using specific language. It should be understood that the scope of the disclosure is not intended to be limited thereby. Any alterations and modifications in the described embodiments, and any further applications of the principles as described herein are contemplated as would normally occur to one skilled in the art to which the invention relates. Element numbers may be repeated throughout an embodiment, but this does not necessarily mean that features of one embodiment are applicable to another embodiment even though they share the same element numbers.
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, a "first element," "component," "region," "layer," or "section" discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The grouping of alternative elements or embodiments of the invention disclosed herein should not be construed as limiting. Each portion of a group may be referred to and claimed, alone or in any combination with other portions of the group or other elements found herein. For convenience and/or patentability reasons, it is contemplated that one or more portions of a group may be included in or deleted from the group.
Further, for ease of description, spatially relative terms, such as "below", "lower", "above", "upper", and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the terms "patterning" and "patterning" are used in this disclosure to describe a step of forming a predetermined pattern on a surface. The patterning step includes various steps and processes and varies from one embodiment to another. In some embodiments, a patterning process is employed to pattern an existing film or layer. Patterning includes forming a mask over the existing film or layer and removing the unmasked film or layer by an etching or other removal process. The mask may be a photoresist or a hard mask. In some embodiments, a patterning process is employed to directly form a patterned layer on a surface. The patterning process includes forming a photoresist film on the surface, performing a photolithography process, and performing a developing process. The remaining photoresist film remains and is integrated into the semiconductor device.
The present disclosure will be described in detail with reference to the accompanying drawings having element numbers. It should be understood that the drawings are in greatly simplified form and are not drawn to scale. Furthermore, the dimensions of the drawings have been exaggerated in order to provide a clear illustration and understanding of the present invention.
Fig. 1-6 are 3D and cross-sectional views illustrating the fabrication of a cell region of a semiconductor memory device 10 having a plurality of air gaps in accordance with the prior art. Fig. 7 is a representative flow diagram illustrating a method 700 of fabricating a semiconductor memory device 800 according to an embodiment of the present disclosure. Fig. 8-16 are cross-sectional schematic and SEM image views illustrating a portion of a semiconductor memory device during an intermediate stage of performing a fabrication method or after performing steps in some embodiments of the present disclosure.
Referring to fig. 8, in step S101, a substrate 801 is provided, and the substrate 801 has a cell region 801a and a peripheral region 801b. In this disclosure, the term "substrate" means and includes a base material or structure of material formed thereon. It should be understood that the substrate may comprise a single material, multiple layers of different materials, one or more layers having regions of different materials or different structures therein, or other similar configurations. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, the substrate 801 may be a semiconductor substrate, a base semiconductor substrate on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate 801 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 801 may include elemental semiconductor material, compound semiconductor material, and/or alloy semiconductor material. Examples of the elemental semiconductor may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor may include SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP, but are not limited thereto. In some embodiments, the substrate 801 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate, a silicon-on-insulator (SOI) substrate, or the like. In some embodiments, the substrate 801 is a multi-layer structure including a polysilicon layer and a metal layer sequentially stacked on the substrate 801. In some embodiments, the substrate 801 includes a metal layer.
Referring to fig. 9, in step S103, a first bit line structure 803 is formed on a surface S1 of the cell region 801a, wherein the first bit line structure 803 sequentially includes a bit line contact 803a, a tungsten layer 803b and a nitride layer 803c, the bit line contact 803a is disposed on the surface S1 of the cell region 801a, the tungsten layer 803b is disposed on the bit line contact 803a, the nitride layer 803c is disposed on the tungsten layer 803b, the first bit line structure 803 has an upper surface TS1 and two sidewalls SW3 and SW4, the upper surface TS1 faces away from the substrate 801, the sidewalls SW3 and SW4 connect the upper surface TS1 of the first bit structure 803 to the substrate 801, and the first bit line structure 803 is sandwiched between a pair of spacers 805 and 807, wherein each spacer 805 or 807 includes a spacer oxide layer 809 sandwiched between two spacer nitride layers 811 and 813, wherein a barrier layer 815 conformally covers the sidewalls 803 and the sidewalls 801 and 807 of adjacent to the first bit line structure SW3 and the sidewalls 803 and the sidewalls 807 a. In some embodiments, the first bit line structure 803 is a pillar having a rounded top. In some embodiments, the first bit line structure 803 includes a sidewall, an upwardly sloped upper portion, an upper portion, and a downwardly sloped portion. In some embodiments, the upwardly inclined upper portion, the upper portion, and the downwardly inclined portion together form the rounded top.
In some embodiments, the semiconductor structure 800 further includes an adhesion layer (not shown) disposed on the substrate 801 between adjacent pairs of bit line structures 803. The purpose of the adhesive layer is to increase the adhesion between a landing pad 817 (to be formed in a later processing step) and the barrier layer 815 to prevent the landing pad 817 from peeling.
In step S103, the barrier layer 815 may comprise silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride or the like, for example. It should be understood that in this disclosure, silicon oxynitride refers to a substance comprising silicon, nitrogen, and oxygen, wherein a content of oxygen is greater than a content of nitrogen. Silicon nitride refers to a material comprising silicon, oxygen, and nitrogen, wherein a nitrogen content is greater than an oxygen content. Optionally, a cleaning process using a reducing agent may be optionally performed to remove defects from the substrate 801. The reducing agent may be titanium tetrachloride (titanium tetrachloride), tantalum tetrachloride (tantalum tetrachloride), or a combination thereof.
Referring to fig. 10, in step S105, a landing pad 817 is deposited on the barrier layer 815 and on the upper surface TS1 of the first bit line structure 803. In step S105, a process such as Atomic Layer Deposition (ALD), atomic Layer Epitaxy (ALE), atomic Layer Chemical Vapor Deposition (ALCVD), spin-on, sputtering, or the like may be used to apply the landing pad 817 over the barrier layer 815 and on the upper surface TS1 of the first bit line structure. In accordance with a preferred embodiment of the present disclosure, the deposition of landing pad 817 over barrier layer 815 and on upper surface TS1 of first bit line structure 803 is performed using ALD. Optionally, a planarization process, such as chemical mechanical polishing, may be performed after step S105.
Referring to fig. 11, in step S107, an upper corner TC1 of the landing pad 817 IS removed to form an inclined surface IS2, and the inclined surface IS2 connects an upper surface TS2 to a sidewall SW5 of the landing pad 817. An upper opening O1 of the spacer 805 or 807 IS formed in the inclined surface IS 2. In some embodiments of the present disclosure, the inclined surface IS2 IS a convex surface. In step S107, an etching process, such as an anisotropic dry etching process or a post-Reactive Ion Etching (RIE) process, may be performed to remove the upper corner TC1 of the landing pad 817, and the inclined surface IS2 IS a convex surface. In some embodiments of the present disclosure, a directional etch is performed to remove the upper corner TC1 of the landing pad 817 in fig. 11. In some embodiments, multiple etching steps are performed to achieve a desired configuration or a combined configuration of the sloped surface IS2 of the landing pad 817. In some embodiments, a specific angle dry-etch (titdry-etching) is performed to remove the upper corner TC1 of the landing pad 817.
Referring to fig. 12 and 13, in step S109, an etching process is performed on the nitride layer 803c of the first bit structure 803 and the spacer nitride layer 811 or 813 from the upper opening O1 using a hydrogen fluoride vapor to form a concave surface 819. The next reaction occurs at the beginning of step S109 to produce (NH 4 ) 2 SiF 6(s) ：
1.SiO 2(s) +4HF (g) →SiF 4(g) +2H 2(g)
2.SiF 4(g) +2HF (g) +2NH 3(g) →(NH 4 ) 2 SiF 6(s)
3.(NH 4 ) 2 SiF 6(s) →SiF 4(g) +2HF (g) +2NH 3(g)
As shown in fig. 12, (NH) at the final part of reaction 2 4 ) 2 SiF 6(s) Is generated on the upper opening O1 of the spacer 805 or 807. The chemical species begins to decompose or surround the nitride layer 803c and the spacer nitride layer 811 or 813 of the first bit line structure 803 to enhance an etching rate. As shown in fig. 13, after step S109 is performed, a concave surface 819 is formed.
Referring to fig. 14, in step S111, an etching process is performed on the spacer nitride layer 809 from the concave surface 819 using a hydrogen fluoride vapor. An etching process such as an anisotropic dry etching process or a post-Reactive Ion Etching (RIE) process is performed in step S111. By controlling (NH) in step S111 4 ) 2 SiF 6(s) The vaporization rate (vaporization rate) of an air gap AG3 is obtained. In the present disclosure, the term air gap (air gap) is used to denote a chamber that may be filled with air, have a gas other than air, or in particular an inert gas, such as argon, or it may be a vacuum.
Referring to fig. 15, in step S113, a silicon nitride layer 821 is deposited on the semiconductor memory device 800 to seal the air gap AG4. A process such as ALD, ALE, ALCVD, spin-on, sputtering or the like may be used to apply the silicon nitride layer 821 to the semiconductor memory element 800 to seal the air gap AG3. In accordance with a preferred embodiment of the present disclosure, the step of depositing silicon nitride layer 821 on semiconductor memory element 800 is performed using ALD. Optionally, a planarization process such as chemical mechanical polishing may be performed after step S113.
Fig. 16 is an SEM image view illustrating a portion of the semiconductor memory device after performing step S113 in fig. 7 according to an embodiment of the present disclosure. A concave surface is formed on the nitride layer and the spacer nitride layer of the first bit line structure.
Due to the design of this preparation method of the present disclosure, (NH 4 ) 2 SiF 6(s) Is formed on an upper opening of a spacer. This chemical species begins to decompose and surround the nitride layer and a spacer nitride layer of the first bit line structure to increase the etch rate. By controlling (NH) in a subsequent step of etching the spacer oxide layer 4 ) 2 SiF 6(s) A desired profile of an air gap can be obtained. Thus, the methods of preparation of the present disclosure address problems encountered in the prior art, such as difficulties associated with a size dimension of an opening region of a spacer oxide, associated with HF vapor etch time, associated with leakage current, and other problems. Furthermore, for the fabrication methods of the present disclosure, an additional patterning process is not required to form the separate cells and surrounding regions.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.
Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those of skill in the art will appreciate from the disclosure that a process, machine, manufacture, composition of matter, means, methods, or steps, presently existing or future developed that perform the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of the present invention.

Claims (19)

1. A method of fabricating a semiconductor memory device, comprising:
receiving a substrate, wherein the substrate is provided with a unit area and a peripheral area;
forming a first bit line structure on a surface of the cell region, wherein the first bit line structure comprises a bit line contact, a tungsten layer and a nitride layer in sequence, the bit line contact is disposed on the surface of the cell region, the tungsten layer is disposed on the bit line contact, the nitride layer is disposed on the tungsten layer, the first bit line structure has an upper surface and two sidewalls, the upper surface is far away from the substrate, the two sidewalls connect the upper surface to the substrate, the first bit line structure is sandwiched between a pair of spacers, wherein each spacer comprises a spacer oxide layer sandwiched between two spacer nitride layers, wherein a barrier layer conformally covers a plurality of the sidewalls adjacent to the first bit line structure and a plurality of the spacers of the cell region;
depositing a landing pad on the barrier layer and on the upper surface of the first bit line structure;
removing an upper corner of the landing pad to form an inclined surface connecting an upper surface of the landing pad to a sidewall of the landing pad, wherein an upper opening of the spacer is formed in the inclined surface;
etching the nitride layer and the spacer nitride layer of the first bit line structure from the upper opening to form a concave surface;
etching the spacer oxide layer from the concave surface to form an air gap; and
a silicon nitride layer is deposited to seal the air gap.
2. The method of claim 1, wherein the substrate is a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate, or a silicon-on-insulator substrate.
3. The method of claim 1, wherein the substrate is a multi-layered structure having a polysilicon layer and a metal layer sequentially stacked on the substrate.
4. The method of claim 1, wherein the substrate comprises a metal layer.
5. The method of claim 1, further comprising performing a cleaning process with a reducing agent prior to depositing a landing pad on the barrier layer and on the upper surface of the first bit line structure, wherein the reducing agent is selected from the group consisting of: titanium tetrachloride, tantalum tetrachloride, or a combination thereof.
6. The method of claim 1, wherein depositing a landing pad on the barrier layer and on the upper surface of the first bit line structure is performed using atomic layer deposition.
7. The method of claim 1, further comprising performing a planarization process after depositing a landing pad on the barrier layer and on the upper surface of the first bit line structure.
8. The method of claim 1, wherein a spacer etch is performed to remove the upper corner of the landing pad and the sloped surface is a convex surface.
9. The method of claim 1, wherein etching the nitride layer and the spacer nitride layer of the first bit line structure from the upper opening using a hydrogen fluoride vapor is performed using an anisotropic dry etching process.
10. The method of claim 1, wherein etching the nitride layer and the spacer nitride layer of the first bit line structure from the upper opening to form a concave surface uses hydrogen fluoride vapor to generate (NH) 4 ) 2 SiF 6(s) The step of etching the spacer oxide layer from the concave surface to form an air gap is performed by controlling (NH 4 ) 2 SiF 6(s) Is performed by the vaporization rate of the gas.
11. The method of claim 1, wherein the step of depositing a silicon nitride layer to seal the air gap is performed using atomic layer deposition.
12. The method of claim 1, wherein a directional etch is performed to remove the upper corner of the landing pad and the sloped surface is a concave surface.
13. The method of claim 1, wherein a specific angle dry etch is performed to remove the upper corner of the landing pad.
14. A method of fabricating a semiconductor memory device, comprising:
receiving a silicon substrate, wherein the silicon substrate is provided with a unit area and a peripheral area;
forming a first bit line structure on a surface of the cell region, wherein the first bit line structure sequentially comprises a bit line contact, a tungsten layer and a nitride layer, the bit line contact is disposed on the surface of the cell region, the tungsten layer is disposed on the bit line contact, the nitride layer is disposed on the tungsten layer, the first bit line structure comprises an upper surface and two sidewalls, the upper surface is away from the substrate, the two sidewalls connect the upper surface to the substrate, the first bit line structure is sandwiched between a pair of spacers, wherein each spacer comprises a spacer oxide layer sandwiched between two spacer nitride layers, wherein a barrier layer conformally covers a plurality of the sidewalls adjacent to the first bit line structure and a plurality of the spacers of the cell region;
performing an atomic layer deposition to deposit a landing pad on the barrier layer and on the upper surface of the first bit line structure;
performing a directional etching to remove an upper corner of the landing pad to form a concave surface having an upper opening of the spacer, the upper opening being formed in the concave surface;
performing an anisotropic dry etching process to etch the nitride layer and the spacer nitride layer of the first bit line structure from the opening so as to form a concave surface;
etching the spacer oxide layer from the concave surface to form an air gap; and
a silicon nitride layer is deposited to seal the air gap.
15. The method of claim 14, wherein the silicon substrate has a multi-layer structure with a polysilicon layer and a metal layer sequentially stacked on the substrate.
16. The method of claim 14, further comprising performing a cleaning process using a reducing agent prior to performing an atomic layer deposition to deposit a landing pad on the barrier layer and on the upper surface of the first bit line structure, wherein the reducing agent is selected from the group consisting of: titanium tetrachloride, tantalum tetrachloride, or a combination thereof.
17. The method of claim 14, wherein etching the nitride layer and the spacer nitride layer of the first bit line structure from the upper opening to form a concave surface uses hydrogen fluoride vapor to generate (NH 4 ) 2 SiF 6(s) The step of etching the spacer oxide layer from the concave surface to form an air gap is performed by controlling (NH 4 ) 2 SiF 6(s) Is performed by the vaporization rate of the gas.
18. The method of claim 14, further comprising performing a planarization process after performing an atomic layer deposition to deposit a landing pad on the barrier layer and on the upper surface of the first bit line structure.
19. The method of claim 14, wherein the step of depositing a silicon nitride layer to seal the air gap is performed using atomic layer deposition.
CN202210811620.8A 2021-12-09 2022-07-11 Method for manufacturing semiconductor memory element Pending CN116261325A (en)

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