TWI794113B - Semiconductor device having air cavity - Google Patents

Abstract

The present disclosure provides a semiconductor device having an air cavity. The semiconductor device includes a substrate, a first patterned conductive layer, a first dielectric layer, and a second patterned conductive layer. The first patterned conductive layer is on the substrate. The first dielectric layer is on the first patterned conductive layer. The second patterned conductive layer is on the first dielectric layer. The semiconductor device has an air cavity between the first patterned conductive layer and the second patterned conductive layer.

Description

Semiconductor element with air cavity

This application claims priority to US Patent Application Nos. 17/715,215 and 17/715,272 (ie, the priority date is "April 7, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it concerns a semiconductor component with an air cavity.

With the rapid development of the electronic industry, the development of semiconductor components has achieved high performance and miniaturization. As, for example, the size of semiconductor devices shrinks, parasitic capacitances within semiconductor devices are very important to operational performance. To solve this problem, multiple metal traces can be shortened to reduce parasitic capacitance.

However, although the parasitic capacitance can be reduced, such changes in the metal wiring may adversely affect the operating performance of the semiconductor device.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor element includes a base, a first patterned conductive layer, a first dielectric layer and a second patterned conductive layer. The first patterned conductive layer is disposed on the base. The first dielectric layer is disposed on the first patterned conductive layer. The second patterned conductive layer is disposed on the first dielectric layer. The semiconductor element has an air cavity between the first patterned conductive layer and the second patterned conductive layer.

Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an interconnection structure, a first dielectric layer and a redistribution layer (RDL). The interconnect structure includes an upper patterned conductive layer. The first dielectric layer is disposed on the upper patterned conductive layer. The redistribution layer is disposed on the first dielectric layer. The semiconductor device has an air cavity between the redistribution layer and the interconnect structure.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The fabrication method includes providing an interconnection structure. The fabrication method also includes forming a first dielectric layer on the interconnection structure. The manufacturing method also includes forming a sacrificial pattern on the first dielectric layer. The manufacturing method also includes forming a redistribution layer on the first dielectric layer and the sacrificial pattern. The manufacturing method further includes removing the sacrificial pattern to form an air cavity in the redistribution layer.

In the semiconductor element, due to the design of the air cavity, the parasitic capacitance generated by the interconnection structure, the dielectric layer and the patterned conductive layer (or RDL) can be significantly reduced, thereby improving the operation of the semiconductor element efficacy.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Embodiments or examples of the present disclosure shown in the drawings will now be described using specific language. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modification or improvement of the described embodiments, and any further application of the principles described in this document, would occur as would normally occur to one of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another, even if they share the same element number.

It should be understood that although the terms "first", "second", "third" etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second device , component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. Presence, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device 1 according to some embodiments of the present disclosure. The semiconductor device 1 includes a substrate 10 , an interconnection structure 20 , a dielectric layer 30 , a patterned conductive layer 40 , an air cavity 50 and a contact structure 60 .

For example, the semiconductor substrate 10 may include silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, arsenic phosphide GaN, InP, InGaP or any other Group IV-IV, III-V or I-VI semiconductor materials.

In some embodiments, the semiconductor substrate 10 may have one or more integrated circuits. An integrated circuit may include one or more MOS devices, one or more flash memory cells, or any combination thereof. In some embodiments, the substrate 10 has a surface 101 (also denoted as "an upper surface"). In some embodiments, the substrate 10 includes a plurality of conductive pads 110 disposed adjacent to the surface 101 . The conductive pads 110 can be disposed on the surface 101 of the substrate 10 . In some embodiments, the conductive pads 110 are used to electrically connect the integrated circuits of the substrate 10 to the interconnection structure 20 . For example, the conductive pads 110 may include copper, nickel, cobalt, aluminum, tungsten or any combination thereof.

The interconnect structure 20 may be disposed or formed on the substrate 10 . In some embodiments, the interconnect structure 20 includes a patterned conductive layer 210 (also denoted as "an upper patterned conductive layer"), a patterned conductive layer 220, conductive vias 230 and 240, and a dielectric layer 250. . In some embodiments, the patterned conductive layers 210 and 220 and the conductive vias 230 and 240 are formed in or embedded in the dielectric layer 250 .

In some embodiments, the patterned conductive layer 210 is the uppermost patterned conductive layer of the interconnect structure 20 . The patterned conductive layer 210 can be used to electrically connect to a redistribution layer (RDL) (ie, the patterned conductive layer 40 ). In some embodiments, the patterned conductive layer 210 includes a connection portion 210a and a wiring portion 210b. In some embodiments, the connection part 210a is directly connected to or directly contacts the wiring part 210b. In some embodiments, the connection portion 210 a of the patterned conductive layer 210 is used to electrically connect to a redistribution layer (ie, the patterned conductive layer 40 ).

In some embodiments, the patterned conductive layer 210 is electrically connected to the patterned conductive layer 220 through the conductive via 230 . In some embodiments, the patterned conductive layer 220 is electrically connected to the conductive pad 110 through the conductive via 240 . In some embodiments, the patterned conductive layers 210 and 220 and the conductive vias 230 and 240 may comprise or include aluminum, copper, tungsten, cobalt, or alloys thereof. The number of the patterned conductive layers and the conductive vias of the interconnection structure 20 can vary according to practical applications, and is not limited thereto.

A dielectric layer 30 may be disposed or formed on the interconnect structure 20 . In some embodiments, the dielectric layer 30 is disposed or formed on the patterned conductive layer 210 . In some embodiments, the dielectric layer 30 directly contacts the patterned conductive layer 210 . In some embodiments, the dielectric layer 30 may include or include an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

A patterned conductive layer 40 may be disposed or formed on the dielectric layer 30 . In some embodiments, the patterned conductive layer 40 is disposed or formed on a surface 301 (also denoted as “an upper surface”) of the dielectric layer 30 . In some embodiments, the patterned conductive layer 40 may be a redistribution layer. In some embodiments, a thickness T1 of the patterned conductive layer 40 may be equal to or greater than about 0.8 μm. In some embodiments, the thickness T1 of the patterned conductive layer 40 may be from about 0.8 μm to about 1 μm. In some embodiments, the patterned conductive layer 40 may comprise or include aluminum, copper, tungsten, cobalt, nickel, gold, or alloys thereof.

Air cavity 50 (also denoted as “an air gap”) may be formed or located between interconnect structure 20 and patterned conductive layer 40 . In some embodiments, the air cavity 50 is located between the patterned conductive layer 210 and the patterned conductive layer 40 . In some embodiments, the air cavity 50 is located between the patterned conductive layer 40 and the dielectric layer 30 .

In some embodiments, the air cavity 50 is located within the patterned conductive layer 40 . In some embodiments, a portion of the dielectric layer 30 (ie, the surface 301 ) is exposed to the air cavity 50 . In some embodiments, a portion 301 a of the surface 301 of the dielectric layer 30 is defined by the patterned conductive layer 40 and the surface 301 of the dielectric layer 30 . In some embodiments, the air cavity 50 is defined by the patterned conductive layer 40 and the portion 301 a of the surface 301 of the dielectric layer 30 . In some embodiments, a surface 501 (also denoted as “an upper surface”) of the air cavity 50 is defined by the patterned conductive layer 40 . In some embodiments, a surface 502 (also denoted as "bottom surface") of the air cavity 50 and a surface 402 (also denoted as "bottom surface") of the patterned conductive layer 40 are substantially at the same height.

In some embodiments, the air cavity 50 has a height H1 equal to or greater than about 2000 Å. In some embodiments, the height H1 of the air cavity 50 is from about 2000 Å to about 2500 Å. In some embodiments, a ratio of the height H1 of the air cavity 50 to the thickness T1 of the patterned conductive layer 40 is equal to or greater than about 0.25. In some embodiments, a ratio of the height H1 of the air cavity 50 to the thickness T1 of the patterned conductive layer 40 is from about 0.25 to about 0.5.

The contact structure 60 can electrically connect the interconnection structure 20 and the patterned conductive layer 40 . In some embodiments, the contact structure 60 is electrically connected to the patterned conductive layer 210 and the patterned conductive layer 40 . In some embodiments, the contact structure 60 passes through or passes through the dielectric layer 30 . In some embodiments, the contact structure 60 does not overlap the air cavity 50 in a top view. In some embodiments, the contact structure 60 may comprise or include aluminum, copper, tungsten, cobalt, nickel, gold, or alloys thereof.

According to some embodiments of the present disclosure, due to the design of the air cavity 50, the parasitic capacitance caused by the interconnection structure 20, the dielectric layer 30, and the patterned conductive layer 40 (or redistribution layer) can be significantly reduced, and also Therefore, the operating performance of the semiconductor element 1 can be improved.

In addition, according to some embodiments of the present disclosure, the air cavity 50 is formed in the patterned conductive layer 40 (or redistribution layer), so the parasitic capacitance can be reduced by changing the volume and/or position of the air cavity 50 according to actual needs. , without changing or improving the wiring pattern of the semiconductor device 1 (that is, the configuration of the patterned conductive layer 210 and the contact structure 60 ). Therefore, regardless of the design of the air cavity 50, the wiring pattern can follow the original wiring design rules, so that the parasitic capacitance can be reduced without changing or adjusting the wiring design rules. Therefore, it is possible to prevent the operating performance of the semiconductor element 1 from being adversely affected.

Moreover, according to some embodiments of the present disclosure, due to the design of the ratio of the height H1 of the air cavity 50 to the thickness T1 of the patterned conductive layer 40, a sacrificial pattern for forming the air cavity 50 (which will be described in detail later in the text) The thickness of a pattern 520) (corresponding to or approximately equal to the height H1 of the air cavity 50) is thick enough to avoid peeling thereof. In addition, the formed patterned conductive layer 40 can also have a sufficient thickness on the air cavity 50 to provide satisfactory electrical connection performance.

FIG. 2A is a schematic cross-sectional view illustrating a semiconductor device 2A according to some embodiments of the present disclosure. The semiconductor device 2A includes a substrate 10 , an interconnection structure 20 , dielectric layers 30 and 80 , a patterned conductive layer 40 , an air cavity 50 and a contact structure 60 .

For example, the semiconductor substrate 10 may include silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, arsenic phosphide GaN, InP, InGaP or any other Group IV-IV, III-V or I-VI semiconductor materials.

In some embodiments, the semiconductor substrate 10 may have one or more integrated circuits. An integrated circuit may include one or more MOS devices, one or more flash memory cells, or any combination thereof. In some embodiments, the substrate 10 has a surface 101 (also denoted as "an upper surface"). In some embodiments, the substrate 10 includes a plurality of conductive pads 110 disposed adjacent to the surface 101 . The conductive pads 110 can be disposed on the surface 101 of the substrate 10 . In some embodiments, the conductive pads 110 are used to electrically connect the integrated circuits of the substrate 10 to the interconnection structure 20 . For example, the conductive pads 110 may include copper, nickel, cobalt, aluminum, tungsten or any combination thereof.

The interconnect structure 20 may be disposed or formed on the substrate 10 . In some embodiments, the interconnect structure 20 includes a patterned conductive layer 210 (also denoted as "an upper patterned conductive layer"), a patterned conductive layer 220, conductive vias 230 and 240, and a dielectric layer 250. . In some embodiments, the patterned conductive layers 210 and 220 and the conductive vias 230 and 240 are formed in or embedded in the dielectric layer 250 .

In some embodiments, the patterned conductive layer 210 is the uppermost patterned conductive layer of the interconnect structure 20 . The patterned conductive layer 210 can be used to electrically connect to a redistribution layer (RDL) (ie, the patterned conductive layer 40 ). In some embodiments, the patterned conductive layer 210 includes a connection portion 210a and a wiring portion 210b. In some embodiments, the connection part 210a is directly connected to or directly contacts the wiring part 210b. In some embodiments, the connection portion 210 a of the patterned conductive layer 210 is used to electrically connect to a redistribution layer (ie, the patterned conductive layer 40 ).

In some embodiments, the patterned conductive layer 210 is electrically connected to the patterned conductive layer 220 through the conductive via 230 . In some embodiments, the patterned conductive layer 220 is electrically connected to the conductive pad 110 through the conductive via 240 . In some embodiments, the patterned conductive layers 210 and 220 and the conductive vias 230 and 240 may comprise or include aluminum, copper, tungsten, cobalt, or alloys thereof. The number of the patterned conductive layers and the conductive vias of the interconnection structure 20 can vary according to practical applications, and is not limited thereto.

A dielectric layer 30 may be disposed or formed on the interconnect structure 20 . In some embodiments, the dielectric layer 30 is disposed or formed on the patterned conductive layer 210 . In some embodiments, the dielectric layer 30 directly contacts the patterned conductive layer 210 . In some embodiments, the dielectric layer 30 may include or include an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

A patterned conductive layer 40 may be disposed or formed on the dielectric layer 30 . In some embodiments, the patterned conductive layer 40 is disposed or formed on a surface 301 (also denoted as “an upper surface”) of the dielectric layer 30 . In some embodiments, the patterned conductive layer 40 may be a redistribution layer. In some embodiments, a thickness T1 of the patterned conductive layer 40 may be equal to or greater than about 0.8 μm. In some embodiments, the thickness T1 of the patterned conductive layer 40 may be from about 0.8 μm to about 1 μm.

In some embodiments, the patterned conductive layer 40 includes a seed layer 410 and a conductive layer 420 . In some embodiments, a seed layer 410 is disposed or formed on the surface 301 of the dielectric layer 30 , and a conductive layer 420 is formed on the seed layer 410 . In some embodiments, the seed layer 410 may comprise or include titanium, copper, or alloys thereof, or any combination thereof. In some embodiments, conductive layer 420 may comprise or include aluminum, copper, tungsten, cobalt, nickel, gold, or alloys thereof.

Air cavity 50 (also denoted as “an air gap”) may be formed or located between interconnect structure 20 and patterned conductive layer 40 . In some embodiments, the air cavity 50 is located between the patterned conductive layer 210 and the patterned conductive layer 40 . In some embodiments, the air cavity 50 is located between the patterned conductive layer 40 and the dielectric layer 30 .

In some embodiments, the air cavity 50 is located within the patterned conductive layer 40 . In some embodiments, a portion of the dielectric layer 30 (ie, the surface 301 ) is exposed to the air cavity 50 . In some embodiments, a portion 301 a of the surface 301 of the dielectric layer 30 is defined by the patterned conductive layer 40 and the surface 301 of the dielectric layer 30 . In some embodiments, the air cavity 50 is defined by the patterned conductive layer 40 and the portion 301 a of the surface 301 of the dielectric layer 30 . In some embodiments, a surface 501 (also denoted as “an upper surface”) of the air cavity 50 is defined by the patterned conductive layer 40 . In some embodiments, a surface 502 (also denoted as "bottom surface") of the air cavity 50 and a surface 402 (also denoted as "bottom surface") of the patterned conductive layer 40 are substantially at the same height.

In some embodiments, a portion of the seed layer 410 is exposed to the air cavity 50 . In some embodiments, a surface 410 a of the seed layer 410 is exposed to the air cavity 50 . In some embodiments, a portion of the conductive layer 420 is exposed in the air cavity 50 . In some embodiments, a surface 420 a of the conductive layer 420 is exposed to the air cavity 50 . In some embodiments, the air cavity 50 is defined by the seed layer 410 , the conductive layer 420 and the surface 301 of the dielectric layer 30 . In some embodiments, the air cavity 50 is defined by the surface 410 a of the seed layer 410 , the surface 420 a of the conductive layer 420 , and a portion 301 a of the surface 301 of the dielectric layer 30 .

In some embodiments, the air cavity 50 has a height H1 equal to or greater than about 2000 Å. In some embodiments, the height H1 of the air cavity 50 is from about 2000 Å to about 2500 Å. In some embodiments, a ratio of the height H1 of the air cavity 50 to the thickness T1 of the patterned conductive layer 40 (ie the sum of the thickness of the seed layer 410 and the thickness of the conductive layer 450 ) is equal to or greater than about 0.25. In some embodiments, the ratio of the height of the air cavity 50 to the thickness T1 of the patterned conductive layer 40 is from about 0.25 to about 0.5.

The contact structure 60 can electrically connect the interconnection structure 20 and the patterned conductive layer 40 . In some embodiments, the contact structure 60 is electrically connected to the patterned conductive layer 210 and the patterned conductive layer 40 . In some embodiments, the contact structure 60 passes through or passes through the dielectric layer 30 . In some embodiments, the contact structure 60 does not overlap the air cavity 50 in a top view.

In some embodiments, the contact structure 60 includes a seed layer 610 and a conductive layer 620 . In some embodiments, the seed layer 610 is disposed or formed on the patterned conductive layer 210 , and the conductive layer 620 is formed on the seed layer 610 . In some embodiments, the seed layer 610 comprises or includes titanium, copper, or alloys thereof, or any combination thereof. In some embodiments, conductive layer 620 may comprise or include aluminum, copper, tungsten, cobalt, nickel, gold, or alloys thereof. In some embodiments, the seed layer 410 of the patterned conductive layer 40 and the seed layer 610 of the contact structure 60 comprise or include the same material. In some embodiments, the conductive layer 420 of the patterned conductive layer 40 and the conductive layer 620 of the contact structure 60 comprise or include the same material.

A dielectric layer 80 may be disposed or formed on the patterned conductive layer 40 . In some embodiments, a dielectric layer 80 is disposed or formed on the patterned conductive layer 40 . In some embodiments, the dielectric layer 80 covers the patterned conductive layer 40 . In some embodiments, the dielectric layer 80 directly contacts the patterned conductive layer 40 . In some embodiments, the dielectric layer 80 has an opening 70A (also denoted as “a through hole”) to expose a portion of the patterned conductive layer 40 . In some embodiments, opening 70A does not overlap air cavity 50 in a top view. In some embodiments, the dielectric layer 80 may include or include an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

FIG. 2B is a schematic cross-sectional view illustrating a semiconductor device 2B according to some embodiments of the present disclosure. The semiconductor device 2B includes a substrate 10 , an interconnect structure 20 , dielectric layers 30 and 80 , patterned conductive layers 40 and 90 , an air cavity 50 and contact structures 60 and 70 .

For example, the semiconductor substrate 10 may include silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, arsenic phosphide GaN, InP, InGaP or any other Group IV-IV, III-V or I-VI semiconductor materials.

In some embodiments, the semiconductor substrate 10 may have one or more integrated circuits. An integrated circuit may include one or more MOS devices, one or more flash memory cells, or any combination thereof. In some embodiments, the substrate 10 has a surface 101 (also denoted as "an upper surface"). In some embodiments, the substrate 10 includes a plurality of conductive pads 110 disposed adjacent to the surface 101 . The conductive pads 110 can be disposed on the surface 101 of the substrate 10 . In some embodiments, the conductive pads 110 are used to electrically connect the integrated circuits of the substrate 10 to the interconnection structure 20 . For example, the conductive pads 110 may include copper, nickel, cobalt, aluminum, tungsten or any combination thereof.

The interconnect structure 20 may be disposed or formed on the substrate 10 . In some embodiments, the interconnect structure 20 includes a patterned conductive layer 210 (also denoted as "an upper patterned conductive layer"), a patterned conductive layer 220, conductive vias 230 and 240, and a dielectric layer 250. . In some embodiments, the patterned conductive layers 210 and 220 and the conductive vias 230 and 240 are formed in or embedded in the dielectric layer 250 .

In some embodiments, the patterned conductive layer 210 is the uppermost patterned conductive layer of the interconnect structure 20 . The patterned conductive layer 210 can be used to electrically connect to a redistribution layer (RDL) (ie, the patterned conductive layer 40 ). In some embodiments, the patterned conductive layer 210 includes a connection portion 210a and a wiring portion 210b. In some embodiments, the connection part 210a is directly connected to or directly contacts the wiring part 210b. In some embodiments, the connection portion 210 a of the patterned conductive layer 210 is used to electrically connect to a redistribution layer (ie, the patterned conductive layer 40 ).

In some embodiments, the patterned conductive layer 210 is electrically connected to the patterned conductive layer 220 through the conductive via 230 . In some embodiments, the patterned conductive layer 220 is electrically connected to the conductive pad 110 through the conductive via 240 . In some embodiments, the patterned conductive layers 210 and 220 and the conductive vias 230 and 240 may comprise or include aluminum, copper, tungsten, cobalt, or alloys thereof. The number of the patterned conductive layers and the conductive vias of the interconnection structure 20 can vary according to practical applications, and is not limited thereto.

A dielectric layer 30 may be disposed or formed on the interconnect structure 20 . In some embodiments, the dielectric layer 30 is disposed or formed on the patterned conductive layer 210 . In some embodiments, the dielectric layer 30 directly contacts the patterned conductive layer 210 . In some embodiments, the dielectric layer 30 may include or include an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

A patterned conductive layer 40 may be disposed or formed on the dielectric layer 30 . In some embodiments, the patterned conductive layer 40 is disposed or formed on a surface 301 (also denoted as “an upper surface”) of the dielectric layer 30 . In some embodiments, the patterned conductive layer 40 may be a redistribution layer. In some embodiments, a thickness T1 of the patterned conductive layer 40 may be equal to or greater than about 0.8 μm. In some embodiments, the thickness T1 of the patterned conductive layer 40 may be from about 0.8 μm to about 1 μm.

In some embodiments, the patterned conductive layer 40 includes a seed layer 410 and a conductive layer 420 . In some embodiments, a seed layer 410 is disposed or formed on the surface 301 of the dielectric layer 30 , and a conductive layer 420 is formed on the seed layer 410 . In some embodiments, the seed layer 410 may comprise or include titanium, copper, or alloys thereof, or any combination thereof. In some embodiments, conductive layer 420 may comprise or include aluminum, copper, tungsten, cobalt, nickel, gold, or alloys thereof.

Air cavity 50 (also denoted as “an air gap”) may be formed or located between interconnect structure 20 and patterned conductive layer 40 . In some embodiments, the air cavity 50 is located between the patterned conductive layer 210 and the patterned conductive layer 40 . In some embodiments, the air cavity 50 is located between the patterned conductive layer 40 and the dielectric layer 30 .

In some embodiments, the air cavity 50 is located within the patterned conductive layer 40 . In some embodiments, a portion of the dielectric layer 30 (ie, the surface 301 ) is exposed to the air cavity 50 . In some embodiments, a portion 301 a of the surface 301 of the dielectric layer 30 is defined by the patterned conductive layer 40 and the surface 301 of the dielectric layer 30 . In some embodiments, the air cavity 50 is defined by the patterned conductive layer 40 and the portion 301 a of the surface 301 of the dielectric layer 30 . In some embodiments, a surface 501 (also denoted as “an upper surface”) of the air cavity 50 is defined by the patterned conductive layer 40 . In some embodiments, a surface 502 (also denoted as "bottom surface") of the air cavity 50 and a surface 402 (also denoted as "bottom surface") of the patterned conductive layer 40 are substantially at the same height.

In some embodiments, a portion of the seed layer 410 is exposed to the air cavity 50 . In some embodiments, a surface 410 a of the seed layer 410 is exposed to the air cavity 50 . In some embodiments, a portion of the conductive layer 420 is exposed in the air cavity 50 . In some embodiments, a surface 420 a of the conductive layer 420 is exposed to the air cavity 50 . In some embodiments, the air cavity 50 is defined by the seed layer 410 , the conductive layer 420 and the surface 301 of the dielectric layer 30 . In some embodiments, the air cavity 50 is defined by the surface 410 a of the seed layer 410 , the surface 420 a of the conductive layer 420 , and a portion 301 a of the surface 301 of the dielectric layer 30 .

In some embodiments, the air cavity 50 has a height H1 equal to or greater than about 2000 Å. In some embodiments, the height H1 of the air cavity 50 is from about 2000 Å to about 2500 Å. In some embodiments, a ratio of the height H1 of the air cavity 50 to the thickness T1 of the patterned conductive layer 40 (ie the sum of the thickness of the seed layer 410 and the thickness of the conductive layer 450 ) is equal to or greater than about 0.25. In some embodiments, the ratio of the height of the air cavity 50 to the thickness T1 of the patterned conductive layer 40 is from about 0.25 to about 0.5.

The contact structure 60 can electrically connect the interconnection structure 20 and the patterned conductive layer 40 . In some embodiments, the contact structure 60 is electrically connected to the patterned conductive layer 210 and the patterned conductive layer 40 . In some embodiments, the contact structure 60 passes through or passes through the dielectric layer 30 . In some embodiments, the contact structure 60 does not overlap the air cavity 50 in a top view.

In some embodiments, the contact structure 60 includes a seed layer 610 and a conductive layer 620 . In some embodiments, the seed layer 610 is disposed or formed on the patterned conductive layer 210 , and the conductive layer 620 is formed on the seed layer 610 . In some embodiments, the seed layer 610 comprises or includes titanium, copper, or alloys thereof, or any combination thereof. In some embodiments, conductive layer 620 may comprise or include aluminum, copper, tungsten, cobalt, nickel, gold, or alloys thereof. In some embodiments, the seed layer 410 of the patterned conductive layer 40 and the seed layer 610 of the contact structure 60 comprise or include the same material. In some embodiments, the conductive layer 420 of the patterned conductive layer 40 and the conductive layer 620 of the contact structure 60 comprise or include the same material.

The contact structure 70 may be disposed or formed on the patterned conductive layer 40 . In some embodiments, the contact structure 70 does not overlap the air cavity 50 in a top view. In some embodiments, the contact structure 70 is electrically connected to the patterned conductive layer 40 .

A dielectric layer 80 may be disposed or formed on the patterned conductive layer 40 . In some embodiments, a dielectric layer 80 is disposed or formed on the patterned conductive layer 40 . In some embodiments, the dielectric layer 80 covers the patterned conductive layer 40 . In some embodiments, the dielectric layer 80 directly contacts the patterned conductive layer 40 . In some embodiments, the contact structure 70 passes through or passes through the dielectric layer 80 . In some embodiments, the dielectric layer 80 may include or include an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

A patterned conductive layer 90 may be disposed or formed on the dielectric layer 80 . In some embodiments, the patterned conductive layer 90 is electrically connected to the patterned conductive layer 40 via the contact structure 70 . In some embodiments, the patterned conductive layer 90 may be a redistribution layer.

In some embodiments, the patterned conductive layer 90 includes a seed layer 910 and a conductive layer 920 . In some embodiments, the seed layer 910 is disposed or formed on the dielectric layer 80 and the conductive layer 920 is formed on the seed layer 910 . In some embodiments, the seed layer 910 may comprise or comprise titanium, copper, or alloys thereof, or any combination thereof. In some embodiments, conductive layer 920 may comprise or include aluminum, copper, tungsten, cobalt, nickel, gold, or alloys thereof. In some embodiments, the seed layer 910 of the patterned conductive layer 90 and the seed layer 710 of the contact structure 70 comprise or include the same material. In some embodiments, the conductive layer 920 of the patterned conductive layer 90 and the conductive layer 720 of the contact structure 70 comprise or include the same material.

FIG. 3 is a schematic top view illustrating a semiconductor device 3 according to some embodiments of the present disclosure. The semiconductor device 3 includes a substrate (not shown in FIG. 3 ), an interconnection structure 20 , a patterned conductive layer 40 , an air cavity 50 , a contact structure 60 and a dielectric layer 80 . It should be understood that some elements or structures are omitted for clarity. For example, for clarity, the wiring portion 210 b of the patterned conductive layer 210 of the interconnection structure 20 is omitted in FIG. 3 .

In some embodiments, in a top view, the connection portion 210a of the patterned conductive layer 210 of the interconnection structure 20 does not overlap with the air cavity 50 . In a top view, the contact structure 60 does not overlap the air cavity 50 . In some embodiments, the opening 70A of the dielectric layer 80 does not overlap the air cavity 50 in a top view.

In some embodiments, the air chamber 50 includes one or more air channels (ie, air channels 51 , 52 , 53 , 54 ). In some embodiments, the air channels 51 , 52 , 53 , 54 extend within the patterned conductive layer 40 .

In some embodiments, air channels 51 extend within patterned conductive layer 40 . In some embodiments, the air channel 51 has an end 510a terminating at the dielectric layer 80 . In some embodiments, the end 510 a of the air channel 51 is bounded by a portion of the dielectric layer 80 . In some embodiments, the air channel 51 also has an end 510b disposed opposite to the end 510a and terminated at the patterned conductive layer 40 . In some embodiments, the end 510 b of the air channel 51 is defined by a portion of the patterned conductive layer 40 .

In some embodiments, air channels 52 extend within patterned conductive layer 40 . In some embodiments, air channel 52 has an end 520a terminating at dielectric layer 80 . In some embodiments, the end 520 a of the air channel 52 is bounded by a portion of the dielectric layer 80 . In some embodiments, the air channel 52 also has an end 520b disposed opposite to the end 520a and connected to the air channel 53 .

In some embodiments, air channel 53 is connected to air channel 52 . In some embodiments, air channels 53 extend within patterned conductive layer 40 . In some embodiments, air channel 53 has an end 530a terminating at dielectric layer 80 . In some embodiments, the end 530 a of the air channel 53 is bounded by a portion of the dielectric layer 80 . In some embodiments, air channel 53 also has an end 530b disposed opposite end 530a and terminating at dielectric layer 80 . In some embodiments, the end 530 b of the air channel 53 is bounded by a portion of the dielectric layer 80 . In some embodiments, air channel 52 is aligned with air channel 53 .

In some embodiments, air channels 54 extend within patterned conductive layer 40 . In some embodiments, air channel 54 has an end 540a terminating at dielectric layer 80 . In some embodiments, the end 540 a of the air channel 54 is bounded by a portion of the dielectric layer 80 . In some embodiments, air channel 54 also has an end 540b disposed opposite end 540a and terminating at dielectric layer 80 . In some embodiments, the end 540b of the air channel 54 is bounded by a portion of the dielectric layer 80 .

In some embodiments, a width of the air channels (ie, the air channels 51 , 52 , 53 , 54 ) in a direction along the section line BB′ is equal to or greater than about 3 μm. In some embodiments, a width of each portion (also denoted as a "support foot") of the patterned conductive layer 40 on opposite sides of the air channel in a direction along the section line BB' is equal to or greater than About 1 μm. The sum of the widths of the two supporting legs and the width of the air passage in a direction along the section line BB' can be a width of the patterned conductive layer 40 in a direction along the section line BB'. In some embodiments, a ratio of a width of the air channel to a width of the patterned conductive layer 40 in a direction along the section line BB' is equal to or less than about 0.6. According to some embodiments of the present disclosure, due to the aforementioned design, the supporting legs of the patterned conductive layer 40 can provide sufficient structural support, so the patterned conductive layer 40 with the air cavity 50 formed therein can provide sufficient structural support. stability without collapsing.

FIG. 4A is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. In some embodiments, FIG. 4A is a schematic cross-sectional view along the section line AA' of FIG. 3 .

In some embodiments, the contact structure 60 does not overlap the air channel 54 in a top view. In some embodiments, opening 70A does not overlap air channel 54 in a top view.

FIG. 4B is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. In some embodiments, FIG. 4B is a schematic cross-sectional view along the section line BB' of FIG. 3 .

In some embodiments, the surface 501 (or upper surface) of the air channel 51 is defined by the patterned conductive layer 40 . In some embodiments, the surface 502 (or lower surface) of the air channel 51 is defined by the portion of the surface 301 of the dielectric layer 30 .

FIG. 4C is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. In some embodiments, FIG. 4C is a schematic cross-sectional view along the line CC' of FIG. 3 .

In some embodiments, a portion of dielectric layer 80 is exposed to air cavity 50 . In some embodiments, a portion of dielectric layer 80 is exposed at air channel 51 .

In some embodiments, the end 510 a of the air channel 51 is bounded by a portion of the dielectric layer 80 . In some embodiments, the end 510 a of the air channel 51 is bounded by a portion 80 a of a surface of the dielectric layer 80 . In some embodiments, the end 510 b of the air channel 51 is defined by the seed layer 410 and the conductive layer 420 of the patterned conductive layer 40 .

5A, 5B, 5C, 5D, 5E, 5F, and 5G are schematic cross-sectional views illustrating different stages of the method for manufacturing the semiconductor device 2A according to some embodiments of the present disclosure.

Referring to FIG. 5A , an interconnect structure 20 may be provided, and a dielectric layer 30 may be formed on the interconnect structure 20 . In some embodiments, the interconnect structure 20 is formed on a substrate 10 . In some embodiments, the dielectric layer 30 has one or more openings 60A (or denoted as “through holes”) to expose a portion of the patterned conductive layer 210 . In some embodiments, a dielectric material may be formed on the interconnect structure 20 , and a lithography process may be performed to form the opening 60A through the dielectric material to form the dielectric layer 30 .

Referring to FIG. 5B , a sacrificial material 500A may be formed on the dielectric layer 30 . In some embodiments, a seed layer material 410A is formed on the dielectric layer 30 and in the opening 60A, and a sacrificial material 500A is formed on the seed layer material 410A. In some embodiments, the fabrication technique of the seed layer material 410A may include plating. In some embodiments, the seed layer material 410A is or includes titanium or copper. In some embodiments, the sacrificial material 500A is or includes a photoresist material. In some embodiments, sacrificial material 500A is a positive photoresist.

Referring to FIG. 5C , a pattern 520 (also denoted as “a sacrificial pattern”) can be formed on the dielectric layer 30 . In some embodiments, a sacrificial layer 500 including patterns 510 and 520 is formed on the dielectric layer 30 . In some embodiments, the pattern 510 has a thickness 510T, the pattern 520 (or the sacrificial pattern) has a thickness 520T, and the thickness 520T is smaller than the thickness 510T.

In some embodiments, the pattern 510 of the sacrificial layer 500 defines a predetermined region R1 on the dielectric layer 30, and the predetermined region R1 is predetermined for a patterned conductive layer 40 to be formed in the next step. in. In some embodiments, the pattern 520 completely overlaps the predetermined region R1 defined by the pattern 510 . In some embodiments, the pattern 520 is within the predetermined region R1 defined by the pattern 510 .

In some embodiments, the fabrication technique of the sacrificial layer 500 may include the following steps. In some embodiments, a light mask 600 is disposed on the sacrificial material 500A, and the light mask 600 has a blocking area 601 , an opaque area 602 and a clear area 603 . In some embodiments, the blocking region 601 is configured to block exposure radiation from passing through, the opaque region 602 is configured to allow the exposure laser portion to pass through, and the clear region 603 is configured to allow exposure radiation to pass through. In some embodiments, the blocking region 601 includes or includes a light blocking material or a light absorbing material. In some embodiments, opaque region 602 comprises or includes a material that is substantially opaque to radiation of a predetermined wavelength for exposure. In some embodiments, for example, the material of the opaque region 602 includes chromium or chromium oxide. In some embodiments, clear region 603 comprises or includes a material that is substantially transparent to radiation of a predetermined wavelength for exposure.

In some embodiments, a lithography process is performed on the sacrificial material 500A according to the photomask 600 to form the sacrificial layer 500 including the patterns 510 and 520 . In some embodiments, the pattern 510 is directly formed under the blocking region 601 of the photomask 600 by performing a lithography process. In some embodiments, a portion of the sacrificial material 500A directly under the opaque region 602 of the photomask 600 is partially removed by performing a lithography process to form the pattern 520 directly on the opaque region 602 of the photomask 600 below. In some embodiments, a portion of the sacrificial material 500A directly under the clear region 603 of the photomask 600 is completely removed by performing a lithography process. In some embodiments, a portion of the seed layer material 410A is exposed by the sacrificial layer 500 directly under the clear region 603 of the photomask 600 . In some embodiments, a portion of the seed layer material 410A in the predetermined region R1 is exposed by the sacrificial layer 500 . In some embodiments, pattern 510 is directly connected to pattern 520 .

Referring to FIG. 5D , a patterned conductive layer can be formed on the dielectric layer 30 and the pattern 520 of the sacrificial layer 500 . In some embodiments, a conductive layer 420 is formed on the seed layer material 410A. In some embodiments, the conductive layer 420 is formed in the predetermined region R1. The patterned conductive layer may include a conductive layer 420 and a seed layer material 410A. In some embodiments, the fabrication technique of the conductive layer 420 includes plating. In some embodiments, the conductive layer 420 is not formed on the pattern 510 of the sacrificial layer 500 .

In some embodiments, after the conductive layer 420 (or the patterned conductive layer) is formed on the pattern 520, a portion 520c of the pattern 520 is exposed from the conductive layer 420 (or the patterned conductive layer). In some embodiments, the portion 520c is a side surface of the pattern 520 , which is substantially perpendicular to an upper surface 521 and side surfaces 522 , 523 of the pattern 520 .

Referring to FIG. 5E , the pattern 520 of the sacrificial layer 500 can be removed to form an air cavity 50 in the conductive layer 420 . In some embodiments, the pattern 520 of the sacrificial layer 500 is removed to form an air cavity 50 within the patterned conductive layer (ie, including the conductive layer 420 and the seed layer material 410A). In some embodiments, the pattern 510 of the sacrificial layer 500 is also removed. In some embodiments, the patterns 510 and 520 of the sacrificial layer 500 are removed in the same step. In some embodiments, the conductive layer 420 is exposed to the air cavity 50 . In some embodiments, the patterns 510 and 520 of the sacrificial layer 500 are removed by a photoresist stripping process. In some embodiments, the patterns 510 and 520 of the sacrificial layer 500 are removed by a removing solution.

Referring to FIG. 5F , a portion of the seed layer material 410A exposed from the conductive layer 420 is removed to form a patterned conductive layer 40 including the seed layer 410 and the conductive layer 420 . In some embodiments, the patterned conductive layer 40 is formed in the predetermined region R1.

Referring to FIG. 5G , a dielectric layer 80 may be formed on the patterned conductive layer 40 . In some embodiments, the dielectric layer 80 has one or more openings 70A (also denoted as “through vias”) to expose a portion of the patterned conductive layer 40 . In some embodiments, a dielectric material may be formed on the patterned conductive layer 40 , and a lithography process may be performed to form a plurality of openings 70A through the dielectric material to form the dielectric layer 80 . Thus, the semiconductor element 2A is formed.

According to some embodiments of the present disclosure, by using the photomask 600 to form the sacrificial layer 500 to form the patterned conductive layer 40 and the air cavity 50 in the patterned conductive layer 40, the parasitic capacitance of the formed semiconductor device 2A can be reduced. , without performing additional steps or improving existing steps, for example, without improving the configuration of the patterned conductive layer 210 , the configuration of the patterned conductive layer 40 , the configuration of the contact structure 60 and the like. Therefore, the parasitic capacitance of the formed semiconductor device 2A can be reduced by a relatively simplified manufacturing process, and the cost can also be reduced.

FIG. 6A , FIG. 6B , and FIG. 6C are schematic cross-sectional views illustrating different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

FIG. 6A shows one or more stages of a method of fabricating a semiconductor device along line CC' of FIG. 3 according to some embodiments of the present disclosure.

Referring to FIG. 3 and FIG. 6A , an interconnection structure 20 may be disposed or formed on a substrate 10 , and a dielectric layer 30 may be formed on the interconnection structure 20 .

In some embodiments, a seed layer material 410A is formed on the dielectric layer 30 , and a sacrificial layer 500 including patterns 510 and 520 is formed on the dielectric layer 30 . In some embodiments, the pattern 510 has a thickness 510T, the pattern 520 (or the sacrificial pattern) has a thickness 520T, and the thickness 520T is smaller than the thickness 510T.

In some embodiments, the pattern 510 of the sacrificial layer 500 defines a predetermined region R1 on the dielectric layer 30, and the predetermined region R1 is predetermined for a patterned conductive layer 40 to be formed therein in a subsequent step. . In some embodiments, the pattern 520 completely overlaps the predetermined region R1 defined by the pattern 510 . In some embodiments, the pattern 520 is within the predetermined region R1 defined by the pattern 510 .

In some embodiments, the fabrication technique of the sacrificial layer 500 may include the following steps. In some embodiments, a sacrificial material is formed over the dielectric layer 30 and the seed layer material 410A. In some embodiments, a light mask 600 is disposed on the sacrificial material, and the light mask 600 has a blocking area 601 , an opaque area 602 and a clear area 603 . In some embodiments, the blocking region 601 is configured to block exposure radiation from passing through, the opaque region 602 is configured to allow the exposure laser portion to pass through, and the clear region 603 is configured to allow exposure radiation to pass through. In some embodiments, the blocking region 601 includes or includes a light blocking material or a light absorbing material. In some embodiments, opaque region 602 comprises or includes a material that is substantially opaque to radiation of a predetermined wavelength for exposure. In some embodiments, for example, the material of the opaque region 602 includes chromium or chromium oxide. In some embodiments, clear region 603 comprises or includes a material that is substantially transparent to radiation of a predetermined wavelength for exposure.

In some embodiments, a lithography process is performed on the sacrificial material according to the photomask 600 to form the sacrificial layer 500 including the patterns 510 and 520 . In some embodiments, the pattern 510 is directly formed under the blocking region 601 of the photomask 600 by performing a lithography process. In some embodiments, a portion of the sacrificial material 500A directly under the opaque region 602 of the photomask 600 is partially removed by performing a lithography process to form the pattern 520 directly on the opaque region 602 of the photomask 600 below. In some embodiments, a portion of the sacrificial material directly below the clear region 603 of the photomask 600 is completely removed by performing a lithography process. In some embodiments, a portion of the seed layer material 410A is exposed by the sacrificial layer 500 directly under the clear region 603 of the photomask 600 . In some embodiments, a portion of the seed layer material 410A in the predetermined region R1 is exposed by the sacrificial layer 500 . In some embodiments, pattern 510 is directly connected to pattern 520 .

FIG. 6B shows one or more stages of a method of fabricating a semiconductor device along line CC' of FIG. 3 according to some embodiments of the present disclosure.

Referring to FIG. 3 and FIG. 6B , a conductive layer 420 may be formed on the seed layer material 410A and the pattern 520 of the sacrificial layer 500 . In some embodiments, the conductive layer 420 is formed in the predetermined region R1. In some embodiments, the fabrication technique of the conductive layer 420 includes plating. In some embodiments, the conductive layer 420 is not formed on the pattern 510 of the sacrificial layer 500 .

In some embodiments, a portion 520 of the pattern 520 is exposed from the conductive layer 420 after the conductive layer 420 is formed on the pattern 520 . In some embodiments, the portion 520c is directly connected to the pattern 510 .

FIG. 6C shows one or more stages of a method of fabricating a semiconductor device along line CC' of FIG. 3 according to some embodiments of the present disclosure.

Referring to FIG. 3 and FIG. 6C , the pattern 520 of the sacrificial layer 500 can be removed to form an air cavity 50 in the conductive layer 420 . In some embodiments, the pattern 510 of the sacrificial layer 500 is also removed. In some embodiments, the patterns 510 and 520 of the sacrificial layer 500 are removed in the same step. In some embodiments, the conductive layer 420 is exposed to the air cavity 50 . In some embodiments, the patterns 510 and 520 of the sacrificial layer 500 are removed by a photoresist stripping process. The patterns 510 and 520 of the sacrificial layer 500 are removed by a removal solution.

In some embodiments, a portion of the seed layer material 410A exposed from the conductive layer 420 may be removed to form a patterned conductive layer 40 including the seed layer 410 and the conductive layer 420 . In some embodiments, the patterned conductive layer 40 is formed in the predetermined region R1. In some embodiments, an air cavity 50 is formed within the patterned conductive layer 40 .

Next, please refer to FIG. 3 and FIG. 4C , a dielectric layer 80 may be formed on the patterned conductive layer 40 . Thus, the semiconductor device 3 as shown in FIG. 4C is formed.

FIG. 7 is a schematic flowchart illustrating a method 700 for fabricating a semiconductor device according to some embodiments of the present disclosure.

The manufacturing method 700 starts with step S71, which is to provide an interconnection structure.

Fabrication method 700 continues with step S72, which is a first dielectric layer is formed on the interconnect structure.

The fabrication method 700 continues with step S73, which is a sacrificial pattern formed on the first dielectric layer.

The fabrication method 700 continues with step S74, which is a redistribution layer formed on the first dielectric layer and the sacrificial pattern.

The fabrication method 700 continues with step S75, which is to remove the sacrificial pattern to form an air cavity in the RDL.

The preparation method 700 is just an example, and is not intended to limit the present disclosure beyond what is clearly stated in the scope of the application. Additional steps may be provided before, during, or after each step of manufacturing method 700, and some of the steps described may be replaced, eliminated, or moved for such additional embodiments of the manufacturing method. In some embodiments, the preparation method 700 may further include some steps not described in FIG. 7 . In some embodiments, preparation method 700 may include one or more steps described in FIG. 7 .

FIG. 8 is a schematic flow diagram illustrating a method 800 for fabricating a semiconductor device according to some embodiments of the present disclosure.

The manufacturing method 800 starts with step S81, which is to form a first patterned conductive layer on a substrate.

The manufacturing method 800 continues with step S82, which is a first dielectric layer is formed on the first patterned conductive layer.

The manufacturing method 800 continues with step S83, which is a second patterned conductive layer formed on the first dielectric layer.

The manufacturing method 800 continues with step S84, which is an air cavity formed between the first patterned conductive layer and the second patterned conductive layer.

The preparation method 800 is just an example, and is not intended to limit the present disclosure beyond what is clearly stated in the scope of the application. Additional steps may be provided before, during, or after each step of manufacturing method 800, and some of the steps described may be replaced, eliminated, or moved for such additional embodiments of the manufacturing method. In some embodiments, the preparation method 800 may further include some steps not described in FIG. 8 . In some embodiments, preparation method 800 may include one or more steps described in FIG. 8 .

An embodiment of the present disclosure provides a semiconductor device. The semiconductor element includes a base, a first patterned conductive layer, a first dielectric layer and a second patterned conductive layer. The first patterned conductive layer is disposed on the base. The first dielectric layer is disposed on the first patterned conductive layer. The second patterned conductive layer is disposed on the first dielectric layer. The semiconductor element has an air cavity between the first patterned conductive layer and the second patterned conductive layer.

Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an interconnection structure, a first dielectric layer and a redistribution layer (RDL). The interconnect structure includes an upper patterned conductive layer. The first dielectric layer is disposed on the upper patterned conductive layer. The redistribution layer is disposed on the first dielectric layer. The semiconductor device has an air cavity between the redistribution layer and the interconnect structure.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The manufacturing method includes providing an interconnection structure. The fabrication method also includes forming a first dielectric layer on the interconnection structure. The manufacturing method also includes forming a sacrificial pattern on the first dielectric layer. The manufacturing method also includes forming a redistribution layer on the first dielectric layer and the sacrificial pattern. The manufacturing method further includes removing the sacrificial pattern to form an air cavity in the redistribution layer.

In the semiconductor element, due to the design of the air cavity, the parasitic capacitance generated by the interconnection structure, the dielectric layer and the patterned conductive layer (or RDL) can be significantly reduced, thereby improving the operation of the semiconductor element efficacy.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included in the patent scope of this application.

1: Semiconductor components

2A: Semiconductor components

2B: Semiconductor components

3: Semiconductor components

10: Base

20:Interconnect structure

30: Dielectric layer

40: Patterned conductive layer

50: air cavity

51: Air channel

52:Air channel

53:Air channel

54:Air channel

60: Contact structure

60A: Opening

70:Contact structure

70A: Opening

80:Dielectric layer

80a: part

90: Conductive layer

101: surface

110: conductive pad

210: patterned conductive layer

210a: connection part

210b: Wiring Department

220: patterned conductive layer

230: Conductive vias

240: Conductive Via

250: dielectric layer

301: surface

301a: part

402: surface

410: Seed layer

410a: surface

410A: Seed layer material

420: conductive layer

420a: surface

500: sacrificial layer

500A: sacrificial material

501: surface

502: surface

510: pattern

510a: terminal

510b: end

510T: Thickness

520: pattern

520a: end

520b: end

520c: part

520T: Thickness

521: upper surface

522: side surface

523: side surface

530a: end

530b: end

540a: end

540b: end

600: light mask

601: blocking area

602: Opaque area

603: clear area

610: Seed layer

620: conductive layer

700: Preparation method

800: Preparation method

910: Seed layer

920: conductive layer

H1: height

R1: reservation area

S71: Steps

S72: step

S73: step

S74: step

S75: Steps

S81: step

S82: step

S83: step

S84: step

T1: Thickness

A more complete understanding of the present disclosure can be obtained by reference to the detailed description and claims. The disclosure should also be understood in association with drawing element numbers that represent like elements throughout the description. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2A is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2B is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a schematic top view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 4A is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 4B is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 4C is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 5A is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 5B is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 5C is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 5D is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 5E is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 5F is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 5G is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 6A is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 6B is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 6C is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 6D is a schematic cross-sectional view illustrating a stage of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 7 is a schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 8 is a schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure.

1: Semiconductor components

10: Base

20:Interconnect structure

30: Dielectric layer

40: Patterned conductive layer

50: air cavity

60: Contact structure

101: surface

110: conductive pad

210: patterned conductive layer

210a: connection part

210b: Wiring Department

220: patterned conductive layer

230: Conductive vias

240: Conductive Via

250: dielectric layer

301: surface

301a: part

402: surface

501: surface

502: surface

H1: height

T1: Thickness

Claims (18)

A semiconductor element, comprising: a substrate; a first patterned conductive layer disposed on the substrate; a first dielectric layer disposed on the first patterned conductive layer; and a second patterned conductive layer, disposed on the first dielectric layer; wherein the semiconductor element has an air cavity between the first patterned conductive layer and the second patterned conductive layer; wherein the second patterned conductive layer includes a seed layer, A portion of the seed layer is exposed to the air cavity. The semiconductor device as claimed in claim 1, wherein the air cavity is disposed between the second patterned conductive layer and the first dielectric layer. The semiconductor device as claimed in claim 1, wherein the air cavity is disposed in the second patterned conductive layer. The semiconductor device as claimed in claim 3, wherein a part of the first dielectric layer is exposed in the air cavity. The semiconductor device according to claim 1, further comprising a first contact structure electrically connecting the first patterned conductive layer and the second patterned conductive layer, wherein in a top view, the first contact The structure does not overlap the air cavity. The semiconductor device according to claim 5, further comprising a second contact structure disposed on the second patterned conductive layer, wherein the second contact structure does not overlap with the air cavity in a top view. The semiconductor device as claimed in claim 1, further comprising a second dielectric layer disposed on the second patterned conductive layer, wherein a part of the second dielectric layer is exposed to the air cavity. The semiconductor device as claimed in claim 1, wherein the air cavity includes an air channel extending in the second patterned conductive layer. The semiconductor device as claimed in claim 1, wherein: the air cavity includes a first air channel and a second air channel, and the second air channel is aligned with the first air channel; and the first air channel and the The second air channels are connected to each other and extend in the second patterned conductive layer. A semiconductor element, comprising: an interconnection structure including an upper patterned conductive layer; a first dielectric layer disposed on the upper patterned conductive layer; and a redistribution layer disposed on the first dielectric layer ; wherein the semiconductor element has an air cavity between the redistribution layer and the interconnect structure; Wherein the air cavity is defined by the redistribution layer and an upper surface of the first dielectric layer. The semiconductor device as claimed in claim 10, wherein the air cavity is disposed in the redistribution layer. The semiconductor device of claim 11, wherein a ratio of a height of the air cavity to a height of the redistribution layer is from about 0.25 to about 0.5. The semiconductor device as claimed in claim 10, wherein the lower surface of the air cavity and the lower surface of the redistribution layer are substantially at the same height. The semiconductor device as claimed in claim 10, wherein the air cavity is disposed between the redistribution layer and the first dielectric layer. The semiconductor device according to claim 10, further comprising a first contact structure electrically connecting the interconnection structure and the redistribution layer, wherein the first contact structure does not overlap with the air cavity in a top view. The semiconductor device as claimed in claim 15, further comprising: a second dielectric layer disposed on the redistribution layer; and a second contact structure electrically connected to the redistribution layer and passing through the second dielectric layer The electrical layer, wherein the second contact structure does not overlap the air cavity in a top view. The semiconductor device as claimed in claim 10, wherein the air cavity includes an air passage, and the Extension within the redistribution layer. The semiconductor device as claimed in claim 17, further comprising a second dielectric layer covering the redistribution layer, wherein the air channel has a first end, and the first end is formed by the second defined by a portion of the dielectric layer.

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