TWI793818B - Chip testing board and testing method and system thereof - Google Patents

Abstract

A chip testing board is disclosed. The chip testing board configured to test a chip by using a main signal and a second signal, comprises: a body having a plurality of through holes connected with two sides of the body; a chip test area arranged on a side of the body; and a main signal connector arranged on the same side of the body for connecting the chip test area without passing through the through holes; wherein the chip test area is used to connect the chip and test at least one main signal of the chip through the main signal connector

Description

Wafer test board and its test method and system

The present disclosure relates to a wafer test board and its testing method and system.

Existing LCD mobile phone display driver chips, or display screens for wearable watches, and large-size TV display driver chips, these design factories and test factories test the single chip (display driver chip) in order to test the electrical properties of the single chip or For analysis, it will be pulled from the output terminal or input terminal on the chip to the test point of the chip test board through the way of pulling wires, and connected to the user's test environment through the vias (Via) around the test board. , so when the signal is transmitted, such a via design will have capacitive and inductive effects on the signal, which will affect the integrity of the high-speed signal. Furthermore, the COB (chip on board) design of the existing driver IC chip is all for the convenience of commonality and simple design and convenient use. However, with the evolution of the times, the chip signal speed of the driver IC is getting faster and faster. The traditional COB test The application can no longer meet the conditions for testing signal integrity.

Therefore, this disclosure proposes a chip test board and its testing method and system to solve the problem of capacitive and inductive interference due to the use of via testing when testing high-speed signals on chips, which affects the integrity of high-speed signals. sex issue.

An embodiment of the present disclosure provides a chip test board for testing a chip according to a main signal and a secondary signal, comprising: a body with a plurality of through holes connecting two sides of the body; a chip test area set on one side of the body ; and the main signal connector, which is arranged on the same side of the body, is used to connect the chip test area without going through the through holes; wherein, the chip test area is used to connect the chip, and perform at least one operation on the chip through the main signal connector. Main signal test.

An embodiment of the present disclosure provides a chip test system, including: a chip test board; a chip set in a chip test area; a main signal test platform for providing a main signal; and a secondary signal test platform for providing a secondary signal , wherein the chip test board is used to test the chip according to the main signal and the secondary signal, including: a body with a plurality of through holes connecting the two sides of the body; a chip test area set on one side of the body; and a main signal connector, It is arranged on the same side of the main body, and is used for connecting the chip test area without passing through holes; wherein, the chip test area is used for connecting the chip, and testing the chip for at least one main signal through the main signal connector.

An embodiment of the present disclosure provides a chip testing method, comprising the following steps: providing a chip test board; setting the chip in the chip test area; and performing at least one main signal test on the chip through the main signal connector, wherein the chip The test board is used to test the chip according to the main signal and the secondary signal, including: the main body, which has a plurality of through holes connecting the two sides of the main body; the chip test area, which is set on one side of the main body; and the main signal connector, which is set on the main body The same side is used for connecting the chip testing area without passing through holes; wherein, the chip testing area is used for connecting the chip, and testing the chip for at least one main signal through the main signal connector.

In order to further understand the features and technical content of the disclosure, please refer to the following detailed description and drawings related to the disclosure. However, the provided drawings are only for reference and illustration, and are not intended to limit the disclosure.

FIG. 1 shows a wafer test board according to an embodiment of the present disclosure. As shown in FIG. 1 , the chip test board 1 of the present disclosure is used to test the chip 13 according to the main signal and the secondary signal. The chip test board 1 includes: a body 10 with a plurality of through holes 101 connected to two sides of the body 10; The chip test area 11 is arranged on one side of the body 10; and the main signal connector 12 is arranged on the same side of the body 10, and is used to connect the chip test area 11 without passing through the through holes 101; wherein, the chip test area 11 is used to connect the chip 13, and perform at least one main signal test on the chip 13 through the main signal connector 12. In particular, the chip test area 11 receives the main signal through the main signal connector 12 and transmits it to the chip 13 , and the chip 13 generates a feedback signal in response to the main signal and outputs it through the main signal connector 12 to perform the main signal test on the chip 13 . In addition, the wafer test area 11 receives the secondary signal through the plurality of through holes 101 and transmits it to the chip 13 . The chip 13 generates a response signal in response to the secondary signal and outputs it through the through hole 101 to perform the secondary signal test on the chip 13 .

The wafer test area 11 of the present disclosure includes: a plurality of test points 111 arranged on the first surface 1a of the wafer test board 1, and the plurality of test points are distributed and arranged around the periphery of the wafer 13 test area 11; a plurality of test needles 112 are arranged on the wafer On the second surface 1 b of the test board 1 , the plurality of test pins 112 are respectively connected to the test points 111 ; wherein, the through holes 101 are respectively connected between the test pins 112 and the test points 111 . In addition, the wafer test area 11 receives secondary signals through the plurality of test needles 112, the plurality of through holes 101 and the plurality of test points 111 and transmits them to the chip 13; 101 and a plurality of test points 111 are output to perform a secondary signal test on the chip 13 . In particular, the transmission rate of the main signal is greater than 100 Mbps (100 Mbps), for example, network transmission signal, data transmission signal or other signals with high speed or high frequency. Secondary signals with transmission rates below 100 Mbps, for example, other low-speed or low-frequency signals such as power signals.

FIG. 2 shows a wafer testing system according to an embodiment of the present disclosure. Please refer to FIG. 1 at the same time, the chip test system 2 of the present disclosure includes: a chip 13 is arranged in the chip test area 11; a main signal test platform 14 is used to provide the main signal; and a secondary signal test platform 15 is used to provide the secondary signal . The chip test system 2 also includes: a chip test board 1, and the chip test board 1 includes: a body 10 with a plurality of through holes 101 connected to two sides of the body 10; a chip test area 11 arranged on one side of the body 10; and main signal The connector 12 is arranged on the same side of the body 10, and is used to connect the chip test area 11 without passing through the through holes 101; wherein, the chip test area 11 is used to connect the chip 13, and the chip 13 is connected to the chip 13 through the main signal connector 12. Perform at least one major signal test. In particular, the chip test area 11 receives the main signal through the main signal connector 12 and transmits it to the chip 13 , and the chip 13 generates a feedback signal in response to the main signal and outputs it through the main signal connector 12 to perform the main signal test on the chip 13 . In addition, the wafer test area 11 receives the secondary signal through the plurality of through holes 101 and transmits it to the chip 13 . The chip 13 generates a response signal in response to the secondary signal and outputs it through the through hole 101 to perform the secondary signal test on the chip 13 .

The wafer test area 11 of the present disclosure includes: a plurality of test points 111 arranged on the first surface 1a of the wafer test board 1, and the plurality of test points are distributed and arranged around the periphery of the wafer 13 test area 11; a plurality of test needles 112 are arranged on the wafer On the second surface 1 b of the test board 1 , the plurality of test pins 112 are respectively connected to the test points 111 ; wherein, the through holes 101 are respectively connected between the test pins 112 and the test points 111 . In addition, the wafer test area 11 receives secondary signals through the plurality of test needles 112, the plurality of through holes 101 and the plurality of test points 111 and transmits them to the chip 13; 101 and a plurality of test points 111 are output to perform a secondary signal test on the chip 13 . In particular, the transmission rate of the main signal is greater than 100 Mbps (100 Mbps), for example, network transmission signal, data transmission signal or other signals with high speed or high frequency. Secondary signals with transmission rates below 100 Mbps, for example, other low-speed or low-frequency signals such as power signals.

FIG. 3 shows a block diagram of a secondary signal test according to an embodiment of the disclosure. As shown in Figure 3, when the chip 13 is connected with the multi-point test point 111 and the secondary signal test is carried out, the secondary signal test platform 15 can be transmitted to the chip 13 by the test pin, and when the chip 13 receives the secondary signal, it will generate The response signal is transmitted to the secondary test platform 15 through the test pin 112 to perform a secondary signal test on the chip 13 . FIG. 4 shows a block diagram of a secondary signal test according to another embodiment of the disclosure. As shown in Figure 4, when the chip is not connected to multiple test points and the secondary signal test is performed, the transmission line L can be connected to the secondary test platform 15 through the through hole 101 or other through holes 113, and the secondary signal test platform 15 It can be transmitted to the chip 13 by the connection line L passing through the through hole 101 or other through holes 113, and when the chip 13 receives the secondary signal, it will generate a response signal and transmit it to the secondary signal through the connection line L of the through hole 101 or other through holes 113. The test platform 15 is used to test the secondary signal of the chip 13 .

FIG. 5 shows a diagram of an integrated signal test platform according to an embodiment of the present disclosure. As shown in Figure 5, the main signal is generated by the integrated signal test platform 141, and transmitted to the chip 13 through the integrated signal test platform 141, when the chip 13 receives the main signal, it will generate a feedback signal and transmit it to the chip 13 through the main signal connector 12. The integrated signal test platform 141 is used to perform main signal test on the chip 13 . The secondary signal is also generated by the integrated signal test platform 141 and transmitted to the chip 13 through the through hole 113 or a plurality of test pins 112. When the chip 13 receives the secondary signal, it will generate a response signal and pass through the through hole 101 or other through holes 113 Or the plurality of test pins 112 are transmitted to the integrated signal test platform 141 to perform secondary signal test on the chip 13 . In particular, the transmission rate of the main signal is greater than 100 megabits per second (100Mbps), such as network transmission signals, data transmission signals or other signals with high speed or high frequency. Secondary signals with transmission rates below 100 Mbps, for example, other low-speed or low-frequency signals such as power signals. In addition, please refer to FIG. 5 and FIG. 3 , when the chip 13 is connected to the multi-point test point 111 and the secondary signal test is performed, the integrated signal test platform 141 can be transmitted to the chip 13 by the test pin, and when the chip 13 receives the secondary signal , a response signal will be generated and transmitted to the integrated signal test platform 141 through the test pin 112 to perform a secondary signal test on the chip 13 . Or, please refer to FIG. 5 and FIG. 4 at the same time. When the chip 13 is not connected to the multi-point test point 111 and the secondary signal test is performed, the transmission line L can be connected to the secondary integrated signal through the through hole 101 or other through holes 113. The test platform 141 and the secondary signal test platform 15 can be transmitted to the chip 13 by the connection line L passing through the through hole 101 or other through holes 113, and when the chip 13 receives the secondary signal, it will generate a response signal and pass through the through hole 101 or other through holes. The connection line L of the hole 113 is transmitted to the integrated signal testing platform 141 to perform secondary signal testing on the chip 13 .

FIG. 6 shows a flowchart of a wafer testing method according to an embodiment of the present disclosure. As shown in Figure 6, and referring to Figure 1 at the same time, the wafer testing method of the present disclosure includes the following steps: providing a wafer testing board 1 (S601); setting the wafer 13 in the wafer testing area 11 (S602); and passing the main signal connector 12 Perform at least one major signal test on the chip 13 (S603). The aforementioned chip test board 1 includes: a body 10, which has a plurality of through holes 101 connected to two sides of the body 10; a chip test area 11, which is arranged on one side of the body 10; and a main signal connector 12, which is arranged on the same side of the body 10 , for connecting the chip test area 11 without passing through the through holes 101 ; wherein, the chip test area 11 is used for connecting the chip 13 , and performing at least one main signal test on the chip 13 through the main signal connector 12 . In particular, the chip test area 11 receives the main signal through the main signal connector 12 and transmits it to the chip 13 , and the chip 13 generates a feedback signal in response to the main signal and outputs it through the main signal connector 12 to perform the main signal test on the chip 13 . In addition, the wafer test area 11 receives the secondary signal through the plurality of through holes 101 and transmits it to the chip 13 . The chip 13 generates a response signal in response to the secondary signal and outputs it through the through hole 101 to perform the secondary signal test on the chip 13 .

In particular, the main signal testing step includes the following steps: generating the main signal from the main signal testing platform 14; transmitting the main signal to the chip 13 through the main signal connector 12; generating a feedback signal when the chip 13 responds to the main signal; and connecting the main signal through the main signal The device 12 transmits the feedback signal to the main signal test platform 14 . In addition, the chip testing method of the present disclosure further includes a secondary signal testing step, including the following steps: generating secondary signals from the secondary signal testing platform 15; transmitting the secondary signals to the chip 13 through the through holes 101; responding with the chip 13 A response signal is generated during the secondary signal; and the feedback signal is transmitted to the primary signal testing platform 14 through the through holes 101 .

The wafer test area 11 of the present disclosure also includes: a plurality of test points 111 arranged on the first surface 1a of the wafer test board 1, and the plurality of test points are distributed and arranged around the periphery of the wafer 13 test area 11; a plurality of test needles 112 are arranged on On the second surface 1b of the wafer test board 1 , the plurality of test pins 112 are respectively connected to the test points 111 ; wherein the through holes 101 are respectively connected between the test pins 112 and the test points 111 . In addition, the wafer test area 11 receives secondary signals through the plurality of test needles 112, the plurality of through holes 101 and the plurality of test points 111 and transmits them to the chip 13; 101 and a plurality of test points 111 are output to perform a secondary signal test on the chip 13 . In particular, the transmission rate of the main signal is greater than 100 Mbps (100 Mbps), for example, network transmission signal, data transmission signal or other signals with high speed or high frequency. Secondary signals with transmission rates below 100 Mbps, for example, other low-speed or low-frequency signals such as power signals.

The chip test board and its test method disclosed in this disclosure are designed for the high-speed signal application of the test board in the prior art. The through hole itself has parasitic capacitance and inductance to the ground. The main impact of the parasitic capacitance and inductance of the via hole on the circuit is The rise time of the signal is prolonged, reducing the speed of the circuit and the integrity of the high-speed signal. Therefore, the chip test board and testing method disclosed herein do not use via design for main signals, and directly connect the high-speed signals through high-speed connectors to maintain the integrity of the high-speed signals.

The present disclosure has been described by the above-mentioned related embodiments, but the above-mentioned embodiments are only examples for implementing the present disclosure. It must be pointed out that the disclosed embodiments do not limit the scope of this disclosure. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the patent claims are included in the scope of the present disclosure.

1: Test board 11: Testing area 12: Connector 13: Wafer 101: Through hole 111: Test point 112: Test needle 113: through hole 1a, 1b: surface 14, 15, 141: Test platform S601, S602, S603: steps

FIG. 1 shows a wafer test board according to an embodiment of the present disclosure.

FIG. 2 shows a wafer testing system according to an embodiment of the present disclosure.

FIG. 3 shows a block diagram of a secondary signal test according to an embodiment of the disclosure.

FIG. 4 shows a block diagram of a secondary signal test according to another embodiment of the disclosure.

FIG. 5 shows a diagram of an integrated signal test platform according to an embodiment of the present disclosure.

FIG. 6 shows a flowchart of a wafer testing method according to an embodiment of the present disclosure.

1: Test board

11: Testing area

12: Connector

13: Wafer

101: Through hole

111: Test point

112: Test needle

113: through hole

1a, 1b: surface

Claims (8)

A chip test board is used to test a chip according to a main signal and a secondary signal, comprising: a body with a plurality of through holes connecting two sides of the body; a chip test area set on one side of the body; and A main signal connector, arranged on the same side of the body, is used to connect the chip test area without going through the through holes; wherein, the chip test area is used to connect the chip, and the chip test area passes the main signal The connector receives the main signal and transmits it to the chip, and the main signal connector transmits the main signal to the chip without passing through the through holes; wherein the chip generates a feedback signal in response to the main signal and passes through the main signal connector output to perform the main signal test on the chip, and the main signal connector does not transmit the feedback signal generated by the chip after receiving the main signal through the through holes. The chip test board as described in claim 1, wherein the chip test area receives the secondary signal through the plurality of through holes and transmits it to the chip, and the chip generates a response signal in response to the secondary signal and outputs it through the through hole to perform the secondary signal test on the chip. The wafer test board as claimed in claim 1, wherein the wafer test area includes: a plurality of test points arranged on a first surface of the wafer test board, and the plurality of test points are distributed and arranged around the periphery of the wafer test area A plurality of test pins are arranged on a second surface of the chip test board, and the plurality of test pins are respectively connected to the test points; wherein, the through holes are respectively connected between the test pins and the test points . The chip test board as described in claim 3, wherein the chip test area receives the secondary signal through the plurality of test needles, the plurality of through holes and the plurality of test points and transmits it to the chip; the chip responds to the secondary signal A response signal is generated and output through the plurality of test needles, the plurality of through holes and the plurality of test points to perform the secondary signal test on the chip. The wafer test board as described in any one of claim 1 to claim 4, wherein the transmission rate of the primary signal is greater than 100 Mbps, and the transmission rate of the secondary signal is lower than 100 Mbps per second (100Mbps). A chip test system, comprising: a chip test board as described in any one of claim 1 to claim 5; a chip set in the chip test area; a main signal test platform for providing the main signal; and a The primary signal test platform is used to provide the secondary signal. A chip testing method, comprising the following steps: providing a chip test board as described in any one of claim 1 to claim 5; setting the chip in the chip test area; and performing at least one test on the chip through the main signal connector The main signal test, wherein the main signal test includes the following steps: generating the main signal by a main signal test platform; transmitting the main signal to the chip through the main signal connector, and the main signal connector does not pass through the through holes transmitting the primary signal to the chip; generating the feedback signal with the chip in response to the primary signal; and The feedback signal is transmitted to the main signal testing platform through the main signal connector, and the main signal connector does not transmit the feedback signal generated by the chip after receiving the main signal through the through holes. The chip testing method as described in claim 7, further comprising a secondary signal testing step, including the following steps: generating the secondary signal by a secondary signal testing platform; transmitting the secondary signal to the chip through the transmission lines of the through holes ; generate a response signal when the chip responds to the secondary signal; and transmit the response signal to the secondary signal testing platform through the transmission lines of the through holes.

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