TWI782378B - memory device - Google Patents

Abstract

The memory device of the present invention includes: a memory cell array, which stores data; a control circuit, which responds to commands to control the memory cell array; and a receiver, which is based on the first signal, the second signal, or the operation result of the address and the command And become activated state, and can receive instruction or data.

Description

memory device

The embodiment relates to a memory device.

As a memory device, a NAND (Not-AND: Inverted And) type flash memory is known.

The memory device of the embodiment includes: a memory cell array, which stores data; a control circuit, which responds to commands to control the memory cell array; and a receiver, which is based on the first signal, the second signal, or the operation result of the address and the command And become activated state, and can receive instruction or data.

01h: write command

05h: read command

1: Memory system

10: NAND flash memory

11a: PMOS transistor

11b: NMOS transistor

11c~11f: PMOS transistor

11g~11i: NMOS transistor

20: Memory controller

30: host machine

80h: write command

100:LUN

101: Input and output interface

101a: AND operation circuit

101b: OR operation circuit

101c: NAND operation circuit

101d: Inverter

101g: NAND operation circuit

101g1: NAND operation circuit

101h: NAND operation circuit

101i: NAND operation circuit

101j: OR operation circuit

101k: NAND operation circuit

101l: NAND operation circuit

101m: NAND operation circuit

101n: inverter

101o: AND operation circuit

101p:OR operation circuit

101q: switch circuit

101r: switch circuit

101s: OR operation circuit

101t: switch circuit

101u: switch circuit

101v: 1st receiver

101w: The second receiver

102: Control signal input interface

103: Control circuit

104: instruction register

104a: memory department

105: Address register

105a: memory department

106: Status register

110: memory cell array

111: sense amplifier

112: data register

113: row decoder

114: line buffer

115: column address decoder

116: column address buffer decoder

120: Receiver

130: Transmitter

210: host interface (host I/F)

220: built-in memory (RAM)

230: Processor (CPU)

240: buffer memory

250: NAND interface (NAND I/F)

ADD: address

ALE: address latch enable signal

BCE: chip enable signal

BDQS: data strobe signal

BRE: read enable signal

BWE: write enable signal

BWP: write protection signal

C1: row address

C2: row address

CLE: command latch enable signal

CMD: command

D0~Dn: write data

DQ: Input and output signals

DQ0~DQ7: Input and output signals

DQS: data strobe signal

E0h: instruction

EFh: instruction

ENBn: signal

EN:Signal

FFh: initialization command

GP0: memory group

GP1: memory group

IREFN: reference voltage

MS: signal

N1~N7: nodes

NP:signal

R1~R3: column address

RE: read enable signal

RY/BBY: Ready. busy signal

T0~T29: time

t _CALS : period

VDD: power supply voltage

VREF: reference voltage

W-B0~W-B3: Information

XXh: instruction

YYh: instruction

^~ ALE: reversal signal

^~ BCE: reverse signal

^~ BWE: reverse signal

^~ BWP: reverse signal

^~ CLE: reverse signal

Fig. 1 is a block diagram of the memory system of the first embodiment.

Fig. 2 is a block diagram of the LUN of the memory system of the first embodiment.

Fig. 3 is a circuit diagram of the input/output interface of the memory system of the first embodiment.

Fig. 4 is a schematic diagram of the operation of the memory system of the first embodiment.

Fig. 5 is a timing chart showing an example of a write operation in the memory system of the first embodiment.

Fig. 6 is a timing chart showing an example of the read operation of the memory system of the first embodiment.

Fig. 7 is a circuit diagram of the input-output interface of the memory system of the second embodiment.

Fig. 8 is a timing chart showing an example of a write operation in the memory system of the second embodiment.

Fig. 9 is a timing chart showing an example of a write operation in the memory system of the second embodiment.

Fig. 10 is a timing chart showing an example of a write operation in the memory system of the second embodiment.

Fig. 11 is a timing chart showing an example of the read operation of the memory system of the second embodiment.

Fig. 12 is a timing chart showing an example of the read operation of the memory system according to the second embodiment.

Fig. 13 is a timing chart showing an example of the read operation of the memory system according to the second embodiment.

Fig. 14 is a timing chart showing an example of the read operation of the memory system of the second embodiment.

Fig. 15 is a timing chart showing an example of a write operation in the memory system according to Variation 1 of the second embodiment.

Fig. 16 is a timing chart showing an example of a read operation of the memory system according to Variation 1 of the second embodiment.

Fig. 17 is a circuit diagram of the input/output interface of the memory system according to Variation 2 of the second embodiment.

Fig. 18 is a circuit diagram of the input/output interface of the memory system of the third embodiment.

Fig. 19 is a timing chart showing an example of a write operation in the memory system of the third embodiment.

Fig. 20 is a timing chart showing an example of a write operation in the memory system of the third embodiment.

Fig. 21 is a timing chart showing an example of a write operation in the memory system of the third embodiment.

Fig. 22 is a timing chart showing an example of the read operation of the memory system according to the third embodiment.

Fig. 23 is a timing chart showing an example of the read operation of the memory system according to the third embodiment.

Fig. 24 is a timing chart showing an example of the read operation of the memory system according to the third embodiment.

Fig. 25 is a timing chart showing an example of the read operation of the memory system according to the third embodiment.

Fig. 26 is a timing chart showing an example of a write operation in the memory system of the third embodiment.

Fig. 27 is a timing chart showing an example of the read operation of the memory system according to the third embodiment.

Fig. 28 is a circuit diagram of the input/output interface of the memory system according to the variation of the third embodiment.

Fig. 29 is a circuit diagram of the input/output interface of the memory system of the fourth embodiment.

Fig. 30 is a diagram showing the mode selection operation of the memory system of the fourth embodiment.

Fig. 31 is a circuit diagram of the input/output interface of the memory system of the first modification of the fourth embodiment.

Fig. 32 is a circuit diagram of the input/output interface of the memory system of the second modification of the fourth embodiment.

Fig. 33 is a circuit diagram of the input/output interface of the memory system according to Variation 3 of the fourth embodiment.

Fig. 34 is a circuit diagram of the input/output interface of the memory system of the fifth embodiment.

Fig. 35 is a timing chart showing an example of a write operation in the memory system of the fifth embodiment.

Fig. 36 is a timing chart showing an example of a write operation in the memory system of the fifth embodiment.

Fig. 37 is a timing chart showing an example of a write operation in the memory system of the fifth embodiment.

Fig. 38 is a timing chart showing an example of the read operation of the memory system according to the fifth embodiment.

Fig. 39 is a timing chart showing an example of the read operation of the memory system according to the fifth embodiment.

Fig. 40 is a timing chart showing an example of the read operation of the memory system according to the fifth embodiment.

Fig. 41 is a timing chart showing an example of the read operation of the memory system according to the fifth embodiment.

Fig. 42 is a timing chart showing an example of a write operation in the memory system according to a modification of the fifth embodiment.

Fig. 43 is a timing chart showing an example of a write operation in the memory system according to a modified example of the fifth embodiment.

Fig. 44 is a timing chart showing an example of a write operation in the memory system according to a modified example of the fifth embodiment.

Fig. 45 is a timing chart showing an example of the read operation of the memory system according to the modified example of the fifth embodiment.

Fig. 46 shows the timing sequence of the example of the read operation of the memory system in the modification example of the fifth embodiment picture.

Fig. 47 is a timing chart showing an example of the read operation of the memory system according to the modified example of the fifth embodiment.

Fig. 48 is a timing chart showing an example of the read operation of the memory system according to the modified example of the fifth embodiment.

Fig. 49 is a circuit diagram of the input/output interface of the memory system of the sixth embodiment.

Fig. 50 is a circuit diagram showing a receiver of the memory system according to the seventh embodiment.

Fig. 51 is a circuit diagram showing the first receiver of the memory system according to the seventh embodiment.

Fig. 52 is a circuit diagram showing the second receiver of the memory system according to the seventh embodiment.

Fig. 53 is a diagram showing operating conditions of the memory system in the first to fifth embodiments.

Hereinafter, embodiments will be described with reference to the drawings. In the above description, common reference signs are attached to common parts throughout the entire drawings.

<1> First Embodiment

The semiconductor memory device of the first embodiment will be described. In the following, as a semiconductor memory device, a NAND type flash memory is taken as an example for description.

<1-1> Composition

<1-1-1> The overall composition of the memory system

First, a general configuration of a memory system including a semiconductor memory device according to the present embodiment will be described using FIG. 1 . Fig. 1 is a block diagram of the memory system of the present embodiment.

As shown in FIG. 1 , the memory system 1 includes a NAND flash memory 10 and a memory controller 20 . The NAND type flash memory 10 and the memory controller 20 are, for example, a semiconductor device that can be formed by combining the above, for example, an SD card (Secure Digital Card: Secure Digital Card) like memory card, or SSD (solid state drive: solid state drive), etc.

The NAND type flash memory 10 has a plurality of memory cell transistors, and does not store data volatilely. The memory controller 20 is connected to the NAND flash memory 10 through the NAND bus, and connected to the host machine 30 through the host bus. Furthermore, the memory controller 20 controls the NAND type flash memory 10 , responds to the command received from the host device 30 , and accesses the NAND type flash memory 10 . The host device 30 is, for example, a digital camera or a personal computer, and the host bus is, for example, a bus conforming to the SDTM (Study Data Tabulation Model: Research Data Tabulation Model) interface.

The NAND bus carries out the sending and receiving of signals according to the NAND interface. Specific examples of the above signals are chip enable signal BCE, command latch enable signal CLE, address latch enable signal ALE, write enable signal BWE, read enable signal RE, BRE, write protect signal BWP , data strobe signal DQS, BDQS, input and output signal DQ, and ready. Busy signal RY/BBY. In cases where it is not necessary to distinguish the above-mentioned signals, they may be described only as signals.

The chip enable signal BCE is a signal for selecting a LUN (Logical unit number) 100 included in the NAND flash memory 10 . Chip enable signal BCE is asserted (“Low” level) when LUN 100 is selected.

The command latch enable signal CLE is used to notify the NAND flash memory 10 of the input and output signal DQ to the NAND flash memory 10 as a command. The command latch enable signal CLE is asserted (“High” level (Low<High)) when the command is fetched into the NAND flash memory 10 .

The address latch enable signal ALE is used to inform the NAND flash memory 10 of the input and output signal DQ to the NAND flash memory 10 as an address. Address Latch Enable Letter The signal ALE is asserted (“high” level) when an address is fetched into the NAND-type flash memory 10 .

The write enable signal BWE is a signal for capturing the input and output signal DQ to the NAND flash memory 10 . The write enable signal BWE is asserted (“low” level) when the input and output signals DQ are captured to the NAND flash memory 10 .

The read enable signal RE is a signal for reading the input/output signal DQ from the NAND flash memory 10 . The read enable signal BRE is the complementary signal of RE. The read enable signals RE and BRE are established when the input and output signals DQ are read from the NAND flash memory 10 (RE=“high” level, BRE=“low” level).

The write protection signal BWP is a signal used to protect data from accidental erasure or writing when the input signal is uncertain when the NAND flash memory 10 is powered on or cut off. . The write protect signal BWP is asserted (“low” level) when protecting data.

The input/output signal DQ is, for example, an 8-bit signal. Moreover, the input and output signals DQ are commands, addresses, writing data, reading data, etc. that are sent and received between the NAND flash memory 10 and the memory controller 20 .

The data strobe signal DQS is a signal for transmitting and receiving the input and output signal DQ (data) between the memory controller 20 and the NAND flash memory 10 . The data strobe signal BDQS is the complementary signal of DQS. The NAND flash memory 10 receives the input and output signal DQ (data) in accordance with the timing of the data strobe signals DQS and BDQS supplied from the memory controller 20 . The memory controller 20 receives the input and output signals DQ (data) in accordance with the timing of the data strobe signals DQS and BDQS supplied from the NAND flash memory 10 . The data strobe signals DQS and BDQS are established when the input and output signals DQ are sent and received (DQS=“low” level, BDQS=“high” level).

Ready. Busy signal RY/BBY represents whether the LUN 100 is in a ready state (a state that can receive commands from the memory controller 20) or a busy state (cannot receive commands from the memory controller 20). The status of the command of the controller 20) signal. Ready. Busy signal RY/BBY is set to "low" level in case of busy state.

<1-1-2> The composition of the memory controller

The details of the configuration of the memory controller 20 will be described using FIG. 1 . As shown in Figure 1, the memory controller 20 has a host interface (Host I/F) 210, a built-in memory (RAM: Random access memory, random access memory) 220, a processor (CPU: Central processing unit, central processing unit) 230, buffer memory 240, and NAND interface (NAND I/F) 250.

The host interface 210 is connected to the host machine 30 through a host bus, and transmits commands and data received from the host machine 30 to the processor 230 and the buffer memory 240 respectively. The host interface 210 responds to the command of the processor 230 and transmits the data in the buffer memory 240 to the host machine 30 .

The processor 230 controls the overall operation of the memory controller 20 . For example, when the processor 230 receives a write command from the host device 30 , it issues a write command to the NAND interface 250 in response thereto. The same is true for reading and erasing. The processor 230 executes various processes for managing the NAND flash memory 10 such as wear leveling.

The NAND interface 250 is connected to the NAND flash memory 10 through the NAND bus, and is responsible for communication with the NAND flash memory 10 . Furthermore, based on the command received from the processor 230, the chip enable signal BCE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal BWE, the read enable signal RE, BRE, the write protection signal BWP, and the data strobe signals DQS and BDQS are output to the NAND flash memory 10 . When writing, the write command issued by the processor 230 and the write data in the buffer memory 240 are sent to the NAND flash memory 10 as the input and output signals DQ. Furthermore, when reading out, The read command issued by the processor 230 is sent to the NAND flash memory 10 as the input and output signal DQ, and then the data read from the NAND flash memory 10 is received as the input and output signal DQ and sent to the Buffer memory 240.

The buffer memory 240 temporarily holds written data or read data.

The built-in memory 220 is, for example, a semiconductor memory such as DRAM (Dynamic random access memory), and is used as a working area of the processor 230 . Moreover, the built-in memory 220 holds firmware for managing the NAND flash memory 10, various management tables, and the like.

<1-1-3> NAND flash memory

<1-1-3-1> Composition of NAND flash memory

Next, the configuration of the NAND flash memory 10 will be described.

As shown in FIG. 1 , the NAND flash memory 10 includes a plurality of memory banks (in the example of FIG. 1 , GP0 and GP1 as an example).

Each memory group GP includes a plurality of LUNs 100 (four as an example in the example of FIG. 1 ). When differentiating a plurality of LUNs 100, it is indicated by a symbol of LUN (m: m is an arbitrary integer). Specifically, the memory group GP0 has LUN(0)-LUN(3), and the memory group GP1 has LUN(4)-LUN(7). LUN100 is the smallest unit that can be controlled independently. LUN100 only needs to have at least one memory chip, and may also have more than two memory chips. In this embodiment, the case where the LUN 100 has one memory chip will be described.

In this embodiment, an independent chip enable signal BCE is input to each memory group GP. In other words, the same chip enable signal BCE is input to the LUNs 100 in the same memory group GP.

In a certain memory group GP, the active LUN 100 can be one or multiple.

<1-1-3-2> The composition of LUN100

Next, the configuration of the LUN 100 will be described using FIG. 2 .

The memory controller 20 and the LUN 100 are connected through an input/output interface 101 and a control signal input interface 102 .

The input-output interface 101 has a receiver 120 and a transmitter 130 . Furthermore, the receiver 120 inputs the input and output signals ( DQ0 ˜ DQ7 ) through the data input and output lines (wiring for transmitting and receiving the input and output signals DQ in the NAND bus). The transmitter 130 outputs input and output signals ( DQ0 ˜ DQ7 ) through the data input and output lines.

The I/O interface 101 outputs the data strobe signals DQS and BDQS to the memory controller 20 when outputting the I/O signals (DQ0-DQ7) from the data I/O lines.

The control signal input interface 102 receives chip enable signal BCE, command latch enable signal CLE, address latch enable signal ALE, write enable signal BWE, read enable signal RE, BRE from the memory controller 20 , write protection signal BWP, and data strobe signals DQS, BDQS.

Although not shown in FIG. 2 , Vcc/Vss/Vccq/Vssq terminals and the like for power supply are also provided on the LUN 100 .

The control circuit 103 outputs the data read from the memory cell array (Memory cell array) 110 to the memory controller 20 through the I/O interface 101 . The control circuit 103 receives write, read, erase, and status via the control signal input interface 102. Read and other commands, addresses, and write data.

The control circuit 103 controls the command register (Command register) 104, the address register (Address register) 105, status register (Status register) 106, sense amplifier (Sense amp) 111, data register (Data register) 112, row decoder (Column decoder) 113, and column address decoder (Row address decoder) 115.

The control circuit 103 supplies required voltages to the memory cell array 110 , the sense amplifier 111 , and the column decoder 115 during data programming, verification, reading, and erasing.

The command register 104 stores commands input from the control circuit 103 .

The address register 105 stores, for example, an address supplied from the memory controller 20 . Moreover, the address register 105 converts the stored address into an internal physical address (row address and column address). Then, the address register 105 supplies the row address to the column buffer (Column buffer) 114 , and supplies the column address to the column address buffer decoder (Row address buffer decoder) 116 .

The state register 106 is used to notify the outside of various states of the LUN 100 . The status register 106 has a ready/busy register (not shown) that holds data indicating whether the LUN 100 is in a ready/busy state, and a write status register that holds data indicating pass/fail of writing. memory (not shown), etc.

The memory cell array 110 includes a plurality of bit lines BL, a plurality of word lines WL, and source lines SL. The memory cell array 110 is composed of a plurality of blocks BLK in which electrically rewritable memory cell transistors (also referred to simply as memory cells) MC are arranged in a matrix. The memory cell transistor MC has, for example, a multilayer gate including a control gate electrode and a charge storage layer (for example, a floating gate electrode), and changes the threshold value of the transistor according to the amount of charge injected into the floating gate electrode. Memorize binary or multi-valued data. In addition, the memory cell transistor MC may also have a MONOS (Metal-Oxide-Nitride-Oxide-Silicon: Metal-Oxide-Nitride-Oxide-Silicon) structure that traps electrons in a nitride film.

Furthermore, the configuration of the memory cell array 110 may also be other configurations. That is, with respect to memory cells The configuration of the array 110 is described, for example, in US Patent Application No. 12/407,403 filed on March 19, 2009, entitled "Three-dimensional Laminated Non-Volatile Semiconductor Memory". Also, it is described in U.S. Patent Application No. 12/406,524 filed on March 18, 2009 entitled "Three-dimensional Laminated Non-Volatile Semiconductor Memory", 2010 entitled "Non-Volatile Semiconductor Memory Device and Method of Manufacturing It" U.S. Patent Application No. 12/679,991, filed March 25, 2009, and U.S. Patent Application No. 12/532,030, filed March 23, 2009, entitled "Semiconductor Memory and Method of Manufacturing Same." The patent applications mentioned above are incorporated in the specification of this application by reference in their entirety.

The sense amplifier 111 senses the data read from the memory cell transistor MC to the bit line when the data is read out.

The data temporary register 112 is constituted by SRAM ((Static Random Access Memory: static random access memory) etc. The data temporary register 112 memorizes the data supplied from the memory controller 20, or is detected by the sense amplifier 111 verification results, etc.

The row decoder 113 decodes the row address signal stored in the row buffer 114 , and outputs a selection signal for selecting any one of the bit lines BL to the sense amplifier 111 .

The row buffer 114 temporarily stores the row address signal input from the address register 105 .

The column address decoder 115 decodes the column address signal input through the column address buffer decoder 116 . Moreover, the column address decoder 115 selects and drives the word line WL and the selection gate lines SGD and SGS of the memory cell array 110 .

The column address buffer decoder 116 temporarily stores the column address signal input from the address register 105 .

<1-1-3-3> Composition of input and output interface

Next, the configuration of the input/output interface 101 will be specifically described using FIG. 3 .

As shown in Figure 3, the input and output interface 101 is based on the command latch enable signal CLE, address latch The lock enable signal ALE and the signal from the instruction register 104 or the address register 105 are used to input and output the signal DQ.

Specifically, the command register 104 outputs the command CMD stored in the storage unit 104 a to the AND (AND) operation circuit 101 a of the input-output interface 101 based on the write enable signal BWE. When the command register 104 outputs the command CMD, it maintains the "high" level state before inputting the next command. The address register 105 outputs the address ADD stored in the memory unit 105 a to the AND operation circuit 101 a of the input-output interface 101 based on the write enable signal BWE. When the address register 105 selects its own LUN 100, it maintains the "high" level state.

The AND operation circuit 101a outputs the operation result to the OR ("or") operation circuit 101b based on the command CMD and the address ADD. The AND operation circuit 101a outputs a signal of a "high" level only when the command CMD and the address ADD are both at a "high" level.

The OR operation circuit 101b generates the signal EN based on the operation result of the AND operation circuit 101a, the command latch enable signal CLE, or the address latch enable signal ALE. The OR operation circuit 101b outputs a "low" level only when all of the operation result of the AND operation circuit 101a, the command latch enable signal CLE, and the address latch enable signal ALE are "low" levels. Signal EN. In other words, the OR operation circuit 101b outputs "high" when at least one of the operation result of the AND operation circuit 101a, the command latch enable signal CLE, and the address latch enable signal ALE is at a "high" level Level signal EN. In the following, it is sometimes described as "rising" for setting the signal EN from the "low" level to the "high" level, and "falling" for setting the signal EN from the "high" level to the "low" level. ".

The receiver 120 receives the input and output signal DQ inside the LUN 100 based on the signal EN and the input and output signal DQ. Specifically, the NAND operation circuit 101c is based on the signal EN supplied from the OR operation circuit 101b and the input/output signal DQ supplied from the memory controller 20, and generate a signal. The NAND operation circuit 101c generates a signal of a "low" level only when the signal EN and the input and output signals DQ are both at a "high" level. Furthermore, the inverter 101d inverts and outputs the operation result of the NAND operation circuit 101c. That is, the receiver 120 receives the input and output signal DQ inside the LUN 100 only when the signal EN and the input and output signal DQ are at “high” levels.

In the following, the state in which the signal EN of the "high" level is input to the receiver 120 may be described as an "activation state", and the state in which the signal EN of the "low" level is input may be described as a "standby state". When the receiver 120 is activated, it is in a state capable of receiving input and output data DQ. Furthermore, when the receiver 120 is in the standby state, it is in a state where it cannot receive input/output data DQ.

<1-2> Action

<1-2-1> Summary of the actions of the memory system

The outline of the operation of the memory system of this embodiment will be described using FIG. 4 .

In FIG. 4 , focusing on the operation of the memory group GP0, the outline of the operation in the case of changing the access (write operation, read operation, etc.) from LUN(0) to LUN(1) will be described. As shown in Figure 4, during the access to LUN(0), the signal EN in LUN(0) becomes "high" level, and the signal EN in LUN(1)~LUN(3) becomes "low" level . That is, during access to LUN(0), the receiver 120 of LUN(0) is set to the active state, and the receivers 120 of LUN(1)˜LUN(3) are set to the standby state.

Moreover, at time T0, the memory system 1 performs a LUN switching operation. At this time, at least the signal EN in all LUNs (LUN(0)˜LUN(3)) in the memory group GP0 becomes “high”. That is, during the LUN switching operation, at least the receivers 120 in all the LUNs (LUN(0)˜LUN(3)) in the memory group GP0 are set to the active state.

At time T1, if the address of LUN(1) is determined as the selected LUN address, start to Access to LUN(1). During the access to LUN(1), the signal EN in LUN(1) becomes "high" level, and the signals EN in LUN(0), LUN(2), and LUN(3) become "low" level. That is, during access to LUN(1), the receiver 120 of LUN(1) is set to the active state, and the receivers 120 of LUN(0), LUN(2), and LUN(3) are set to the standby state .

<1-2-2> Writing operation example 1

Using FIG. 5, an example 1 of the writing operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

At time T2, the memory controller 20 asserts (“high” level) the command latch enable signal CLE. At the time point of time T2, the chip enable signal BCE is asserted (“low” level). If the command latch enable signal CLE is asserted, the signal EN becomes “high” as illustrated in FIG. 3 .

The LUN 100 must wait for the period t _CALS as the period required for setting the command input from the assertion of the command latch enable signal CLE.

At time T3 after the time period t _CALS elapses from time T2, the memory controller 20 issues commands “01h” and “80h”.

The command "01h" is a command issued when the memory cell transistor MC can hold 3-bit data. More specifically, the command "01h" is a command specifying the first page. Although the command "01h" is described here as an example, it is not limited thereto. If the memory controller 20 specifies other pages, other commands can also be input. Command "80h" is a command for specifying a write operation.

The memory controller 20 asserts ("low" level) the write enable signal BWE whenever signals such as commands, addresses, and data are issued. Moreover, whenever the write enable signal BWE is triggered, the signal is captured to the LUN 100 .

Next, the memory controller 20 issues addresses (C1, C2: row addresses, R1~R3: column addresses) over 5 cycles, for example, and asserts ("high" level) the address latch enable signal ALE.

When issuing addresses, the command latch enable signal CLE is negated ("low" level), but the address latch enable signal ALE is asserted. If the address latch enable signal ALE is asserted, the signal EN becomes "high" as illustrated in FIG. 3 . That is, when receiving the address, the LUN 100 maintains the signal EN at a "high" level.

However, for example, by including the selected LUN address in the column address R3 and supplying the column address R3 to the LUN 100 , the selection of the LUN 100 is determined. If the selection of the LUN 100 is confirmed, the address latch circuit 105 outputs a signal of "high" level in the selection of the LUN 100 as illustrated in FIG. 3 . As a result, the signal EN in the selection LUN 100 maintains the "high" level. On the other hand, in the non-selected LUN 100, the address latch circuit 105 outputs a signal of "low" level. As a result, the signal EN in the selection LUN 100 becomes "low". In other words, the receiver 120 of the selected LUN 100 is maintained in the active state, and the receiver 120 of the non-selected LUN 100 is in the standby state.

Secondly, the memory controller 20 outputs the writing data (D0˜Dn) over a plurality of cycles. During the above period, the signals ALE and CLE are negated (“L” level). Write data received by LUN 100 is held in a page buffer within sense amplifier 111 .

Although not shown in FIG. 5 , the memory controller 20 issues the write command “10H” and asserts the command latch enable signal CLE. If the command “10h” is received, the control circuit 103 starts the writing operation, and the LUN 100 becomes busy (RY/BBY=“low” level).

<1-2-3> Read operation example 1

Using FIG. 6, an example 1 of the read operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

At time T5, the memory controller 20 asserts the command latch enable signal CLE. At the time point of time T5, the chip enable signal BCE is asserted. If the command latch enable signal CLE is asserted, the signal EN becomes "high".

At time T6 after the time period t _CALS elapses from time T5, the memory controller 20 issues the read command "05h".

Next, the memory controller 20 issues addresses (C1, C2: row addresses, R1~R3: column addresses) over 5 cycles, for example, and asserts ("high" level) the address latch enable signal ALE.

The memory controller 20 issues the command "E0h". The LUN 100 starts a read operation upon receiving the command "E0h".

The command register 104 recognizes the action requested from the memory controller 20 as a read action. Then, the instruction register 104 supplies the signal of "low" level to the AND operation circuit 101a (refer to FIG. 3 ). Thereby, the signal EN becomes "low" level.

That is, the receiver 120 becomes a standby state.

<1-3> Effect

According to the above-mentioned embodiment, the electrical connection between the LUN 100 and the data input and output lines is appropriately controlled by using the address ADD, the command CMD, the command latch enable signal CLE, the address latch enable signal ALE, and the like.

For example, in the write operation, if the non-selected LUN 100 receives write data, useless current flows through the LUN 100 . However, by adopting the above-mentioned embodiment, the operating current of the non-selected LUN 100 can be suppressed.

Also, in the read operation, LUN 100 does not need to receive data. By adopting the above-mentioned embodiment, the operating current of LUN 100 can be suppressed.

<2> Second Embodiment

The second embodiment will be described. In the second embodiment, another configuration of the input/output interface will be described. Furthermore, the basic configuration and basic operation of the memory device of the second embodiment are the same as those of the memory device of the first embodiment described above. Therefore, the description of the first embodiment described above is omitted. Explanation of the matters described in the first embodiment and the matters that can be deduced from the above-mentioned first embodiment.

<2-1> Composition of input and output interface

Next, the configuration of the input/output interface 101 of the memory system according to the second embodiment will be specifically described using FIG. 7 .

As shown in FIG. 7 , the input and output interface 101 performs input and output signals based on the command latch enable signal CLE, the address latch enable signal ALE, and signals from the command register 104 or the address register 105. DQ input and output.

Specifically, the NAND operation circuit 101g outputs an operation result to the NAND operation circuit 101h based on the command latch enable signal CLE and the address latch enable signal ALE. The NAND operation circuit 101g generates a signal of a "low" level only when the command latch enable signal CLE and the address latch enable signal ALE are both at a "high" level.

The NAND arithmetic circuit 101h and the NAND arithmetic circuit 101i constitute an RS flip-flop circuit. Specifically, the NAND arithmetic circuit 101h outputs an arithmetic result based on the arithmetic results of the NAND arithmetic circuit 101g and the NAND arithmetic circuit 101i. The NAND operation circuit 101i outputs the operation result based on the operation result of the NAND operation circuit 101h and the signal (such as the command CMD) from the command register 104 .

Briefly explain the operation of this RS flip-flop circuit. When the signal from the NAND operation circuit 101g is at a "high" level and the signal from the command register 104 is at a "low" level, the NAND operation circuit 101h outputs a signal at a "low" level. Furthermore, when the signal from the NAND operation circuit 101g is at a "low" level and the signal from the instruction register 104 is at a "high" level, the NAND operation circuit 101h outputs a signal at a "high" level. Also, in the state where the output signal of the NAND operation circuit 101h is determined, even if the signal from the NAND operation circuit 101g or the signal from the command register 104 changes, the NAND operation is maintained. Calculate the output signal of circuit 101h.

The OR operation circuit 101j generates the signal EN based on the operation result of the NAND operation circuit 101h and the signal from the address register 105 . The OR operation circuit 101j outputs the signal EN of the "low" level only when the operation result of the NAND operation circuit 101h and the signal from the address register 105 are both at the "low" level. In other words, when at least one of the operation result of the NAND operation circuit 101h and the signal from the address register 105 is at a "high" level, the OR operation circuit 101j outputs a "high" level signal EN.

The receiver 120 receives the input and output signal DQ inside the LUN 100 only when the signal EN and the input and output signal DQ are both at “high” level.

<2-2> Action

The difference between the operation described in the first embodiment and the operation in the second embodiment lies in the rising method of the signal EN in the LUN 100 .

In the memory system 1 of the first embodiment, the signal EN is raised based on the assertion of the command latch enable signal CLE. In the memory system 1 of the second embodiment, the signal EN is raised by simultaneously asserting the command latch enable signal CLE and the address latch enable signal ALE. The operation of simultaneously asserting the command latch enable signal CLE and the address latch enable signal ALE is an operation for raising the signal EN.

<2-2-1> Writing operation example 2

Using FIG. 8, an example 2 of the write operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

At time T8, the memory controller 20 asserts the command latch enable signal CLE and the address latch enable signal ALE. Thereby, as explained using FIG. 7, the signal EN becomes "high" level. Then, the memory controller 20 negates the command latch enable signal CLE and the address latch enable signal ALE. Therefore, although the input signal of the NAND operation circuit 101h changes, the input signal of the NAND operation circuit 101i does not change, so the output signal of the NAND operation circuit 101h is maintained at a "high" level. As a result, signal EN is held at "high" level.

At time T9 after the time period _tCALS elapses from time T8, the memory controller 20 issues write commands "01h" and "80h".

At time T10, if the selection of the LUN 100 is determined, the address latch circuit 105 outputs a signal of "high" level in the selected LUN 100 as illustrated in FIG. 7 . As a result, the signal EN in the LUN 100 maintains the "high" level. On the other hand, in the non-selected LUN 100, the address latch circuit 105 outputs a signal of "low" level. As a result, the signal EN in the selection LUN 100 becomes "low". In other words, the receiver 120 of the selected LUN 100 maintains the active state, and the non-selected LUN 100 is set to the standby state.

The memory controller 20 issues addresses (C1, C2: row addresses, R1~R3: column addresses) over 5 cycles, for example, and asserts ("high" level) the address latch enable signal ALE.

Secondly, the memory controller 20 outputs the writing data (D0˜Dn) across a plurality of cycles. During the above-mentioned period, the signals ALE and CLE are negated. Write data received by LUN 100 is held in a page buffer within sense amplifier 111 .

<2-2-2> Writing operation example 3

Using FIG. 9 and FIG. 10, an example 3 of the writing operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in the writing operation example 3 is the same as that in the writing operation example 2, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described.

For example, the selected LUN address is included in the column address R3. By supplying the column address R3 to the LUN100, the selection of the LUN100 is confirmed. If you select LUN100 to confirm, select the The signal EN in the non-selected LUN 100 is maintained at a "high" level, and the signal EN in the non-selected LUN 100 becomes a "low" level. In other words, the receiver 120 of the selected LUN 100 is maintained in the active state, and the non-selected LUN 100 is set in the standby state.

As shown in FIG. 9, after receiving the column address R3, the signal EN in the non-selected LUN 100 becomes "low" immediately. As shown in FIG. 10 , the signal EN in the LUN 100 can also be changed to "low" level according to the timing before and after the input and output of data.

<2-2-3> Read operation example 2

Using FIG. 11, an example 2 of the read operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in the read operation example 2 is the same as that in the write operation example 2.

At time T13, the memory controller 20 asserts the command latch enable signal CLE and the address latch enable signal ALE. Thereby, as explained using FIG. 7, the signal EN becomes "high" level.

At time T14 after the period t _CALS has elapsed from time T13, the read command "05h" is issued.

If the command register 104 receives “05h”, it will recognize the action requested from the memory controller 20 as a read action. Then, the instruction register 104 supplies the signal of "low" level to the AND operation circuit 101a (refer to FIG. 3 ). Thereby, the signal EN becomes "low" level.

That is, the receiver 120 becomes a standby state.

<2-2-4> Read operation example 3

Using FIGS. 12 to 14, an example 3 of the read operation of the memory system 1 according to this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in the read operation example 3 is the same as that in the read operation example 2, so the description thereof is omitted. Here, the falling timing of the signal EN of the LUN 100 will be described.

The command register 104 recognizes the action requested from the memory controller 20 as a read action. However Then, the instruction register 104 supplies the signal of "low" level to the AND operation circuit 101a (refer to FIG. 3 ). Thereby, the signal EN becomes "low" level.

That is, the receiver 120 becomes a standby state.

As shown in FIG. 12, after receiving the column address R3, the signal EN in the LUN 100 becomes "low" immediately. Also, as shown in FIG. 13, the signal EN in the LUN 100 may immediately become "low" after receiving the command "E0h". Also, as shown in FIG. 14, the signal EN in the LUN 100 may be changed to a "low" level according to the timing before and after the input and output of data.

<2-3> Effect

According to the above-mentioned embodiment, by simultaneously asserting the command latch enable signal CLE and the address latch enable signal ALE, the receivers 120 of the plurality of LUNs 100 become activated.

With the high speed of data input and output, it is necessary to speed up the instruction address input cycle. For example, in the case of the first embodiment, if the input and output of data are speeded up, the period required for setting the command input becomes insufficient after the establishment of the command latch enable signal CLE, and it is too late to generate Possibility of setting problems. In other words, before the command is input, the LUN 100 cannot be electrically connected to the data input and output line through the receiver 120 , and there is a possibility that the LUN 100 cannot properly receive the command.

Therefore, in the present embodiment, before the command latch enable signal CLE is asserted for command input, the receiver 120 is set to the active state. Thereby, compared with the first embodiment, the substantial period t _CALS can be relaxed. Therefore, it is possible to provide a memory system capable of appropriately transmitting and receiving the input and output signals DQ as the input and output speeds of data are increased.

<2-4> Variation 1 of the second embodiment

<2-4-1> Writing operation example 4

Using FIG. 15, an example 4 of the write operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in the address operation example 4 is the same as that in the address operation example 2 of the second embodiment, so the description thereof is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described.

For example, the selected LUN address is included in the column address R3. By supplying the column address R3 to the LUN100, the selection of the LUN100 is confirmed. As shown in FIG. 7 , if the LUN 100 is selected and the command “XXh” is input, the output signal of the command register 104 becomes “low”. On the other hand, in the selected LUN 100, the address register 105 maintains the signal of “high” level, and in the non-selected LUN 100, the address register 105 outputs the signal of “low” level. Therefore, the signal EN in the selected LUN 100 maintains a "high" level, and the signal EN in the non-selected LUN 100 becomes a "low" level. In other words, the receiver 120 of the selected LUN 100 maintains the activated state, and the receiver 120 of the non-selected LUN 100 is set to the standby state.

<2-4-2> Read operation example 4

Using FIG. 16, an example 4 of the read operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in the read operation example 4 is the same as that in the read operation example 2 of the second embodiment, so the description thereof is omitted. Here, the falling timing of the signal EN of the LUN 100 will be described.

If the command register 104 receives “XXh”, it will recognize the action requested from the memory controller 20 as a read action. Then, the instruction register 104 supplies the signal of "low" level to the AND operation circuit 101a (refer to FIG. 3 ). Thereby, the signal EN becomes "low" level. That is, the receiver 120 becomes a standby state.

<2-5> Variation 2 of the second embodiment

Using FIG. 17, the structure of the input-output interface 101 of the memory system of the modification 2 of 2nd Embodiment is demonstrated concretely.

The input/output interface 101 shown in FIG. 17 has a circuit for controlling in such a manner that the receiver 120 is not electrically connected to the LUN 100 and the data input/output line when outputting data.

Specifically, as shown in FIG. 17 , the input/output interface 101 includes a NAND arithmetic circuit 101k. Moreover, the NAND operation circuit 101k is based on the inverted signal ~CLE of the command latch enable signal CLE, the inverted signal ^~ ALE of the address latch enable signal ALE, the inverted signal ^~ BCE of the chip enable signal BCE, ^and write The enabling signal BWE is enabled, and the operation result is output to the NAND operation circuit 101l. The NAND operation circuit 101k generates a signal of a "low" level only when the signals ^~ CLE, ^~ ALE, ^~ BCE, and BWE are all at a "high" level.

The NAND arithmetic circuit 101l and the NAND arithmetic circuit 101m constitute an RS flip-flop circuit. Specifically, the NAND arithmetic circuit 101l outputs an arithmetic result based on the arithmetic results of the NAND arithmetic circuit 101k and the NAND arithmetic circuit 101m. The NAND operation circuit 101m outputs the operation result based on the operation result of the NAND operation circuit 101l and the read enable signal BRE.

Briefly explain the operation of this RS flip-flop circuit. When the signal from the NAND operation circuit 101k is at a "high" level and the read enable signal BRE is at a "low" level, the NAND operation circuit 101l outputs a signal at a "low" level. Furthermore, when the signal from the NAND operation circuit 101k is at a "low" level and the read enable signal BRE is at a "high" level, the NAND operation circuit 101l outputs a signal at a "high" level. Also, in the state where the output signal of the NAND arithmetic circuit 101l is fixed, even if the signal from the NAND arithmetic circuit 101k or the read enable signal BRE changes, the output signal of the NAND arithmetic circuit 101l is held.

And the inverter 101n inverts the output signal of the NAND operation circuit 101l, and supplies it to the AND operation circuit 101o.

The AND operation circuit 101o outputs the operation result to the OR operation circuit 101p based on the output signal of the inverter 101n and the signal from the address register 105 . The AND operation circuit 101a outputs a signal of a "high" level only when the output signal of the inverter 101n and the signal from the address register 105 are both at a "high" level.

The OR operation circuit 101p generates a signal EN based on the operation results of the AND operation circuit 101o and the NAND operation circuit 101h. The OR operation circuit 101p outputs the signal EN of the "low" level only when the operation results of the AND operation circuit 101o and the NAND operation circuit 101h are both at the "low" level. In other words, the OR operation circuit 101p outputs a signal EN of a "high" level when at least one of the operation results of the AND operation circuit 101o and the NAND operation circuit 101h is at a "high" level.

During data output, the signals ^~ CLE, ^~ ALE, ^~ BCE, BWE, and BREA all become "high" levels. As a result, the output signal of the NAND operation circuit 1011 is a signal of "high" level. As a result, the signal EN becomes "low" during data output.

In this way, the I/O interface 101 of the memory system in the second modification of the second embodiment can be controlled in such a way that the receiver 120 is not electrically connected to the LUN 100 and the data I/O line when outputting data.

<3> Third Embodiment

A third embodiment will be described. In the third embodiment, another configuration of the input/output interface will be described. Furthermore, the basic configuration and basic operation of the memory device of the third embodiment are the same as those of the memory devices of the first and second embodiments described above. Therefore, the description of the matters described in the above-mentioned first and second embodiments and the matters that can be inferred from the above-mentioned first and second embodiments will be omitted.

<3-1> Composition of input and output interface

Next, using FIG. 18, the configuration of the input/output interface 101 of the memory system according to the third embodiment will be specifically described. The input/output interface 101 of the memory system of the third embodiment is compared with the input/output interface 101 of the memory system of the second embodiment, and further based on the inversion signal ^~ BWE of the write enable signal BWE, the input and output signals are performed. DQ input and output.

Specifically, the NAND calculation circuit 101g1 outputs calculation results to the NAND calculation circuit 101h based on the signals CLE, ALE, and ^~ BWE. The NAND operation circuit 101g1 generates a signal of a "low" level only when the signals CLE, ALE, and ^-BWE are all at a "high" level.

<3-2> Action

The difference between the operation described in the second embodiment and the operation in the third embodiment lies in the rising method of the signal EN in the LUN 100 .

In the memory system 1 of the second embodiment, the signal EN is raised by simultaneously asserting the command latch enable signal CLE and the address latch enable signal ALE. On the other hand, in the memory system 1 of the third embodiment, by simultaneously asserting the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE, the signal EN rise. That is, the operation of simultaneously asserting the signals CLE, ALE, and BWE is an operation for raising the signal EN.

<3-2-1> Writing operation example 5

Using FIG. 19, an example 5 of the writing operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

At time T8, the memory controller 20 asserts the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE. Thereby, as explained using FIG. 18, the signal EN becomes "high" level. Then, the memory controller 20 negates the instruction latch enable signal CLE, address latch enable signal ALE, and write enable signal BWE. Therefore, although the input signal of the NAND operation circuit 101h changes, the input signal of the NAND operation circuit 101i does not change, so the output signal of the NAND operation circuit 101h is kept at a "high" level. As a result, signal EN is held at "high" level.

Operations after time T9 are the same as those described using FIG. 8 .

<3-2-2> Other access actions

As shown in FIG. 20 , the rising method of the signal EN in the writing operation example 5 can also be applied to the writing operation example 3 described in FIG. 9 .

Similarly, as shown in FIG. 21 , the rising method of the signal EN in the writing operation example 5 can also be applied to the writing operation example 3 described in FIG. 10 .

As shown in FIG. 22 , the rising method of the signal EN in the writing operation example 5 can also be applied to the writing operation example 2 described in FIG. 11 .

Similarly, as shown in FIG. 23 , the rising method of the signal EN in the writing operation example 5 can also be applied to the writing operation example 3 described in FIG. 12 .

Similarly, as shown in FIG. 24 , the rising method of the signal EN in the writing operation example 5 can also be applied to the writing operation example 3 described in FIG. 13 .

Similarly, as shown in FIG. 25 , the rising method of the signal EN in the writing operation example 5 can also be applied to the writing operation example 3 described in FIG. 14 .

Similarly, as shown in FIG. 26 , the rising method of the signal EN in the writing operation example 5 can also be applied to the writing operation example 4 described in FIG. 15 .

Similarly, as shown in FIG. 27 , the rising method of the signal EN in the writing operation example 5 can also be applied to the writing operation example 4 described in FIG. 16 .

<3-3>Effect

According to the above-mentioned embodiment, the same effect as that of the second embodiment can be obtained.

<3-4> Variation of the third embodiment

Next, using FIG. 28, the configuration of the input/output interface 101 of the memory system according to the modified example of the third embodiment will be specifically described. The I/O interface 101 of the memory system in the variation of the third embodiment is compared with the I/O interface 101 of the memory system in the variation 2 of the second embodiment, and further based on the inversion signal of the write enable signal BWE ^~ BWE, and carry out the input and output of the input and output signal DQ.

Specifically, the NAND calculation circuit 101g1 outputs calculation results to the NAND calculation circuit 101h based on the signals CLE, ALE, and ^~ BWE. The NAND operation circuit 101g1 generates a signal of a "low" level only when the signals CLE, ALE, and ^-BWE are all at a "high" level.

<4> Fourth Embodiment

A fourth embodiment will be described. In the fourth embodiment, another configuration of the input/output interface will be described. Furthermore, the basic configuration and basic operation of the memory device of the fourth embodiment are the same as those of the memory devices of the first to third embodiments described above. Therefore, the description of the matters described in the above-mentioned first to third embodiments and the matters that can be inferred from the above-mentioned first to third embodiments will be omitted.

<4-1> Composition of input and output interface

As shown in FIG. 29, the input-output interface 101 of the memory system 1 of the first embodiment and the input-output interface 101 of the memory system 1 of the second embodiment can be combined.

Furthermore, as shown in FIG. 29, it is possible to select which one of the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the second embodiment is used by a switch circuit 101q. The signal EN of the person. For example, by using the Set feature (Set Feature)" action, etc., generate a signal MS, and input it to the switch circuit 101q, and select the output signal. "Set feature" action is, for example, an action to change the operation mode of LUN100.

<4-2> Action

Here, the mode selection operation of the memory system of this embodiment will be described using FIG. 30 .

As shown in FIG. 30 , when the memory system 1 is powered on (Power on), the LUN 100 is set to the first operation mode. Furthermore, the memory controller 20 issues an initialization command "FFh". Next, the memory controller 20 performs a "set feature" action.

Specifically, the memory controller 20 sequentially issues the commands "EFh" and "YYh" of the "setting feature" operation to the LUN 100, and then issues information on changing the operation mode (W-B0~W-B3).

If the LUN 100 receives the commands “EFh” and “YYh” and information (W-B0~W-B3), it changes the operation mode. For example, in this embodiment, it is changed to the second operation mode.

Here, the operation of the switch circuit 101q when changing from the first operation mode to the second operation mode will be briefly described. As shown in FIG. 29, for example, in the first operation mode, the switch circuit 101q may be controlled so as to selectively output the output signal of the OR circuit 101b as a signal EN. However, by switching to the second operation mode, the switch circuit 101q is controlled so that the output signal of the OR circuit 101j is selectively output as the signal EN.

Then, the LUN 100 operates in the second operation mode as long as the operation mode is not changed by the "setting characteristic" operation.

When it is desired to operate the LUN 100 in the first operation mode, it is necessary to change the operation mode by performing the "setting feature" operation again.

<4-3> Effect

By using the switch circuit 101q as described above, the first and second embodiments can be appropriately combined and operated appropriately.

<4-4> Variation 1 of the fourth embodiment

As shown in FIG. 31, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the modification 2 of the second embodiment can be combined.

Moreover, as shown in FIG. 31, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface of the memory system 1 of the second modification of the second embodiment can be selected and used by a switch circuit 101r. Which one of 101 is the signal. For example, the output signal can be selected by generating the signal MS by utilizing the action of "set feature" and inputting it to the switch circuit 101r. The "setting feature" operation is the same as that described using FIG. 30 .

<4-5> Variation 2 of the fourth embodiment

As shown in FIG. 32, the input-output interface 101 of the memory system 1 of the first embodiment and the input-output interface 101 of the memory system 1 of the third embodiment can be combined.

Furthermore, as shown in FIG. 32, it is possible to select which one of the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the third embodiment is used by a switch circuit 101q. the signal of the For example, the output signal can be selected by generating the signal MS by utilizing the action of "set feature" and inputting it to the switch circuit 101q. The "setting feature" operation is the same as that described using FIG. 30 .

<4-6> Variation 3 of the fourth embodiment

As shown in FIG. 33, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the modified example of the third embodiment can be combined.

Moreover, as shown in FIG. 33, the input/output interface 101 of the memory system 1 of the first embodiment and the memory system of the modification example of the third embodiment can be selected and used by a switch circuit 101r. Which one of the input and output interfaces 101 is the signal of 1. For example, the output signal can be selected by generating the signal MS by utilizing the action of "set feature" and inputting it to the switch circuit 101r. The "setting feature" operation is the same as that described using FIG. 30 .

<5> Fifth Embodiment

A fifth embodiment will be described. In the fifth embodiment, another configuration of the input/output interface will be described. Furthermore, the basic configuration and basic operation of the memory device of the fifth embodiment are the same as those of the memory devices of the first and second embodiments described above. Therefore, the description of the matters described in the above-mentioned first and second embodiments and the matters that can be inferred from the above-mentioned first and second embodiments will be omitted.

<5-1> Composition of input and output interface

Next, the configuration of the input/output interface 101 will be specifically described using FIG. 34 .

As shown in FIG. 34 , the I/O interface 101 performs input and output of the I/O signal DQ based on the inversion signal ^~ BWP of the write-protect signal BWP or the signal from the address register 105 .

The OR operation circuit 101s generates the signal EN based on the signal ^~ BWP and the signal from the address register 105 . The OR operation circuit 101s outputs the signal EN of the "low" level only when the signal ^~ BWP and the signal from the address register 105 are both at the "low" level. In other words, when at least one of the signal ^~ BWP and the signal from the address register 105 is at a "high" level, the OR operation circuit 101s outputs a "high" level signal EN.

The receiver 120 receives the input and output signal DQ inside the LUN 100 based on the signal EN and the input and output signal DQ. The receiver 120 receives the input and output signal DQ inside the LUN 100 only when the signal EN and the input and output signal DQ are both at “high” level.

<5-2> Action

<5-2-1> Writing operation example 6

Using FIG. 35, an example 6 of the write operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

At time T20, the memory controller 20 asserts (“low” level) the write protect signal BWP. During the assertion of the write-protect signal BWP, the signal EN is kept at a "high" level.

At time T21 after the period t _CALS elapses from time T20, the memory controller 20 issues write commands "01h" and "80h".

After determining the address of the LUN 100 , at time T22 , the memory controller 20 negates (“high” level) the write-protect signal BWP. If the write protect signal BWP is negated, the signal EN in the unselected LUN 100 becomes "low". On the other hand, in the selected LUN 100, since the signal of the address register 105 is kept at a "high" level, the signal EN is kept at a "high" level.

Other operations are the same as those described using FIG. 8 .

As described above, in this embodiment, the write protect signal BWP is used to control the signal EN. On the other hand, when this operation is realized, the write protection operation cannot be performed. However, if an operation such as "setting a feature" is used, it is possible to appropriately switch between the mode in which the present embodiment is operated and the mode in which the write-protect operation is used.

<5-2-2> Writing operation example 7

Using FIG. 36 and FIG. 37, a write operation example 7 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in the write operation example 7 is the same as that in the write operation example 6, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described.

For example, the selected LUN address is included in the column address R3. After determining the address of LUN100 Then, at time T23, the memory controller 20 negates ("high" level) the write-protect signal BWP. If the write protect signal BWP is negated, the signal EN in the unselected LUN 100 becomes "low". On the other hand, in the selected LUN 100, since the signal of the address register 105 is kept at a "high" level, the signal EN is kept at a "high" level.

As shown in FIG. 36, after receiving the column address R3, the signal EN in the non-selected LUN 100 becomes "low" immediately. As shown in FIG. 37 , the signal EN in the LUN 100 may not be selected to become "low" according to the timing before and after the input and output of data.

<5-2-3> Read operation example 5

Using FIG. 38, a fifth example of the read operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

At time T25, the memory controller 20 asserts the write protect signal BWP. During the assertion of the write-protect signal BWP, the signal EN is kept at a "high" level.

At time T26 after the time period t _CALS elapses from time T25, the read command "05h" is issued.

After determining the read operation, at time T27, the memory controller 20 negates ("high" level) the write-protect signal BWP. If the write-protect signal BWP is negated, the signal EN in the selection LUN 100 becomes "low".

<5-2-4> Read operation example 6

Using FIGS. 39 to 41, an example 6 of the read operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in the read operation example 6 is the same as that in the read operation example 5, so the description thereof is omitted. Here, the falling timing of the signal EN of the LUN 100 will be described.

After determining the read operation, at time T28, the memory controller 20 negates ("high" level) the write-protect signal BWP. If the write protect signal BWP is negated, LUN100 is selected The internal signal EN becomes "low" level.

As shown in FIG. 39, after receiving the column address R3, the signal EN in the LUN 100 becomes "low" immediately. Also, as shown in FIG. 40, the signal EN in the LUN 100 may immediately become "low" after receiving the command "E0h". Also, as shown in FIG. 41, the signal EN in the LUN 100 may be changed to "low" level according to the timing before and after the input and output of data.

<5-3> Effect

According to the above-mentioned embodiment, the same effect as that of the second embodiment can be obtained.

<5-4> Variations of the fifth embodiment

In the fifth embodiment, the signal EN is controlled using the write protect signal BWP. However, it is also possible to use the signal NP dedicated to the control of the signal EN. In the above case, as shown in FIG. 34 , instead of the signal ^~ BWP, the signal NP is input to the OR operation circuit 101s. The above-mentioned signal NP is set to be input from the memory controller 20 to the NAND flash memory 10 .

<5-4-1> Writing operation example 8

Using FIG. 42, an example 8 of the writing operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

At time T20, the memory controller 20 asserts (“high” level) the signal NP. During the assertion of the signal NP, the signal EN is kept at a "high" level.

At time T21 after the period t _CALS elapses from time T20, the memory controller 20 issues write commands "01h" and "80h".

After determining the address of the LUN 100, at time T22, the memory controller 20 negates ("low" level) the signal NP. If the signal NP is negated, the signal EN in the non-selected LUN 100 becomes "low". On the other hand, in the selected LUN 100, since the signal of the address register 105 is kept at the "high" level, the signal EN is kept at the "high" level.

Other operations are the same as those described using FIG. 8 .

As above, in this embodiment, the signal EN is controlled using the signal NP.

<5-4-2> Writing operation example 9

Using FIG. 43 and FIG. 44, a write operation example 9 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in the write operation example 9 is the same as that in the write operation example 8, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described.

For example, the selected LUN address is included in the column address R3. After determining the address of the LUN 100, at time T23, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the non-selected LUN 100 becomes "low". On the other hand, in the selected LUN 100, since the signal of the address register 105 is kept at the "high" level, the signal EN is kept at the "high" level.

As shown in FIG. 43, after receiving the column address R3, the signal EN in the non-selected LUN 100 becomes "low" immediately. As shown in FIG. 44 , the signal EN in the LUN 100 may not be selected to become "low" according to the timing before and after the input and output of data.

<5-4-3> Read operation example 7

Using FIG. 45, an example 7 of the read operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

At time T25, the memory controller 20 asserts the signal NP. During the assertion of the signal NP, the signal EN is kept at a "high" level.

At time T26 after the time period t _CALS elapses from time T25, the read command "05h" is issued.

After determining the read operation, at time T27, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the selection LUN 100 becomes "low".

<5-4-4> Read operation example 8

Using FIGS. 46 to 48, an example 8 of the read operation of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in the read operation example 8 is the same as that in the read operation example 7, so the description thereof is omitted. Here, the falling timing of the signal EN of the LUN 100 will be described.

After determining the read action, at time T28, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the selection LUN 100 becomes "low".

As shown in FIG. 46, after receiving the column address R3, the signal EN in the LUN 100 becomes "low" immediately. Also, as shown in FIG. 47, the signal EN in the LUN 100 may immediately become "low" after receiving the command "E0h". Also, as shown in FIG. 48, the signal EN in the LUN 100 can be changed to "low" level according to the timing before and after the input and output of data.

<6> sixth embodiment

The sixth embodiment will be described. In the sixth embodiment, another configuration of the input/output interface will be described. Furthermore, the basic configuration and basic operation of the memory device of the sixth embodiment are the same as those of the memory devices of the first and fifth embodiments described above. Therefore, the description of the matters described in the above-mentioned first and fifth embodiments and the matters that can be inferred from the above-mentioned first and fifth embodiments will be omitted.

<6-1> Composition of input and output interface

As shown in FIG. 49, the input-output interface 101 of the memory system 1 of the first embodiment and the input-output interface 101 of the memory system 1 of the fifth embodiment can be combined.

Furthermore, as shown in FIG. 49, it is possible to select which of the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the fifth embodiment is to be used by a switch circuit 101t. The signal EN of the person. For example, by using the Set Feature action and so on, the signal MS is generated and input to the switch circuit 101t to select the output signal. The "setting feature" operation is the same as that described using FIG. 30 .

<7> seventh embodiment

A seventh embodiment will be described. In the seventh embodiment, another configuration of the receiver will be described. Furthermore, the basic configuration and basic operation of the memory device of the seventh embodiment are the same as those of the memory devices of the first to sixth embodiments described above. Therefore, the description of the matters described in the above-mentioned first to sixth embodiments and the matters that can be inferred from the above-mentioned first to sixth embodiments will be omitted. The receiver described below can be applied to each of the above-mentioned embodiments.

<7-1> The composition of the receiver

Another example of the receiver 120 will be described using FIG. 50 .

For example, during standby (when data is not being exchanged), it is preferable to suppress the consumption current in order to reduce power consumption. Therefore, in this embodiment, the receiver 120 includes a first receiver 101v that cannot operate at high speed but consumes a low current, a second receiver 101w that can operate at high speed but consumes a high current, and selects the first receiver 101v. The switch circuit 101u connecting the device 101v and the second receiver 101w.

The switch circuit 101u connects the data input and output lines to the first receiver 101v when the signal EN is at a "low" level, and connects the data input and output lines to the second receiver 101v when the signal EN is at a "high" level. Receiver 101w.

<7-2> The composition of the first receiver

A circuit example of the first receiver 101v will be described using FIG. 51 .

As shown in FIG. 51, the first receiver 101v includes a PMOS (Positive-channel Metal Oxide Aemiconductor: positive channel metal oxide semiconductor) transistor 11a and an NMOS (Negative-channel Metal Oxide Semiconductor: negative channel metal oxide semiconductor). material semiconductor) transistor 11b inverter.

The power supply voltage VDD is applied to the source of the PMOS transistor 11a, the drain is connected to the output terminal (node N2), and the gate is connected to the input terminal (node N1). The drain of the NMOS transistor 11b is connected to the output terminal (node N2), the source is connected to the ground potential, and the gate is connected to the input terminal (node N1).

That is, the first receiver 101v outputs a "high" level signal from the output terminal when the input signal is "low" level, and outputs a "high" level signal from the output terminal when the input signal is "high" level. "Low" level signal.

<7-3> The composition of the second receiver

A circuit example of the second receiver 101w will be described using FIG. 52 .

As shown in FIG. 52, the second receiver 101w includes a mirror circuit including PMOS transistors 11c, 11d, 11e, and 11f and NMOS transistors 11g, 11h, and 11i.

The power supply voltage VDD is applied to the source of the PMOS transistor 11c, and the signal ENBn (an inverted signal of the signal EN) is input to the gate. The PMOS transistor 11c flows current when the signal ENBn is at a "low" level.

The source of the PMOS transistor 11e is connected to the drain of the PMOS transistor 11c, and the drain is connected to the gate.

The power supply voltage VDD is applied to the source of the PMOS transistor 11d, and the signal ENBn is input to the gate. The PMOS transistor 11d flows current when the signal ENBn is at a "low" level.

The source of the PMOS transistor 11f is connected to the drain of the PMOS transistor 11d, and the drain is connected to the output terminal (node N6), and the gate is connected to the node N5. The PMOS transistor 11f flows the same current as the PMOS transistor 11e.

The drain of the NMOS transistor 11g is connected to the node N5, the source is connected to the node N7, and The gate applies a reference voltage VREF. The NMOS transistor 11g flows a reference current.

The drain of the NMOS transistor 11h is connected to the output terminal (node N6), the source is connected to the node N7, and the gate is connected to the input terminal.

The drain of the NMOS transistor 11i is connected to the node N7, the source is connected to the ground potential, and the reference voltage IREFN is applied to the gate. The above-mentioned NMOS transistor 11i functions as a constant current source.

That is, the second receiver 101w outputs a signal of a "high" level from the output terminal when the signal ENBn is at a "low" level and the input signal is at a "low" level, and when the signal ENBn is at a "low" level When it is accurate and the input signal is "high" level, a "low" level signal is output from the output terminal.

<8>Supplementary instructions

Furthermore, FIG. 53 shows the conditions for the signal EN to rise (to activate all the LUNs 100 ) in each of the above-mentioned embodiments.

In addition, in each of the above-mentioned embodiments, various descriptions have been given for the falling timing of the signal EN, but it is not limited to the above-mentioned timing and can be changed as appropriate. Specifically, it is only necessary that the timing signal EN falls before and after the start of data input and output. Thereby, it is possible to suppress consumption of useless current to non-selected LUNs or LUNs during a read operation.

Also, in each embodiment of the present invention:

(1) In the read operation, the voltage applied to the selected word line for the A level read operation is, for example, between 0V~0.55V. It is not limited thereto, and may be any one of 0.1V-0.24V, 0.21V-0.31V, 0.31V-0.4V, 0.4V-0.5V, and 0.5V-0.55V.

The voltage applied to the selected word line for the read operation of the B level is, for example, 1.5V~2.3V between. It is not limited thereto, and may be any one of 1.65V-1.8V, 1.8V-1.95V, 1.95V-2.1V, or 2.1V-2.3V.

The voltage applied to the selected word line for the read operation of the C level is, for example, between 3.0V~4.0V. It is not limited thereto, and may be any one of 3.0V-3.2V, 3.2V-3.4V, 3.4V-3.5V, 3.5V-3.6V, or 3.6V-4.0V.

The time (tR) of the readout operation can also be set between, for example, 25 μs to 38 μs, 38 μs to 70 μs, or 70 μs to 80 μs.

(2) The write operation includes a program operation and a verify operation as described above. In the writing operation, the voltage initially applied to the selected word line in the programming operation is, for example, between 13.7V~14.3V. It is not limited thereto, and may be set, for example, between any one of 13.7V to 14.0V and 14.0V to 14.6V.

It is also possible to change the initial voltage applied to the selected word line when writing to the odd-numbered word line and the initial voltage applied to the selected word line when writing to the even-numbered word line.

When the programming operation is set to the ISPP method (Incremental Step Pulse Program: Incremental Step Pulse Program), the boosted voltage is, for example, about 0.5V.

The voltage applied to the non-selected word lines may be, for example, between 6.0V and 7.3V. It is not limited thereto, and may be set, for example, between 7.3V to 8.4V, or may be set below 6.0V.

It is also possible to change the applied pass voltage according to whether the unselected word line is an odd-numbered word line or an even-numbered word line.

The writing operation time (tProg) may be, for example, set between 1700 μs to 1800 μs, 1800 μs to 1900 μs, and 1900 μs to 2000 μs.

(3) During the erasing action, The voltage initially applied to the wafer formed on the upper part of the semiconductor substrate and on which the above-mentioned memory cells are arranged is, for example, between 12V and 13.6V. It is not limited to the above-mentioned cases, and may be set between, for example, 13.6V-14.8V, 14.8V-19.0V, 19.0-19.08V, or 19.8V-21V.

The erasing operation time (tErase) can also be set, for example, between 3000 μs˜4000 μs, 4000 μs˜5000 μs, and 4000 μs˜9000 μs.

(4) The structure of the memory cell has a charge storage layer arranged on a semiconductor substrate (silicon substrate) through a tunnel insulating film with a thickness of 4~10nm. The above-mentioned charge storage layer may be a multilayer structure of an insulating film such as SiN or SiON with a film thickness of 2-3 nm, and polysilicon with a film thickness of 3-8 nm. In addition, metals such as Ru may be added to polysilicon. There is an insulating film on the charge storage layer. The above-mentioned insulating film has, for example, a lower layer High-k (high dielectric constant) film with a film thickness of 3-10 nm, and silicon oxide with a film thickness of 4-10 nm sandwiched between the upper layer High-k film with a film thickness of 3-10 nm. membrane. Examples of the High-k film include HfO and the like. Also, the film thickness of the silicon oxide film can be made thicker than the film thickness of the High-k film. On the insulating film, a control electrode with a film thickness of 30nm~70nm is formed by a material with a film thickness of 3~10nm. Here, the material for adjusting the work function is, for example, a metal oxide film such as TaO or a metal nitride film such as TaN. As the control electrode, W or the like can be used.

Also, an air gap can be formed between the memory cells.

As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, Various changes can be implemented in the range which does not deviate from the summary. Furthermore, the above-mentioned embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, if some constituent elements are removed from the disclosed constituent elements and a specific effect can still be obtained, it can also be extracted as an invention.

101: Input and output interface

101c: NAND operation circuit

101d: Inverter

101g: NAND operation circuit

101h: NAND operation circuit

101i: NAND operation circuit

101j: OR operation circuit

104: instruction register

105: Address register

105a: memory department

120: Receiver

ADD: address

ALE: address latch enable signal

BWE: write enable signal

CLE: command latch enable signal

DQ: Input and output signals

EN:Signal

Claims (16)

A memory device comprising: a memory cell array, which is configured to store data; a data input and output interface, wherein instructions, addresses, and data to be written to the memory cell array are input from an external controller to the data input and output interface , and the data read from the above-mentioned memory cell array is output from the above-mentioned data input-output interface to the above-mentioned external controller; a transmitter, which is connected to the above-mentioned data input-output interface, and is configured to be driven by an enabling signal; and a control circuit, which It is composed of: in response to the reception of a read command when the first control signal is asserted and the reception of a read address following the read command when the second control signal is asserted, the memory cell array is executed. Read operation; wherein before receiving the read command, when the first signal and the second signal are simultaneously asserted (concurrent assertion), the enable signal is set to the first level, and at least after receiving the above After reading the command, it maintains the above-mentioned 1st level. The memory device according to claim 1, which further includes: a command register (command register), which is configured to store instructions; and an address register (address register), which is configured to store addresses, wherein the first signal A signal for causing the command register to store the command is included, and the second signal includes a signal for making the address register to store the address. The memory device according to claim 2, wherein the enabling signal is set to the first level based on the result of a first logical operation, the first logical operation is a logical operation between an instruction and the result of a second logical operation, and the first logical operation 2. The logical operation result is a logical operation between the first signal and the second signal. The memory device according to claim 3, wherein the logic operation of the result of the first logic operation is an RS flip-flop (Reset and Set flip flop), and the logic operation of the result of the second logic operation is a NAND gate (NAND gate). The memory device according to claim 1, wherein the above-mentioned transmitter outputs the above-mentioned data read from the above-mentioned memory cell array through the above-mentioned data input-output interface. The memory device according to claim 5, wherein the data read from the memory cell array is sent together with a data strobe signal through the data input and output interface. The memory device according to claim 6, wherein when the first signal and the second signal are simultaneously asserted, upon toggle of the third signal, the enabling signal is set to the first level. The memory device according to claim 7, further comprising: an instruction register, which is configured to store instructions; and an address register, which is configured to store addresses; wherein the above-mentioned first signal is used to temporarily store the above-mentioned instructions The second signal includes a signal for storing an address in the address register, and the third signal includes a signal for making the memory device take an instruction or data. A memory device comprising: a memory cell array, which is configured to store data; a data input and output interface, wherein instructions, addresses, and data to be written to the memory cell array are input from an external controller to the data input and output interface , and the data read from the above-mentioned memory cell array is output from the above-mentioned data input-output interface to the above-mentioned external controller; the receiver, which is connected to the above-mentioned data input-output interface, and is configured to be driven by an enabling signal; and the control circuit, which It is composed of: in response to the reception of the write command when the first control signal is asserted, the reception of the write address following the write command when the second control signal is asserted, and the above-mentioned first control signal and the above-mentioned second When the control signals are not established, following the reception of the above-mentioned data to be written into the above-mentioned memory cell array after the above-mentioned write-in address, the above-mentioned memory cell array is executed to write; wherein before the above-mentioned write command is received, When the above-mentioned first signal and the above-mentioned second signal are asserted at the same time, the above-mentioned enable signal is set to the first level, and at least when the above-mentioned write After the command is entered, it remains at the first level above. The memory device according to claim 9, which further includes: an instruction register configured to store instructions; and an address register configured to store addresses; wherein the first signal includes a register for temporarily storing the above-mentioned instructions The second signal includes a signal for storing the address in the address register. The memory device according to claim 10, wherein the enable signal is set to the first level based on a result of a first logical operation, the first logical operation is a logical operation between an instruction and a result of a second logical operation, and the first logical operation 2. The logical operation result is a logical operation between the first signal and the second signal. The memory device according to claim 11, wherein the logic operation of the result of the first logic operation is an RS flip-flop, and the logic operation of the result of the second logic operation is a NAND gate. The memory device according to claim 9, wherein the receiver receives the data to be written into the memory cell array through the data input and output interface. Such as the memory device of claim 13, wherein the above-mentioned data to be written into the above-mentioned memory cell array is through the above-mentioned data input and output interface Received together with the data strobe signal. The memory device according to claim 14, wherein when the first signal and the second signal are asserted at the same time, when the third signal is switched, the enabling signal is set to the first level. The memory device according to claim 15, further comprising: a command register configured to store instructions; and an address register configured to store addresses; wherein the first signal includes a command register for temporarily storing the command The second signal includes a signal for making the address register store an address, and the third signal includes a signal for making the memory device accept instructions or data.

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