TWI608349B - Memory device - Google Patents

Description

Memory device

The embodiment relates to a memory device.

As a memory device, a NAND (Not-AND) type flash memory is known.

The memory device of the embodiment includes: a memory cell array, the memory data; a control circuit that controls the memory cell array in response to the command; and a receiver based on the operation result of the first signal, the second signal, or the address and the instruction It becomes the startup state and can receive instructions or data.

01h‧‧‧Write instruction

05h‧‧‧Read instructions

1‧‧‧ memory system

10‧‧‧NAND flash memory

11a‧‧‧ PMOS transistor

11b‧‧‧NMOS transistor

11c~11f‧‧‧ PMOS transistor

11g~11i‧‧‧NMOS transistor

20‧‧‧ memory controller

30‧‧‧Host machine

80h‧‧‧write instructions

100‧‧‧LUN

101‧‧‧Input and output interface

101a‧‧‧AND operation circuit

101b‧‧‧OR operation circuit

101c‧‧‧NAND computing circuit

101d‧‧‧Inverter

101g‧‧‧NAND computing circuit

101g1‧‧‧NAND computing circuit

101h‧‧‧NAND computing circuit

101i‧‧‧NAND computing circuit

101j‧‧‧OR operation circuit

101k‧‧‧NAND computing circuit

101l‧‧‧NAND computing circuit

101m‧‧‧NAND computing circuit

101n‧‧‧Inverter

101o‧‧‧AND operation circuit

101p‧‧‧OR operation circuit

101q‧‧‧Switch circuit

101r‧‧‧Switch circuit

101s‧‧‧OR operation circuit

101t‧‧‧Switch circuit

101u‧‧‧Switch circuit

101v‧‧‧1st receiver

101w‧‧‧2nd Receiver

102‧‧‧Control signal input interface

103‧‧‧Control circuit

104‧‧‧ instruction register

104a‧‧‧Memory Department

105‧‧‧ address register

105a‧‧‧Memory Department

106‧‧‧Status register

110‧‧‧ memory cell array

111‧‧‧Sense Amplifier

112‧‧‧data register

113‧‧‧ line decoder

114‧‧‧ line buffer

115‧‧‧ column address decoder

116‧‧‧ column address buffer decoder

120‧‧‧ Receiver

130‧‧‧transmitter

210‧‧‧Host Interface (Host I/F)

220‧‧‧Internal memory (RAM)

230‧‧‧Processor (CPU)

240‧‧‧Buffered memory

250‧‧‧NAND interface (NAND I/F)

ADD‧‧‧ address

ALE‧‧‧ address latching enable signal

BCE‧‧‧ wafer enabling signal

BDQS‧‧‧ data strobe signal

BRE‧‧‧ reading enable signal

BWE‧‧‧Write enable signal

BWP‧‧‧ write protection signal

C1‧‧‧ address

C2‧‧‧ address

CLE‧‧‧ instruction latching enable signal

CMD‧‧ directive

D0~Dn‧‧‧Write data

DQ‧‧‧ input and output signals

DQ0~DQ7‧‧‧ input and output signals

DQS‧‧‧ data strobe signal

E0h‧‧‧ Directive

EFh‧‧ directive

ENBn‧‧‧ signal

EN‧‧‧ signal

FFh‧‧‧ initialization instructions

GP0‧‧‧ memory group

GP1‧‧‧ memory group

IREFN‧‧‧reference voltage

MS‧‧‧ signal

N1~N7‧‧‧ nodes

NP‧‧ signal

R1~R3‧‧‧ column address

RE‧‧‧Reading enable signal

RY/BBY‧‧‧ is ready. Busy signal

T0~T29‧‧‧ moment

t _CALS ‧‧‧

VDD‧‧‧Power supply voltage

VREF‧‧‧reference voltage

W-B0~W-B3‧‧‧Information

XXh‧‧ directive

YYh‧‧ directive

^~ ALE‧‧‧Reverse signal

^~ BCE‧‧‧Reverse signal

^~ BWE‧‧‧Reverse signal

^~ BWP‧‧‧Reverse signal

^~ CLE‧‧‧Reverse signal

Fig. 1 is a block diagram of a memory system of the first embodiment.

Fig. 2 is a block diagram showing a LUN of the memory system of the first embodiment.

Fig. 3 is a circuit diagram showing an input/output interface of the memory system of the first embodiment.

Fig. 4 is a schematic view showing the operation of the memory system of the first embodiment.

Fig. 5 is a timing chart showing an example of a write operation of the memory system of the first embodiment.

Fig. 6 is a timing chart showing an example of the reading operation of the memory system of the first embodiment.

Fig. 7 is a circuit diagram showing an input/output interface of the memory system of the second embodiment.

Fig. 8 is a timing chart showing an example of a write operation of the memory system of the second embodiment.

Fig. 9 is a timing chart showing an example of a write operation of the memory system of the second embodiment.

Fig. 10 is a timing chart showing an example of a write operation of the memory system of the second embodiment.

Fig. 11 is a timing chart showing an example of the reading operation of the memory system of the second embodiment.

Fig. 12 is a timing chart showing an example of the reading operation of the memory system of the second embodiment.

Fig. 13 is a timing chart showing an example of the reading operation of the memory system of the second embodiment.

Fig. 14 is a timing chart showing an example of the reading operation of the memory system of the second embodiment.

Fig. 15 is a timing chart showing an example of a write operation of the memory system according to the first modification of the second embodiment.

Fig. 16 is a timing chart showing an example of the reading operation of the memory system according to the first modification of the second embodiment.

Fig. 17 is a circuit diagram showing an input/output interface of a memory system according to a second modification of the second embodiment.

Fig. 18 is a circuit diagram showing an input/output interface of the memory system of the third embodiment.

Fig. 19 is a timing chart showing an example of a write operation of the memory system of the third embodiment.

Fig. 20 is a timing chart showing an example of a write operation of the memory system of the third embodiment.

Fig. 21 is a timing chart showing an example of a write operation of the memory system of the third embodiment.

Fig. 22 is a timing chart showing an example of the reading operation of the memory system of the third embodiment.

Fig. 23 is a timing chart showing an example of the read operation of the memory system of the third embodiment.

Fig. 24 is a timing chart showing an example of the reading operation of the memory system of the third embodiment.

Fig. 25 is a timing chart showing an example of the reading operation of the memory system of the third embodiment.

Fig. 26 is a timing chart showing an example of a write operation of the memory system of the third embodiment.

Fig. 27 is a timing chart showing an example of the read operation of the memory system of the third embodiment.

Fig. 28 is a circuit diagram showing an input/output interface of a memory system according to a variation of the third embodiment.

Fig. 29 is a circuit diagram showing an input/output interface of the memory system of the fourth embodiment.

Fig. 30 is a view showing a mode selection operation of the memory system of the fourth embodiment.

Figure 31 is a circuit diagram showing an input/output interface of a memory system according to a first modification of the fourth embodiment.

Figure 32 is a circuit diagram showing an input/output interface of a memory system according to a second modification of the fourth embodiment.

Figure 33 is a circuit diagram showing an input/output interface of a memory system according to a third modification of the fourth embodiment.

Fig. 34 is a circuit diagram showing an input/output interface of the memory system of the fifth embodiment.

Fig. 35 is a timing chart showing an example of a write operation of the memory system of the fifth embodiment.

Fig. 36 is a timing chart showing an example of a write operation of the memory system of the fifth embodiment.

Fig. 37 is a timing chart showing an example of a write operation of the memory system of the fifth embodiment.

38 is a timing chart showing an example of the read operation of the memory system of the fifth embodiment.

Fig. 39 is a timing chart showing an example of the reading operation of the memory system of the fifth embodiment.

Fig. 40 is a timing chart showing an example of the reading operation of the memory system of the fifth embodiment.

Fig. 41 is a timing chart showing an example of the reading operation of the memory system of the fifth embodiment.

Fig. 42 is a timing chart showing an example of a write operation of the memory system according to a modification of the fifth embodiment.

Fig. 43 is a timing chart showing an example of a write operation of the memory system in a variation of the fifth embodiment.

Fig. 44 is a timing chart showing an example of a write operation of the memory system in a variation of the fifth embodiment.

Fig. 45 is a timing chart showing an example of the read operation of the memory system in the variation of the fifth embodiment.

Fig. 46 is a timing chart showing an example of the read operation of the memory system in the variation of the fifth embodiment.

Fig. 47 is a timing chart showing an example of the reading operation of the memory system in the variation of the fifth embodiment.

Fig. 48 is a timing chart showing an example of the reading operation of the memory system in the variation of the fifth embodiment.

Fig. 49 is a circuit diagram showing an input/output interface of the memory system of the sixth embodiment.

Fig. 50 is a circuit diagram showing a receiver of the memory system of the seventh embodiment.

Fig. 51 is a circuit diagram showing a first receiver of the memory system of the seventh embodiment.

Fig. 52 is a circuit diagram showing a second receiver of the memory system of the seventh embodiment.

Fig. 53 is a view showing the operating conditions of the memory system of the first to fifth embodiments.

Hereinafter, embodiments will be described with reference to the drawings. In the description, the common reference numerals are attached to the common parts throughout the drawings.

<1> First Embodiment

The semiconductor memory device of the first embodiment will be described. Hereinafter, a NAND flash memory will be described as an example of a semiconductor memory device.

<1-1> Composition

<1-1-1> The overall composition of the memory system

First, a substantially overall configuration of a memory system including a semiconductor memory device of the present embodiment will be described with reference to Fig. 1 . Fig. 1 is a block diagram of a memory system of the embodiment.

As shown in FIG. 1, the memory system 1 includes a NAND flash memory 10 and a memory controller 20. For example, the NAND flash memory 10 and the memory controller 20 can constitute one semiconductor device by a combination of the above, and examples thereof include a memory card such as an SD card (Secure Digital Card), or SSD (solid state drive), etc.

The NAND type flash memory 10 has a plurality of memory cell transistors instead of volatility memory data. The memory controller 20 is connected to the NAND-type flash memory 10 by a NAND bus, and is connected to the host machine 30 by a host bus. Further, the memory controller 20 controls the NAND-type flash memory 10 to access the NAND-type flash memory 10 in response to a command received from the host device 30. The host machine 30 is, for example, a digital camera or For personal computers, etc., the host bus is, for example, a bus that conforms to the SDTM (Study Data Tabulation Model) interface.

The NAND bus bar transmits and receives signals in accordance with the NAND interface. Specific examples of the signal are a wafer enable signal BCE, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal BWE, a read enable signal RE, a BRE, and a write protection signal BWP. , data strobe signal DQS, BDQS, input and output signal DQ, and ready. Busy signal RY/BBY. When it is not necessary to distinguish the above signals, it may be described only as a signal.

The wafer enable signal BCE is used to select a signal of a LUN (Logical Unit Number) 100 included in the NAND flash memory 10. The wafer enable signal BCE is asserted when the LUN 100 is selected ("Low" level).

The command latch enable signal CLE is used to notify the signal of the NAND type flash memory 10 that the input/output signal DQ of the NAND flash memory 10 is an instruction. The instruction latch enable signal CLE is asserted ("High" level (low <high)) when the instruction is captured to the NAND type flash memory 10.

The address latch enable signal ALE is used to notify the signal of the NAND type flash memory 10 that the input/output signal DQ of the NAND flash memory 10 is the address. The address latch enable signal ALE is asserted ("high" level) when the address is captured to the NAND type flash memory 10.

The write enable signal BWE is used to extract the input/output signal DQ to the signal of the NAND type flash memory 10. The write enable signal BWE is asserted when the input/output signal DQ is drawn to the NAND type flash memory 10 ("low" level).

The read enable signal RE is used to read out the signal of the input/output signal DQ from the NAND type flash memory 10. The complementary signal of the enable signal BRE is read RE. The read enable signals RE and BRE are asserted when the input/output signal DQ is read from the NAND type flash memory 10 (RE = "high" level, BRE = "low" level).

The write protection signal BWP is used to protect the data from accidental erasure or write signals when the input signal of the NAND flash memory 10 is turned on or when the power is turned off. . The write protection signal BWP is asserted when the data is protected ("low" level).

The input/output signal DQ is, for example, an 8-bit signal. Further, the input/output signal DQ is an instruction for transmitting and receiving between the NAND flash memory 10 and the memory controller 20, an address, a write data, and a read data.

The data strobe signal DQS is a signal for transmitting and receiving the input/output signal DQ (data) between the memory controller 20 and the NAND type flash memory 10. The data strobe signal BDQS is a complementary signal of DQS. The NAND type flash memory 10 receives the input/output signal DQ (data) in accordance with the timing of the data strobe signals DQS and BDQS supplied from the memory controller 20. The memory controller 20 receives the input/output signal DQ (data) in accordance with the timing of the data strobe signals DQS and BDQS supplied from the NAND flash memory 10. The data strobe signals DQS and BDQS are established when the input/output signal DQ is transmitted and received (DQS = "low" level, BDQS = "high" level).

Ready. The busy signal RY/BBY indicates a signal that the LUN 100 is in a ready state (a state in which a command from the memory controller 20 can be received) or a busy state (a state in which a command from the memory controller 20 cannot be received). Ready. The busy signal RY/BBY is set to the "low" level in the case of a busy state.

<1-1-2> Composition of memory controller

The details of the configuration of the memory controller 20 will be described with reference to Fig. 1 . As shown in FIG. 1, the memory controller 20 includes a host interface (Host I/F) 210, a built-in memory (RAM: Random access memory) 220, and a processor (CPU: Central processing unit, central Processing unit) 230, buffer memory 240, and NAND interface (NAND I/F) 250.

The host interface 210 is connected to the host machine 30 via the host bus, and will be from the host The commands and data received by the machine 30 are transmitted to the processor 230 and the buffer memory 240, respectively. The host interface 210 responds to the commands of the processor 230 and transfers the data in the buffer memory 240 to the host machine 30.

The processor 230 controls the overall operation of the memory controller 20. For example, processor 230, upon receiving a write command from host machine 30, issues a write command to NAND interface 250 in response thereto. The same is true for reading and erasing. The processor 230 performs various processes for managing the NAND-type flash memory 10 such as wear leveling and the like.

The NAND interface 250 is connected to the NAND-type flash memory 10 via a NAND bus, and is responsible for communication with the NAND-type flash memory 10. Moreover, based on the command received from the processor 230, the wafer enable signal BCE, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal BWE, the read enable signal RE, The BRE, the write protection signal BWP, and the data strobe signals DQS, BDQS are output to the NAND type flash memory 10. At the time of writing, the write command issued by the processor 230 and the write data in the buffer memory 240 are transferred to the NAND flash memory 10 as the input/output signal DQ. Further, at the time of reading, the read command issued by the processor 230 is transmitted to the NAND flash memory 10 as the input/output signal DQ, and the data read from the NAND flash memory 10 is used as the input/output signal DQ. Receive and transfer to buffer memory 240.

The buffer memory 240 temporarily keeps writing data or reading data.

The internal memory 220 is a semiconductor memory such as a DRAM (Dynamic Random Access Memory) and is used as a work area of the processor 230. Further, the internal memory 220 is held to manage the firmware of the NAND-type flash memory 10, various management tables, and the like.

<1-1-3>NAND type flash memory

<1-1-3-1> Composition of NAND flash memory

Next, the configuration of the NAND flash memory 10 will be described.

As shown in FIG. 1, the NAND flash memory 10 has a plurality of memory banks (in the example of FIG. 1, as an example, GP0 and GP1).

Each of the memory groups GP has a plurality of LUNs 100 (four in the example of FIG. 1 as an example). When distinguishing multiple LUNs 100, they are represented by the LUN (m: m is an arbitrary integer). Specifically, the memory group GP0 includes LUN(0) to LUN(3), and the memory group GP1 includes LUN(4) to LUN(7). LUN100 is the smallest unit that can be independently controlled. The LUN 100 may have at least one memory chip, and may have two or more memory chips. In the present embodiment, a case where the LUN 100 has one memory chip will be described.

In the present embodiment, it is assumed that a separate wafer enable signal BCE is input to each of the memory banks GP. In other words, the same wafer enable signal BCE is input to the LUN 100 in the same memory group GP.

In a memory group GP, the LUN 100 of the action may be one or plural.

<1-1-3-2>Composition of LUN100

Next, the configuration of the LUN 100 will be described using FIG.

The memory controller 20 and the LUN 100 are connected via an input/output interface 101 and a control signal input interface 102.

The input/output interface 101 includes a receiver 120 and a transmitter 130. Further, the receiver 120 inputs an input/output signal (DQ0 to DQ7) via a data input/output line (a wiring for transmitting and receiving the input/output signal DQ among the NAND bus bars). The transmitter 130 outputs input and output signals (DQ0 to DQ7) via data input and output lines.

The input/output interface 101 outputs the data strobe signals DQS and BDQS to the memory controller 20 when the input/output signals (DQ0 to DQ7) are output from the data input/output lines.

The control signal input interface 102 receives the wafer enable signal from the memory controller 20 BCE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal BWE, read enable signal RE, BRE, write protection signal BWP, and data strobe signals DQS, BDQS.

Although not shown in FIG. 2, the LUN 100 is also provided with a Vcc/Vss/Vccq/Vssq terminal for power supply.

The control circuit 103 outputs the material read from the memory cell array 110 to the memory controller 20 via the input/output interface 101. The control circuit 103 receives the write, read, erase, and state via the control signal input interface 102. Read various instructions, addresses, and write data.

The control circuit 103 controls an instruction register 104, an address register 105, a status register 106, a sense amplifier (Sense amp) 111, and a data register (Data). Register 112, a column decoder 113, and a row address decoder 115.

The control circuit 103 supplies the desired voltage to the memory cell array 110, the sense amplifier 111, and the column decoder 115 during data programming, verifying, reading, and erasing.

The instruction register 104 memorizes instructions input from the control circuit 103.

The address register 105 memorizes, for example, the address supplied from the memory controller 20. Moreover, the address register 105 converts the memory address into an internal physical address (row address and column address). The address register 105 then supplies the row address to the column buffer 114 and the column address to the Row address buffer decoder 116.

The status register 106 is used to notify various parties of various states inside the LUN 100. The status register 106 has a ready/busy register (not shown) that holds information indicating which of the LUN 100 is in the ready/busy state, and a write status that holds the data indicating the pass/fail of the write. Memory (not shown), etc.

The memory cell array 110 includes a plurality of bit lines BL, a plurality of word lines WL, and a source Polar line SL. The memory cell array 110 is composed of a plurality of blocks BLK in which a memory cell (also referred to simply as a memory cell) MC that can be electrically rewritten is arranged in a matrix. The memory cell MC system has, for example, a gate electrode including a control gate electrode and a charge storage layer (for example, a floating gate electrode), and changes in a threshold value of a transistor determined by the amount of charge injected into the floating gate electrode. Memory binary, or multi-value data. Further, the memory cell MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure having electrons trapped in a nitride film.

Further, the configuration of the memory cell array 110 may be other configurations. In other words, the configuration of the memory cell array 110 is described, for example, in U.S. Patent Application Serial No. 12/407,403, filed on March 19, 2009, which is incorporated herein by reference. Further, it is described in U.S. Patent Application Serial No. 12/406,524, filed on March 18, 2009, which is incorporated herein to U.S. Patent Application Serial No. 12/ 679, 991, filed on March 25, the entire disclosure of which is incorporated herein by reference. The patent applications are hereby incorporated by reference in their entirety in their entirety in their entireties in the the the the the the the

The sense amplifier 111 senses the data read from the memory cell MC to the bit line during the read operation of the data.

The data register 112 is configured by SRAM (Static Random Access Memory), etc. The data register 112 memorizes data supplied from the memory controller 20 or is detected by the sense amplifier 111. Verification results, etc.

The row decoder 113 decodes the row address signal stored in the line buffer 114, and outputs a selection signal of any one of the selected bit lines BL to the sense amplifier 111.

The line buffer 114 temporarily memorizes the row address signal input from the address register 105.

The column address decoder 115 decodes the column address signals input via the column address buffer decoder 116. Moreover, column address decoder 115 selects word line WL that drives memory cell array 110. And select the gate line SGD, SGS.

The column address buffer decoder 116 temporarily stores the column address signals input from the address register 105.

<1-1-3-3> Composition of input and output interface

Next, the configuration of the input/output interface 101 will be specifically described using FIG.

As shown in FIG. 3, the input/output interface 101 performs input and output signals based on the instruction latch enable signal CLE, the address latch enable signal ALE, and the signal from the instruction register 104 or the address register 105. DQ input and output.

Specifically, the instruction register 104 outputs the command CMD stored in the memory unit 104a to the AND (AND) operation circuit 101a of the input/output interface 101 based on the write enable signal BWE. The instruction register 104 maintains a "high" level state prior to inputting the next instruction when outputting the instruction CMD. The address register 105 outputs the address ADD stored in the memory unit 105a to the AND operation circuit 101a of the input/output interface 101 based on the write enable signal BWE. The address register 105 maintains a "high" level state when it selects its own LUN 100.

The AND operation circuit 101a outputs the operation result to the OR (OR) operation circuit 101b based on the instruction CMD and the address ADD. The AND operation circuit 101a outputs a signal of "high" level only when the command CMD and the address ADD are both "high".

The OR operation circuit 101b generates a signal EN based on the operation result of the AND operation circuit 101a, the instruction latch enable signal CLE, or the address latch enable signal ALE. The OR operation circuit 101b outputs the "low" level only when the operation result of the AND operation circuit 101a, the instruction latch enable signal CLE, and the address latch enable signal ALE are all "low" levels. Signal EN. In other words, when the OR operation circuit 101b outputs "high" when at least one of the operation result of the AND operation circuit 101a, the instruction latch enable signal CLE, and the address latch enable signal ALE is "high" level. Level signal EN. In the following, sometimes the signal EN is set to "high" level from the "low" level as "upper" "L", and the signal EN is set to "low" level from the "high" level to "down".

The receiver 120 receives the input and output signal DQ inside the LUN 100 based on the signal EN and the input and output signal DQ. Specifically, the NAND operation circuit 101c generates a signal based on the signal EN supplied from the OR operation circuit 101b and the input/output signal DQ supplied from the memory controller 20. The NAND operation circuit 101c generates a signal of a "low" level only when the signal EN and the input/output signal DQ are both "high". Further, the inverter 101d inverts and outputs the operation result of the NAND operation circuit 101c. That is, the receiver 120 receives the input/output signal DQ inside the LUN 100 only when the signal EN and the input/output signal DQ are both "high".

Hereinafter, the state of the signal EN to which the "high" level is input to the receiver 120 is described as "starting state", and the state of the signal EN to which the "low" level is input may be described as "standby state". When the receiver 120 is in the startup state, it is in a state capable of receiving the input/output data DQ. Further, when the receiver 120 is in the standby state, the input/output data DQ cannot be received.

<1-2> action

<1-2-1> Summary of the operation of the memory system

The outline of the operation of the memory system of the present embodiment will be described with reference to Fig. 4 .

In FIG. 4, focusing on the operation of the memory group GP0, an outline of the operation of changing the access (write operation, read operation, etc.) from LUN (0) to LUN (1) will be described. As shown in Figure 4, the signal EN in the LUN(0) in the access to the LUN(0) becomes the "high" level, and the signal EN in the LUN(1)~LUN(3) becomes the "low" level. . That is, in the access to the LUN (0), the receiver 120 of the LUN (0) is set to the startup state, and the receiver 120 of the LUN (1) to the LUN (3) is set to the standby state.

Further, at time T0, the memory system 1 performs a LUN switching operation. At this time, at least the signal EN in all the LUNs (LUN(0) to LUN(3)) in the memory group GP0 becomes the "high" level. That is, at least when all the memory groups GP0 are in the LUN switching operation The receiver 120 in the LUN (LUN(0)~LUN(3)) is set to the startup state.

At time T1, if the address of the LUN (1) is determined to be the selected LUN address, access to the LUN (1) is started. The signal EN in the LUN (1) in the access to the LUN (1) becomes the "high" level, and the signal EN in the LUN (0), LUN (2), and LUN (3) becomes the "low" level. That is, in the access to the LUN (1), the receiver 120 of the LUN (1) is set to the startup state, and the receiver 120 of the LUN (0), LUN (2), and LUN (3) is set to the standby state. .

<1-2-2> Write operation example 1

The write operation example 1 of the memory system 1 of the present embodiment will be described with reference to Fig. 5 . Here, the instruction sequence of the memory group GP0 will be described.

At time T2, memory controller 20 asserts ("high" level) command latch enable signal CLE. At time T2, the wafer enable signal BCE is asserted ("low" level). If the command latch enable signal CLE is asserted, the signal EN becomes "high" level as illustrated in FIG.

The LUN 100 must wait for the period t _CALS , which is established as the self-instruction latch enable signal CLE for the period required for the setting of the command input.

Period from the time T2 to the time t elapsed after the _CALS T3, the memory controller 20 issuing an instruction "01h" and "80h".

The command "01h" is an instruction issued in the case where the memory cell MC can hold the 3-bit data. More specifically, the instruction "01h" specifies the instruction of page 1. Here, the command "01h" is described as an example, but is not limited thereto. Other instructions may also be input if the memory controller 20 specifies other pages. The instruction "80h" is used to specify the instruction of the write action.

The memory controller 20 asserts ("low" level) write enable signal BWE whenever a signal such as an instruction, address, and data is issued. Moreover, each time the write enable signal BWE is thixotropic, the signal is captured to the LUN 100.

Next, the memory controller 20 issues the address, for example, across 5 cycles (C1, C2: row position) Address, R1~R3: column address), and establish ("high" level) address latch enable signal ALE.

When the address is issued, the instruction latch enable signal CLE is negated ("low" level), but the address latch enable signal ALE is asserted. If the address latch enable signal ALE is asserted, the signal EN becomes a "high" level as illustrated in FIG. That is, the LUN 100 maintains the signal EN at the "high" level when receiving the address.

However, by, for example, the column address R3 includes a selection LUN address and the column address R3 is supplied to the LUN 100, the LUN 100 determination is selected. If the LUN 100 determination is selected, the address latch circuit 105 outputs a "high" level signal in the selection LUN 100 as illustrated in FIG. As a result, the signal EN in the LUN 100 is selected to maintain the "high" level. On the other hand, in the non-selected LUN 100, the address latch circuit 105 outputs a signal of a "low" level. As a result, the signal EN in the LUN 100 is selected to become a "low" level. In other words, the receiver 120 of the selected LUN 100 is maintained in the active state, and the receiver 120 of the non-selected LUN 100 is in the standby state.

Next, the memory controller 20 outputs the write data (D0 to Dn) across a plurality of cycles. During this period, the signals ALE and CLE are negated ("L" level). The write data received by LUN 100 is held in a page buffer within sense amplifier 111.

Although not shown in FIG. 5, the memory controller 20 issues the write command "10H" and asserts the command latch enable signal CLE. When the command "10h" is received, the control circuit 103 starts the write operation, and the LUN 100 becomes busy (RY/BBY = "low" level).

<1-2-3> Read operation example 1

The read operation example 1 of the memory system 1 of the present embodiment will be described with reference to Fig. 6 . Here, the instruction sequence of the memory group GP0 will be described.

At time T5, the memory controller 20 asserts the instruction latch enable signal CLE. At time T5, the wafer enable signal BCE is asserted. If the command latch enable signal CLE is asserted, the signal EN becomes a "high" level.

At time T6 after the period t _CALS elapses from time T5, the memory controller 20 issues a read command "05h".

Next, the memory controller 20 issues an address (C1, C2: row address, R1 to R3: column address), for example, across 5 cycles, and asserts ("high" level) address latch enable signal ALE.

The memory controller 20 issues the command "E0h". When the LUN 100 receives the command "E0h", the read operation is started.

The instruction register 104 recognizes that the action requested from the memory controller 20 is a read operation. Then, the instruction register 104 supplies a signal of "low" level to the AND operation circuit 101a (refer to FIG. 3). Thereby, the signal EN becomes a "low" level.

That is, the receiver 120 becomes a standby state.

<1-3> effect

According to the above embodiment, the electrical connection between the LUN 100 and the data input/output line is appropriately controlled by using the address ADD, the command CMD, the instruction latch enable signal CLE, the address latch enable signal ALE, and the like.

For example, in the write operation, if the non-selected LUN 100 receives the write data, the useless current flows through the LUN 100. However, by adopting the above embodiment, the operating current of the non-selected LUN 100 can be suppressed.

Moreover, in the read operation, the LUN 100 does not need to receive data. By adopting the above embodiment, the operating current of the LUN 100 can be suppressed.

<2> Second embodiment

The second embodiment will be described. In the second embodiment, another configuration of the input/output interface will be described. The basic configuration and basic operation of the memory device of the second embodiment are the same as those of the memory device of the first embodiment described above. Therefore, the matters described in the first embodiment and the descriptions that can be analogized from the first embodiment will be omitted.

<2-1> Composition of input and output interface

Next, the configuration of the input/output interface 101 of the memory system of the second embodiment will be specifically described with reference to Fig. 7 .

As shown in FIG. 7, the input/output interface 101 performs input and output signals based on the instruction latch enable signal CLE, the address latch enable signal ALE, and the signal from the instruction register 104 or the address register 105. DQ input and output.

Specifically, the NAND operation circuit 101g outputs the operation result to the NAND operation circuit 101h based on the instruction latch enable signal CLE and the address latch enable signal ALE. The NAND operation circuit 101g generates a signal of a "low" level only when the instruction latch enable signal CLE and the address latch enable signal ALE are both "high" levels.

The NAND operation circuit 101h and the NAND operation circuit 101i constitute an RS flip-flop circuit. Specifically, the NAND operation circuit 101h outputs the calculation result based on the calculation results of the NAND operation circuit 101g and the NAND operation circuit 101i. The NAND operation circuit 101i outputs the operation result based on the operation result of the NAND operation circuit 101h and the signal (for example, the command CMD) from the instruction register 104.

The operation of the RS flip-flop circuit will be briefly described. When the signal from the NAND operation circuit 101g is "high" and the signal from the instruction register 104 is "low", the NAND operation circuit 101h outputs a "low" level signal. Further, when the signal from the NAND operation circuit 101g is "low" and the signal from the instruction register 104 is "high", the NAND operation circuit 101h outputs a signal of "high" level. Further, in a state where the output signal of the NAND operation circuit 101h is determined, the output signal of the NAND operation circuit 101h is held even if the signal from the NAND operation circuit 101g or the signal from the instruction register 104 changes.

The OR operation circuit 101j generates a signal EN based on the operation result of the NAND operation circuit 101h and the signal from the address register 105. The OR operation circuit 101j is only the operation result of the NAND operation circuit 101h, and the signal from the address register 105 is "low" level. In the case of the case, the signal EN of the "low" level is output. In other words, when the OR operation circuit 101j outputs a result of the NAND operation circuit 101h and at least one of the signals from the address register 105 is at the "high" level, the signal EN of the "high" level is output.

The receiver 120 receives the input/output signal DQ inside the LUN 100 only when the signal EN and the input/output signal DQ are both "high".

<2-2> action

The operation described in the first embodiment differs from the operation in the second embodiment in the method of raising the signal EN in the LUN 100.

In the memory system 1 of the first embodiment, the signal EN is raised based on the establishment of the command latch enable signal CLE. In the memory system 1 of the second embodiment, the signal EN is raised by simultaneously asserting the command latch enable signal CLE and the address latch enable signal ALE. At the same time, the action of asserting the instruction latch enable signal CLE and the address latch enable signal ALE becomes an action for raising the signal EN.

<2-2-1> Write operation example 2

The write operation example 2 of the memory system 1 of the present embodiment will be described with reference to Fig. 8 . Here, the instruction sequence of the memory group GP0 will be described.

At time T8, the memory controller 20 asserts the instruction latch enable signal CLE and the address latch enable signal ALE. Thereby, as explained using FIG. 7, the signal EN becomes a "high" level. Then, the memory controller 20 negates the instruction latch enable signal CLE and the address latch enable signal ALE. Therefore, since the input signal of the NAND operation circuit 101h changes, the input signal of the NAND operation circuit 101i does not change, and therefore the output signal of the NAND operation circuit 101h is maintained at the "high" level. As a result, the signal EN is maintained at the "high" level.

After the time t _CALS T9, memory controller 20 to issue write period from the time T8 after the command "01h" and "80h".

At time T10, if LUN100 is selected for determination, it is selected as illustrated in FIG. Within LUN 100, address latch circuit 105 outputs a "high" level signal. As a result, the signal EN in the LUN 100 maintains a "high" level. On the other hand, in the non-selected LUN 100, the address latch circuit 105 outputs a "low" level signal. As a result, the signal EN in the LUN 100 is selected to become the "low" level. In other words, the receiver 120 that selects the LUN 100 maintains the startup state, and the non-selected LUN 100 is set to the standby state.

The memory controller 20 issues an address (C1, C2: row address, R1 to R3: column address), for example, across 5 cycles, and asserts ("high" level) address latch enable signal ALE.

Next, the memory controller 20 outputs the write data (D0 to Dn) across a plurality of cycles. During this period, the signals ALE and CLE are negated. The write data received by LUN 100 is held in a page buffer within sense amplifier 111.

<2-2-2> Write operation example 3

The write operation example 3 of the memory system 1 of the present embodiment will be described with reference to Figs. 9 and 10 . Here, the instruction sequence of the memory group GP0 will be described.

The method of raising the signal EN in the write operation example 3 is the same as that in the write operation example 2, and thus the description thereof is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described.

For example, the selection LUN address is included in the column address R3. The selection of the LUN 100 is determined by supplying the column address R3 to the LUN 100. If LUN 100 is selected, the signal EN in the LUN 100 is selected to be maintained at the "high" level, and the signal EN in the non-selected LUN 100 is changed to the "low" level. In other words, the receiver 120 that selects the LUN 100 is maintained in the startup state, and the non-selected LUN 100 is set to the standby state.

As shown in FIG. 9, after receiving the column address R3, the signal EN in the non-selected LUN 100 immediately becomes a "low" level. As shown in FIG. 10, it is also possible to select the timing before and after the input and output of the data, instead of selecting the signal EN in the LUN 100 to become a "low" level.

<2-2-3> Read operation example 2

The read operation example 2 of the memory system 1 of the present embodiment will be described with reference to FIG. Bright. Here, the instruction sequence of the memory group GP0 will be described.

The rising method of the signal EN in the read operation example 2 is the same as that in the write operation example 2.

At time T13, the memory controller 20 asserts the instruction latch enable signal CLE and the address latch enable signal ALE. Thereby, as explained using FIG. 7, the signal EN becomes a "high" level.

The read command "05h" is issued at time T14 after the elapse of the period t _CALS from time T13.

When the command register 104 receives "05h", it recognizes that the operation requested from the memory controller 20 is a read operation. Then, the instruction register 104 supplies a signal of "low" level to the AND operation circuit 101a (refer to FIG. 3). Thereby, the signal EN becomes a "low" level.

That is, the receiver 120 becomes a standby state.

<2-2-4> Read operation example 3

The read operation example 3 of the memory system 1 of the present embodiment will be described with reference to Figs. 12 to 14 . Here, the instruction sequence of the memory group GP0 will be described.

The method of raising the signal EN in the read operation example 3 is the same as that of the read operation example 2, and thus the description thereof is omitted. Here, the timing of the falling of the signal EN of the LUN 100 will be described.

The instruction register 104 recognizes that the action requested from the memory controller 20 is a read operation. Then, the instruction register 104 supplies a signal of "low" level to the AND operation circuit 101a (refer to FIG. 3). Thereby, the signal EN becomes a "low" level.

That is, the receiver 120 becomes a standby state.

As shown in FIG. 12, after receiving the column address R3, the signal EN in the LUN 100 immediately becomes a "low" level. Further, as shown in FIG. 13, after receiving the command "E0h", the signal EN in the LUN 100 immediately becomes a "low" level. Moreover, as shown in FIG. 14, the timing before and after the input and output of the data can be made, and the signal EN in the LUN 100 becomes the "low" level.

<2-3> effect

According to the above embodiment, the receiver 120 of the plurality of LUNs 100 is activated by simultaneously establishing the command latch enable signal CLE and the address latch enable signal ALE.

As the input and output of the data is increased, the instruction address input cycle must be speeded up. For example, in the case of the first embodiment, when the input/output of the data is increased, the period required for the setting of the command input becomes insufficient from the establishment of the command latch enable signal CLE, and there is a shortage of time. The possibility of setting the problem. In other words, there is a possibility that the LUN 100 cannot be electrically connected to the data input/output line via the receiver 120 before the input of the command, and the possibility that the LUN 100 cannot properly receive the command is generated.

Therefore, in the present embodiment, the receiver 120 is set to the active state before the command latch enable signal CLE is established in order to input an instruction. Thereby, the substantial period t _CALS can be alleviated as compared with the first embodiment. Therefore, it is possible to provide a memory system capable of appropriately transmitting and receiving the input/output signal DQ in accordance with the increase in the speed of input and output of data.

<2-4> Variation 1 of the second embodiment

<2-4-1> Write operation example 4

The write operation example 4 of the memory system 1 of the present embodiment will be described with reference to Fig. 15 . Here, the instruction sequence of the memory group GP0 will be described.

The method of increasing the signal EN in the write operation example 4 is the same as the write operation example 2 in the second embodiment, and thus the description thereof is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described.

For example, the selection LUN address is included in the column address R3. The selection of the LUN 100 is determined by supplying the column address R3 to the LUN 100. As shown in FIG. 7, if the LUN 100 is selected and the command "XXh" is input, the output signal of the instruction register 104 becomes "low" level. On the other hand, in the selection LUN 100, the address register 105 maintains a "high" level signal. In the non-selected LUN 100, the address register 105 outputs a "low" level signal. Therefore, the signal EN in the LUN 100 is selected to maintain the "high" level, and the LUN 100 is not selected. The signal EN inside becomes a "low" level. In other words, the receiver 120 that selects the LUN 100 maintains the startup state, and the receiver 120 of the non-selected LUN 100 is set to the standby state.

<2-4-2> Read operation example 4

The read operation example 4 of the memory system 1 of the present embodiment will be described with reference to Fig. 16 . Here, the instruction sequence of the memory group GP0 will be described.

The method of raising the signal EN in the read operation example 4 is the same as that of the read operation example 2 of the second embodiment, and thus the description thereof is omitted. Here, the timing of the falling of the signal EN of the LUN 100 will be described.

When the command register 104 receives "XXh", it recognizes that the operation requested from the memory controller 20 is a read operation. Then, the instruction register 104 supplies a signal of "low" level to the AND operation circuit 101a (refer to FIG. 3). Thereby, the signal EN becomes a "low" level. That is, the receiver 120 becomes a standby state.

<2-5> Variation 2 of the second embodiment

The configuration of the input/output interface 101 of the memory system according to the second modification of the second embodiment will be specifically described with reference to Fig. 17 .

The input/output interface 101 shown in FIG. 17 is provided with a circuit for controlling the manner in which the receiver 120 is not electrically connected to the LUN 100 and the data input/output line when the data is output.

Specifically, as shown in FIG. 17, the input/output interface 101 is provided with a NAND arithmetic circuit 101k. Moreover, the NAND operation circuit 101k is based on the inverted signal of the instruction latch enable signal CLE ^~ CLE, the inverted signal of the address latch enable signal ALE ^~ ALE, the inverted signal of the wafer enable signal BCE ^~ BCE, write The signal BWE is energized, and the operation result is output to the NAND operation circuit 101l. The NAND operation circuit 101k generates a signal of a "low" level only when the signals ^~ CLE, ^~ ALE, ^~ BCE, and BWE are all "high" levels.

The NAND operation circuit 101l and the NAND operation circuit 101m constitute an RS flip-flop circuit. Specifically, the NAND operation circuit 101 l outputs the calculation result based on the calculation results of the NAND operation circuit 101k and the NAND operation circuit 101m. NAND operation circuit 101m base The operation result of the NAND operation circuit 101l and the read enable signal BRE are output, and the operation result is output.

The operation of the RS flip-flop circuit will be briefly described. When the signal from the NAND operation circuit 101k is at the "high" level and the read enable signal BRE is at the "low" level, the NAND operation circuit 101l outputs a signal of a "low" level. Further, when the signal from the NAND operation circuit 101k is at the "low" level and the read enable signal BRE is at the "high" level, the NAND operation circuit 101l outputs a signal of the "high" level. Further, in a state where the output signal of the NAND operation circuit 101l is determined, even if the signal from the NAND operation circuit 101k or the read enable signal BRE changes, the output signal of the NAND operation circuit 101l is held.

Further, the inverter 101n inverts the output signal of the NAND operation circuit 101l and supplies it to the AND operation circuit 101o.

The AND operation circuit 101o outputs the operation result to the OR operation circuit 101p based on the output signal of the inverter 101n and the signal from the address register 105. The AND operation circuit 101a outputs a signal of "high" level only when the output signal of the inverter 101n and the signal from the address register 105 are both "high".

The OR operation circuit 101p generates a signal EN based on the calculation results of the AND operation circuit 101o and the NAND operation circuit 101h. The OR operation circuit 101p outputs the signal "EN" of the "low" level only when the operation results of the AND operation circuit 101o and the NAND operation circuit 101h are both "low". In other words, when the OR operation circuit 101p is at the "high" level in at least one of the calculation results of the AND operation circuit 101o and the NAND operation circuit 101h, the signal EN of the "high" level is output.

During the output of the data, the signals ^~ CLE, ^~ ALE, ^~ BCE, BWE, and BREA all become "high" levels. As a result, the output signal of the NAND operation circuit 1011 outputs a signal of "high" level. As a result, during the output of the data, the signal EN becomes a "low" level.

As described above, the input/output interface 101 of the memory system according to the second modification of the second embodiment can be controlled such that the receiver 120 is not electrically connected to the LUN 100 and the data input/output line when the data is output.

<3> Third embodiment

The third embodiment will be described. In the third embodiment, another configuration of the input/output interface will be described. The basic configuration and basic operation of the memory device of the third embodiment are the same as those of the memory devices of the first and second embodiments described above. Therefore, the matters described in the first and second embodiments described above and the matters that can be analogized from the first and second embodiments will be omitted.

<3-1> Composition of input and output interface

Next, the configuration of the input/output interface 101 of the memory system of the third embodiment will be specifically described with reference to Fig. 18 . The input/output interface 101 of the memory system of the third embodiment is further input and output signals based on the inverted signal ^~ BWE of the write enable signal BWE, compared with the input/output interface 101 of the memory system of the second embodiment. DQ input and output.

Specifically, the NAND operation circuit 101g1 outputs the operation result to the NAND operation circuit 101h based on the signals CLE, ALE, and ^~ BWE. The NAND operation circuit 101g1 generates a signal of a "low" level only when the signals CLE, ALE, and ^~ BWE are all "high" levels.

<3-2> action

The operation described in the second embodiment differs from the operation of the third embodiment in the method of raising the signal EN in the LUN 100.

In the memory system 1 of the second embodiment, the signal EN is raised by simultaneously asserting the command latch enable signal CLE and the address latch enable signal ALE. On the other hand, in the memory system 1 of the third embodiment, the signal EN is asserted by simultaneously asserting the instruction latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE. rise. That is, the operations of simultaneously establishing the numbers CLE, ALE, and BWE become actions for raising the signal EN.

<3-2-1> Write operation example 5

The write operation example 5 of the memory system 1 of the present embodiment will be described with reference to Fig. 19 . Here, the instruction sequence of the memory group GP0 will be described.

At time T8, the memory controller 20 asserts the instruction latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE. Thereby, as explained using FIG. 18, the signal EN becomes a "high" level. Then, the memory controller 20 negates the instruction latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE. Therefore, since the input signal of the NAND operation circuit 101h changes, the input signal of the NAND operation circuit 101i does not change, and therefore the output signal of the NAND operation circuit 101h is maintained at the "high" level. As a result, the signal EN is maintained at the "high" level.

The operation after time T9 is the same as the operation described using FIG.

<3-2-2>Other access actions

As shown in FIG. 20, in the write operation example 3 described with reference to FIG. 9, the rising method of the signal EN in the write operation example 5 can be applied.

Similarly, as shown in FIG. 21, in the write operation example 3 described with reference to FIG. 10, the rising method of the signal EN in the write operation example 5 can be applied.

As shown in FIG. 22, in the write operation example 2 described with reference to FIG. 11, the rising method of the signal EN in the write operation example 5 can be applied.

Similarly, as shown in FIG. 23, the rising method of the signal EN in the write operation example 5 can be applied to the write operation example 3 described with reference to FIG.

Similarly, as shown in FIG. 24, the rising method of the signal EN in the write operation example 5 can be applied to the write operation example 3 described with reference to FIG.

Similarly, as shown in FIG. 25, the rising method of the signal EN of the write operation example 5 can be applied to the write operation example 3 described with reference to FIG.

Similarly, as shown in FIG. 26, the rising method of the signal EN in the write operation example 5 can be applied to the write operation example 4 described with reference to FIG.

Similarly, as shown in FIG. 27, in the write operation example 4 described with reference to FIG. 16, the rising method of the signal EN in the write operation example 5 can be applied.

<3-3> effect

According to the above embodiment, the same effects as those of the second embodiment can be obtained.

<3-4> Variation of the third embodiment

Next, the configuration of the input/output interface 101 of the memory system according to the modification of the third embodiment will be specifically described with reference to FIG. The input/output interface 101 of the memory system according to the variation of the third embodiment is further based on the inverted signal of the write enable signal BWE as compared with the input/output interface 101 of the memory system of the second modification of the second embodiment ^. BWE, and input and output of the input and output signal DQ.

Specifically, the NAND operation circuit 101g1 outputs the operation result to the NAND operation circuit 101h based on the signals CLE, ALE, and ^~ BWE. The NAND operation circuit 101g1 generates a signal of a "low" level only when the signals CLE, ALE, and ^~ BWE are all "high" levels.

<4> Fourth embodiment

The fourth embodiment will be described. In the fourth embodiment, another configuration of the input/output interface will be described. Further, the basic configuration and basic operation of the memory device of the fourth embodiment are the same as those of the memory devices of the first to third embodiments described above. Therefore, the matters described in the first to third embodiments described above and the items that can be analogized from the first to third embodiments will be omitted.

<4-1> Composition of input and output interface

As shown in FIG. 29, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the second embodiment can be combined.

Further, as shown in FIG. 29, the first embodiment can be selected by the switch circuit 101q. The signal EN of the input/output interface 101 of the memory system 1 and the input/output interface 101 of the memory system 1 of the second embodiment. For example, the signal MS can be generated by using a "Set Feature" action or the like, and input to the switch circuit 101q to select an output signal. The "set feature" operation is, for example, an operation such as changing the operation mode of the LUN 100.

<4-2> action

Here, the mode selection operation of the memory system of the present embodiment will be described with reference to FIG.

As shown in FIG. 30, when the memory system 1 is powered on (Power on), the LUN 100 is set to the first operation mode. Moreover, the memory controller 20 issues an initialization command "FFh". Next, the memory controller 20 performs a "set feature" operation.

Specifically, the memory controller 20 sequentially issues the commands "EFh" and "YYh" of the "set feature" operation to the LUN 100, and then issues information (W-B0 to W-B3) of the change of the operation mode.

When the LUN 100 receives the commands "EFh" and "YYh" and the information (W-B0 to W-B3), the LUN 100 changes the operation mode. For example, in the present embodiment, the second operation mode is changed.

Here, the operation of the switch circuit 101q in the case where the first operation mode is changed to the second operation mode will be briefly described. As shown in FIG. 29, for example, in the first operation mode, the switch circuit 101q may be controlled such that the output signal of the OR circuit 101b is selectively output as the signal EN. However, by switching to the second operation mode, the switch circuit 101q is controlled such that the output signal of the OR circuit 101j is selectively output as the signal EN.

Then, by the "set feature" operation, the LUN 100 operates in the second operation mode as long as the operation mode is not changed.

When the LUN 100 is to be operated in the first operation mode, the operation mode must be changed again by the "set feature" operation.

<4-3> effect

By using the switch circuit 101q as described above, the first and second embodiments can be combined as appropriate to operate properly.

<4-4> Variation 1 of the fourth embodiment

As shown in FIG. 31, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the second modification of the second embodiment can be combined.

Further, as shown in FIG. 31, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface of the memory system 1 of the second modification of the second embodiment can be selected by the switch circuit 101r. The signal of which one of 101. For example, the signal MS can be generated by using a "set feature" operation or the like, and input to the switch circuit 101r to select an output signal. The "set feature" action is the same as the operation described using FIG.

<4-5> Variation 2 of the fourth embodiment

As shown in FIG. 32, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the third embodiment can be combined.

Further, as shown in FIG. 32, which of the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the third embodiment can be selected by the switch circuit 101q Signal of the person. For example, the signal MS can be generated by using a "set feature" operation or the like, and input to the switch circuit 101q to select an output signal. The "set feature" action is the same as the operation described using FIG.

<4-6> Variation 3 of the fourth embodiment

As shown in FIG. 33, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the modification of the third embodiment can be combined.

Further, as shown in FIG. 33, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 according to the modification of the third embodiment can be selected by the switch circuit 101r. Which one of the signals. For example, by using The "set feature" action or the like generates a signal MS and is input to the switch circuit 101r to select an output signal. The "set feature" action is the same as the operation described using FIG.

<5> Fifth embodiment

The fifth embodiment will be described. In the fifth embodiment, another configuration of the input/output interface will be described. Further, the basic configuration and basic operation of the memory device of the fifth embodiment are the same as those of the memory devices of the first and second embodiments described above. Therefore, the matters described in the first and second embodiments described above and the matters that can be analogized from the first and second embodiments will be omitted.

<5-1> Composition of input and output interface

Next, the configuration of the input/output interface 101 will be specifically described using FIG.

As shown in FIG. 34, the input/output interface 101 performs input and output of the input/output signal DQ based on the inverted signal ^~ BWP of the write protection signal BWP or the signal from the address register 105.

The OR operation circuit 101s generates a signal EN based on the signals ^~ BWP and the signal from the address register 105. The OR operation circuit 101s outputs the signal "EN" of the "low" level only when the signal ^~ BWP and the signal from the address register 105 are "low" level. In other words, the OR operation circuit 101s outputs the signal "EN" of the "high" level when at least one of the signals ^~ BWP and the signal from the address register 105 is "high".

The receiver 120 receives the input and output signal DQ inside the LUN 100 based on the signal EN and the input and output signal DQ. The receiver 120 receives the input/output signal DQ inside the LUN 100 only when the signal EN and the input/output signal DQ are both "high".

<5-2> action

<5-2-1> Write operation example 6

The write operation example 6 of the memory system 1 of the present embodiment will be described with reference to FIG. Bright. Here, the instruction sequence of the memory group GP0 will be described.

At time T20, the memory controller 20 asserts ("low" level) write protection signal BWP. During the assertion of the write protection signal BWP, the signal EN is held at the "high" level.

At time T21 after the period T _CALS elapses from time T20, the memory controller 20 issues write commands "01h" and "80h".

After determining the address of the LUN 100, at time T22, the memory controller 20 writes the protection signal BWP negative ("high" level). If the write protection signal BWP is negated, the signal EN in the non-selected LUN 100 becomes a "low" level. On the other hand, in the selection LUN 100, since the signal of the address register 105 is maintained at the "high" level, the signal EN is maintained at the "high" level.

The other actions are the same as those described using FIG.

As described above, in the present embodiment, the write protection signal BWP is used to control the signal EN. On the other hand, when the present operation is implemented, the write protection operation cannot be performed. However, if an operation such as "setting feature" is used, the mode in which the present embodiment operates and the mode in which the write protection operation is used can be appropriately switched.

<5-2-2> Write operation example 7

The write operation example 7 of the memory system 1 of the present embodiment will be described with reference to FIGS. 36 and 37. Here, the instruction sequence of the memory group GP0 will be described.

The method of raising the signal EN in the write operation example 7 is the same as that in the write operation example 6, and thus the description thereof is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described.

For example, the selection LUN address is included in the column address R3. After determining the address of the LUN 100, at time T23, the memory controller 20 writes the protection signal BWP negative ("high" level). If the write protection signal BWP is negated, the signal EN in the non-selected LUN 100 becomes a "low" level. On the other hand, in the selection of LUN 100, the letter due to the address register 105 The number is maintained at the "high" level, so the signal EN is held at the "high" level.

As shown in FIG. 36, after receiving the column address R3, the signal EN in the non-selected LUN 100 immediately becomes a "low" level. As shown in FIG. 37, the timing before and after the input and output of the data may be selected instead of selecting the signal EN in the LUN 100 to become a "low" level.

<5-2-3> Read operation example 5

The read operation example 5 of the memory system 1 of the present embodiment will be described with reference to Fig. 38. Here, the instruction sequence of the memory group GP0 will be described.

At time T25, the memory controller 20 asserts the write protection signal BWP. During the assertion of the write protection signal BWP, the signal EN is held at the "high" level.

From time to time t after the _CALS T26, T25 elapsed during the release read instruction "05h".

After determining that the read operation is performed, at time T27, the memory controller 20 writes the protection signal BWP negative ("high" level). If the write protection signal BWP is negated, the signal EN in the LUN 100 is selected to become a "low" level.

<5-2-4> Read operation example 6

The read operation example 6 of the memory system 1 of the present embodiment will be described with reference to FIGS. 39 to 41. Here, the instruction sequence of the memory group GP0 will be described.

The method of raising the signal EN in the read operation example 6 is the same as that of the read operation example 5, and thus the description thereof is omitted. Here, the timing of the falling of the signal EN of the LUN 100 will be described.

After determining that the read operation is performed, at time T28, the memory controller 20 writes the protection signal BWP negative ("high" level). If the write protection signal BWP is negated, the signal EN in the LUN 100 is selected to become a "low" level.

As shown in FIG. 39, after receiving the column address R3, the signal EN in the LUN 100 immediately becomes a "low" level. Further, as shown in FIG. 40, after receiving the command "E0h", the signal EN in the LUN 100 immediately becomes a "low" level. Moreover, as shown in FIG. 41, the timing before and after the input and output of the data may be used, and the signal EN in the LUN 100 becomes "low". Level.

<5-3> effect

According to the above embodiment, the same effects as those of the second embodiment can be obtained.

<5-4> Variation of the fifth embodiment

In the fifth embodiment, the control of the signal EN is performed using the write protection signal BWP. However, a signal NP dedicated to the control of the signal EN can also be used. In this case, as shown in FIG. 34, the signal NP is input to the OR operation circuit 101s instead of the signal ^~ BWP. This signal NP is set to be input from the memory controller 20 to the NAND type flash memory 10.

<5-4-1> Write operation example 8

The write operation example 8 of the memory system 1 of the present embodiment will be described with reference to FIG. Here, the instruction sequence of the memory group GP0 will be described.

At time T20, the memory controller 20 asserts ("high" level) signal NP. During the assertion of signal NP, signal EN is held at the "high" level.

At time T21 after the period T _CALS elapses from time T20, the memory controller 20 issues write commands "01h" and "80h".

After determining the address of LUN 100, at time T22, memory controller 20 negates ("low" level) signal NP. If the signal NP is negated, the signal EN in the non-selected LUN 100 becomes a "low" level. On the other hand, in the selection LUN 100, since the signal of the address register 105 is maintained at the "high" level, the signal EN is maintained at the "high" level.

The other actions are the same as those described using FIG.

As described above, in the present embodiment, the signal NP is used to control the signal EN.

<5-4-2> Write operation example 9

The write operation example 9 of the memory system 1 of the present embodiment will be described with reference to FIGS. 43 and 44. Here, the instruction sequence of the memory group GP0 will be described.

The method of raising the signal EN in the write operation example 9 is the same as that in the write operation example 8, and thus the description thereof is omitted. Here, the timing of the falling of the signal EN of the non-selected LUN 100 is described. Bright.

For example, the selection LUN address is included in the column address R3. After determining the address of the LUN 100, at time T23, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the non-selected LUN 100 becomes a "low" level. On the other hand, in the selection LUN 100, since the signal of the address register 105 is maintained at the "high" level, the signal EN is maintained at the "high" level.

As shown in FIG. 43, after receiving the column address R3, the signal EN in the non-selected LUN 100 immediately becomes a "low" level. As shown in FIG. 44, it is also possible to select the timing before and after the input and output of the data, instead of selecting the signal EN in the LUN 100 to become the "low" level.

<5-4-3> Read operation example 7

The read operation example 7 of the memory system 1 of the present embodiment will be described with reference to FIG. Here, the instruction sequence of the memory group GP0 will be described.

At time T25, the memory controller 20 asserts the signal NP. During the assertion of signal NP, signal EN is held at the "high" level.

From time to time t after the _CALS T26, T25 elapsed during the release read instruction "05h".

After determining that the read operation is performed, at time T27, the memory controller 20 rejects the signal NP. If the signal NP is negated, the signal EN in the LUN 100 is selected to become a "low" level.

<5-4-4> Read operation example 8

The read operation example 8 of the memory system 1 of the present embodiment will be described with reference to FIGS. 46 to 48. Here, the instruction sequence of the memory group GP0 will be described.

The method of raising the signal EN in the read operation example 8 is the same as that of the read operation example 7, and thus the description thereof is omitted. Here, the timing of the falling of the signal EN of the LUN 100 will be described.

After determining that the read operation is performed, at time T28, the memory controller 20 rejects the signal NP. If the signal NP is negated, the signal EN in the LUN 100 is selected to become the "low" bit. quasi.

As shown in FIG. 46, after receiving the column address R3, the signal EN in the LUN 100 immediately becomes a "low" level. Further, as shown in FIG. 47, after receiving the command "E0h", the signal EN in the LUN 100 immediately becomes a "low" level. Moreover, as shown in FIG. 48, the timing before and after the input and output of the data can be made, and the signal EN in the LUN 100 becomes the "low" level.

<6> Sixth Embodiment

The sixth embodiment will be described. In the sixth embodiment, another configuration of the input/output interface will be described. Further, the basic configuration and basic operation of the memory device of the sixth embodiment are the same as those of the memory devices of the first and fifth embodiments described above. Therefore, the matters described in the first and fifth embodiments described above and the items that can be analogized from the first and fifth embodiments will be omitted.

<6-1> Composition of input and output interface

As shown in FIG. 49, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the fifth embodiment can be combined.

Further, as shown in FIG. 49, which of the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the fifth embodiment can be selected by the switch circuit 101t The signal of EN. For example, the signal MS can be generated by using a "set feature" operation or the like, and input to the switch circuit 101t to select an output signal. The "set feature" action is the same as the operation described using FIG.

<7> Seventh Embodiment

The seventh embodiment will be described. In the seventh embodiment, another configuration of the receiver will be described. Further, the basic configuration and basic operation of the memory device of the seventh embodiment are the same as those of the memory devices of the first to sixth embodiments described above. Therefore, the description of the matters described in the first to sixth embodiments and the matters that can be analogized from the first to sixth embodiments will be omitted. The receiver described below can be applied to each of the above embodiments.

<7-1> Composition of the receiver

Another example of the receiver 120 will be described using FIG.

For example, in standby mode (when data is not being exchanged), it is preferable to suppress the consumption current in terms of reduction in power consumption. Therefore, in the present embodiment, the receiver 120 includes the first receiver 101v that is inoperable but does not operate at a high speed, and the second receiver 101w that can operate at high speed but consumes a high current, and selects the first receiver. The switch 101u connected to the device 101v and the second receiver 101w.

The switch circuit 101u connects the data input/output line to the first receiver 101v when the signal EN is at the "low" level, and connects the data input/output line to the second when the signal EN is at the "high" level. Receiver 101w.

<7-2> Composition of the first receiver

An example of the circuit of the first receiver 101v will be described with reference to Fig. 51.

As shown in FIG. 51, the first receiver 101v includes a PMOS (Positive-Channel Metal Oxide AEMI Semiconductor) transistor 11a and an NMOS (Negative-channel Metal Mxide Memiconduct). The inverter of the crystal 11b.

A power supply voltage VDD is applied to the source of the PMOS transistor 11a, a drain is connected to the output terminal (node N2), and a gate is connected to the input terminal (node N1). The drain terminal of the NMOS transistor 11b is connected to the output terminal (node N2), the source is connected to the ground potential, and the gate is connected to the input terminal (node N1).

That is, when the input signal is at the "low" level, the first receiver 101v outputs a signal of "high" level from the output terminal, and outputs the output signal from the output terminal when the input signal is at the "high" level. The signal of the "low" level.

<7-3> Composition of the second receiver

A circuit example of the second receiver 101w will be described with reference to Fig. 52.

As shown in FIG. 52, the second receiver 101w includes PMOS transistors 11c and 11d, and 11e, 11f and mirror circuits of NMOS transistors 11g, 11h, 11i.

A power supply voltage VDD is applied to the source of the PMOS transistor 11c, and a gate input signal ENBn (inversion signal of the signal EN) is applied. The PMOS transistor 11c circulates a current when the signal ENBn is at a "low" level.

The drain of the PMOS transistor 11c is connected to the source of the PMOS transistor 11e, and the drain is connected to the gate.

A power supply voltage VDD is applied to the source of the PMOS transistor 11d, and a gate input signal ENBn is applied. The PMOS transistor 11d circulates a current when the signal ENBn is at a "low" level.

The drain of the PMOS transistor 11d is connected to the source of the PMOS transistor 11f, and the drain is connected to the output terminal (node N6), and the gate is connected to the node N5. The PMOS transistor 11f flows through the same current as the PMOS transistor 11e.

The NMOS transistor 11g is connected to the node N5, the source is connected to the node N7, and the reference voltage VREF is applied to the gate. The NMOS transistor 11g flows a reference current.

The NMOS transistor 11h is connected to the output terminal (node N6), the source is connected to the node N7, and the gate is connected to the input terminal.

The NMOS transistor 11i is connected to the node N7, the source is connected to the ground potential, and the reference voltage IREFN is applied to the gate. The NMOS transistor 11i functions as a constant current source.

That is, when the signal ENBn is at the "low" level and the input signal is at the "low" level, the second receiver 101w outputs a signal of "high" level from the output terminal, and the signal ENBn is "low". When the input signal is in the "high" level, the signal of the "low" level is output from the output terminal.

<8>Additional instructions

Further, Fig. 53 shows the condition of the rise of the signal EN (which is to start all the LUNs 100) in the above-described respective embodiments.

Further, in each of the above embodiments, various timings of the falling of the signal EN are performed. The description is not limited to the above-described timing, and can be appropriately changed. Specifically, it is only necessary to decrease the timing signal EN before and after the input and output of the start data. Thereby, consumption of a non-selected LUN or a useless current of the LUN at the time of the read operation can be suppressed.

Further, in each of the embodiments of the present invention:

(1) In the readout action, The voltage applied to the selected word line for the read operation of the A level is, for example, between 0V and 0.55V. It is not limited to this, and may be set between 0.1V to 0.24V, 0.21V to 0.31V, 0.31V to 0.4V, 0.4V to 0.5V, and 0.5V to 0.55V.

The voltage applied to the selected word line for the read operation of the B level is, for example, between 1.5V and 2.3V. It is not limited to this, and may be set between 1.65V and 1.8V, 1.8V to 1.95V, 1.95V to 2.1V, and 2.1V to 2.3V.

The voltage applied to the selected word line for the read operation of the C level is, for example, between 3.0V and 4.0V. It is not limited to this, and may be set between 3.0V and 3.2V, 3.2V to 3.4V, 3.4V to 3.5V, 3.5V to 3.6V, and 3.6V to 4.0V.

The time (tR) as the read operation may be, for example, between 25 μs and 38 μs, between 38 μs and 70 μs, and between 70 μs and 80 μs.

(2) The write operation includes a program operation and a verification operation as described above. In the write action, The voltage initially applied to the selected word line during the programming operation is, for example, between 13.7V and 14.3V. The present invention is not limited thereto, and may be, for example, between 13.7V and 14.0V and between 14.0V and 14.6V.

It is also possible to change the voltage initially applied to the selected word line when writing to the odd-numbered character line, and the voltage initially applied to the selected word line when writing to the even-numbered word line.

When the programming operation is set to the ISPP method (Incremental Step Pulse Program), the voltage to be boosted is, for example, about 0.5 V.

The voltage applied to the unselected word line may be, for example, between 6.0V and 7.3V. The present invention is not limited thereto, and may be, for example, between 7.3 V and 8.4 V, or may be 6.0 V or less.

The applied path voltage can also be changed according to whether the unselected word line is an odd-numbered word line or an even-numbered word line.

The time (tProg) of the writing operation may be, for example, between 1700 μs and 1800 μs, between 1800 μs and 1900 μs, and between 1900 μs and 2000 μs.

(3) in the erasing action, The voltage applied to the wafer formed on the upper portion of the semiconductor substrate and on which the memory cell is placed is, for example, between 12V and 13.6V. The present invention is not limited to this case, and may be, for example, 13.6 V to 14.8 V, 14.8 V to 19.0 V, 19.0 to 19.08 V, and 19.8 V to 21 V.

The time (tErase) of the erasing operation may be, for example, between 3000 μs and 4000 μs, between 4000 μs and 5000 μs, and between 4000 μs and 9000 μs.

(4) The structure of the memory cell has A charge storage layer disposed on the semiconductor substrate (tantalum substrate) with a tunneling insulating film having a thickness of 4 to 10 nm. The charge storage layer may have a laminated structure of SiN having a film thickness of 2 to 3 nm or an insulating film such as SiON and a polycrystalline silicon having a thickness of 3 to 8 nm. Further, a metal such as Ru may be added to the polycrystalline silicon. An insulating film is provided over the charge storage layer. The insulating film has, for example, a layer of High-k (high dielectric constant) film having a thickness of 3 to 10 nm, and a cerium oxide having a film thickness of 4 to 10 nm sandwiched between a layer of a high-k film having a thickness of 3 to 10 nm. membrane. Examples of the high-k film include HfO and the like. Further, the film thickness of the ruthenium oxide film can be made thicker than the film thickness of the High-k film. A control electrode having a thickness of 30 nm to 70 nm is formed on the insulating film with a thickness of 3 to 10 nm. Here, the material for adjusting the work function is, for example, a metal oxide film such as TaO or a metal nitride film such as TaN. The control electrode can use W or the like.

Moreover, an air gap can be formed between the memory cells.

The embodiments of the present invention have been described above, but the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit and scope of the invention. Further, the above embodiment includes various stages of the invention, and various inventions can be obtained by appropriately combining the disclosed constituent elements. For example, if a certain component is removed from the disclosed constituent elements and a specific effect is still obtained, it may be taken as an invention.

101‧‧‧Input and output interface

101c‧‧‧NAND computing circuit

101d‧‧‧Inverter

101g‧‧‧NAND computing circuit

101h‧‧‧NAND computing circuit

101i‧‧‧NAND computing circuit

101j‧‧‧OR operation circuit

104‧‧‧ instruction register

105‧‧‧ address register

105a‧‧‧Memory Department

120‧‧‧ Receiver

ADD‧‧‧ address

ALE‧‧‧ address latching enable signal

BWE‧‧‧Write enable signal

CLE‧‧‧ instruction latching enable signal

DQ‧‧‧ input and output signals

EN‧‧‧ signal

Claims (12)

A memory device comprising: a memory cell array, a memory data thereof; an instruction register, a memory instruction thereof; an address register, a memory address thereof; a control circuit responsive to the instruction to control the memory cell array; and an operation circuit And outputting a third signal based on a first signal for storing the instruction in the instruction register and a second signal for storing the address in the address register; and a receiver The data may be received based on the third signal; the third signal includes: a first level that causes the receiver to be in an active state, and a second level that causes the receiver to be in a standby state; In the circuit system, when at least one of the first signal or the second signal is asserted, the third signal of the first level is output, and then the first signal and the second signal are Negative (negate), still maintaining the output of the third signal of the first level. The memory device of claim 1, wherein the arithmetic circuit receives the address in a first period in which the second signal is asserted, and outputs the first level when the address is an address of the memory device. The third signal outputs the third signal of the second level when the address is not the address of the memory device. The memory device of claim 2, wherein the arithmetic circuit is configured to output the third signal of the second level immediately after receiving the address. The memory device of claim 2, wherein The arithmetic circuit is configured to output the third signal of the second level after receiving the address and before and after input of the data. The memory device of claim 1, wherein the memory device receives a command in a second period in which the first signal is asserted, and receives an address in a third period after the second period and in which the second signal is asserted, wherein the arithmetic circuit is The output of the third signal of the first level is maintained by the second period and the third period. The memory device of claim 3, wherein the instruction is an instruction to write to the data of the memory cell array. The memory device of claim 3, wherein the instruction is an instruction to read data from the memory cell array. The memory device of claim 5, wherein the arithmetic circuit is configured to output the third signal of the second level immediately after the third period. The memory device of claim 5, wherein the arithmetic circuit is configured to output the third signal of the second level after the third period and before and after the input and output of the data. The memory device of claim 5, wherein the arithmetic circuit outputs the third signal of the first level in a fourth period in which the first signal and the second signal are asserted before the second period, In the fifth period between the fourth period and the second period, even if the first signal and the second signal are negative, the output of the third signal of the first level is maintained. The memory device of claim 2, wherein the arithmetic circuit is configured to output the third signal of the second level after the sixth period has elapsed after receiving the address. The memory device of claim 2, wherein the arithmetic circuit is configured to receive the first command after receiving the address and the seventh period in which the first signal is established, and output the second level immediately after the seventh period The third signal described above.