TW201437812A - Methods for accessing memory and controlling access of memory, memory device and memory controller - Google Patents

Abstract

A method for accessing a memory, applied to a memory device coupled to a multiplexed address/data bus and an address bus and comprising a memory array, comprises: receiving a low-order bit signal of an address information through the multiplexed address/data bus and receiving a high-order bit signal of the address information through the address bus; receiving an advanced access signal through the address bus; and performing an access operation on the memory array to access data according to the address information and the advanced access signal and receiving/transmitting the data through the address/data bus.

Description

Memory access method, memory access control method, memory device and memory controller

The present invention relates to a memory device, and more particularly to a Pseudo Static Random Access Memory (PSRAM).

The memory is one of the important components of an electronic device such as a notebook computer, a tablet computer, a smart phone, etc., and can be classified into a dynamic random access memory (DRAM) according to whether or not the data can be saved after the power is turned off. And Static Random Access Memory (SRAM). DRAM has the advantages of small area and low price, but it must be updated frequently to prevent data from being lost due to leakage current. Therefore, DRAM also has problems in access speed and power consumption. On the other hand, SRAM does not need to be updated frequently in operation, and has the advantages of high access speed and low power consumption. However, since an SRAM cell is usually composed of six transistors, it is difficult to achieve high integration. And high prices are missing.

Pseudo Static Random Access Memory (PSRAM) with built-in update circuit and address control The dynamic random access memory of the road looks like SRAM when it operates. In some PSRAMs, in order to save the number of pins, the address information and access data are multiplexed to the same pin, that is, the input and output data and the address input bits share the bus. Figure 1 shows the read operation timing diagram of the PSRAM with multiplexed address/data bus. The figure is a 32Mb address with 16 bits/ Take the PSRAM of the data multiplex bus as an example. In this PSRAM, the lower bits (bits 0~15) of the data D and the address information ADD are transmitted through the address/data multiplex bus, such as the address/data multiplex bus signal A/DQ[15 :0], and the higher bits (bits 16~20) of the address information ADD are transmitted through the address bus, as shown by the address bus signal A[20:16]. In the read operation, the address information ADD is input to the address/data multiplex bus and the address bus, and the write enable signal WE# is not enabled and the latch enable signal LE# is enabled. When the address information ADD is latched. After a specific access time, data D of one character size is output from the address/data multiplex bus. Fig. 2 is a timing chart showing the burst read operation of the PSRAM which is the same as Fig. 1. Figure 2 shows the burst readout of 4 characters. In the burst read operation, the address information ADD is input to the address/data multiplex bus and the address bus, and the write enable signal WE# is not enabled and the latch enable signal LE# is When enabled, the address information ADD is latched according to the rising edge of the first clock signal CLK. After some waiting period (for example, 3 to 8 clock cycles), the character data D[0]~D[3] are continuously outputted from the address/data multiplex bus when the output enable signal OE# is low. .

Generally, in the continuous page read operation of the PSRAM, an instruction to read the page is first transmitted in each page read cycle, for example, the input is to be read. The address information of the page, then the page data is read, and so on until the end of the continuous page read. However, there are many wait cycles in such continuous page read operations. For example, each page read cycle will have the address/data multiplex bus signal A/DQ shown in FIG. 2 [ 15:0] Waiting period between the upper address information ADD and the data D[0], thus reducing the data read rate. Similarly, some wait cycles may occur during sequential page write operations of the PSRAM, reducing the data write rate. Especially when the PSRAM performs its built-in update operation, in order to avoid a conflict between the update operation and the read/write operation, the wait period at this time may be long. In summary, the unnecessary waiting period of the PSRAM for access (read/write) operations affects the data access rate.

In order to reduce the unnecessary waiting period to improve the data access rate of the above PSRAM, the present invention transmits an advanced access signal by using an address input bus that transmits a high bit address signal, so that the memory device performs the advanced access signal according to the advanced access signal. Advanced access operations, so continuous access to data, increased data access rate, and more access modes.

An embodiment of the present invention provides a memory access method, which is applicable to a memory device coupled to an address/data multiplex bus and an address bus, the memory device including a memory array, wherein The memory access method includes: receiving, by the address/data multiplex bus, a low bit address signal of the address information and receiving a high bit address signal of the address information through the address bus; The address bus receives an advanced access signal; and performs an access operation on the memory array to access the data according to the address information and the advanced access signal, and multiplexes the address/data through the address/data Bus receiving/transmitting this capital material.

Another embodiment of the present invention provides a memory access control method for controlling an access operation of a memory device coupled to an address/data multiplex bus and an address bus, the memory device The memory access control method includes: transmitting, by the address/data multiplex bus, a low bit address signal of the address information and transmitting the address information through the address bus Transmitting a high bit address signal to the memory device; transmitting an advanced access signal to the memory device through the address bus; and controlling the memory device to cause the memory device to follow the address information and the The access signal performs an access operation to access data and receives the data from the memory device or transmits the data to the memory device via the address/data multiplex bus.

Another embodiment of the present invention provides a memory device coupled to an address/data multiplex bus and an address bus, including: a memory core including a memory array; and an input terminal coupled Up to the address bus and the memory core, the high-order address signal of the address information and the advanced access signal are received through the address bus; an input/output circuit and a buffer are coupled to the address The address/data multiplex bus and the memory core receive the low bit address signal of the address information through the address/data multiplex bus and receive/transmit through the address/data multiplex bus Data, a control logic coupled to the memory core and the input/output circuit and the buffer, receiving a plurality of control signals, controlling the memory core according to the control signals, so that the memory core is based on the address information And the advanced access signal, performing an access operation on the memory array to access the data.

According to still another embodiment of the present invention, a memory controller receives an access command and generates a plurality of control signals according to the access command to be coupled to an address/data multiplex bus and an address bus. a memory device for controlling an access operation of the memory device, the memory device comprising an array of memory, wherein the memory controller comprises: an input/output unit coupled to the address/data multiplex a bus, the low-order address signal of the address information extracted from the access command is transmitted to the memory device through the address/data multiplex bus, and the address/data multiplex bus is transmitted through the address/data multiplex bus Receiving/transmitting data; an output unit coupled to the address bus, transmitting the high bit address signal of the address information and an advanced access signal to the memory device through the address bus; and An access control logic coupled to the input/output unit and the input unit, controlling the input/output unit and the input unit according to the access instruction, and controlling one of the control signals to latch the enable signal, The memory device an access operation according to the address information and advanced access signal to access data.

80‧‧‧ memory device

82‧‧‧ memory core

800‧‧‧ memory array

810‧‧‧Control logic

820‧‧‧ address decoding logic

830‧‧‧Update configuration register

840‧‧‧ Bus Configurator Register

850‧‧‧Input/Output Circuits and Buffers

900‧‧‧ memory controller

910‧‧‧Input/output unit

911, 912‧‧‧ multiplexers

920‧‧‧Output unit

921‧‧‧Input and output buffers

922‧‧‧Output buffer

923, 961‧‧‧ buffer

930‧‧‧ parallel to serial conversion logic

940‧‧ Advanced Access Control Logic

950‧‧‧ and gate

962, 963‧‧‧ tristate buffer

A[20:16]‧‧‧ address bus signal

A/DQ[15:0], A/DQ[15:8], A/DQ[7:0]‧‧‧ Address/data multiplex bus signal

ADAC‧‧‧Advanced access signal

ADD‧‧‧ address information

ADD[15:0]‧‧‧low bit address signal

ADD[20:16]‧‧‧High bit address signal

CE#‧‧‧chip enable signal

CLK‧‧‧ clock signal

D, D[0],...,D[3], P[0]D[0],...,P[1]D[3]‧‧‧ character data

D[15:0]‧‧‧Write information

High-Z‧‧‧high impedance signal

LB#/UB#‧‧‧Low-level group enable signal/high-order group enable signal

LE#‧‧‧Latch enable signal

O_LE#‧‧‧Original Latch Enable Signal

OE#‧‧‧ output enable signal

OPT‧‧‧ mode parameters

PCNT‧‧‧ page count value

Q[15:0]‧‧‧Reading information

R_ADD[20:0]‧‧‧ address signal

SEL1, SEL2, SEL3‧‧‧ select signal

TE#1, TE#2‧‧‧Three-state enable signal

WAIT‧‧‧waiting signal

WE#‧‧‧Write enable signal

WRAP‧‧‧ order parameters

1 is a timing chart of a read operation of a conventional PSRAM; FIG. 2 is a timing chart of a burst read operation of a conventional PSRAM; and FIG. 3 is a PSRAM according to an embodiment of the present invention. A timing diagram of a sequential character read operation; FIG. 4 is a timing diagram of a sequential page read operation of a PSRAM according to an embodiment of the present invention; and FIG. 5 is a PSRAM according to another embodiment of the present invention. Advanced readout Timing diagram of operation; FIG. 6 is a timing diagram of a continuous character write operation of a PSRAM according to an embodiment of the present invention; and FIG. 7 is a diagram showing an advanced write operation of a PSRAM according to an embodiment of the present invention. FIG. 8 is a schematic diagram of a PSRAM according to an embodiment of the invention; and FIG. 9 is a schematic diagram of a memory controller according to an embodiment of the invention.

The following description is an embodiment of the present invention. The intent is to exemplify the general principles of the invention and should not be construed as limiting the scope of the invention, which is defined by the scope of the claims.

An embodiment of the present invention provides a memory access method, which is suitable for a memory device coupled to an address/data multiplex bus and an address bus, and the memory device includes a memory array. In the disclosure, the memory device is a Pseudo Static Random Access Memory (PSRAM) device. In the memory access method, the memory device receives the low bit address signal of the address information through the address/data multiplex bus and receives the high bit address signal of the address information through the address bus, and also transmits The address bus receives the advanced access signal. Then, the memory array of the memory device is accessed according to the address information and the advanced access signal to access the data, and the data is received/transmitted by the address/data multiplex convergence. The memory access method of the present invention will be described below with reference to Figs.

Figure 3 is a diagram showing the connection of a PSRAM according to an embodiment of the present invention. A timing diagram of the continued character read operation. The PSRAM is coupled to an address/data multiplex bus and an address bus. In the present disclosure, when the chip enable signal CE# is enabled, that is, when the chip enable signal is at a low level, the PSRAM is activated, and when the chip enable signal CE# is at a high level, the PSRAM does not start and enters. Standby mode or deep power down mode. In the present disclosure, when the low-order enable signal/high-order enable signal LB#/UB# is low, the address/data multiplex bus is enabled to input or output signals.

As shown in FIG. 3, the memory receives the low-order bit address signal of the address information ADD through the address/data multiplex bus, and receives the high-order element of the address information ADD through the address bus. (high-order bit) address signal. In the example of FIG. 3, the address information ADD has 21 bits, the address/data multiplex bus has 16 bits, and the address bus has 5 bits, so the address information ADD is 0-15. The low bit is transmitted by the address/data multiplex bus, as shown in the address information ADD on the address/data multiplex bus signal A/DQ[15:0] in Figure 3, and the address information ADD The 16~20 high bits are transmitted by the address bus, as indicated by the address information ADD on the address bus signal A[20:16] in FIG. When the write enable signal WE# is not enabled (enable signal WE# is high order) and the latch enable signal LE# is enabled (latch enable signal LE# is low level), address / The low bit address signal on the data multiplex bus and the high bit address signal on the address bus are latched, that is, the PSRAM retrieves the address information ADD. After the address information ADD is retrieved, a character data D[0] is read from the memory location of the PSRAM memory array that matches the address information ADD according to the address information ADD. When the enable signal LE# is enabled again, the advanced access signal input through the address bus is retrieved. In this example, advanced access signals include The character count value is WCNT. Then, the PSRAM continuously reads out the character data D[1], D[2] whose address is consecutively continued after the character data D[0] from the memory array according to the retrieved character count value WCNT. D[3], wherein the character count value WCNT is used to indicate the number of character data read again, that is, the character count value WCNT is 3 in this example, so after reading the character data D[0] The three character data D[1], D[2], and D[3] will be read out successively, and the addresses of the character data D[0]~D[3] are consecutive. When the output enable signal OE# is enabled (the output enable signal OE# is the lower level), the character data D[0]~D[3] is continuously output through the address/data multiplex bus. In summary, the PSRAM of the present embodiment can perform continuous characters according to the advanced access signals transmitted by the address bus used to transmit the high bit address signals, compared to the read operation shown in FIG. Read out to save unnecessary waiting time on the boundary of the character.

Figure 4 is a timing diagram showing the sequential page read operation of the PSRAM in accordance with an embodiment of the present invention. The PSRAM is coupled to an address/data multiplex bus and an address bus. Similar to FIG. 3, when a continuous page read operation is performed, the memory receives the low bit address signal of the address information ADD through the address/data multiplex bus, and receives the address information ADD through the address bus. High bit address signal. In this example, the advanced access signal input to the PSRAM by the address bus includes a page count value PCNT and at least one sequence parameter WRAP. When the latch enable signal LE# is enabled, the first trigger triggers the address information ADD according to the first trigger of the clock signal CLK in the first enable period during which the latch enable signal LE# is enabled. Is to latch the low bit address signal input through the address/data multiplex bus and to latch the high bit address signal input through the address bus, and according to the first pulse signal CLK in the first enable period Second trigger Take the page count value PCNT. In the present disclosure, the clock signal CLK is triggered by a rising edge. When the address information ADD is retrieved, if the write enable signal WE# is not enabled (the write enable signal WE# is a high order), the access operation is a read operation. Then, according to the address information ADD, the data of the page P[0] is read from the memory location of the PSRAM memory array corresponding to the address information ADD, that is, the character data P[0]D[0]~P[ 0] D[3], wherein the order of the character data P[0]D[0]~P[0]D[3] of the page P[0] is read according to the preset order of the PSRAM (for example, Characters 0, 1, 2, 3) are performed. In this example, a page includes 4 words, which are for illustrative purposes only and are not intended to limit the invention. Then, according to the page count value PCNT, the data of at least one page whose address is consecutively connected after the page P[0] is read out from the memory array, wherein the number of the at least one page is equal to the page count value PCNT. For example, in this example, the page count value PCNT is 1, so the data of the page P[1] following the page P[0] after the address is read from the memory array, that is, the character data P[ 1] D[0]~P[1]D[3]. For a read operation of at least one page other than the page P[0] according to the page count value PCNT, the character read order in each page read operation is at least one before the start of each page is read. During the clock cycle, the latch enable signal LE# is again activated in the enablement period according to the sequence parameter captured by the trigger of the clock signal CLK. For example, as shown in FIG. 4, the reading order of the character data P[1]D[0]~P[1]D[3] of the page P[1] is based on the latch enable signal LE. In the second enabling period, the sequence parameter WRAP is extracted according to the trigger of the clock signal CLK, and the sequence parameter WRAP is captured at least one clock cycle before the page P[1] starts being read. For example, if the value of the sequence parameter WRAP is the first value, the order in which the characters are read is sequentially 0, 1, 2, and 3, if the value of the sequence parameter WRAP is For the second value, the character reading order is in order of characters 1, 2, 3, 0, and so on. If the corresponding sequence parameter WRAP is not captured before a certain page of the at least one page is read, the character reading order of the page may be according to a preset order or a character reading order of the previous page. . Finally, the memory continuously outputs the character data of all read pages through the address/data multiplex bus, such as P[0]D[0]~P[0]D[3] and P shown in FIG. [1] D[0]~P[1]D[3].

Fig. 5 is a timing chart showing an advanced read operation of the PSRAM according to another embodiment of the present invention. The difference between the embodiment of FIG. 5 and the embodiment of FIG. 4 is that the advanced access signal further includes a mode parameter OPT. As described above, the memory receives the low-order address signal of the address information ADD through the address/data multiplex bus, and receives the high-order address signal of the address information ADD through the address bus. In this example, the advanced access signal input through the address bus includes a page count value PCNT, a mode parameter OPT, and at least one sequence parameter WRAP. The address information ADD is retrieved according to the first trigger of the clock signal CLK during the first enable period in which the latch enable signal LE# is enabled, and is based on the second signal of the clock signal CLK during the first enable period. The trigger captures the page count value PCNT. When the address information ADD is retrieved, if the write enable signal WE# is not enabled, the access operation is a read operation. Then, according to the address information ADD, the data of the page P[0] is read from the memory location of the PSRAM memory array corresponding to the address information ADD, that is, the character data P[0]D[0]~P[ 0] D[3], wherein the order in which the character data P[0]D[0]~P[0]D[3] of the page P[0] is read is performed according to the preset order of the PSRAM. The PSRAM can read the data of at least one page other than the page P[0] from the memory array according to the page count value PCNT, wherein the number of the at least one page matches the page count value PCNT. At least one of the at least one page before being read During the clock cycle, during the second enable period of the latch enable signal LE# (eg, during another enable period after the enable of the address information ADD and the page count value PCNT), according to the clock signal CLK The trigger captures the mode parameter OPT. The mode parameter OPT is used to determine the mode of the advanced access operation. If the mode parameter OPT is the first value (for example, 0), it indicates that the address of at least one page to be read is continuous after the page P[0], that is, the continuous page read operation as shown in FIG. In other words, the sequential page read operation of FIG. 4 is a special case of the advanced read operation shown in FIG. 5 (OPT is the first value).

If the mode parameter is the second value (for example, 1), the address of each page in the at least one page to be read is determined according to the address information input through the address bus, and the address information of each page is At least one clock cycle before the page is read, during the enable period of the latch enable signal LE# (eg, during the third enable period), the address bus is drawn from the address bus according to the trigger of the clock signal CLK. Therefore, the at least one page may be a page with discontinuous addresses. For example, if you want to continuously read the data of pages P[0] and P[3], firstly, the low bit address signal and the high bit address signal of the address information ADD of P[0] are input into the bit respectively. The address/data bus and the address bus are used to capture the address information ADD according to the first trigger of the clock signal CLK during the first enable period of the latch enable signal LE#, and the latch enable signal LE# The first enable period captures the page count value PCNT according to the second trigger of the clock signal CLK, wherein the page count value PCNT is 1. Then, the character data P[0]D[0]~P[0]D[3] of the page P[0] is read from the memory array according to the address information ADD. Since the captured page count value PCNT is 1, it means that there is still a page to be read after the page P[0]. At least one clock cycle before the page begins to be read, triggered by the clock signal CLK during the second enable period of the latch enable signal LE# The mode parameter OPT is captured, wherein the mode parameter OPT is the second value, indicating that the address of the page is not continuously connected to the page P[0], and the address information of the address bus is further determined according to the address information transmitted by the address bus. Address. And, at least one clock cycle before the page starts to be read, the address information of the page is captured according to the trigger of the clock signal CLK during the third enable period of the latch enable signal LE#, in this example In the middle is the address information of the page P[3], therefore, the PSRAM reads the data of the page P[3] from the memory array according to the address information of the page P[3]. For example, in the example of FIG. 5, the address information has 21 bits, and the address bus has 5 bits. Therefore, the complete address information transmitted through the address bus requires 5 signal pulses, that is, It takes 5 pulse cycles to fully capture the address information of page P[3], and this address information must be retrieved at least one clock cycle before page P[3] is read. And, at least one clock cycle before the page P[3] starts to be read, the sequence corresponding to the page P[3] is captured according to the trigger of the clock signal CLK during the enable period of the latch enable signal LE#. The parameter WRAP is used to determine the order in which the characters of page P[3] are read. Finally, the memory continuously outputs the character data of all pages P[0] and P[3] through the address/data multiplex bus. In summary, in this case, continuous page readout can be performed even if the page address is not continuous.

If the mode parameter is a third value (for example, 2), all update operations are performed pending before the advanced read operation is completed to avoid collision between the advanced read operation and the update operation. If the mode parameter is the fourth value (for example, 3), indicating that there is an urgent update operation to be inserted, the update operation is performed first, and the advanced read operation that is currently being performed is suspended before the update operation is completed.

Continuous character write operation, continuous page write operation of PSRAM And the advanced write operation is similar to the continuous character read operation, the continuous page read operation, and the advanced read operation described above, the main difference being that the write enable signal WE# is enabled during the write operation. And the output enable signal OE# is not enabled.

Figure 6 is a timing diagram showing successive character write operations of a PSRAM in accordance with an embodiment of the present invention. The PSRAM is coupled to an address/data multiplex bus and an address bus. The memory receives the low-order address signal of the address information ADD through the address/data multiplex bus, and receives the high-order address signal of the address information ADD through the address bus. When the latch enable signal LE# is enabled, the address information ADD is retrieved. Since the write enable signal WE# is enabled after the address information ADD is retrieved, the access operation is a write operation, and the PSRAM is based on The address information ADD is written to the memory location in the memory array corresponding to the address information ADD through the character data D[0] input from the address/data multiplex bus. When the enable signal LE# is enabled again, the advanced access signal input through the address bus is retrieved. In this example, the advanced access signal includes the character count value WCNT. Then, the PSRAM writes the character data D[1]~D[2] input through the address/data multiplex bus to the character data D[0] according to the captured character count value WCNT. To the memory array, where the character count value WCNT is used to indicate the number of character data to be written in addition to the character data D[0], that is, the character count value WCNT is 2 in this example. In the present disclosure, in the case of a write operation, the output enable signal OE# is not enabled.

Figure 7 is a timing diagram showing the advanced write operation of the PSRAM in accordance with an embodiment of the present invention. The memory receives the low-order address signal of the address information ADD through the address/data multiplex bus, and receives the high-order address signal of the address information ADD through the address bus. In this example, the address is converged through the address. The advanced access signal includes a page count value PCNT, a mode parameter OPT, and at least one sequence parameter WRAP. The address information ADD is retrieved according to the first trigger of the clock signal CLK during the first enable period in which the latch enable signal LE# is enabled, and is based on the second signal of the clock signal CLK during the first enable period. The trigger captures the page count value PCNT. When the address information ADD is retrieved, if the write enable signal WE# is enabled (the write enable signal WE# is the lower level), the access operation is a write operation. Then, according to the address information ADD, the character data P[0]D[0]~P[0]D[3] of the page P[0] input through the address/data multiplex bus is according to the preset The character write order (eg, characters 0, 1, 2, 3 in sequence) is written to a memory location in the memory array that matches the address information ADD. Then, the PSRAM can write the data of at least one page other than the page P[0] input through the address/data multiplex bus to the memory array according to the page count value PCNT, wherein the number and page of the at least one page The count value PCNT matches. During at least one clock cycle before the at least one page begins to be written, during the second enable of the latch enable signal LE#, the mode parameter OPT is retrieved according to the trigger of the clock signal CLK. The mode parameter OPT is used to determine the mode of the advanced access operation. If the mode parameter OPT is the first value (for example, 0), it indicates that the address of at least one page to be written is consecutive after the page P[0]. If the mode parameter is the second value (for example, 1), the address of the at least one page to be written is determined according to the address information input through the address bus, and the address information of each page is on the page. At least one clock cycle before being read, during the enable period of the latch enable signal LE#, the address bus is extracted from the address bus according to the trigger of the clock signal CLK. Therefore, the at least one page may be a page with discontinuous addresses. The operation of inputting the address information of each of the at least one page through the address bus is similar to the above-described advanced read operation, and therefore will not be described again. Each of the above at least one page The order in which characters are written can be determined according to the order parameter WRAP. The sequence parameter WRAP is retrieved according to the trigger of the clock signal CLK during the enable period of the latch enable signal LE# during at least one clock cycle before the start of each page is written, according to the sequence taken The parameter WRAP determines the order in which characters are written for each page. If the mode parameter is the third value (for example, 2), all update operations are suspended until the advanced write operation is completed to avoid conflicts between the advanced write operation and the update operation. If the mode parameter is the fourth value (for example, 3), indicating that there is an urgent update operation to be inserted, the update operation is performed first, and the advanced write operation that is currently being performed is suspended before the update operation is completed. The sequential page write operation of the PSRAM is similar to the continuous page read operation described above, and is a special case of the advanced write operation (the OPT is the first value), and therefore will not be described again. In the timing diagrams shown in Figures 4, 5, and 7, the wait signal WAIT is used to avoid collisions between read/write operations and update operations.

In summary, the memory access method provided by the present invention can save unnecessary waiting periods at word boundaries or page boundaries, improve data access rate, and have more meta-access modes.

It should be noted that the above values, such as the character count value WCNT, the number of bits of the address information, the number of bits of the address/data multiplex bus, the number of bits of the address bus, and the words of each page The number of elements, the page count value PCNT, and the like are for illustrative purposes only and are not intended to limit the present invention.

Figure 8 is a schematic illustration of a memory device 80 in accordance with an embodiment of the present invention. The memory device 80 is coupled to an address/data multiplex bus and an address bus (not shown), including a memory core 82, control logic 810, input terminals (not shown), and input/output circuits. And buffer 850. Memory core 82 A memory array 800, an address decoding logic 820, a Refresh Configuration Register 830, and a Bus Configuration Register 840 are included. In this embodiment, the memory device 80 is a pseudo-static random access memory device, and the memory array 800 is a dynamic random access memory array.

The input terminal is coupled to the address bus and the memory core, and receives the address bus signal A[20:16] through the address bus. As shown in the above 3~7, the address bus signal A[20:16] includes the high bit address signal of the address information and the advanced access signal in the advanced read operation and the advanced write operation. In the case where the medium mode parameter is the second value, the address information of the page to be accessed may also be included. Input/output circuit and buffer 850 are coupled to address/data multiplex bus and memory core, through address/data multiplex bus input/output address/data multiplex bus signal A/DQ[15 :0]. As shown in the above 3~7, the address/data multiplex bus signal A/DQ[15:0] includes the low bit address signal of the address information and the read/write data.

The control logic 810 is coupled to the memory core and the input/output circuit and the buffer 850, receives a plurality of control signals, controls the memory core and the input/output circuit and the buffer 850 according to the control signals, and causes the memory device 80 to perform The above access operation. The control signals include a chip enable signal CE#, a write enable signal WE#, an output enable signal OE#, a latch enable signal LE#, a control register enable signal CRE, and a low byte enable signal. LB#, high byte enable signal UB#, clock signal CLK, etc. Control logic 810 also outputs a wait signal WAIT to the processor. The memory core and the input/output circuits and buffer 850 are also time-stamped according to the clock signal CLK. Control through control logic 810 The memory core performs an access operation on the memory array 800 to access data according to the address information and the advanced access signal. The access operations may include the continuous character read operation, the sequential page read operation, the advanced read operation, the continuous character write operation, the continuous page write operation, and the advanced write operation described above.

In the continuous character read operation and the continuous character write operation, the advanced access signal includes a character count value, such as the above-described character count value WCNT. During the first enable of the latch enable signal LE#, the control logic 810 controls the memory core to retrieve the address information. After the address information is retrieved, if the write enable signal WE is not enabled, a continuous character read operation is performed, and if the write enable signal WE is enabled, a continuous character write operation is performed. . In the continuous character read operation, the memory core reads a character data from the memory array 800 according to the address information, and captures the character count value during the second enable of the latch enable signal LE#. And reading at least one character data subsequent to the character data from the memory array 800 according to the character count value, and continuing the character data and the at least one character data through the input/output circuit and the buffer 850. Output to this address/data multiplex bus. The number of the at least one character data is equal to the character count value. The timing diagram of the continuous character read operation is shown in Figure 3. In the continuous character write operation, the memory core writes a character data input by the input/output circuit and the buffer 850 to the memory array 800 according to the address information, and latches the enable signal LE#. During the second enabling period, the character count value is retrieved, and at least one character data input by the input/output circuit and the buffer 850 is successively written to the memory array according to the character count value. 800. The number of the at least one character data is equal to the character count value. The timing diagram for the continuous character write operation is shown in Figure 6.

In the advanced read operation and the advanced write operation, the advanced access signal includes a page count value, a mode parameter, and at least one sequence parameter, such as the page count value PCNT, the mode parameter OPT, and the at least one sequence parameter WRAP. The memory core captures the address information according to the first trigger of the clock signal CLK during the first enable of the latch enable signal LE#, and triggers according to the second trigger of the clock signal CLK during the first enable period. Capture the page count value. If the write enable signal WE# is not enabled when the address information is retrieved, an advanced read operation is performed. Otherwise, if the write enable signal WE# is enabled when the address information is retrieved, then proceed Order write operation. In the advanced read operation, the memory core reads a page of data from the memory array 800 according to the captured address information, and continuously reads at least one page from the memory array 800 according to the page count value. The data is then continuously outputted through the input/output circuit and the buffer 850 by the address/data multiplex bus to the page and the data of the at least one page. In the advanced write operation, the memory core writes the data of a page input by the address/data multiplex bus to the memory array 800 according to the captured address information, and according to the page count value. The data of at least one page transmitted by the address/data multiplex bus is continuously written to the memory array 800. The number of the at least one page is equal to the page count value. In each read or write of the at least one page, the character read or write sequence is based on one of the sequence parameters of the at least one sequence parameter. The memory core captures the sequence parameter according to the trigger of the clock signal CLK during the enablement of the latch enable signal LE# during each of the at least one page beginning to be read or written for at least one clock cycle. To determine the order in which characters are read or written for each of the at least one page.

In addition, at least one clock cycle before being read or written at the beginning During the second period of the latch enable signal LE#, the memory core retrieves the mode parameter according to the trigger of the clock signal CLK. If the mode parameter is the first value, the address of the at least one page is consecutive after the page. If the mode parameter is the second value, the memory core is in accordance with the clock during the third enable period of the latch enable signal LE# during each of the at least one clock cycle before being read or written. The target address captured by the signal CLK from the address bus is the address of each of the at least one page. If the mode parameter is a third value, the control logic 810 suspends the update operation of the memory core before the advanced read operation or the advanced write operation is completed. If the mode parameter is the fourth value, the control logic 810 suspends the advanced read operation or the advanced write operation of the memory core before the update operation of the memory core is completed.

As described above, the continuous page read operation is a special case in which the mode parameter is the first value in the advanced read operation, and the timing chart thereof is as shown in FIG. 4, and therefore will not be described again. Similarly, the continuous page write operation is a special case where the mode parameter is the first value in the advanced write operation, and therefore will not be described again.

FIG. 9 is a schematic diagram of a memory controller 900 in accordance with an embodiment of the present invention. The memory controller 900 can be integrated into a host processor or can be part of a memory interface external to the host processor. The memory controller 900 receives the access command and generates a plurality of control signals according to the access command to a memory device coupled to the address/data multiplex bus and the address bus, for example, FIG. The memory device 80 controls the access operation of the memory device. The control signals may include the above-mentioned chip enable signal CE#, write enable signal WE#, output enable signal OE#, latch enable signal LE#, control register enable signal CRE, low byte Enable signal LB#, high The byte enables the signal UB#, the clock signal CLK, and the like. The memory controller 900 can be coupled to an address register (not shown), a data register (not shown), and an instruction register (not shown), including an input/output unit 910 and an output unit 920. And advanced access control logic 940.

The input/output unit 910 is coupled to the address/data multiplex bus for inputting the address/data multiplex bus signal A/DQ[15:0] from the memory device through the address/data multiplex bus. Or output address/data multiplex bus signal A/DQ[15:0] to the memory device. The address/data multiplex bus signal A/DQ[15:0] includes the low bit address signal ADD[15:0] of the address information ADD fetched from the access command and the read data Q[15:0 ]/Write data D[15:0]. The input/output unit 910 includes a multiplexer 911 and an input and output buffer 921. The input and output buffer 921 includes a buffer 961 and a tri-state buffer 962. The multiplexer 911 is selectively controlled by the selection signal SEL1 of the advanced access control logic 940 to selectively output the low bit address signal ADD[15:0] of the write data D[15:0] or the address information ADD. The output of the multiplexer 911 is coupled to the input of the tristate buffer 962. The tristate buffer 962 is controlled by the tristate enable signal TE1# of the advanced access control logic 940. When the tristate enable signal TE1# is induced When the three-state enable signal TE1# is low level, the tri-state buffer 962 outputs a high-impedance signal High-Z, for example, switching from the input to the output or from the output to the input in the address/data multiplex bus. During the period, the tristate buffer 962 usually outputs a high impedance signal High-Z. When the tri-state enable signal TE1# is not enabled, it outputs the output signal of the multiplexer 921.

Output unit 920 includes multiplexer 912, output buffer 922, and parallel to serial conversion logic 930. The multiplexer 912 receives the high bit of the address information ADD The meta-address signal ADD[20:16] and the advanced access signal ADAC retrieved from the access instruction, and receive the address signal R_ADD[20:0] retrieved from the access instruction through the parallel-to-serial conversion logic 930. ]. The multiplexer 912 is selectively controlled by the selection signals SEL2 and SEL3 of the advanced access control logic 940 to selectively output the high bit address signal ADD[20:16] of the address information ADD, the advanced access signal ADAC or the address. Signal R_ADD[20:0]. The output buffer 922 includes a tristate buffer 963 which is controlled by the tristate enable signal TE2# of the advanced access control logic 940 to selectively output the output signal of the multiplexer 912 or the high impedance signal High-Z.

The advanced fetch control logic 940 is coupled to the input/output unit 910 and the output unit 920, controls the input/output unit 910 and the output unit 920 according to the access command, and controls the latch enable signal LE# so that the memory device can be The address information ADD and the advanced access signal ADAC perform access operations. The advanced access control logic 940 further outputs a latch enable control signal to the AND gate 950, and the gate 950 receives the original latch enable signal O_LE# extracted from the access command and the latch enable control signal. A latch enable signal LE# is generated and output to the memory device through the buffer 923.

It should be noted that the memory controller 900 of FIG. 9 is only an example, and the memory controller 900 may further include a signal generating unit that generates each control signal, such as a clock signal generating unit.

In the memory access control operation of the memory controller 900, the input/output unit 910 transmits the low-order address signal ADD[15:0] of the address information ADD to the memory through the address/data multiplex bus. The device 920 transmits the high-order address signal ADD[20:16] of the address information ADD to the memory device through the address bus. Then, the output unit 920 is further passed through the address bus. The advanced access signal ADAC is transferred to the memory device. The memory device accesses the data according to the address information ADD and the advanced access signal ADAC, and the accessed data is stored in the memory device and the memory controller 900 through the address/data multiplexing bus. Transfer between.

The access operations may include the continuous character read operation described above, the sequential page read operation, the advanced read operation, the continuous character write operation, the continuous character page operation, and the advanced write operation. In the control of the continuous character read operation and the continuous character write operation, the advanced access signal ADAC includes the character count value WCNT. The advanced access control logic 940 enables the latch enable signal LE# during the first enable period by controlling the latch enable control signal to cause the memory device to retrieve the address information ADD during the first enablement. Thereafter, if the memory controller 900 is unable to write the enable signal WE#, the memory device performs a continuous character read operation, and if the memory controller 900 enables the write enable signal WE#, The memory device is subjected to a continuous character write operation. In the control of the continuous character read operation, the memory device reads a character data from the memory location in the memory array that matches the address information ADD based on the address information ADD. The advanced access control logic 940 enables the latch enable signal LE# during the second enable period to cause the memory device to capture the character count value WCNT during the second enable period, and then the memory device according to the character count value The WCNT continuously reads at least one character data following the character data from the memory array. The memory controller 900 enables the output enable signal OE# to cause the memory device to output the character data and the at least one character data to the input/output unit 910 through the address/data multiplex bus. In the control of the continuous character write operation, the memory device writes a character data transmitted by the input/output unit 920 through the address/data multiplex bus to the memory array according to the address information ADD. The memory location in the address information ADD. The advanced access control logic 940 enables the latch enable signal LE# during the second enable period to cause the memory device to capture the character count value WCNT during the second enable period, and then the memory device according to the character count value WCNT, the at least one character data transmitted by the input/output unit 910 through the address/data multiplex bus is successively written to the memory array after the character data is connected. The number of the at least one character data is equal to the character count value WCNT.

In the control of the advanced read operation and the advanced write operation, the advanced access signal ADAC includes a page count value PCNT, a mode parameter OPT, and at least one sequence parameter WRAP. The advanced access control logic 940 enables the latch enable signal LE# during the first enable period, so that the memory device retrieves the address information ADD according to the first trigger of the clock signal CLK during the first enablement period, and The page count value PCNT is retrieved according to the second trigger of the clock signal CLK during the first enable period. When the address information ADD is captured, if the memory controller 900 is unable to write the enable signal WE#, the memory device is caused to perform an advanced read operation, and if the memory controller 900 is enabled to write The enable signal WE# causes the memory device to perform an advanced write operation. In the advanced read operation, the memory device reads the data of a page from the memory location in the memory array corresponding to the address information ADD according to the address information ADD, and according to the page count value PCNT, and then from the memory array. Read at least one page of data continuously. The memory controller 900 enables the output enable signal OE# to cause the memory device to output the page and the data of the at least one page to the input/output unit 910 through the address/data multiplex bus. In the advanced write operation, the memory device writes the data of the page transmitted by the input/output unit 910 through the address/data multiplex bus to the memory array according to the address information ADD. The address information ADD matches the memory location, and according to the page count value PCNT, the data of the at least one page transmitted by the input/output unit 910 through the address/data multiplex bus is continuously written to the memory array. In each read or write of the at least one page, the character read or write sequence is based on one of the sequence parameters of the at least one sequence parameter, wherein each of the at least one page begins to be read or written. When at least one clock cycle is entered, the advanced access control logic 940 enables the latch enable signal LE# to cause the memory device to retrieve the sequence parameters according to the trigger of the clock signal CLK.

In addition, the advanced access control logic 940 enables the latch enable signal LE# during the second enable period to enable the memory device to be in the second direction at least one clock cycle before being read or written. The mode parameter OPT is captured according to the trigger of the clock signal CLK during the energy period. If the mode parameter OPT is the first value, the address of the at least one page is consecutively subsequent to the page. If the mode parameter OPT is the second value, the address of each of the at least one page is based on the address signal R_ADD[20:0] captured by the memory device. At least one clock cycle before each of the at least one page is read or written, the advanced access control logic 940 enables the latch enable signal LE# during the third enable period to cause the memory device to The third enable period is based on the trigger of the clock signal CLK to capture the address signal R_ADD[20:0] transmitted by the output unit 920 through the address bus to determine the address of each of the at least one page. If the mode parameter is a third value, the control logic 810 suspends the update operation of the memory core before the advanced read operation or the advanced write operation is completed. If the mode parameter is the fourth value, the control logic 810 suspends the advanced read operation or the advanced write operation of the memory core before the update operation of the memory core is completed.

As described above, the continuous page read operation is an advanced read operation. The mode parameter is a special case of the first value, and the continuous page write operation is a special case in which the mode parameter is the first value in the advanced write operation, so the memory controller 900 is not repeated for the continuous page read operation and the continuous page write. Control of the operation.

In summary, the PSRAM of the present invention receives the low-order address signal of the address information through the address/data multiplex bus and receives the high-order address signal of the address information through the address bus, and further passes the bit. The access bus receives the advanced access signal during the idle period to perform advanced access operations according to the address information and the advanced access signal, thereby continuously accessing the data, increasing the data access rate, and having more elements. Access mode.

While the invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified and substituted without departing from the spirit and scope of the invention. The scope of the invention should be determined by the scope of the appended claims.

A[20:16]‧‧‧ address bus signal

A/DQ[15:0]‧‧‧ Address/data multiplex bus signal

ADD‧‧‧ address information

CE#‧‧‧chip enable signal

D[0], D[1], D[2], D[3]‧‧‧ character data

LB#/UB#‧‧‧Low-level group enable signal/high-order group enable signal

LE#‧‧‧Latch enable signal

OE#‧‧‧ output enable signal

WCNT‧‧‧ character count

WE#‧‧‧Write enable signal

Claims (21)

A memory access method is applicable to a memory device coupled to an address/data multiplex bus and an address bus, the memory device including a memory array, wherein the memory access method The method comprises: receiving, by the address/data multiplex bus, a low bit address signal of the address information and receiving the high bit address signal of the address information through the address bus; receiving the bus through the address bus Advanced access signal; and performing an access operation on the memory array to access data according to the address information and the advanced access signal, and receiving/transmitting the data through the address/data multiplex bus data. The memory access method of claim 1, wherein the advanced access signal comprises a character count value, and the memory access method further comprises: receiving a latch enable signal and a write Enabling a signal; after the address information is retrieved during the first enablement of the latch enable signal, if the write enable signal is not enabled, reading from the memory array according to the address information a character data, the character count value is captured during a second enable period of the latch enable signal, and at least one subsequent to the character data is continuously read from the memory array according to the character count value Character data, and continuously outputting the character data and the at least one character data through the address/data multiplex bus; if the write enable signal is enabled, the bit is based on the address information One character data transmitted from the address/data multiplex bus is written to the memory array, and the character count is retrieved during the second enablement of the latch enable signal a value, according to the character count value, the at least one character data transmitted by the address/data multiplex bus is successively written to the memory array after the character data; wherein the at least one character data The number is equal to the character count value. The memory access method of claim 1, wherein the advanced access signal comprises a page count value, and the memory access method further comprises: receiving a clock signal, a latch enable signal, and a write enable signal; during the first enable of the latch enable signal, the address information is retrieved according to the first trigger of the clock signal; during the first enablement, according to the clock signal The second trigger captures the page count value; if the write enable signal is not enabled when the address information is captured, reading a page of the data from the memory array according to the address information, And continuously reading at least -page data from the memory array according to the page count value, and continuously outputting the page and the at least-page data through the address/data multiplex bus; and if the address information When the write enable signal is enabled, the data of a page transmitted by the address/data multiplex bus is written to the memory array according to the address information, and according to the page Count value, the address / data multiplex convergence At least transmitted - data is continuously written into the page memory array; wherein the at least one page number is equal to the page count value. The memory access method of claim 3, wherein the advanced access signal comprises a page count value and at least one sequence parameter, wherein each In the reading or writing of the at least one page, the character reading or writing sequence is caused by the latching according to each of the at least one page beginning to be read or written at least one clock cycle. One of the sequence parameters of the at least one sequence parameter retrieved according to the trigger of the clock signal during the enable of the signal. The memory access method of claim 4, wherein the address of the at least one page is consecutive after the page. The memory access method of claim 4, wherein the memory device has an update function, the advanced access signal further includes a mode parameter, and the memory access method further comprises: at least - The mode parameter is captured according to the trigger of the clock signal during the second enablement of the latch enable signal during the second enable period of the latch enable signal; if the mode parameter is a a value, the address of the at least one page is consecutive after the page; if the mode parameter is a second value, each of the at least - page addresses are read out for each of the at least - pages or During at least one clock cycle before writing, during the third enablement of the latch enable signal, the target address retrieved from the address bus according to the trigger of the clock signal; if the mode parameter is A third value suspends the performing the update operation before the access operation is completed; and if the mode parameter is a fourth value, the access operation is suspended until the update operation is completed. The memory access method of claim 1, wherein the memory device is a pseudo-static random access memory device. A memory access control method for controlling an access operation of a memory device coupled to an address/data multiplex bus and an address bus, the memory device including a memory array, wherein The memory access control method includes: transmitting a low bit address signal of the address information through the address/data multiplex bus and transmitting the high bit address signal of the address information through the address bus to the address a memory device that transmits an advanced access signal to the memory device through the address bus; and controls the memory device to cause the memory device to save according to the address information and the advanced access signal The operation is performed to access the data, and the data is received from the memory device or transmitted to the memory device by the address/data multiplex bus. The memory access control method of claim 8, wherein the advanced access signal comprises a character count value, and the control signals comprise a latch enable signal and a write enable signal. The memory access control method further includes: enabling the latch enable signal during a first enable period to control the memory device to capture the address information during the first enablement: if not Writing a enable signal controls the memory device to read a character data from the memory array according to the address information, and enable the latch enable signal to control the memory during a second enable period The device captures the character count value during the second enabling period, so that the memory device continuously reads from the memory array according to the character count value to continue after the character data Controlling the memory device to continuously output the character data and the at least one character data through the address/data multiplex bus; and if the write enable signal is enabled, controlling the memory The body device writes a character data transmitted by the address/data multiplex bus to the memory array according to the address information, and enables the latch enable signal to control during a second enable period. The memory device captures the character count value, so that the memory device continuously writes at least one character data transmitted by the address/data multiplex bus according to the character count value after the character data is connected to the character data. The memory array is entered; wherein the number of the character data is equal to the character count value. The memory access control method of claim 8, wherein the advanced access signal comprises a page count value, the control signals including a clock signal, a latch enable signal, and a write The memory access control method further includes: enabling the latch enable signal during a first enable period to control the memory device to be first according to the clock signal during the first enablement period Triggering the address information, and extracting the page count value according to the second trigger of the clock signal during the first enabling period; if the address information is captured, the writing enable signal is not enabled. And causing the memory device to read data of a page from the memory array according to the address information, and continuously reading data of at least one page from the memory array according to the page count value, and then causing the memory The device continuously outputs the page and the data of the at least one page through the address/data multiplex bus; and enables the write enable signal if the address information is captured The body device writes the data of a page transmitted by the address/data multiplex bus to the memory array according to the address information, and according to the page count value, the address/data multiplex bus The transmitted data of at least one page is continuously written to the memory array; wherein the number of the at least one page is equal to the page count value. The memory access control method of claim 10, wherein the advanced access signal further comprises at least one sequence parameter, wherein the character is read or written in each of the at least one page. The read or write sequence enables the latch enable signal to cause the memory device to trigger according to the clock signal according to at least one clock cycle before each of the at least one page is read or written. One of the sequence parameters of the at least one sequence parameter retrieved The memory access control method of claim 11, wherein the address of the at least one page is consecutive after the page. The memory access control method of claim 11, wherein the memory device has an update function, the advanced access signal further includes a mode parameter, and the memory access control method further includes: When at least one page begins to be read or written for at least one clock cycle, the latch enable signal is enabled during a second enable period, so that the memory device is in accordance with the clock during the second enablement period The triggering of the signal captures the mode parameter; if the mode parameter is a first value, the address of the at least one page is consecutive after the page; if the mode parameter is a second value, each of the at least The address of a page is at least one clock cycle before each of the at least one read or write, The latch enable signal is enabled during the third enable period to enable the memory device to capture the target address transmitted by the address bus according to the trigger of the clock signal during the third enable period If the mode parameter is a third value, controlling the memory device to suspend the update operation before the memory device completes the access operation; and if the mode parameter is a fourth value, then the memory device is The memory device is controlled to suspend the access operation before the update operation is completed. The memory memory access control method of claim 8, wherein the memory device is a pseudo static random access memory device. A memory controller receives an access command and generates a plurality of control signals according to the access command to a memory device coupled to the address/data multiplex bus and the address bus to control The memory device includes an array of memory, wherein the memory controller includes: an input/output unit coupled to the address/data multiplex bus, from which the memory device is to be stored The low-order address signal of the address information extracted by the instruction is transmitted to the memory device through the address/data multiplex bus, and the data is received/transmitted through the address/data multiplex bus; an output The unit is coupled to the address bus, and transmits the high bit address signal and the advanced access signal of the address information to the memory device through the address bus; and an access control logic coupled Connecting to the input/output unit and the input unit, controlling the input/output unit and the input unit according to the access command, and controlling one of the control signals to latch the enable signal to enable the memory The device performs an access operation according to the address information and the advanced access signal to access the data. The memory controller of claim 15, wherein the advanced access signal comprises a character count value, and the control signals further comprise a write enable signal, wherein the access control logic Enabling the latch enable signal during a first enable period to control the memory device to capture the address information during the first enablement: if the memory controller does not enable the write enable signal Controlling the memory device to read a character data from the memory array according to the address information, the access control logic enabling the latch enable signal during a second enable period to control the memory The device captures the character count value, so that the memory device continuously reads at least one character data subsequent to the character data from the memory array according to the character count value, and the input/output unit transmits the The address/data multiplex bus continuously receives the character data and the at least one character data; if the memory controller enables the write enable signal, controlling the memory device according to the address information The input/output unit is transparent Writing a character data of the address/data multiplex bus to the memory device to the memory array, the access control logic enabling the latch enable signal during a second enable period to Controlling the memory device to capture the character count value, and causing the memory device to transmit the input/output unit to the at least one of the memory device through the address/data multiplex bus according to the character count value The character data is successively written to the memory array after the character data; wherein the number of the character data is equal to the character count value. The memory controller of claim 15, wherein the advanced access signal comprises a page count value, and the control signals further comprise a clock signal and a write enable signal, wherein the access control The logic enables the latch enable signal during a first enable period to control the memory device to retrieve the address information according to the first trigger of the clock signal during the first enablement period, and The page count value is captured according to the second trigger of the clock signal during the coincidence period, wherein: if the memory controller does not enable the write enable signal when the address information is captured, the memory is enabled The device reads data of a page from the memory array according to the address information, and continuously reads data of at least one page from the memory array according to the page count value, and then causes the memory device to transmit the address through the address / data multiplex bus continuously outputs the page and the data of the at least one page to the input/output unit; if the memory controller enables the write enable signal when the address information is captured, Memory device based The address information is written to the memory array of the page transmitted by the address/data multiplex bus, and the address/data multiplex bus is transmitted according to the page count value. At least one page of data is continuously written to the memory array; wherein the number of the at least one page is equal to the page count value. The memory controller of claim 17, wherein the advanced access signal further comprises at least one sequence parameter, wherein in each read or write of the at least one page, the character readout Or the write sequence is based on the at least one clock cycle before each of the at least one page is read or written, the access control logic enables the latch enable signal to cause the memory device to follow the clock One of the sequence parameters of the at least one sequence parameter retrieved by the triggering of the signal. The memory controller of claim 18, wherein the address of the at least one page is consecutive after the page. The memory controller of claim 18, wherein the memory device has an update function, the advanced access signal further includes a mode parameter, wherein before the at least one page begins to be read or written The at least one clock cycle, the access control logic enables the latch enable signal during a second enable period, so that the memory device captures the trigger according to the clock signal during the second enablement period a mode parameter; if the mode parameter is a first value, the address of the at least one page is consecutively connected to the page; if the mode parameter is a second value, the address of each of the at least one page is The access control logic enables the latch enable signal during a third enable period to enable the memory device to trigger according to the clock signal during each of the at least one clock cycle before the readout. Taking the target address transmitted by the address bus; if the mode parameter is a third value, the memory controller controls the memory device to be suspended before the memory device completes the access operation Update operation; The fourth mode is a parameter value, the memory device before updating the operation is completed, the memory controller controls the memory device to suspend the access operation. The memory controller of claim 15, wherein the memory device is a pseudo-static random access memory device.