TW201523252A - Semiconductor memory device, system starting-up method and computer program product - Google Patents

Abstract

A semiconductor memory device comprising: a memory array, composed of non-volatile memory cells; a setting unit, setting a page address of a first read when starting-up; and a control unit, performing an internal sequence to read out a page address from the setting unit when starting-up and transmit page data read out from the memory array based on the read-out page address to a page buffer.

Description

Semiconductor memory device, system startup method, and computer program product

The present invention relates to a semiconductor memory of a NAND type flash memory or the like, and particularly relates to a semiconductor memory having a function of transmitting data at the time of startup of a system or the like.

The NAND type flash memory includes a memory cell array composed of a plurality of NAND strings in which a plurality of memory cells are connected in series. Compared with NOR-type flash memory, NAND-type flash memory can realize a highly integrated memory cell array. Therefore, NAND-type flash memory is suitable for storing large-capacity data such as image data and music data. In addition to the above uses, the NAND type flash memory can also be used as a memory for providing a boot code when the electronic device or system is booted. The boot code is information for starting an operating system of an electronic device or system on the host side.

Fig. 1 is a view showing a system configuration of a semiconductor memory which can output a boot code to a host system according to the prior art (Patent Document 1). As shown in FIG. 1A, the semiconductor memory 10 includes input/output pins 12, The body controller 14 and the memory unit 16 are memorized. The input/output pin 12 is for inputting/outputting data between the semiconductor 10 and the host device 30. The memory controller 14 includes a host interface 20 for transferring data between the input/output pin 12 and the host device 30, a memory interface 22 for transferring data to and from the memory unit 16, control data transfer, and the like. A Micro Processing Unit (MPU) 24 and a Read Only Memory (ROM) 26 and a Random Access Memory (RAM) 28 for storing code and data. The memory portion 16 includes two wafers, such as a NAND type flash memory chip. Further, as shown in FIG. 1B, the memory portion 16 includes a physical access area 16A accessible by a physical address and a logical access area 16B accessible by a logical address. The activation code of the host device 30 is stored in the physical access area 16A. The boot code is material for starting the operating system or the like of the host device 30. With the above composition, the boot code can be provided to the host device 30 in the case where the host device 30 corresponds only to the physical access mode.

Patent literature:

Patent Document 1 Japanese Patent Laid-Open Publication No. 2009-175877.

In a host system in which a NAND type flash memory is used as a memory for storing a boot code, a boot code may be read from a flash memory at startup or power up, and then the system is booted. Although there are many ways to start the chipset and operating system, in order to get faster after booting The flash memory read boot code, the system other than the flash memory (on-chip ROM and host device in the chipset) must have the read command and address information read out for the first time. . Therefore, it takes a certain amount of time to start the system.

It is an object of the present invention to provide a semiconductor memory that can reduce system startup time. In addition, it is an object of the present invention to provide a semiconductor memory that can freely set an address that is initially read at startup.

An embodiment of the present invention provides a semiconductor memory device including: a memory array formed by a non-volatile memory unit; and a setting unit configured to set a page address of the memory array initially read at startup; And a control unit executing an internal program to read the page address from the setting unit at the startup, and to extract the page data corresponding to the read page address from the memory according to the read page address The array is transferred to a page buffer. In a preferred example, the setting unit further sets identification information for identifying whether the page address has been stored, and the control unit determines whether to execute the internal program according to the identification information. In a preferred example, the setting unit includes a temporary register accessed by the control unit at the time of startup, and the temporary storage device stores the page address in a predetermined area. In a preferred example, the temporary register further stores flag information indicating whether the page address has been stored. In a preferred example, the setting unit sets the page address in response to a user instruction executed by a host device. In a preferred example, the internal program is to open the semiconductor record A power-on program executed when the power of the device is restored, and the internal program includes execution of the read command. In a preferred example, the semiconductor memory device is a flash memory.

An embodiment of the present invention provides a system startup method, which is applicable to a system including a semiconductor memory device and a host device, including: setting a page address of a memory array that is initially read at startup to the semiconductor memory device; An internal program for reading the set page address when the semiconductor memory device is activated, and transmitting page data corresponding to the read page address from the memory array to the read page address A page buffer.

An embodiment of the present invention provides a computer program product, which is executed by a semiconductor memory device to perform a booting method. The booting method includes: executing an internal program from a temporary register that sets a page address initially read when booting The page address is read out, and the page data corresponding to the read page address is transferred from a memory array to a page buffer according to the read page address. In a preferred example, the booting method further includes: executing the internal program according to the identification information for identifying whether the page address is set to the temporary register.

According to the present invention, the startup time of the system can be shortened by setting the page address initially read at startup and automatically transmitting the page data of the page address at the startup to the page buffer. In addition, by changing the setting of the page address, the degree of freedom of address mapping can be expanded.

1‧‧‧ Flag check

2‧‧‧Read page address M

3‧‧‧Transfer page address M to address register

4‧‧‧Execute read confirmation command

5‧‧‧Transfer page address M data to page buffer

10‧‧‧Semiconductor memory

12‧‧‧Input/output pins

14‧‧‧ memory controller

16‧‧‧ Memory Department

16A‧‧‧ physical access area

16B‧‧‧Logical access area

20‧‧‧Host interface

22‧‧‧ memory interface

24‧‧‧Microprocessing unit

26‧‧‧Read-only memory

28‧‧‧ Random access memory

30‧‧‧Host device

100‧‧‧flash memory

110‧‧‧Memory array

120‧‧‧Input/Output Buffer

130‧‧‧ address register

140‧‧‧data register

150‧‧‧ Controller

160‧‧‧Word line selection circuit

170‧‧‧Page Buffer/Sensor Circuit

180‧‧‧ row selection circuit

190‧‧‧Internal voltage generation circuit

130‧‧‧ address register

170‧‧‧Page Buffer

200‧‧‧ system

210‧‧‧Host device

220‧‧‧ memory module

230‧‧‧ memory controller

240‧‧‧Configuration register

242‧‧‧ Address storage area

244‧‧‧ Flag area

Ax‧‧‧Listing address information

Ay‧‧‧ Location Information

BLK(0), BLK(1), BLK(m)‧‧‧ blocks

BST, SST‧‧‧ select transistor

C1, C2, C3‧‧‧ control signals

GBL0, GBL1, GBLn-1, GBLn‧‧‧ bit line

I/O‧‧‧ external input/output terminals

MC0, MC1, MC2, MC31‧‧‧ memory unit

NU‧‧‧ tandem units

S100, S102, S104‧‧‧ steps

S200, S202, S204..., S216‧‧‧ steps

SGD, SGS‧‧‧ select gate line

SL‧‧‧Common source line

TD, TS‧‧‧ select transistor

Vers‧‧‧ erase voltage

Vpass‧‧‧ pulse voltage

Vprog‧‧‧ stylized voltage

Vread‧‧‧Read pulse voltage

WL0, WL1, WL2, WL31‧‧‧ character line

1A and 1B are schematic views of the composition of a semiconductor memory system for outputting a boot code according to the prior art.

2 is a schematic diagram showing an example of the composition of a flash memory according to an embodiment of the present invention.

Figure 3 is a circuit diagram showing the composition of a NAND string in accordance with an embodiment of the present invention.

Fig. 4 is a view showing an example of voltage applied to each unit of the flash memory of the embodiment of the present invention.

Fig. 5 is a schematic diagram showing a system including a flash memory according to an embodiment of the present invention.

Figure 6 is a flow chart for setting the address of the page when the flash memory is started.

Figure 7 is a diagram showing an example of setting address information to flash memory.

Figure 8 is a flow chart showing the operation of the flash memory in accordance with an embodiment of the present invention.

Figure 9 is a schematic diagram of the startup operation of the flash memory according to an embodiment of the present invention.

Embodiments of the present invention will be described in detail below with reference to the drawings. In addition, it should be noted that, for the sake of easy understanding, the size ratio of each component in the drawing may be adjusted, and may be different from the size ratio in the actual device.

2 is a group of flash memory according to an embodiment of the present invention In the schematic diagram, it should be noted that the flash memory composition shown in FIG. 2 is merely exemplary, and the present invention is not necessarily limited to such a composition.

The flash memory 100 in this embodiment includes: a memory array 110 composed of a plurality of memory cells arranged in a matrix; an input/output buffer 120 connected to an external input/output terminal I/O and saved. Input/output data; address register 130 for receiving address data from input/output buffer 120; data register 140 for storing input/output data; controller 150 for inputting from/ The command data of the output buffer 120 and an external control signal (a chip enable signal and an address latch enable signal (not shown) are provided to control the control signals C1 of each unit. C2, C3, etc.; the word line selection circuit 160 is configured to decode the column address information Ax received from the address register 130, and perform memory block selection and word line selection according to the decoding result. And a page buffer/sense circuit 170 for holding data read from a page selected by the word line selection circuit 160 and storing data to be written to the selected page; the row selection circuit 180, Temporary storage from the address 130 received row address Ay, and selects row data in page buffer 170 according to the decoding result; and internal voltage generating circuit 190 for generating voltages necessary for data reading, programming, erasing, etc. (stylized voltage Vprog, pulse voltage Vpass, read pulse voltage Vread, erase voltage Vers, etc.).

The memory array 110 has blocks BLK(0), BLK(1), ..., BLK(m) arranged in the row direction. A page buffer/sense circuit 170 is disposed at one end of the block. Nonetheless, the page buffer/sense circuit 170 can also be configured at the other end of the block or at both ends of the block.

As shown in FIG. 3, one memory block is formed by a plurality of NAND string units NU, and n+1 pieces of serial units NU arranged in the column direction are arranged in one memory block. The composition of each serial unit NU includes a plurality of memory cells MCi (i = 0, 1, ..., 31) connected in series, one end of the serial unit NU and connected to the drain side of the memory cell MC31. The selection transistor TD and the selection transistor TS located at the other end of the serial unit NU and connected to the source side of the memory cell MC0. The drain of each of the selection transistors TD is connected to its corresponding one bit line GBL, and the source of the selection transistor TS is connected to the common source line SL.

The control gate of the memory cell MCi is connected to the word line WLi. The gates of the selection transistors TD and TS are respectively connected to the selection gate lines SGD and SGS extending in parallel with the word line WLi. When the word line selection circuit 160 selects a memory block based on the column address Ax, the selection transistors TD, TS are selectively driven through the selection gate lines SGS, SGD of the memory block.

Conventionally, the memory cell has a Metal Oxide Semiconductor (MOS) structure including a source/drain formed by an N-type diffusion region formed in the P well region, and is formed at the source/drain A tunnel oxide film on the channel, a floating gate (charge accumulation layer) formed on the tunnel oxide film, and a control gate formed on the floating gate through the dielectric layer. When there is no accumulated charge in the floating gate, that is, when the data "1" is written, the threshold is at a negative value and the memory cell is normally on. When there is accumulated charge in the floating gate, that is, when data "0" is written, the threshold is shifted toward the positive direction and the memory unit Normally off.

Fig. 4 is a diagram showing an example of a bias voltage applied in various operations of the flash memory. In the read operation, a specific positive voltage is applied to the bit line, a specific voltage (eg, 0V) is applied to the selected word line (select word line), and a pulse voltage Vpass (eg, 4.5V) is applied to the non-selection. The word line is applied with a positive voltage (for example, 4.5 V) to select the gate lines SGD and SGS, the bit line selection transistor TD and the source line selection transistor TS are turned on, and 0 V is applied to the common source line SL. In the stylized (write) operation, a high voltage stylized voltage Vprog (15~20V) is applied to the selected word line, and an intermediate potential voltage (for example, 10V) is applied to the unselected word line to turn on the bit. The line selection transistor TD turns off the source line selection transistor TS and supplies the potential corresponding to the data "0" or "1" to the bit line GBL. In the erase operation, 0V is applied to the selected word line in the block, a high voltage (for example, 20V) is applied to the P well region, the electrons of the floating gate are pulled to the substrate, and the data is erased in units of blocks.

Fig. 5 is a schematic diagram showing an example of a system including the flash memory of the embodiment. As shown in FIG. 5, system 200 includes a host device 210 and a memory module 220 coupled to host device 210. The host device 210 is not particularly limited, but may be an electronic device such as a computer, a digital camera, or a printer, or a wafer mounted on a wafer set. The memory module 220 includes a memory controller 230 and a flash memory 100 having the same functions as the memory controller 14 shown in FIG. The memory controller 230 controls data transfer between the host device 210 and the flash memory 100.

The following describes the address information setting of the flash memory. Initially, in order to set the address information initially read at startup to the flash memory The user command is executed by the host device. Figure 6 is a flow chart showing the setting operation of the address information.

First, an instruction to program address information from the host device 210 is started (step S100). This command is a user command used by the user, and is different from the program of the general stylized start command (80h, 81h, 85h). When the instruction to program the address information is started, the host device 210 transmits a preset command and an external control signal to the flash memory 100 to set the address information initially read when the system is started to the flash memory 100.

Next, the user specifies the address information initially read at the time of startup and inputs the address information originally read at the time of startup (step S102). In a preferred embodiment, the address information includes page addresses within the memory array 110. The page address that can be specified by the user is located in the area in the memory array 110. The input address information in the host device 210 is temporarily stored in the data register 140 of the flash memory 100, for example, via the memory controller 230.

Next, the host device 210 executes a stylization confirmation command (step S104). In response to the execution of this instruction, the flash memory 100 performs stylization of the address information. In a preferred embodiment, the controller 150 programs the address information stored in the data buffer 140 to a configuration register (CR) that must be accessed or referenced during flash memory startup. . Figure 7 is a block diagram of a configuration register. The configuration register 240 stores the page location received from the host device 210 in the address storage area 242 and will indicate a flag for storing the page address event (flag For example, "1" is stored in the flag area 244. On the other hand, if the page address is not stylized, the flag remains "0".

The configuration register 240 is a register for setting the operation information of the flash memory 100. For example, information necessary for the startup of the flash memory is set in other areas of the configuration register 240. For example, detecting the circuit characteristics of the selected wafer or test component at a semiconductor wafer stage, and then storing a trimming code or adjusting the level for setting the operation of the flash memory according to the above detection result. (trimming level). Under normal operation, the user cannot see the stored content of the configuration register 240, but can confirm the stored content by executing a specific mode or instruction. In a preferred embodiment, the controller 150 includes a firmware or state machine for programming the page address to the configuration register in response to the host device 210 executing the user command.

Next, the automatic transfer of data of the flash memory at the time of system startup will be described with reference to the flowchart of FIG. When the system 200 shown in FIG. 5 is activated, the power of the flash memory 100 is turned on (step S200), and the controller 150 executes a power up sequence. In a preferred embodiment, controller 150 includes a program or state machine that executes a power on procedure. In the power-on procedure, the controller 150 accesses the configuration register 240 to check (confirm) the flag set in the flag area 244 to determine the next internal operation. If the boot up page address is not stylized, that is, if the flag is "0", the flash memory 100 performs the same startup as usual, waiting for the initial instruction from the host device 210. Input (step S204).

On the other hand, if the flag is set to "1", since the page address originally read at the time of startup has been programmed, the controller 150 executes the internal command "00h" (step S206), from the configuration register 240. Address storage area 242 The page address is read (step S208), and the read page address is set to the address register 130 (step S210). Then, the controller 150 executes the internal command "30h" (step S212). In response to the controller 150 executing the internal command "30h", the word line selection circuit 160 selects the page address, and the page material of the selected page address is transferred to the page buffer 170 (step S214). The page data transmitted to the page buffer 170, that is, the activated data, is output from the input/output buffer 120 to the memory controller 230 or the host device by responding to the toggle of the read clock signal RE#. 210 (step S216).

Figure 9 is a schematic representation of the flow chart of Figure 8. As shown in FIG. 9, the binary value of the flag of the configuration register 240 is checked (operation 1). If the flag is "1", the page address M is read (operation 2), and then the page address is set. M is stored in the address register 130 (Operation 3). Next, a read confirmation command (operation 4) is executed, and the page material of the page address M is read and transferred to the page buffer 170 (operation 5).

With the embodiment, when the power is turned on or turned on, the flash memory can internally set the read command and the page address, and the page address data is automatically transferred to the page buffer and output from the page buffer, therefore, The system can omit instructions, address inputs, and initial read busy (tR) detection, reducing the wait time initially read when the system is booted.

In addition, since the page address initially read at startup can be set to any place belonging to the user area, the degree of freedom of address mapping can be expanded. By executing the user instruction shown in Figure 6, the page address that is programmed into the configuration register can be arbitrarily replaced with another page address. For example, when a memory array of a flash memory is defective, in order to avoid Use the block where the defect occurred, and change the read page address at startup.

In the above embodiment, although the address information including the page address and the flag is programmed into the configuration register, the address information is not limited to being programmed into the configuration register. It is stylized to other non-volatile overwrite registers that are accessed or referenced by controller 150 in the power-on sequence. In addition, the startup data stored in the page address initially read at startup can be freely programmed by the user. Further, in the above embodiment, although "00h" and "30h" are used as examples of the internal read command executed by the flash memory, the present invention is not limited thereto, and in short, it may be turned on at the power source. In the program, the flash memory can read the command or control signal set to the page address in the scratchpad according to the internal read command without receiving the command from the outside. In the above embodiment, although the flash memory storing the binary data in the memory unit is taken as an example, the present invention is not limited thereto. For example, the present invention is also applicable to the storage of multi-value data in the memory unit. Flash memory.

The preferred embodiments of the present invention have been described in detail above, but it should be noted that the invention is not limited to the specific embodiments. A person skilled in the art can make various changes, substitutions and substitutions without departing from the spirit and scope of the invention as set forth in the appended claims.

1‧‧‧ Flag check

2‧‧‧Read page address M

3‧‧‧Transfer page address M to address register

4‧‧‧Execute read confirmation command

5‧‧‧Transfer page address M data to page buffer

130‧‧‧ address register

170‧‧‧Page Buffer

240‧‧‧Configuration register

242‧‧‧ Address storage area

244‧‧‧ Flag area

Claims (11)

A semiconductor memory device comprising: a memory array composed of a non-volatile memory unit; a setting unit configured to set a page address of the memory array initially read at startup; and a control unit to execute An internal program for reading a page address from the setting unit at startup, and transferring page data corresponding to the read page address from the memory array to a page buffer according to the read page address Device. The semiconductor memory device of claim 1, wherein the setting unit further sets identification information for identifying whether a page address has been stored, and the control unit determines whether to execute the internal program according to the identification information. The semiconductor memory device of claim 1, wherein the setting unit comprises a temporary register accessed by the control unit at the time of startup, and the temporary storage device stores the page address in a predetermined area. The semiconductor memory device of claim 3, wherein the register further stores flag information indicating whether a page address has been stored. The semiconductor memory device of claim 1, wherein the setting unit sets the page address in response to a user instruction executed by a host device. The semiconductor memory device of claim 1, wherein the internal program is executed when the power of the semiconductor memory device is turned on. A power-on program of the line, and the above internal program includes execution of the read command. The semiconductor memory device of claim 1, wherein the semiconductor memory device is a flash memory. A system startup method for a system including a semiconductor memory device and a host device includes: setting a page address of a memory array initially read at startup to the semiconductor memory device; executing an internal program to The semiconductor memory device reads the set page address when starting, and transfers the page data corresponding to the read page address from the memory array to a page buffer according to the read page address. The system startup method of claim 8, wherein the step of setting a page address of the memory array initially read at the time of startup to the semiconductor memory device comprises: according to a user instruction executed by the host device The above page address is stylized into a scratchpad. A computer program product is executed by a semiconductor memory device for performing a booting method, the booting method comprising: executing an internal program, reading the page address from a temporary register configured with a page address initially read when booting And transferring the page data corresponding to the read page address from a memory array to a page buffer according to the read page address. The computer program product of claim 10, wherein the starting method further comprises: The above internal procedure is executed based on the identification information for identifying whether the above page address has been set to the above temporary register.