TW202137003A - Memory device including a memory cell array, a control circuit and a receiver - Google Patents

Abstract

A memory device of the present invention includes a memory cell array to store data, a control circuit to respond to a command to control the memory cell array and a receiver. The receiver is configured to switch to an activated state based on a first signal, a second signal, or an operation result of an address and a command to receive commands or data.

Description

Memory device

The embodiment is related to a memory device.

As a memory device, a NAND (Not-AND) type flash memory is known.

The memory device of the embodiment includes: a memory cell array, which stores data; a control circuit, which responds to commands to control the memory cell array; and a receiver, which is based on the first signal, the second signal, or the operation result of the address and the command It becomes the activated state and can receive commands or data.

Hereinafter, the embodiment will be described with reference to the drawings. In this description, common reference signs are given to common parts throughout all the drawings. <1> First Embodiment The semiconductor memory device of the first embodiment will be described. In the following, as a semiconductor memory device, a NAND flash memory is taken as an example for description. <1-1> Configuration <1-1-1> Overall configuration of the memory system First, the general configuration of the memory system including the semiconductor memory device of the present embodiment will be described with reference to FIG. 1. Fig. 1 is a block diagram of the memory system of this embodiment. As shown in FIG. 1, the memory system 1 includes a NAND flash memory 10 and a memory controller 20. The NAND flash memory 10 and the memory controller 20 can be combined to form a semiconductor device, for example, a memory card such as an SD card (Secure Digital Card), or SSD (solid state drive: solid state drive), etc. The NAND flash memory 10 has a plurality of memory cell transistors, and stores data non-volatilely. The memory controller 20 is connected to the NAND flash memory 10 through a NAND bus, and is connected to the host machine 30 through a host bus. Furthermore, the memory controller 20 controls the NAND flash memory 10, responds to commands received from the host machine 30, and accesses the NAND flash memory 10. The host machine 30 is, for example, a digital camera or a personal computer, and the host bus is a bus that complies with the SDTM (Study Data Tabulation Model) interface, for example. The NAND bus carries out the transmission and reception of signals following the NAND interface. Specific examples of this signal are chip enable signal BCE, command latch enable signal CLE, address latch enable signal ALE, write enable signal BWE, read enable signal RE, BRE, write protection signal BWP , Data strobe signal DQS, BDQS, input and output signal DQ, and ready·busy signal RY/BBY. When there is no need to distinguish the situations of the above-mentioned signals, it may be merely described as a signal. The chip enabling signal BCE is a signal used to select a LUN (Logical unit number) 100 included in the NAND flash memory 10. The chip enable signal BCE is established when LUN100 is selected ("Low" level). The command latch enable signal CLE is used to notify the input and output signal DQ of the NAND flash memory 10 as a command to the NAND flash memory 10. The command latch enable signal CLE is established when the command is retrieved into the NAND flash memory 10 ("High" level (low<high)). The address latch enable signal ALE is a signal used to inform the NAND flash memory 10 that the input and output signal DQ to the NAND flash memory 10 is an address. The address latch enable signal ALE is asserted when the address is retrieved to the NAND flash memory 10 ("high" level). The write enable signal BWE is a signal used to retrieve the input and output signal DQ to the NAND flash memory 10. The write enable signal BWE is established when the input/output signal DQ is retrieved to the NAND flash memory 10 (“low” level). The read enable signal RE is a signal used to read the input and output signal DQ from the NAND flash memory 10. The read enable signal BRE is the complementary signal of RE. The read enable signals RE and BRE are established when the input/output signal DQ is read from the NAND flash memory 10 (RE=“high” level, BRE=“low” level)). The write protection signal BWP is a signal used to protect data from accidental erasure or writing when the input signal of the NAND flash memory 10 is switched on or off when the input signal is uncertain. . The write protection signal BWP is established when the data is protected ("low" level). The input and output signal DQ is, for example, an 8-bit signal. Moreover, the input and output signal DQ is a command, address, data writing, and data reading, etc. which are sent and received between the NAND flash memory 10 and the memory controller 20. The data strobe signal DQS is a signal used to send and receive input and output signals DQ (data) between the memory controller 20 and the NAND flash memory 10. The data strobe signal BDQS is the complementary signal of DQS. The NAND flash memory 10 receives the input and output signal DQ (data) in accordance with the timing of the data strobe signals DQS and BDQS supplied from the memory controller 20. The memory controller 20 receives the input and output signal DQ (data) according to the timing of the data strobe signals DQS and BDQS supplied from the NAND flash memory 10. The data strobe signals DQS and BDQS are established when the input and output signals DQ are sent and received (DQS = "low" level, BDQS = "high" level). The ready·busy signal RY/BBY is a signal indicating whether the LUN 100 is in a ready state (a state that can receive commands from the memory controller 20) or a busy state (a state that cannot receive commands from the memory controller 20). The ready/busy signal RY/BBY is set to a "low" level when in a busy state. <1-1-2> The structure of the memory controller Using FIG. 1, the details of the structure of the memory controller 20 will be described. As shown in FIG. 1, the memory controller 20 includes a host interface (Host I/F) 210, a built-in memory (RAM: Random access memory, random access memory) 220, a processor (CPU: Central processing unit, central Processing unit) 230, buffer memory 240, and NAND interface (NAND I/F) 250. The host interface 210 is connected to the host machine 30 via the host bus, and transmits commands and data received from the host machine 30 to the processor 230 and the buffer memory 240, respectively. The host interface 210 responds to commands from the processor 230 and transmits the data in the buffer memory 240 to the host machine 30. The processor 230 controls the overall operation of the memory controller 20. For example, when the processor 230 receives a write command from the host machine 30, it responds to it and issues a write command to the NAND interface 250. The same is true when reading and erasing. The processor 230 performs various processes for managing the NAND flash memory 10 such as wear leveling. The NAND interface 250 is connected to the NAND flash memory 10 via a NAND bus, and is responsible for communication with the NAND flash memory 10. Moreover, based on the command received from the processor 230, the chip enable signal BCE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal BWE, the read enable signal RE, The BRE, the write protection signal BWP, and the data strobe signals DQS and BDQS are output to the NAND flash memory 10. When writing, the write command issued by the processor 230 and the write data in the buffer memory 240 are sent to the NAND flash memory 10 as the input/output signal DQ. Furthermore, when reading, the read command issued by the processor 230 is transmitted to the NAND flash memory 10 as the input and output signal DQ, and the data read from the NAND flash memory 10 is used as the input and output signal DQ Receive it and send it to the buffer memory 240. The buffer memory 240 temporarily holds the written data or the read data. The built-in memory 220 is a semiconductor memory such as DRAM (Dynamic random access memory), and is used as a working area of the processor 230. Moreover, the built-in memory 220 retains firmware for managing the NAND flash memory 10, various management tables, and the like. <1-1-3> NAND-type flash memory <1-1-3-1> Structure of NAND-type flash memory Next, the structure of the NAND-type flash memory 10 will be described. As shown in FIG. 1, the NAND flash memory 10 includes a plurality of memory banks (in the example of FIG. 1, as an example, GP0 and GP1). The memory group GP is provided with a plurality of LUNs 100 (4 as an example in the example of FIG. 1). When distinguishing a plurality of LUNs 100 respectively, it is indicated by the mark of LUN (m: m is an arbitrary integer). Specifically, the memory group GP0 includes LUN(0) to LUN(3), and the memory group GP1 includes LUN(4) to LUN(7). LUN100 is the smallest unit that can be independently controlled. The LUN100 only needs to have at least one memory chip, and may also have more than two memory chips. In this embodiment, the case where LUN 100 includes one memory chip will be described. In this embodiment, it is assumed that an independent chip enable signal BCE is input to each memory group GP. In other words, the same chip enabling signal BCE is input to LUN 100 in the same memory group GP. In a certain memory group GP, there can be one LUN100 or multiple LUNs. <1-1-3-2> Structure of LUN100 Next, the structure of LUN100 will be described with reference to Figure 2. The memory controller 20 and the LUN 100 are connected via an input/output interface 101 and a control signal input interface 102. The input/output interface 101 includes a receiver 120 and a transmitter 130. In addition, the receiver 120 inputs input and output signals (DQ0 to DQ7) via a data input and output line (a wiring for transmitting and receiving input and output signals DQ in the NAND bus). The transmitter 130 outputs input and output signals (DQ0 to DQ7) through the data input and output lines. The input/output interface 101 outputs data strobe signals DQS and BDQS to the memory controller 20 when outputting input and output signals (DQ0 to DQ7) from the data input and output lines. The control signal input interface 102 receives the chip enable signal BCE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal BWE, and the read enable signal RE, BRE from the memory controller 20 , Write protection signal BWP, and data strobe signals DQS, BDQS. Although not shown in FIG. 2, the LUN 100 is also provided with Vcc/Vss/Vccq/Vssq terminals for power supply. The control circuit 103 outputs the data read from the memory cell array 110 to the memory controller 20 through the input/output interface 101. The control circuit 103 receives various commands such as writing, reading, erasing, and status/reading, addresses, and writing data through the control signal input interface 102. The control circuit 103 controls the command register (Command register) 104, the address register (Address register) 105, the status register (Status register) 106, the sense amplifier (Sense amp) 111, and the data register (Data register 112, Column decoder 113, and Row address decoder 115. The control circuit 103 supplies required voltages to the memory cell array 110, the sense amplifier 111, and the column decoder 115 during data programming, verification, reading, and erasing. The command register 104 stores commands input from the control circuit 103. The address register 105 stores, for example, the address supplied from the memory controller 20. Moreover, the address register 105 converts the memorized address into an internal physical address (row address and column address). Then, the address register 105 supplies the row address to the column buffer 114, and supplies the column address to the row address buffer decoder 116. The status register 106 is used to notify external parties of various statuses inside the LUN 100. The status register 106 has a ready/busy register (not shown) that holds the data indicating which of the LUN 100 is in the ready/busy state, and the write state temporarily that holds the data indicating the pass/fail of the write. Memory (not shown) and so on. The memory cell array 110 includes a plurality of bit lines BL, a plurality of word lines WL, and a source line SL. The memory cell array 110 is composed of a plurality of blocks BLK arranged in a matrix of memory cell transistors (also referred to as memory cells) that can be rewritten electrically. The memory cell transistor MC has, for example, a laminated gate including a control gate electrode and a charge storage layer (such as a floating gate electrode), and is based on the change in the threshold value of the transistor determined by the amount of charge injected into the floating gate electrode Memorize binary or multi-value data. In addition, the memory cell transistor MC may also be a structure of MONOS (Metal-Oxide-Nitride-Oxide-Silicon: Metal-Oxide-Nitride-Oxide-Silicon) that traps electrons in the nitride film. Furthermore, the structure of the memory cell array 110 may also be other structures. That is, the structure of the memory cell array 110 is described in, for example, US Patent Application No. 12/407,403 filed on March 19, 2009 called "Three-dimensional multilayer non-volatile semiconductor memory." Also, it is described in US Patent Application No. 12/406,524 filed on March 18, 2009 called "Three-dimensional multilayer non-volatile semiconductor memory", 2010 called "Non-volatile semiconductor memory device and its manufacturing method" U.S. Patent Application No. 12/679,991 filed on March 25, 2005, and U.S. Patent Application No. 12/532,030 filed on March 23, 2009 called "Semiconductor memory and its manufacturing method". These patent applications are incorporated into the specification of this application as a whole by reference. The sense amplifier 111 senses the data read from the memory cell transistor MC to the bit line when the data is read. The data register 112 is composed of SRAM ((Static Random Access Memory)) etc. The data register 112 stores the data supplied from the memory controller 20 or is detected by the sense amplifier 111 The verification result, etc. The row decoder 113 decodes the row address signal stored in the row buffer 114, and outputs the selection signal of any one of the selected bit lines BL to the sense amplifier 111. The row buffer 114 temporarily stores The row address signal input from the address register 105. The column address decoder 115 decodes the column address signal input via the column address buffer decoder 116. Moreover, the column address decoder 115 selects to drive the memory cell array 110 character line WL and select gate lines SGD, SGS. The column address buffer decoder 116 temporarily stores the column address signal input from the address register 105. <1-1-3-3> I/O interface Secondly, the structure of the input and output interface 101 will be explained in detail using Fig. 3. As shown in Fig. 3, the input and output interface 101 is based on the command latch enable signal CLE, the address latch enable signal ALE, and from the command temporary The signal of the register 104 or the address register 105 is input and output of the input/output signal DQ. Specifically, the command register 104 outputs the command CMD stored in the memory 104a based on the write enable signal BWE The AND operation circuit 101a to the input and output interface 101. When the command register 104 outputs a command CMD, it maintains a "high" level state before inputting the next command. The address register 105 is based on writing The enabling signal BWE outputs the address ADD stored in the memory 105a to the AND operation circuit 101a of the input/output interface 101. The address register 105 maintains a "high" level state when the LUN 100 of its own is selected. The AND operation circuit 101a outputs the operation result to the OR operation circuit 101b based on the command CMD and the address ADD. The AND operation circuit 101a only works when the command CMD and the address ADD are both "high" levels , Output a "high" level signal. The OR operation circuit 101b generates the signal EN based on the operation result of the AND operation circuit 101a, the instruction latch enable signal CLE, or the address latch enable signal ALE. The OR operation circuit 101b Only when the operation result of the AND operation circuit 101a, the command latch enable signal CLE, and the address latch enable signal ALE are all at the "low" level, the "low" level signal EN is output. , That is, when at least one of the operation result of the AND operation circuit 101a, the instruction latch enable signal CLE, and the address latch enable signal ALE is at a "high" level, the OR operation circuit 101b outputs a "high" bit Standard signal EN. In the following, sometimes the signal EN from the "low" level to the "high" level is recorded as "rising", And to set the signal EN from the "high" level to the "low" level is recorded as "down". The receiver 120 receives the input/output signal DQ inside the LUN 100 based on the signal EN and the input/output signal DQ. Specifically, the NAND operation circuit 101c generates a signal based on the signal EN supplied from the OR operation circuit 101b and the input/output signal DQ supplied from the memory controller 20. The NAND operation circuit 101c generates a "low" level signal only when the signal EN and the input/output signal DQ are both at the "high" level. Furthermore, the inverter 101d inverts and outputs the operation result of the NAND operation circuit 101c. That is, the receiver 120 receives the input/output signal DQ inside the LUN 100 only when the signal EN and the input/output signal DQ are both at a "high" level. In the following, the state of the signal EN inputting the "high" level to the receiver 120 is sometimes described as the "active state", and the state of the signal EN inputting the "low" level is sometimes described as the "standby state". When the receiver 120 is in the activated state, it is in a state capable of receiving input and output data DQ. Furthermore, when the receiver 120 is in the standby state, it is in a state where it cannot receive the input and output data DQ. <1-2> Operation <1-2-1> Outline of the operation of the memory system Using Fig. 4, the outline of the operation of the memory system of this embodiment will be described. In FIG. 4, focusing on the operation of the memory group GP0, the outline of the operation of changing the access (write operation, read operation, etc.) from LUN(0) to LUN(1) is explained. As shown in Figure 4, during the access to LUN(0), the signal EN in LUN(0) becomes "high" level, and the signal EN in LUN(1)～LUN(3) becomes "low" level . That is, during the access to LUN(0), the receiver 120 of LUN(0) is set to the activated state, and the receiver 120 of LUN(1)-LUN(3) is set to the standby state. Furthermore, at time T0, the memory system 1 performs a LUN switching operation. At this time, at least the signal EN in all LUNs (LUN(0)～LUN(3)) in the memory group GP0 becomes the "high" level. That is, during the LUN switching operation, at least the receivers 120 in all the LUNs (LUN(0)-LUN(3)) in the memory group GP0 are set to the activated state. At time T1, if the address of LUN(1) is determined as the selected LUN address, then access to LUN(1) is started. During the access to LUN(1), the signal EN in LUN(1) becomes “high” level, and the signal EN in LUN(0), LUN(2), and LUN(3) becomes “low” level. That is, during the access to LUN(1), the receiver 120 of LUN(1) is set to the active state, and the receiver 120 of LUN(0), LUN(2), and LUN(3) are set to the standby state . <1-2-2> Write operation example 1 Using FIG. 5, the write operation example 1 of the memory system 1 of the present embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. At time T2, the memory controller 20 asserts ("high" level) the command latch enable signal CLE. At the time point of time T2, the chip enabling signal BCE is established ("low" level). If the command latch enable signal CLE is established, the signal EN becomes a "high" level as illustrated in FIG. 3. LUN100 must wait for the period t _CALS as the period required for the setting of command input since the command latch enable signal CLE is established. At time T3 after the period t _{CALS has} elapsed since time T2, the memory controller 20 issues commands "01h" and "80h". The command "01h" is a command issued when the memory cell transistor MC can hold 3-bit data. More specifically, the command "01h" is the command that specifies the first page. Although the command "01h" is described here as an example, it is not limited to this. If the memory controller 20 specifies other pages, other commands can also be input. The command "80h" is a command used to specify the write action. The memory controller 20 asserts ("low" level) the write enable signal BWE every time signals such as commands, addresses, and data are issued. Moreover, whenever the write enable signal BWE is triggered, the signal is captured to LUN 100. Next, the memory controller 20 issues addresses (C1, C2: row addresses, R1 to R3: column addresses), for example, across 5 cycles, and asserts (“high” level) the address latch enable signal ALE. When the address is issued, the instruction latch enable signal CLE is negated ("low" level), but the address latch enable signal ALE is established. If the address latch enable signal ALE is established, the signal EN becomes a "high" level as illustrated in FIG. 3. That is, when receiving the address, the LUN 100 maintains the signal EN at the "high" level. However, by, for example, including the selected LUN address in the row address R3, and supplying the row address R3 to LUN 100, the selection of LUN 100 is determined. If the LUN 100 is selected and confirmed, the address latch circuit 105 outputs a "high" level signal in the selection of the LUN 100 as illustrated in FIG. 3. As a result, the signal EN in the LUN 100 is selected to maintain the "high" level. On the other hand, in the non-selected LUN 100, the address latch circuit 105 outputs a "low" level signal. As a result, the signal EN in the selection LUN 100 becomes a "low" level. In other words, the receiver 120 of the selected LUN 100 is maintained in the activated state, and the receiver 120 of the non-selected LUN 100 is in the standby state. Next, the memory controller 20 outputs write data (D0 to Dn) across a plurality of cycles. During this period, the signals ALE and CLE are negated ("L" level). The write data received by the LUN 100 is held in the page buffer in the sense amplifier 111. Although not shown in FIG. 5, the memory controller 20 issues the write command "10H" and establishes the command latch enable signal CLE. If the command "10h" is received, the control circuit 103 starts the write operation, and the LUN 100 becomes a busy state (RY/BBY = "low" level). <1-2-3> Reading operation example 1 Using FIG. 6, the reading operation example 1 of the memory system 1 of the present embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. At time T5, the memory controller 20 asserts the command latch enable signal CLE. At time T5, the chip enabling signal BCE is established. If the command latch enable signal CLE is established, the signal EN becomes a "high" level. At time T6 after the period t _{CALS has} elapsed since time T5, the memory controller 20 issues a read command "05h". Next, the memory controller 20 issues addresses (C1, C2: row addresses, R1 to R3: column addresses), for example, across 5 cycles, and asserts (“high” level) the address latch enable signal ALE. The memory controller 20 issues a command "E0h". When LUN 100 receives the command "E0h", it starts the read operation. The command register 104 recognizes that the action requested from the memory controller 20 is a read action. Then, the command register 104 supplies the "low" level signal to the AND operation circuit 101a (refer to FIG. 3). Thereby, the signal EN becomes a "low" level. That is, the receiver 120 becomes a standby state. <1-3> Effect According to the above implementation form, use address ADD, command CMD, command latch enable signal CLE, address latch enable signal ALE, etc., to appropriately control the electrical connection between LUN100 and data input and output lines . For example, in a write operation, if the non-selected LUN 100 receives the written data, then useless current flows through the LUN 100. However, by adopting the above-mentioned embodiment, the operating current of the non-selected LUN 100 can be suppressed. In addition, LUN 100 does not need to receive data during the read operation. By adopting the above-mentioned embodiment, the operating current of LUN100 can be suppressed. <2> Second Embodiment The second embodiment will be described. In the second embodiment, another configuration of the input/output interface will be described. Furthermore, the basic structure and basic operation of the memory device of the second embodiment are the same as those of the memory device of the first embodiment described above. Therefore, descriptions of matters described in the above-mentioned first embodiment and matters that can be analogized from the above-mentioned first embodiment are omitted. <2-1> The structure of the input/output interface Next, the structure of the input/output interface 101 of the memory system of the second embodiment will be described in detail using FIG. 7. As shown in FIG. 7, the input and output interface 101 performs input and output signals based on the command latch enable signal CLE, the address latch enable signal ALE, and the signal from the command register 104 or the address register 105 Input and output of DQ. Specifically, the NAND operation circuit 101g outputs the operation result to the NAND operation circuit 101h based on the command latch enable signal CLE and the address latch enable signal ALE. The NAND operation circuit 101g generates a "low" level signal only when the command latch enable signal CLE and the address latch enable signal ALE are both at a "high" level. The NAND operation circuit 101h and the NAND operation circuit 101i constitute an RS flip-flop circuit. Specifically, the NAND operation circuit 101h outputs the operation result based on the operation result of the NAND operation circuit 101g and the NAND operation circuit 101i. The NAND operation circuit 101i outputs the operation result based on the operation result of the NAND operation circuit 101h and the signal from the command register 104 (for example, the command CMD). The operation of the RS flip-flop circuit is briefly described. When the signal from the NAND operation circuit 101g is at the "high" level and the signal from the command register 104 is at the "low" level, the NAND operation circuit 101h outputs the signal at the "low" level. Furthermore, when the signal from the NAND operation circuit 101g is at the "low" level and the signal from the command register 104 is at the "high" level, the NAND operation circuit 101h outputs the signal at the "high" level. Furthermore, in the state where the output signal of the NAND operation circuit 101h is confirmed, even if the signal from the NAND operation circuit 101g or the signal from the command register 104 changes, the output signal of the NAND operation circuit 101h is maintained. The OR operation circuit 101j generates the signal EN based on the operation result of the NAND operation circuit 101h and the signal from the address register 105. The OR operation circuit 101j outputs the "low" level signal EN only when the operation result of the NAND operation circuit 101h and the signal from the address register 105 are both "low" level. In other words, the OR operation circuit 101j outputs the "high" level signal EN when at least one of the operation result of the NAND operation circuit 101h and the signal from the address register 105 is at a "high" level. The receiver 120 receives the input/output signal DQ inside the LUN 100 only when the signal EN and the input/output signal DQ are both at a "high" level. <2-2> Operation The operation described in the first embodiment is different from the operation in the second embodiment in the method of raising the signal EN in LUN100. In the memory system 1 of the first embodiment, the signal EN is raised based on the establishment of the command latch enable signal CLE. In the memory system 1 of the second embodiment, the signal EN is raised by simultaneously establishing the command latch enable signal CLE and the address latch enable signal ALE. At the same time, the action of establishing the command latch enable signal CLE and the address latch enable signal ALE becomes an action for raising the signal EN. <2-2-1> Writing operation example 2 Using FIG. 8, the writing operation example 2 of the memory system 1 of the present embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. At time T8, the memory controller 20 establishes the command latch enable signal CLE and the address latch enable signal ALE. Thereby, as explained using FIG. 7, the signal EN becomes a "high" level. Then, the memory controller 20 negates the command latch enable signal CLE and the address latch enable signal ALE. Therefore, although the input signal of the NAND arithmetic circuit 101h changes, but the input signal of the NAND arithmetic circuit 101i does not change, the output signal of the NAND arithmetic circuit 101h is maintained at a "high" level. As a result, the signal EN is maintained at the "high" level. At time T9 after the period t _{CALS has} elapsed since time T8, the memory controller 20 issues write commands "01h" and "80h". At time T10, if the selection of LUN 100 is confirmed, the address latch circuit 105 outputs a "high" level signal in the selection of LUN 100 as illustrated in FIG. 7. As a result, the signal EN in LUN 100 maintains a "high" level. On the other hand, in the non-selected LUN 100, the address latch circuit 105 outputs a "low" level signal. As a result, the signal EN in the selected LUN 100 becomes a "low" level. In other words, the receiver 120 of the selected LUN 100 maintains the activated state, and the non-selected LUN 100 is set to the standby state. The memory controller 20 issues addresses (C1, C2: row addresses, R1 to R3: column addresses), for example, over 5 cycles, and asserts ("high" level) the address latch enable signal ALE. Secondly, the memory controller 20 outputs the written data (D0-Dn) across a plurality of cycles. During this period, the signals ALE and CLE are negated. The write data received by the LUN 100 is held in the page buffer in the sense amplifier 111. <2-2-2> Write operation example 3 With reference to Figs. 9 and 10, the write operation example 3 of the memory system 1 of the present embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. The rising method of the signal EN in the writing operation example 3 is the same as that in the writing operation example 2, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described. For example, the column address R3 includes the selected LUN address. By supplying the column address R3 to LUN100, it is determined to select LUN100. If the selected LUN 100 is confirmed, the signal EN in the selected LUN 100 is maintained at a "high" level, and the signal EN in the non-selected LUN 100 becomes a "low" level. In other words, the receiver 120 of the selected LUN 100 is maintained in the activated state, and the non-selected LUN 100 is set in the standby state. As shown in FIG. 9, it is also possible that the signal EN in the non-selected LUN 100 becomes "low" immediately after the column address R3 is received. As shown in Figure 10, it is also possible to follow the time sequence before and after the input and output of the data, instead of selecting the signal EN in the LUN 100 to change to the "low" level. <2-2-3> Reading operation example 2 Using FIG. 11, the reading operation example 2 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. The rising method of the signal EN in the read operation example 2 is the same as in the write operation example 2. At time T13, the memory controller 20 establishes the command latch enable signal CLE and the address latch enable signal ALE. Thereby, as explained using FIG. 7, the signal EN becomes a "high" level. At time T14 after the period t _{CALS has} elapsed since time T13, the read command "05h" is issued. If the command register 104 receives "05h", it recognizes that the action requested from the memory controller 20 is a read action. Then, the command register 104 supplies the "low" level signal to the AND operation circuit 101a (refer to FIG. 3). Thereby, the signal EN becomes a "low" level. That is, the receiver 120 becomes a standby state. <2-2-4> Reading operation example 3 Using FIGS. 12 to 14, the reading operation example 3 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. The rising method of the signal EN in the reading operation example 3 is the same as that in the reading operation example 2, so the description is omitted. Here, the falling timing of the signal EN of LUN100 will be described. The command register 104 recognizes that the action requested from the memory controller 20 is a read action. Then, the command register 104 supplies the "low" level signal to the AND operation circuit 101a (refer to FIG. 3). Thereby, the signal EN becomes a "low" level. That is, the receiver 120 becomes a standby state. As shown in FIG. 12, after receiving the column address R3, the signal EN in the LUN 100 immediately becomes a "low" level. Also, as shown in FIG. 13, after receiving the command "E0h", the signal EN in LUN 100 immediately changes to the "low" level. Moreover, as shown in Fig. 14, it is also possible to follow the time sequence before and after the input and output of the data, and the signal EN in the LUN 100 becomes a "low" level. <2-3> Effect According to the above-mentioned embodiment, by simultaneously establishing the command latch enable signal CLE and the address latch enable signal ALE, the receivers 120 of a plurality of LUNs 100 become activated. Along with the speeding up of data input and output, it is necessary to speed up the instruction address input cycle. For example, in the case of the first embodiment, if the input and output of data is increased at a high speed, the period required for the setting of the command input becomes insufficient since the command latch enable signal CLE is established, and it is too late. Possibility of setting problems. In other words, there is a possibility that the LUN 100 cannot be electrically connected to the data input/output line through the receiver 120 before the command is input, which may cause the problem that the LUN 100 cannot properly receive the command. Therefore, in this embodiment, before the command latch enable signal CLE is established in order to input a command, the receiver 120 is set to the activated state. As a result, compared with the first embodiment, the substantial period t _CALS can be alleviated. Therefore, it is possible to provide a memory system that can increase the speed of data input and output, and can appropriately perform the transmission and reception of input and output signals DQ. <2-4> Modification 1 of the second embodiment <2-4-1> Write operation example 4 Using FIG. 15, the writing operation example 4 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. The method of raising the signal EN in the address operation example 4 is the same as that in the address operation example 2 of the second embodiment, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described. For example, the column address R3 includes the selected LUN address. By supplying the column address R3 to LUN100, it is determined to select LUN100. As shown in FIG. 7, if the LUN 100 is selected and the command “XXh” is input, the output signal of the command register 104 becomes “low” level. On the other hand, in the selected LUN 100, the address register 105 maintains a "high" level signal, and in the non-selected LUN 100, the address register 105 outputs a "low" level signal. Therefore, the signal EN in the selected LUN 100 maintains a "high" level, and the signal EN in the non-selected LUN 100 becomes a "low" level. In other words, the receiver 120 of the selected LUN 100 maintains the activated state, and the receiver 120 of the non-selected LUN 100 is set to the standby state. <2-4-2> Reading operation example 4 Using FIG. 16, the reading operation example 4 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. The method of raising the signal EN in the reading operation example 4 is the same as that in the reading operation example 2 of the second embodiment, so the description is omitted. Here, the falling timing of the signal EN of LUN100 will be described. If the command register 104 receives "XXh", it recognizes that the action requested from the memory controller 20 is a read action. Then, the command register 104 supplies the "low" level signal to the AND operation circuit 101a (refer to FIG. 3). Thereby, the signal EN becomes a "low" level. That is, the receiver 120 becomes a standby state. <2-5> Variation 2 of the second embodiment The configuration of the input/output interface 101 of the memory system of Variation 2 of the second embodiment will be specifically described with reference to FIG. 17. The input/output interface 101 shown in FIG. 17 is provided with a circuit for controlling such that when outputting data, the receiver 120 is not electrically connected to the LUN 100 and the data input/output line. Specifically, as shown in FIG. 17, the input/output interface 101 includes a NAND arithmetic circuit 101k. Furthermore, the NAND arithmetic circuit 101k is based on the inverted signal of the command latch enable signal CLE ^~ CLE, the inverted signal of the address latch enable signal ALE ^~ ALE, the inverted signal of the chip enable signal BCE ^~ BCE, write The signal BWE is energized, and the operation result is output to the NAND operation circuit 1011. The NAND arithmetic circuit 101k ^{generates a "low" level signal only when the signals ~} CLE, ^~ ALE, ^~ BCE, and BWE are all "high" levels. The NAND arithmetic circuit 101l and the NAND arithmetic circuit 101m constitute an RS flip-flop circuit. Specifically, the NAND operation circuit 1011 outputs the operation result based on the operation result of the NAND operation circuit 101k and the NAND operation circuit 101m. The NAND operation circuit 101m outputs the operation result based on the operation result of the NAND operation circuit 1011 and the read enable signal BRE. The operation of the RS flip-flop circuit is briefly described. When the signal from the NAND arithmetic circuit 101k is at the "high" level and the read enable signal BRE is at the "low" level, the NAND arithmetic circuit 101l outputs a signal at the "low" level. Furthermore, when the signal from the NAND arithmetic circuit 101k is at the "low" level and the read enable signal BRE is at the "high" level, the NAND arithmetic circuit 101l outputs a signal at the "high" level. In addition, in a state where the output signal of the NAND operation circuit 1011 is determined, even if the signal from the NAND operation circuit 101k or the read enable signal BRE changes, the output signal of the NAND operation circuit 1011 is maintained. Furthermore, the inverter 101n inverts the output signal of the NAND operation circuit 101l, and supplies it to the AND operation circuit 101o. The AND operation circuit 101o outputs the operation result to the OR operation circuit 101p based on the output signal of the inverter 101n and the signal from the address register 105. The AND operation circuit 101a outputs a signal of "high" level only when the output signal of the inverter 101n and the signal from the address register 105 are both "high" level. The OR operation circuit 101p generates the signal EN based on the operation results of the AND operation circuit 101o and the NAND operation circuit 101h. The OR operation circuit 101p outputs the "low" level signal EN only when the operation results of the AND operation circuit 101o and the NAND operation circuit 101h are both at the "low" level. In other words, the OR operation circuit 101p outputs the "high" level signal EN when at least one of the operation results of the AND operation circuit 101o and the NAND operation circuit 101h is at the "high" level. During data output, the signals ^~ CLE, ^~ ALE, ^~ BCE, BWE, and BREA all become "high" levels. As a result, the output signal of the NAND arithmetic circuit 1011 outputs a signal of "high" level. As a result, during the data output period, the signal EN becomes a "low" level. In this way, the input/output interface 101 of the memory system of the second embodiment of the variation 2 can be controlled in such a way that the receiver 120 is not electrically connected to the LUN 100 and the data input/output line when outputting data. <3> Third Embodiment The third embodiment will be described. In the third embodiment, another configuration of the input/output interface will be described. Furthermore, the basic structure and basic operation of the memory device of the third embodiment are the same as the memory devices of the first and second embodiments described above. Therefore, descriptions of matters described in the above-mentioned first and second embodiments and matters that can be analogized from the above-mentioned first and second embodiments are omitted. <3-1> The structure of the input/output interface Next, using FIG. 18, the structure of the input/output interface 101 of the memory system of the third embodiment will be described in detail. Compared with the input/output interface 101 of the memory system of the third embodiment, the input/output interface 101 of the memory system of the second embodiment further performs input/output signals ^{based on the inversion signal ~ BWE of the write enable signal BWE} Input and output of DQ. Specifically, the NAND operation circuit 101g1 outputs the operation result to the NAND operation circuit 101h based on the signals CLE, ALE, and ^~BWE. The NAND arithmetic circuit 101g1 generates a "low" level signal only when the signals CLE, ALE, and ^~ BWE are all at the "high" level. <3-2> Operation The operation described in the second embodiment differs from the operation in the third embodiment in the method of raising the signal EN in LUN100. In the memory system 1 of the second embodiment, the signal EN is raised by simultaneously establishing the command latch enable signal CLE and the address latch enable signal ALE. On the other hand, in the memory system 1 of the third embodiment, by simultaneously establishing the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE, the signal EN rise. That is, the operation of simultaneously establishing the numbers CLE, ALE, and BWE becomes an operation for raising the signal EN. <3-2-1> Write operation example 5 Using FIG. 19, a write operation example 5 of the memory system 1 of the present embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. At time T8, the memory controller 20 establishes the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE. Thereby, as explained using FIG. 18, the signal EN becomes a "high" level. Then, the memory controller 20 negates the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE. Therefore, although the input signal of the NAND arithmetic circuit 101h changes, but the input signal of the NAND arithmetic circuit 101i does not change, the output signal of the NAND arithmetic circuit 101h is maintained at a "high" level. As a result, the signal EN is maintained at the "high" level. The operation after time T9 is the same as the operation explained using FIG. 8. <3-2-2> Other access operations are shown in FIG. 20, and in the write operation example 3 described in FIG. 9, the rising method of the signal EN of the write operation example 5 can also be applied. Similarly, as shown in FIG. 21, in the write operation example 3 described in FIG. 10, the rising method of the signal EN of the write operation example 5 may be applied. As shown in FIG. 22, in the writing operation example 2 described in FIG. 11, the rising method of the signal EN of the writing operation example 5 can also be applied. Similarly, as shown in FIG. 23, in the write operation example 3 described in FIG. 12, the rising method of the signal EN of the write operation example 5 may be applied. Similarly, as shown in FIG. 24, in the write operation example 3 described in FIG. 13, the rising method of the signal EN of the write operation example 5 may be applied. Similarly, as shown in FIG. 25, in the write operation example 3 described in FIG. 14, the rising method of the signal EN of the write operation example 5 may be applied. Similarly, as shown in FIG. 26, in the write operation example 4 described in FIG. 15, the rising method of the signal EN of the write operation example 5 may be applied. Similarly, as shown in FIG. 27, in the write operation example 4 described in FIG. 16, the rising method of the signal EN of the write operation example 5 may be applied. <3-3> Effects According to the above-mentioned embodiment, the same effects as in the second embodiment can be obtained. <3-4> Variations of the third embodiment Next, using FIG. 28, the configuration of the input/output interface 101 of the memory system of the variation of the third embodiment will be described in detail. Compared with the input/output interface 101 of the memory system of the modification example of the third embodiment and the input/output interface 101 of the memory system of the modification 2 of the second embodiment, it is further based on the inversion signal of the write enable signal BWE ^~ BWE, and input and output the input and output signal DQ. Specifically, the NAND operation circuit 101g1 outputs the operation result to the NAND operation circuit 101h based on the signals CLE, ALE, and ^~BWE. The NAND arithmetic circuit 101g1 generates a "low" level signal only when the signals CLE, ALE, and ^~ BWE are all at the "high" level. <4> Fourth Embodiment The fourth embodiment will be described. In the fourth embodiment, another configuration of the input/output interface will be described. Furthermore, the basic structure and basic operation of the memory device of the fourth embodiment are the same as the memory devices of the first to third embodiments described above. Therefore, descriptions of matters described in the above-mentioned first to third embodiments and matters that can be analogized from the above-mentioned first to third embodiments are omitted. <4-1> The structure of the input/output interface is shown in FIG. 29, and the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the second embodiment can be combined. Moreover, as shown in FIG. 29, the switch circuit 101q can be used to select which of the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the second embodiment is used者之signal EN. For example, the signal MS can be generated by using a "Set Feature" action or the like and input to the switch circuit 101q to select the output signal. The "setting feature" action is an action such as changing the action mode of LUN100. <4-2> Operation Here, using FIG. 30, the mode selection operation of the memory system of this embodiment will be described. As shown in FIG. 30, when the memory system 1 is powered on (Power on), LUN 100 is set to the first operation mode. Furthermore, the memory controller 20 issues an initialization command "FFh". Next, the memory controller 20 performs the "setting feature" action. Specifically, the memory controller 20 sequentially issues the commands "EFh" and "YYh" for the action of "setting the characteristics" to the LUN 100, and then issues information on the change of the action mode (W-B0 to W-B3). When LUN100 receives commands "EFh" and "YYh" and information (W-B0～W-B3), it changes the operation mode. For example, in this embodiment, it is changed to the second operation mode. Here, the operation of the switch circuit 101q in the case of changing from the first operation mode to the second operation mode will be briefly described. As shown in FIG. 29, for example, in the first operation mode, the switch circuit 101q may be controlled to selectively output the output signal of the OR circuit 101b as the signal EN. However, by switching to the second operation mode, the switch circuit 101q is controlled so that the output signal of the OR circuit 101j is selectively output as the signal EN. Then, as long as the operation mode is not changed by the "set characteristics" operation, the LUN 100 operates in the second operation mode. When you want to make LUN100 operate in the first operation mode, you must change the operation mode by performing the "set feature" action again. <4-3> Effect By using the switch circuit 101q as described above, it is possible to appropriately combine the first and second embodiments to appropriately operate. <4-4> Modification 1 of the fourth embodiment As shown in Fig. 31, the input/output interface 101 of the memory system 1 of the first embodiment and the memory system 1 of the modification 2 of the second embodiment can be combined The input and output interface 101. Moreover, as shown in FIG. 31, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface of the memory system 1 of the modification 2 of the second embodiment can be selected and used by the switch circuit 101r. Which one of 101 signals. For example, the signal MS can be generated by using the "set feature" action or the like, and input to the switch circuit 101r, to select the output signal. The operation of "setting the feature" is the same as the operation explained using FIG. 30. <4-5> Modification 2 of the fourth embodiment As shown in Fig. 32, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface of the memory system 1 of the third embodiment can be combined 101. Furthermore, as shown in FIG. 32, the switch circuit 101q can be used to select which of the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the third embodiment is used The signal of the person. For example, the signal MS can be generated by using the "set feature" action or the like, and input to the switch circuit 101q, to select the output signal. The operation of "setting the feature" is the same as the operation explained using FIG. 30. <4-6> Modification 3 of the fourth embodiment As shown in FIG. 33, it is possible to combine the input/output interface 101 of the memory system 1 of the first embodiment and the memory system 1 of the modification of the third embodiment. Input and output interface 101. Moreover, as shown in FIG. 33, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the modified example of the third embodiment can be selected and used by the switch circuit 101r. Which one of the signals. For example, the signal MS can be generated by using the "set feature" action or the like, and input to the switch circuit 101r, to select the output signal. The operation of "setting the feature" is the same as the operation explained using FIG. 30. <5> Fifth Embodiment The fifth embodiment will be described. In the fifth embodiment, another configuration of the input/output interface will be described. Furthermore, the basic structure and basic operation of the memory device of the fifth embodiment are the same as the memory devices of the first and second embodiments described above. Therefore, descriptions of matters described in the above-mentioned first and second embodiments and matters that can be analogized from the above-mentioned first and second embodiments are omitted. <5-1> The structure of the input/output interface Next, the structure of the input/output interface 101 will be described in detail using FIG. 34. As shown in FIG. 34, the I/O interface 101 ^{inputs and outputs the I/O signal DQ based on the inverted signal ~} BWP of the write protection signal BWP, or the signal from the address register 105. The OR operation circuit 101s ^{generates the signal EN based on the signal ~} BWP and the signal from the address register 105. The OR operation circuit 101s ^{outputs the "low" level signal EN only when the signal ~} BWP and the signal from the address register 105 are both "low" level. ^{In other words, when at least one of the signal ~} BWP and the signal from the address register 105 is at the "high" level, the OR operation circuit 101s outputs the "high" level signal EN. The receiver 120 receives the input/output signal DQ inside the LUN 100 based on the signal EN and the input/output signal DQ. The receiver 120 receives the input/output signal DQ inside the LUN 100 only when the signal EN and the input/output signal DQ are both at a "high" level. <5-2> Operation <5-2-1> Write operation example 6 Using FIG. 35, a write operation example 6 of the memory system 1 of the present embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. At time T20, the memory controller 20 asserts ("low" level) the write protection signal BWP. During the period when the write protection signal BWP is established, the signal EN is maintained at a "high" level. At time T21 after the period t _{CALS has} elapsed since time T20, the memory controller 20 issues write commands "01h" and "80h". After determining the address of LUN 100, at time T22, the memory controller 20 negates ("high" level) the write protection signal BWP. If the write protection signal BWP is negated, the signal EN in the non-selected LUN 100 becomes a "low" level. On the other hand, in the selected LUN 100, since the signal of the address register 105 is maintained at the "high" level, the signal EN is maintained at the "high" level. The other operations are the same as those described using FIG. 8. As described above, in this embodiment, the write protection signal BWP and the control signal EN are used. On the other hand, when this action is implemented, the write protection action cannot be performed. However, if actions such as "setting features" are used, it is possible to appropriately switch between the mode for operating this embodiment and the mode for using the write protection operation. <5-2-2> Write operation example 7 With reference to Figs. 36 and 37, a write operation example 7 of the memory system 1 of the present embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. The method of raising the signal EN in the address operation example 7 is the same as that in the address operation example 6, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described. For example, the column address R3 includes the selected LUN address. After determining the address of LUN 100, at time T23, the memory controller 20 negates ("high" level) the write protection signal BWP. If the write protection signal BWP is negated, the signal EN in the non-selected LUN 100 becomes a "low" level. On the other hand, in the selected LUN 100, since the signal of the address register 105 is maintained at the "high" level, the signal EN is maintained at the "high" level. As shown in FIG. 36, after receiving the column address R3, the signal EN in the non-selected LUN 100 immediately becomes a "low" level. As shown in Figure 37, it is also possible to follow the time sequence before and after the input and output of the data, instead of selecting the signal EN in the LUN 100 to change to the "low" level. <5-2-3> Reading operation example 5 Using FIG. 38, the reading operation example 5 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. At time T25, the memory controller 20 asserts the write protection signal BWP. During the period when the write protection signal BWP is established, the signal EN is maintained at a "high" level. At time T26 after the period t _{CALS has} elapsed since time T25, the read command "05h" is issued. After determining that it is a read operation, at time T27, the memory controller 20 negates ("high" level) the write protection signal BWP. If the write protection signal BWP is negated, the signal EN in the LUN 100 is selected to become a "low" level. <5-2-4> Reading operation example 6 Using FIGS. 39 to 41, the reading operation example 6 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. The rising method of the signal EN of the read operation example 6 is the same as that of the read operation example 5, so the description is omitted. Here, the falling timing of the signal EN of LUN100 will be described. After determining that it is a read operation, at time T28, the memory controller 20 negates ("high" level) the write protection signal BWP. If the write protection signal BWP is negated, the signal EN in the LUN 100 is selected to become a "low" level. As shown in Fig. 39, after receiving the column address R3, the signal EN in the LUN 100 immediately becomes a "low" level. Also, as shown in FIG. 40, after receiving the command "E0h", the signal EN in the LUN 100 immediately changes to the "low" level. Also, as shown in Fig. 41, according to the time sequence before and after the input and output of the data, the signal EN in the LUN 100 becomes the "low" level. <5-3> Effects According to the above-mentioned embodiment, the same effects as in the second embodiment can be obtained. <5-4> Variations of the fifth embodiment In the fifth embodiment, the write protection signal BWP is used to control the signal EN. However, it is also possible to use the signal NP dedicated to the control of the signal EN. In this case, as shown in FIG. 34, the signal NP is input to the OR operation circuit 101s instead of the ^{signal ~BWP.} The signal NP is set to be input from the memory controller 20 to the NAND flash memory 10. <5-4-1> Writing operation example 8 Using FIG. 42, the writing operation example 8 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. At time T20, the memory controller 20 asserts ("High" level) signal NP. During the period when the signal NP is established, the signal EN is maintained at the "high" level. At time T21 after the period t _{CALS has} elapsed since time T20, the memory controller 20 issues write commands "01h" and "80h". After determining the address of LUN 100, at time T22, memory controller 20 negates ("low" level) signal NP. If the signal NP is negated, the signal EN in the non-selected LUN 100 becomes a "low" level. On the other hand, in the selected LUN 100, since the signal of the address register 105 is maintained at the "high" level, the signal EN is maintained at the "high" level. The other operations are the same as those described using FIG. 8. As described above, in this embodiment, the signal NP and the control signal EN are used. <5-4-2> Write operation example 9 With reference to Figs. 43 and 44, a write operation example 9 of the memory system 1 of the present embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. The method of raising the signal EN in the writing operation example 9 is the same as that in the writing operation example 8, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN 100 will be described. For example, the column address R3 includes the selected LUN address. After determining the address of LUN 100, at time T23, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the non-selected LUN 100 becomes a "low" level. On the other hand, in the selected LUN 100, since the signal of the address register 105 is maintained at the "high" level, the signal EN is maintained at the "high" level. As shown in FIG. 43, after receiving the column address R3, the signal EN in the non-selected LUN 100 immediately becomes a "low" level. As shown in Figure 44, it is also possible to follow the time sequence before and after the input and output of the data, instead of selecting the signal EN in the LUN 100 to change to the "low" level. <5-4-3> Reading operation example 7 Using FIG. 45, the reading operation example 7 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. At time T25, the memory controller 20 asserts the signal NP. During the period when the signal NP is established, the signal EN is maintained at the "high" level. At time T26 after the period t _{CALS has} elapsed since time T25, the read command "05h" is issued. After determining that it is a read operation, at time T27, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the LUN 100 is selected to become a "low" level. <5-4-4> Reading operation example 8 Using FIGS. 46 to 48, the reading operation example 8 of the memory system 1 of this embodiment will be described. Here, the instruction sequence of the memory group GP0 will be described. The rising method of the signal EN in the reading operation example 8 is the same as that in the reading operation example 7, so the description is omitted. Here, the falling timing of the signal EN of LUN100 will be described. After determining that it is a read operation, at time T28, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the LUN 100 is selected to become a "low" level. As shown in FIG. 46, after receiving the column address R3, the signal EN in the LUN 100 immediately becomes a "low" level. Also, as shown in FIG. 47, after receiving the command "E0h", the signal EN in the LUN 100 immediately changes to the "low" level. Also, as shown in Fig. 48, it is also possible to follow the time sequence before and after the input and output of the data, and the signal EN in the LUN 100 becomes a "low" level. <6> Sixth Embodiment The sixth embodiment will be described. In the sixth embodiment, another configuration of the input/output interface will be described. Furthermore, the basic structure and basic operation of the memory device of the sixth embodiment are the same as the memory devices of the first and fifth embodiments described above. Therefore, descriptions of matters described in the above-mentioned first and fifth embodiments and matters that can be analogized from the above-mentioned first and fifth embodiments are omitted. <6-1> The configuration of the input/output interface is shown in FIG. 49, which can combine the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the fifth embodiment. Furthermore, as shown in FIG. 49, the switch circuit 101t can be used to select which of the input/output interface 101 of the memory system 1 of the first embodiment or the input/output interface 101 of the memory system 1 of the fifth embodiment is used者之signal EN. For example, the signal MS can be generated by using the "set feature" action, etc., and input to the switch circuit 101t to select the output signal. The operation of "setting the feature" is the same as the operation explained using FIG. 30. <7> Seventh Embodiment The seventh embodiment will be described. In the seventh embodiment, another configuration of the receiver will be described. Furthermore, the basic structure and basic operation of the memory device of the seventh embodiment are the same as the memory devices of the first to sixth embodiments described above. Therefore, descriptions of matters described in the first to sixth embodiments described above and matters that can be analogized from the first to sixth embodiments described above are omitted. The receiver described below can be applied to the above-mentioned embodiments. <7-1> The structure of the receiver Using FIG. 50, another example of the receiver 120 will be described. For example, during standby (when data is not being transferred), it is better to suppress current consumption in terms of reducing power consumption. Therefore, in this embodiment, the receiver 120 includes a first receiver 101v that cannot operate at high speed but low current consumption, a second receiver 101w that can operate at high speed but high current consumption, and selects the first receiver. The switch circuit 101u of the connection between the receiver 101v and the second receiver 101w. The switch circuit 101u connects the data input and output line to the first receiver 101v when the signal EN is at the "low" level, and connects the data input and output line to the second receiver when the signal EN is at the "high" level. The receiver 101w. <7-2> The configuration of the first receiver Using FIG. 51, a circuit example of the first receiver 101v will be described. As shown in FIG. 51, the first receiver 101v includes a PMOS (Positive-channel Metal Oxide Aemiconductor: positive-channel metal oxide semiconductor) transistor 11a and an NMOS (Negative-channel Metal Mxide Memiconductor: negative-channel metal oxide semiconductor) transistor 11a. Inverter of crystal 11b. The power supply voltage VDD is applied to the source of the PMOS transistor 11a, the drain is connected to the output terminal (node N2), and the gate is connected to the input terminal (node N1). The drain of the NMOS transistor 11b is connected to the output terminal (node N2), the source is connected to the ground potential, and the gate is connected to the input terminal (node N1). That is, the first receiver 101v outputs a "high" level signal from the output terminal when the input signal is at a "low" level, and outputs a signal from the output terminal when the input signal is at a "high" level "Low" level signal. <7-3> The configuration of the second receiver Using FIG. 52, a circuit example of the second receiver 101w will be described. As shown in FIG. 52, the second receiver 101w includes a mirror circuit including PMOS transistors 11c, 11d, 11e, and 11f and NMOS transistors 11g, 11h, and 11i. The power supply voltage VDD is applied to the source of the PMOS transistor 11c, and a signal ENBn (inverted signal of the signal EN) is input to the gate. The PMOS transistor 11c flows current when the signal ENBn is at the "low" level. The source of the PMOS transistor 11e is connected to the drain of the PMOS transistor 11c, and the drain is connected to the gate. The power supply voltage VDD is applied to the source of the PMOS transistor 11d, and the signal ENBn is input to the gate. The PMOS transistor 11d flows current when the signal ENBn is at the "low" level. The source of the PMOS transistor 11f is connected to the drain of the PMOS transistor 11d, and the drain is connected to the output terminal (node N6), and the gate is connected to the node N5. The PMOS transistor 11f flows the same current as the PMOS transistor 11e. The drain of the NMOS transistor 11g is connected to the node N5, the source is connected to the node N7, and a reference voltage VREF is applied to the gate. The reference current flows through the NMOS transistor 11g. The drain of the NMOS transistor 11h is connected to the output terminal (node N6), the source is connected to the node N7, and the gate is connected to the input terminal. The drain of the NMOS transistor 11i is connected to the node N7, the source is connected to the ground potential, and a reference voltage IREFN is applied to the gate. This NMOS transistor 11i functions as a constant current source. That is, when the signal ENBn is at the "low" level and the input signal is at the "low" level, the second receiver 101w outputs a "high" level signal from the output terminal, when the signal ENBn is at the "low" level. When the input signal is at the "high" level, the output terminal will output the "low" level signal. <8> Supplementary explanation In addition, Fig. 53 shows the conditions for the signal EN to rise (to enable all LUNs 100) in the above-mentioned embodiments. In addition, in each of the above-mentioned embodiments, the falling timing of the signal EN has been variously described, but it is not limited to the above-mentioned timing and can be changed as appropriate. Specifically, as long as the timing signal EN before and after the input and output of the start data falls. In this way, it is possible to suppress useless current consumption for non-selected LUNs or LUNs during read operations. In addition, in each embodiment of the present invention: (1) In the read operation, the voltage applied to the selected word line in the read operation of the A level is, for example, between 0 V and 0.55 V. It is not limited to this, and it may be set to any one of 0.1 V to 0.24 V, 0.21 V to 0.31 V, 0.31 V to 0.4 V, 0.4 V to 0.5 V, and 0.5 V to 0.55 V. The voltage applied to the selected word line for the read operation of the B level is, for example, between 1.5 V and 2.3 V. It is not limited to this, and it may be set to any one of 1.65 V to 1.8 V, 1.8 V to 1.95 V, 1.95 V to 2.1 V, and 2.1 V to 2.3 V. The voltage applied to the selected word line for the read operation of the C level is, for example, between 3.0 V and 4.0 V. It is not limited to this, and it may be set to any of 3.0 V to 3.2 V, 3.2 V to 3.4 V, 3.4 V to 3.5 V, 3.5 V to 3.6 V, and 3.6 V to 4.0 V. As the time (tR) of the read operation, it can also be set between 25 μs to 38 μs, 38 μs to 70 μs, or 70 μs to 80 μs, for example. (2) The write operation includes a program operation and a verification operation as described above. In the writing operation, the voltage initially applied to the selected word line during the programming operation is, for example, between 13.7 V and 14.3 V. It is not limited to this, for example, it may be set to any one of 13.7 V to 14.0 V and 14.0 V to 14.6 V. It is also possible to change the voltage initially applied to the selected word line when writing to the odd-numbered character line, and the voltage initially applied to the selected word line when writing to the even-numbered character line. When the programming action is set to the ISPP mode (Incremental Step Pulse Program), the boosted voltage is, for example, about 0.5 V. The voltage applied to the non-selected character line may also be between 6.0 V and 7.3 V, for example. It is not limited to this, for example, it may be between 7.3 V and 8.4 V, or it may be 6.0 V or less. It is also possible to change the applied path voltage according to whether the non-selected character line is an odd-numbered character line or an even-numbered character line. The time (tProg) of the write operation can also be set between 1700 μs to 1800 μs, 1800 μs to 1900 μs, or 1900 μs to 2000 μs, for example. (3) In the erasing operation, the voltage initially applied to the wafer formed on the upper part of the semiconductor substrate with the above-mentioned memory cells arranged thereon is, for example, between 12 V and 13.6 V. It is not limited to this case, and it may be set to, for example, between 13.6 V to 14.8 V, 14.8 V to 19.0 V, 19.0 to 19.08 V, and 19.8 V to 21 V. As the erasing time (tErase), it can also be set between 3000 μs to 4000 μs, 4000 μs to 5000 μs, or 4000 μs to 9000 μs, for example. (4) The structure of the memory cell has a charge storage layer arranged on a semiconductor substrate (silicon substrate) through a tunnel insulating film with a thickness of 4-10 nm. The charge storage layer can be a laminated structure of SiN with a thickness of 2 to 3 nm, or an insulating film such as SiON, and a polysilicon with a thickness of 3 to 8 nm. In addition, metals such as Ru may be added to polysilicon. There is an insulating film on the charge storage layer. The insulating film has, for example, a lower layer High-k (high dielectric constant) film with a film thickness of 3-10 nm, and a film thickness of 4-10 nm sandwiched by the upper layer High-k film with a film thickness of 3-10 nm. The silicon oxide film. Examples of High-k films include HfO. In addition, the film thickness of the silicon oxide film can be set to be thicker than the film thickness of the High-k film. On the insulating film, a control electrode with a film thickness of 30 nm to 70 nm is formed through a material with a thickness of 3-10 nm. Here, the material for work function adjustment is, for example, a metal oxide film such as TaO, and a metal nitride film such as TaN. W etc. can be used for the control electrode. In addition, air gaps can be formed between memory cells. Although the embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments, and can be implemented with various changes without departing from the spirit of the present invention. Furthermore, the foregoing embodiments include inventions of various stages, and various inventions can be extracted by appropriately combining the constituent elements disclosed. For example, if some constituent elements are removed from the disclosed constituent elements, and certain effects can still be obtained, it can also be extracted as an invention.

01h: write command 05h: read command 1: memory system 10: NAND flash memory 11a: PMOS transistor 11b: NMOS transistor 11c～11f: PMOS transistor 11g～11i: NMOS transistor 20: memory Controller 30: host machine 80h: write command 100: LUN 101: input and output interface 101a: AND operation circuit 101b: OR operation circuit 101c: NAND operation circuit 101d: inverter 101g: NAND operation circuit 101g1: NAND operation circuit 101h : NAND operation circuit 101i: NAND operation circuit 101j: OR operation circuit 101k: NAND operation circuit 101l: NAND operation circuit 101m: NAND operation circuit 101n: inverter 101o: AND operation circuit 101p: OR operation circuit 101q: switch circuit 101r: Switching circuit 101s: OR operation circuit 101t: Switching circuit 101u: Switching circuit 101v: First receiver 101w: Second receiver 102: Control signal input interface 103: Control circuit 104: Command register 104a: Memory 105: Bit Address register 105a: Memory 106: State register 110: Memory cell array 111: Sense amplifier 112: Data register 113: Row decoder 114: Row buffer 115: Column address decoder 116: Column Address buffer decoder 120: receiver 130: transmitter 210: host interface (host I/F) 220: built-in memory (RAM) 230: processor (CPU) 240: buffer memory 250: NAND interface (NAND I /F) ADD: address ALE: address latch enable signal BCE: chip enable signal BDQS: data strobe signal BRE: read enable signal BWE: write enable signal BWP: write protection signal C1: Row address C2: Row address CLE: Command latch enable signal CMD: Command D0～Dn: Write data DQ: Input and output signal DQ0～DQ7: Input and output signal DQS: Data strobe signal E0h: Command EFh: Command ENBn: signal EN: signal FFh: initialization command GP0: memory group GP1: memory group IREFN: reference voltage MS: signal N1～N7: node NP: signal R1～R3: column address RE: read enable signal RY /BBY: Ready·Busy signal T0～T29: Time t _CALS : Period VDD: Power supply voltage VREF: Reference voltage W-B0～W-B3: Information XXh: Command YYh: Command ^～ ALE: Reverse signal ^～ BCE: Reverse Signal ^~ BWE: Reverse signal ^~ BWP: Reverse signal ^~ CLE: Reverse signal

Fig. 1 is a block diagram of the memory system of the first embodiment. Fig. 2 is a block diagram of the LUN of the memory system of the first embodiment. Fig. 3 is a circuit diagram of the input/output interface of the memory system of the first embodiment. Fig. 4 is a schematic diagram of the operation of the memory system of the first embodiment. Fig. 5 is a timing chart showing an example of a write operation in the memory system of the first embodiment. Fig. 6 is a timing chart showing an example of a read operation of the memory system of the first embodiment. Fig. 7 is a circuit diagram of the input/output interface of the memory system of the second embodiment. Fig. 8 is a timing chart showing an example of a write operation in the memory system of the second embodiment. Fig. 9 is a timing chart showing an example of a write operation in the memory system of the second embodiment. Fig. 10 is a timing chart showing an example of a write operation in the memory system of the second embodiment. Fig. 11 is a timing chart showing an example of a read operation of the memory system of the second embodiment. Fig. 12 is a timing chart showing an example of the read operation of the memory system of the second embodiment. Fig. 13 is a timing chart showing an example of a read operation of the memory system of the second embodiment. Fig. 14 is a timing chart showing an example of the read operation of the memory system of the second embodiment. Fig. 15 is a timing chart showing an example of a write operation in the memory system of Modification 1 of the second embodiment. Fig. 16 is a timing chart showing an example of the read operation of the memory system of Modification 1 of the second embodiment. Fig. 17 is a circuit diagram of the input/output interface of the memory system of Modification 2 of the second embodiment. Fig. 18 is a circuit diagram of the input/output interface of the memory system of the third embodiment. Fig. 19 is a timing chart showing an example of a write operation in the memory system of the third embodiment. Fig. 20 is a timing chart showing an example of a write operation in the memory system of the third embodiment. Fig. 21 is a timing chart showing an example of a write operation in the memory system of the third embodiment. Fig. 22 is a timing chart showing an example of the read operation of the memory system of the third embodiment. Fig. 23 is a timing chart showing an example of the read operation of the memory system of the third embodiment. Fig. 24 is a timing chart showing an example of a read operation of the memory system of the third embodiment. Fig. 25 is a timing chart showing an example of the read operation of the memory system of the third embodiment. Fig. 26 is a timing chart showing an example of a write operation in the memory system of the third embodiment. Fig. 27 is a timing chart showing an example of the read operation of the memory system of the third embodiment. Fig. 28 is a circuit diagram of the input/output interface of the memory system of a modification of the third embodiment. Fig. 29 is a circuit diagram of the input/output interface of the memory system of the fourth embodiment. Fig. 30 is a diagram showing the mode selection operation of the memory system of the fourth embodiment. Fig. 31 is a circuit diagram of the input/output interface of the memory system of Modification 1 of the fourth embodiment. Fig. 32 is a circuit diagram of the input/output interface of the memory system of Modification 2 of the fourth embodiment. FIG. 33 is a circuit diagram of the input and output interface of the memory system of the third modification of the fourth embodiment. Fig. 34 is a circuit diagram of the input/output interface of the memory system of the fifth embodiment. Fig. 35 is a timing chart showing an example of a write operation in the memory system of the fifth embodiment. Fig. 36 is a timing chart showing an example of a write operation in the memory system of the fifth embodiment. Fig. 37 is a timing chart showing an example of a write operation in the memory system of the fifth embodiment. Fig. 38 is a timing chart showing an example of a read operation of the memory system of the fifth embodiment. Fig. 39 is a timing chart showing an example of the read operation of the memory system of the fifth embodiment. Fig. 40 is a timing chart showing an example of the read operation of the memory system of the fifth embodiment. Fig. 41 is a timing chart showing an example of a read operation of the memory system of the fifth embodiment. Fig. 42 is a timing chart showing an example of a write operation in the memory system of a modified example of the fifth embodiment. Fig. 43 is a timing chart showing an example of a write operation in the memory system of a modified example of the fifth embodiment. Fig. 44 is a timing chart showing an example of a write operation in the memory system of a modified example of the fifth embodiment. Fig. 45 is a timing chart showing an example of a read operation of the memory system of a modified example of the fifth embodiment. Fig. 46 is a timing chart showing an example of a read operation of the memory system of a modified example of the fifth embodiment. Fig. 47 is a timing chart showing an example of a read operation of the memory system of a modified example of the fifth embodiment. Fig. 48 is a timing chart showing an example of a read operation of the memory system of a modified example of the fifth embodiment. Fig. 49 is a circuit diagram of the input/output interface of the memory system of the sixth embodiment. Fig. 50 is a circuit diagram of the receiver of the memory system of the seventh embodiment. Fig. 51 is a circuit diagram of the first receiver of the memory system of the seventh embodiment. Fig. 52 is a circuit diagram showing the second receiver of the memory system of the seventh embodiment. Fig. 53 is a diagram showing the operating conditions of the memory system of the first to fifth embodiments.

101: Input and output interface

101c: NAND operation circuit

101d: inverter

101g: NAND operation circuit

101h: NAND operation circuit

101i: NAND operation circuit

101j: OR operation circuit

104: Command register

105: Address register

105a: Memory Department

120: receiver

ADD: address

ALE: address latch enable signal

BWE: Write enabling signal

CLE: instruction latch enable signal

DQ: Input and output signal

EN: Signal

Claims (1)

A memory device comprising: Memory cell array, its memory data; A control circuit, which responds to instructions to control the aforementioned memory cell array; An arithmetic circuit that outputs a third signal based on the first signal for storing the command in the command register and the second signal for storing the address in the address register; and A receiver, which can receive data based on the third signal; The third signal includes: a first level to make the receiver in an active state, and a second level to make the receiver in a standby state; The arithmetic circuit is: at least one of the first signal or the second signal is asserted in the first period, and the first signal and the second signal are asserted in the second period after the first period Both are negated, and if at least one of the first signal or the second signal is re-established in the third period after the second period, the first level can be maintained during the second period The output of the third signal above.

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