TWI780908B - Ring oscillator circuit and information processing device - Google Patents
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Abstract
本發明主要揭示一種環形振盪器電路,其基礎上包含一第一偏置單元、一第二偏置單元以及一環形振盪器單元,其中該第一偏置單元依據一電源電壓產生一第一偏置電壓與一第二偏置電壓,且該第二偏置單元依據該電源電壓以及所述第一偏置電壓而產生一第一工作電壓與一第二工作電壓。並且,該環形振盪器單元耦接該電源電壓與該接地端,且同時耦接傳送自該第一偏置單元的該第二偏置電壓以及傳送自該第二偏置單元的該第一工作電壓和該第二工作電壓。依據本發明之設計,該環形振盪器單元包括N個級聯的反相器,且所述第一工作電壓供電至各所述反相器的一第一偏置端,而所述第二工作電壓則供電至各所述反相器的一第二偏置端。如此設計,各所述反相器不由電子晶片的電源電壓所偏置,因此由第N個反相器所輸出的時鐘信號的頻率不受電源電壓和溫度的影響,從而保持時鐘信號的頻率的穩定。The present invention mainly discloses a ring oscillator circuit, which basically includes a first bias unit, a second bias unit and a ring oscillator unit, wherein the first bias unit generates a first bias according to a power supply voltage setting voltage and a second bias voltage, and the second bias unit generates a first working voltage and a second working voltage according to the power supply voltage and the first bias voltage. In addition, the ring oscillator unit is coupled to the power supply voltage and the ground terminal, and is simultaneously coupled to the second bias voltage transmitted from the first bias unit and the first working voltage transmitted from the second bias unit. voltage and the second operating voltage. According to the design of the present invention, the ring oscillator unit includes N cascaded inverters, and the first operating voltage supplies power to a first bias terminal of each of the inverters, and the second operating voltage The voltage is then supplied to a second bias terminal of each of the inverters. Designed in this way, each of the inverters is not biased by the power supply voltage of the electronic chip, so the frequency of the clock signal output by the Nth inverter is not affected by the power supply voltage and temperature, thereby maintaining the frequency of the clock signal. Stablize.
Description
本發明係關於振盪器之技術領域,尤指具低溫度漂移係數和低電源漂移係數的一種環形振盪器電路。The invention relates to the technical field of oscillators, in particular to a ring oscillator circuit with low temperature drift coefficient and low power supply drift coefficient.
已知,電子振盪器(electronic oscillator)是用來產生具有周期性的類比訊號(如弦波、方波、或三角波)的一種特殊電子電路,目前已經被廣泛地應用在積體電路晶片(即,電子晶片)之中,用以提供一時鐘信號,使該電子晶片內的電路單元依據所述時鐘信號而協同工作。It is known that an electronic oscillator is a special electronic circuit used to generate a periodic analog signal (such as a sine wave, a square wave, or a triangle wave), and has been widely used in integrated circuit chips (ie , electronic chip), to provide a clock signal, so that the circuit units in the electronic chip work together according to the clock signal.
圖1顯示習知的一種環形振盪器(Ring oscillator)電路的電路拓樸圖。如圖1所示,電子工程師都知道,習知的環形振盪器電路1a包括N個級聯的反相器11a,其中N為大於或等於3的奇數,且第1個反相器11a與第N個反相器11a首尾級聯。在滿足巴克豪森準則(Barkhausen criterion)的情況下,該環形振盪器電路1a起振從而輸出一時鐘信號CLK。並且,該時鐘信號CLK的頻率可利用下式(a)表示:
·········································· (a)
FIG. 1 shows a circuit topology diagram of a conventional ring oscillator (Ring oscillator) circuit. As shown in FIG. 1, electronic engineers know that the known ring oscillator circuit 1a includes
於上式(a)中,N為所述反相器11a的數量,且Td為單個反相器11a的延遲時間。更詳細地說明,如圖1所示,所述反相器11a包括互相疊接的一P型MOSFET元件111a與一N型MOSFET元件112a。因此,該時鐘信號CLK的頻率可利用下式(b)表示:
································ (b)
In the above formula (a), N is the number of the
於上式(b)中,Ceff為反相器11a的輸入輸出節點等效電容,VDD為電子晶片的第一電源電壓(通常為高電壓),VSS為為電子晶片的第二電源電壓(通常為接地或相對於VDD的低電壓),且I為反相器11a的工作電流。進一步地,由式(a)與式(b)可發現,工作電壓(或稱電源電壓)與工作電流的漂移必然對時鐘信號CLK的頻率造成顯著影響。值得注意的是,在電子晶片工作時,受到信號耦合、雜訊、晶片片自發熱等影響,工作電壓和工作溫度難以避免的會發生變化,進而導致時鐘信號CLK的頻率產生偏移,使得該電子晶片內的電路單元無法完美地實現協同工作,導致電子晶片出現工作異常。In the above formula (b), Ceff is the equivalent capacitance of the input and output nodes of the
由上述說明可知,本領域亟需具低溫度漂移係數和低電源漂移係數的一種環形振盪器電路。From the above description, it can be seen that there is an urgent need in the art for a ring oscillator circuit with low temperature drift coefficient and low power supply drift coefficient.
本發明之主要目的在於提供一種環形振盪器電路,其基礎上包含一第一偏置單元、一第二偏置單元以及一環形振盪器單元,其中該第一偏置單元依據一電源電壓產生一第一偏置電壓與一第二偏置電壓,且該第二偏置單元依據該電源電壓以及所述第一偏置電壓而產生一第一工作電壓與一第二工作電壓。並且,該環形振盪器單元耦接該電源電壓與該接地端,且同時耦接傳送自該第一偏置單元的該第二偏置電壓以及傳送自該第二偏置單元的該第一工作電壓和該第二工作電壓。依據本發明之設計,該環形振盪器單元包括N個級聯的反相器,且所述第一工作電壓供電至各所述反相器的一第一偏置端,而所述第二工作電壓則供電至各所述反相器的一第二偏置端。如此設計,各所述反相器不由電子晶片的電源電壓所偏置,因此由第N個反相器所輸出的時鐘信號的頻率不受電源電壓和溫度的影響,從而保持時鐘信號的頻率的穩定。The main object of the present invention is to provide a ring oscillator circuit, which basically includes a first bias unit, a second bias unit and a ring oscillator unit, wherein the first bias unit generates a The first bias voltage and a second bias voltage, and the second bias unit generates a first operating voltage and a second operating voltage according to the power supply voltage and the first bias voltage. In addition, the ring oscillator unit is coupled to the power supply voltage and the ground terminal, and is simultaneously coupled to the second bias voltage transmitted from the first bias unit and the first working voltage transmitted from the second bias unit. voltage and the second operating voltage. According to the design of the present invention, the ring oscillator unit includes N cascaded inverters, and the first operating voltage supplies power to a first bias terminal of each of the inverters, and the second operating voltage The voltage is then supplied to a second bias terminal of each of the inverters. Designed in this way, each of the inverters is not biased by the power supply voltage of the electronic chip, so the frequency of the clock signal output by the Nth inverter is not affected by the power supply voltage and temperature, thereby maintaining the frequency of the clock signal. Stablize.
為達成上述目的,本發明提出所述環形振盪器電路路的實施例,其包括:To achieve the above object, the present invention proposes an embodiment of the ring oscillator circuit, which includes:
一第一偏置單元,耦接一電源電壓和一接地端,用以產生一第一偏置電壓與一第二偏置電壓;a first bias unit, coupled to a power supply voltage and a ground terminal, for generating a first bias voltage and a second bias voltage;
一第二偏置單元,耦接傳送自該第一偏置單元的該第一偏置電壓、該電源電壓和該接地端,用以產生一第一工作電壓與一第二工作電壓;以及a second bias unit, coupled to the first bias voltage transmitted from the first bias unit, the power supply voltage and the ground terminal, for generating a first operating voltage and a second operating voltage; and
一環形振盪器單元,耦接傳送自該第一偏置單元的該第二偏置電壓、傳送自該第二偏置單元的該第一工作電壓以及該第二工作電壓、該電源電壓、與該接地端,且包括N個級聯的反相器,其中N為大於或等於3的奇數,且第1個所述反相器與第N個所述反相器首尾級聯;A ring oscillator unit, coupled to the second bias voltage transmitted from the first bias unit, the first operating voltage and the second operating voltage transmitted from the second bias unit, the power supply voltage, and The ground terminal, and includes N cascaded inverters, where N is an odd number greater than or equal to 3, and the first inverter is cascaded end-to-end with the Nth inverter;
其中,所述第一工作電壓供電至各個所述反相器的一第一偏置端,且所述第二工作電壓供電至各個所述反相器的一第二偏置端。Wherein, the first working voltage is supplied to a first bias terminal of each of the inverters, and the second working voltage is supplied to a second bias terminal of each of the inverters.
在一實施例中,本發明之所述環形振盪器電路更包括:一啟動單元,其耦接該電源電壓和該接地端,用以啟動該第一偏置單元。In one embodiment, the ring oscillator circuit of the present invention further includes: a startup unit coupled to the power supply voltage and the ground terminal for starting the first bias unit.
在一實施例中,該第二偏置單元包括:In one embodiment, the second bias unit includes:
一第一P型MOSFET元件,其一源極端耦接該電源電壓,且其一閘極端耦接該第一偏置電壓;A first P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to the first bias voltage;
一第一N型MOSFET元件,其一汲極端耦接該第一P型MOSFET元件的一汲極端,且其一源極端耦接該接地端;其中,該第一N型MOSFET元件的該汲極端還耦接其一閘極端;A first N-type MOSFET element, a drain end of which is coupled to a drain end of the first P-type MOSFET element, and a source end of which is coupled to the ground end; wherein, the drain end of the first N-type MOSFET element Also coupled to one gate terminal;
一第二P型MOSFET元件,其一源極端耦接該電源電壓,且其一閘極端耦接該第一偏置電壓;以及A second P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to the first bias voltage; and
一第二N型MOSFET元件,其一汲極端耦接該第二P型MOSFET元件的一汲極端,且其一源極端耦接該接地端;其中,該第二N型MOSFET元件的該汲極端還耦接其一閘極端。A second N-type MOSFET element, a drain end of which is coupled to a drain end of the second P-type MOSFET element, and a source end of which is coupled to the ground end; wherein, the drain end of the second N-type MOSFET element Also couple to one of its gate terminals.
在一實施例中,該啟動單元包括:In one embodiment, the startup unit includes:
一第三P型MOSFET元件,其一源極端耦接該電源電壓,且其一閘極端透過一第一電阻而耦接該接地端;A third P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to the ground end through a first resistor;
一第三N型MOSFET元件,其一汲極端耦接該第三P型MOSFET元件的一汲極端,且其一源極端耦接該接地端;A third N-type MOSFET element, a drain end of which is coupled to a drain end of the third P-type MOSFET element, and a source end of which is coupled to the ground end;
一第四P型MOSFET元件,其一源極端耦接該電源電壓;A fourth P-type MOSFET element, one source terminal of which is coupled to the power supply voltage;
一第四N型MOSFET元件,其一汲極端耦接該第四P型MOSFET元件的一汲極端,其一源極端耦接該接地端,且其一閘極端耦接該第三N型MOSFET元件的一閘極端;其中,該第四N型MOSFET元件的該汲極端還耦接其所述閘極端;以及A fourth N-type MOSFET element, one drain end of which is coupled to a drain end of the fourth P-type MOSFET element, one source end thereof is coupled to the ground end, and one gate end thereof is coupled to the third N-type MOSFET element a gate terminal of the fourth N-type MOSFET element; wherein, the drain terminal of the fourth N-type MOSFET element is also coupled to the gate terminal thereof; and
一第五N型MOSFET元件,其一汲極端耦接該第四P型MOSFET元件的一閘極端,其一源極端耦接該接地端,且其一閘極端耦接該第三P型MOSFET元件的該汲極端與該第三N型MOSFET元件的該汲極端之間的一第一共接點。A fifth N-type MOSFET element, one drain end is coupled to a gate end of the fourth P-type MOSFET element, one source end is coupled to the ground end, and one gate end is coupled to the third P-type MOSFET element A first common point between the drain terminal of the third N-type MOSFET element and the drain terminal of the third N-type MOSFET element.
在一可行實施例中,該第一偏置單元包括:In a feasible embodiment, the first bias unit includes:
一第五P型MOSFET元件,其一源極端耦接該電源電壓;a fifth P-type MOSFET element, one source end of which is coupled to the power supply voltage;
一第六N型MOSFET元件,其一汲極端耦接該第五P型MOSFET元件的一汲極端,其一源極端耦接該接地端,且其一閘極端耦接其所述汲極端;A sixth N-type MOSFET element, one drain end of which is coupled to a drain end of the fifth P-type MOSFET element, one source end thereof is coupled to the ground end, and one gate end thereof is coupled to the drain end thereof;
一第六P型MOSFET元件,其一源極端耦接該電源電壓,其一閘極端耦接該第五P型MOSFET元件的一閘極端;其中,該第五N型MOSFET元件的該汲極端與該第四P型MOSFET元件的該閘極端之間的一第二共接點係耦接至該第六P型MOSFET元件的該閘極端與該第五P型MOSFET元件的該閘極端之間的一第三共接點,且該第六P型MOSFET元件的一汲極端耦接該第三共接點;A sixth P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to a gate end of the fifth P-type MOSFET element; wherein, the drain end of the fifth N-type MOSFET element is connected to the A second common point between the gate terminals of the fourth P-type MOSFET element is coupled to the gate terminal between the gate terminal of the sixth P-type MOSFET element and the gate terminal of the fifth P-type MOSFET element. a third common point, and a drain end of the sixth P-type MOSFET element is coupled to the third common point;
至少一第七N型MOSFET元件,其中,各所述第七N型MOSFET元件的一汲極端耦接該第六P型MOSFET元件的該汲極端,且其一源極端透過一第二電阻而耦接該接地端;其中,各所述第七N型MOSFET元件的一閘極端耦接該第六N型MOSFET元件的該閘極端。At least one seventh N-type MOSFET element, wherein a drain end of each of the seventh N-type MOSFET elements is coupled to the drain end of the sixth P-type MOSFET element, and a source end thereof is coupled to the drain end through a second resistor connected to the ground terminal; wherein, a gate terminal of each seventh N-type MOSFET element is coupled to the gate terminal of the sixth N-type MOSFET element.
在另一可行實施例中,該第一偏置單元包括:In another feasible embodiment, the first bias unit includes:
一第五P型MOSFET元件,其一源極端耦接該電源電壓;a fifth P-type MOSFET element, one source end of which is coupled to the power supply voltage;
一第六P型MOSFET元件,其一源極端耦接該電源電壓,其一閘極端耦接該第五P型MOSFET元件的一閘極端;其中,該第五N型MOSFET元件的該汲極端與該第四P型MOSFET元件的該閘極端之間的一第二共接點係耦接至該第六P型MOSFET元件的該閘極端與該第五P型MOSFET元件的該閘極端之間的一第三共接點;A sixth P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to a gate end of the fifth P-type MOSFET element; wherein, the drain end of the fifth N-type MOSFET element is connected to the A second common point between the gate terminals of the fourth P-type MOSFET element is coupled to the gate terminal between the gate terminal of the sixth P-type MOSFET element and the gate terminal of the fifth P-type MOSFET element. - a third common contact;
一運算放大器,具有一正輸入端、一負輸入端和一輸出端,並以其所述正輸入端耦接該第六P型MOSFET元件的一汲極端,以其所述負輸入端耦接該第五P型MOSFET元件的一汲極端,且以其所述輸出端同時耦接該第三共接點;An operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and is coupled to a drain terminal of the sixth P-type MOSFET element with its positive input terminal, and coupled to the sixth P-type MOSFET element with its negative input terminal. a drain end of the fifth P-type MOSFET element, and the output end thereof is simultaneously coupled to the third common point;
一第一BJT元件,其一射極端耦接該運算放大器的該負輸入端,且其一集極端與一基極端皆耦接該接地端;a first BJT element, an emitter end of which is coupled to the negative input end of the operational amplifier, and a collector end and a base end of which are both coupled to the ground end;
至少一第二BJT元件,其中各所述第二BJT元件之一射極端係透過一第二電阻耦接該第六P型MOSFET元件的該汲極端,且其一集極端與一基極端皆耦接該接地端。at least one second BJT element, wherein an emitter of each second BJT element is coupled to the drain end of the sixth P-type MOSFET element through a second resistor, and a collector end and a base end thereof are both coupled Connect to the ground terminal.
在一實施例中,該環形振盪器單元更包括:In one embodiment, the ring oscillator unit further includes:
一第緩衝器,其一輸入端耦接該第一N型MOSFET元件的該源極端以接收所述第一工作電壓,且以其一輸出端輸出一第一緩衝工作電壓;a first buffer, one input end of which is coupled to the source end of the first N-type MOSFET element to receive the first operating voltage, and an output end thereof to output a first buffered operating voltage;
一第二緩衝器,其一輸入端耦接該第二N型MOSFET元件的該源極端以接收所述第二工作電壓,且以其一輸出端傳送一第二緩衝工作電壓;a second buffer, one input end of which is coupled to the source end of the second N-type MOSFET element to receive the second operating voltage, and an output end thereof to transmit a second buffered operating voltage;
一第一主動負載,其一第一端耦接該第一緩衝器的該輸出端;a first active load, a first terminal of which is coupled to the output terminal of the first buffer;
一第一主動元件,具有一第一端、一第二端與一第三端,其中該第一端耦接該第六N型MOSFET元件的該閘極端和所述第七N型MOSFET元件的該閘極端之間的一第四共接點,該第二端耦接該主動負載的一第二端,且該第三端耦接該接地端;A first active element having a first end, a second end and a third end, wherein the first end is coupled to the gate end of the sixth N-type MOSFET element and the seventh N-type MOSFET element a fourth common point between the gate terminals, the second terminal is coupled to a second terminal of the active load, and the third terminal is coupled to the ground terminal;
一第二主動負載,其一第一端耦接該第二緩衝器的該輸出端;a second active load, a first end of which is coupled to the output end of the second buffer;
一第二主動元件,具有一第一端、一第二端與一第三端,其中該第一端耦接該第三共接點,該第二端耦接該第二主動負載的一第二端,且該第三端耦接該電源電壓;A second active element has a first end, a second end and a third end, wherein the first end is coupled to the third common point, and the second end is coupled to a first end of the second active load two terminals, and the third terminal is coupled to the power supply voltage;
N個第一偏置電壓傳送元件,其中,各所述第一偏置電壓傳送元件具有一第一端、一第二端與一第三端,該第一端耦接該第一主動元件的該第二端,該第二端耦接所述反相器的該第一偏置端,且該第三端耦接該第一緩衝器的該輸出端;N first bias voltage transmission elements, wherein each of the first bias voltage transmission elements has a first end, a second end and a third end, and the first end is coupled to the first active element. the second terminal, the second terminal is coupled to the first bias terminal of the inverter, and the third terminal is coupled to the output terminal of the first buffer;
N個第二偏置電壓傳送元件,其中,各所述第二偏置電壓傳送元件具有一第一端、一第二端與一第三端,該第一端耦接該第二主動元件的該第二端,該第二端耦接所述反相器的該第二偏置端,且該第三端耦接該第二緩衝器的該輸出端;以及N second bias voltage transmission elements, wherein each of the second bias voltage transmission elements has a first end, a second end and a third end, and the first end is coupled to the second active element. the second terminal, the second terminal is coupled to the second bias terminal of the inverter, and the third terminal is coupled to the output terminal of the second buffer; and
一第三緩衝器,其一輸入端耦接第N個所述反相器的輸出端,且以其一輸出端輸出一時鐘信號。A third buffer, one input end of which is coupled to the output end of the Nth inverter, and one output end of which outputs a clock signal.
在一實施例中,該第一主動負載為一二極體連接形式(Diode-connected)之P型MOSFET元件,且該第二主動負載為一二極體連接形式之N型MOSFET元件。In one embodiment, the first active load is a diode-connected P-type MOSFET device, and the second active load is a diode-connected N-type MOSFET device.
在一實施例中,該第一主動元件和所述第二偏置電壓傳送元件皆為一N型MOSFET元件,且該第二主動元件和所述第一偏置電壓傳送元件為一P型MOSFET元件。In one embodiment, both the first active element and the second bias voltage transmission element are N-type MOSFET elements, and the second active element and the first bias voltage transmission element are P-type MOSFETs element.
本發明同時提供一種資訊處理裝置,其具有至少一電子晶片,且該電子晶片包含如前所述本發明之環形振盪器電路。The present invention also provides an information processing device, which has at least one electronic chip, and the electronic chip includes the ring oscillator circuit of the present invention as mentioned above.
在一實施例中,該資訊處理裝置是選自於由智慧型電視、智慧型手機、智慧型手錶、智慧手環、平板電腦、桌上型電腦、工業電腦、筆記型電腦、一體式電腦、門禁裝置、指紋式打卡裝置、和電子式門鎖所組成群組之中的一種電子裝置。In one embodiment, the information processing device is selected from smart TVs, smart phones, smart watches, smart bracelets, tablet computers, desktop computers, industrial computers, notebook computers, all-in-one computers, An electronic device in the group consisting of access control devices, fingerprint punching devices, and electronic door locks.
為使 貴審查委員能進一步瞭解本發明之結構、特徵、目的、與其優點,茲附以圖式及較佳具體實施例之詳細說明如後。In order to enable your examiners to further understand the structure, features, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred specific embodiments are hereby attached.
圖2顯示本發明之一種環形振盪器電路的方塊圖。比較圖2與圖1之後可知,除了包括N個級聯的反相器131的一環形振盪器單元13之外,本發明之環形振盪器電路1還進一步包括:一啟動單元10、一第一偏置單元11以及一第二偏置單元12。本發明之環形振盪器電路1係應用於一電子晶片之中,利用該第一偏置單元11依據該電子晶片的電源電壓VDD而產生一第一偏置電壓Vbp與一第二偏置電壓Vbn,且利用該第二偏置單元12依據該電源電壓VDD以及所述第一偏置電壓Vbp而產生一第一工作電壓VH與一第二工作電壓VL,從而以所述第一工作電壓VH供電至該環形振盪器單元13的各所述反相器131的一第一偏置端(即,高電壓偏置端),且以所述第二工作電壓VL供電至該環形振盪器單元13的各所述反相器131的一第二偏置端(即,低電壓偏置端)。如此設計,係使各所述反相器131不由電子晶片的電源電壓VDD所偏置,因此由第N個反相器131所輸出的時鐘信號CLK的頻率不受電源電壓VDD與和溫度的影響,從而保持時鐘信號的頻率的穩定。FIG. 2 shows a block diagram of a ring oscillator circuit of the present invention. After comparing Fig. 2 with Fig. 1, it can be seen that, in addition to a
圖3顯示本發明之環形振盪器電路的第一電路拓樸圖。如圖2與圖3所示,該啟動單元10耦接該電源電壓V
DD和該接地端GND,且包括一第三P型MOSFET元件Mp3、一第三N型MOSFET元件Mn3、一第四P型MOSFET元件Mp4、一第四N型MOSFET元件Mn4、與一第五N型MOSFET元件Mn5。值得說明的是,所謂“第一”、“第二”、...、“第七”只是用以區別不同的N型MOSFET元件及/或P型MOSFET元件,並非用以表示元件的先後次序關係。依據本發明之設計,該第三P型MOSFET元件Mp3的源極端耦接該電源電壓VDD,且其閘極端透過一第一電阻R1而耦接該接地端GND。另一方面,該第三N型MOSFET元件Mn3的汲極端耦接該第三P型MOSFET元件Mp3的汲極端,且其源極端耦接該接地端GND。
FIG. 3 shows the first circuit topology of the ring oscillator circuit of the present invention. As shown in FIG. 2 and FIG. 3, the
承上述說明,該第四P型MOSFET元件Mp4的源極端耦接該電源電壓VDD。另一方面,該第四N型MOSFET元件Mn4的汲極端耦接該第四P型MOSFET元件Mp4的一汲極端,其源極端耦接該接地端GND,且其閘極端耦接該第三N型MOSFET元件Mn3的一閘極端。並且,該第四N型MOSFET元件Mn4的汲極端還耦接其閘極端。如圖3所示,該第五N型MOSFET元件Mn5的汲極端耦接該第四P型MOSFET元件Mp4的閘極端,其源極端耦接該接地端GND。並且,該第五N型MOSFET元件Mn5的閘極端還耦接該第三P型MOSFET元件Mp3的汲極端與該第三N型MOSFET元件Mn3的汲極端之間的一第一共接點N1。According to the above description, the source terminal of the fourth P-type MOSFET element Mp4 is coupled to the power supply voltage VDD. On the other hand, the drain terminal of the fourth N-type MOSFET element Mn4 is coupled to a drain terminal of the fourth P-type MOSFET element Mp4, its source terminal is coupled to the ground terminal GND, and its gate terminal is coupled to the third N-type MOSFET element Mp4. A gate terminal of the type MOSFET element Mn3. Moreover, the drain terminal of the fourth N-type MOSFET element Mn4 is also coupled to the gate terminal thereof. As shown in FIG. 3 , the drain terminal of the fifth N-type MOSFET element Mn5 is coupled to the gate terminal of the fourth P-type MOSFET element Mp4 , and the source terminal thereof is coupled to the ground terminal GND. Moreover, the gate terminal of the fifth N-type MOSFET element Mn5 is also coupled to a first common node N1 between the drain terminal of the third P-type MOSFET element Mp3 and the drain terminal of the third N-type MOSFET element Mn3 .
如圖2與圖3所示,該第一偏置單元11耦接電源電壓VDD和接地端GND,用以產生一第一偏置電壓Vbp與一第二偏置電壓Vbn,且包括:一第五P型MOSFET元件Mp5、一第六P型MOSFET元件Mp6、一運算放大器111、一第一BJT元件Q1、以及至少一第二BJT元件Q2。其中,該第五P型MOSFET元件Mp5的源極端耦接該電源電壓VDD。另一方面,該第六P型MOSFET元件Mp6的源極端耦接該電源電壓VDD,且其閘極端耦接該第五P型MOSFET元件Mp5的閘極端。並且,該第五N型MOSFET元件Mn5的汲極端與該第四P型MOSFET元件Mp4的閘極端之間的一第二共接點N2係耦接至該第六P型MOSFET元件Mp6的閘極端與該第五P型MOSFET元件Mp5的閘極端之間的一第三共接點N3。更詳細地說明,該運算放大器111具有一正輸入端、一負輸入端和一輸出端,並以其正輸入端耦接該第六P型MOSFET元件Mp6的汲極端,以其負輸入端耦接該第五P型MOSFET元件Mp5的汲極端,且以其輸出端同時耦接該第三共接點N3。如圖3所示,該第一BJT元件Q1的射極端耦接該運算放大器121的負輸入端,且其集極端與基極端皆耦接該接地端GND。依據本發明之設計,該第一BJT元件Q1和所述至少一第二BJT元件Q2之間具有一元件數量比,且該元件數量比為1:m。其中,各所述第二BJT元件Q2的射極端係透過一第二電阻R2耦接該第六P型MOSFET元件Mp6的汲極端,且其集極端與基極端皆耦接該接地端GND。As shown in FIG. 2 and FIG. 3 , the
如圖2與圖3所示,該第二偏置單元12耦接傳送自該第一偏置單元11的該第一偏置電壓Vbp、該電源電壓VDD和該接地端GND,用以產生一第一工作電壓VH與一第二工作電壓VL,且包括:一第一P型MOSFET元件Mp1、一第一N型MOSFET元件Mn1、一第二P型MOSFET元件Mp2、以及一第二N型MOSFET元件Mn2。其中,該第一P型MOSFET元件Mp1的源極端耦接該電源電壓VDD,且其閘極端耦接該第三共接點N3以接收所述第一偏置電壓Vbp。另一方面,該第一N型MOSFET元件Mn1的汲極端耦接該第一P型MOSFET元件Mp1的汲極端,且其源極端耦接該接地端GND。並且,該第一N型MOSFET元件Mn1的汲極端還耦接其閘極端。如圖3所示,該第二P型MOSFET元件Mp2的源極端耦接該電源電壓VDD,且其閘極端耦接該第三共接點N3以接收所述第一偏置電壓Vbp。另一方面,該第二N型MOSFET元件Mn2的汲極端耦接該第二P型MOSFET元件Mp2的汲極端,且其源極端耦接該接地端GND。並且,該第二N型MOSFET元件Mn2的該汲極端還耦接其閘極端。As shown in FIG. 2 and FIG. 3, the
如圖2與圖3所示,該環形振盪器單元13耦接傳送自該第一偏置單元11的該第二偏置電壓Vbn、傳送自該第二偏置單元12的該第一工作電壓VH以及該第二工作電壓VL、該電源電壓V
DD、與該接地端GND。除了N個級聯的反相器131以外,該環形振盪器單元13還包括:一第一緩衝器13H、一第二緩衝器13L、一第一主動負載Mp8、一第一主動元件Mn8、一第二主動負載Mn9、一第二主動元件Mp9、N個第一偏置電壓傳送元件(Mp10, Mp11, Mp12)、N個第二偏置電壓傳送元件(Mn10, Mn11, Mn12)、以及一第三緩衝器133。其中,所述第一偏置電壓傳送元件為一P型MOSFET元件,且所述第二偏置電壓傳送元件為一N型MOSFET元件。
As shown in FIG. 2 and FIG. 3 , the
依圖3所繪可知,N為大於或等於3的奇數,且第1個所述反相器131與第N個所述反相器111首尾級聯。依據本發明之設計,該第一緩衝器13H的輸入端耦接該第一N型MOSFET元件Mn1的該源極端以接收所述第一工作電壓VH,且以其輸出端輸出一第一緩衝工作電壓VH_buf。另一方面,該第二緩衝器13L的輸入端耦接該第二N型MOSFET元件Mn2的該源極端以接收所述第二工作電壓VL,且以其輸出端傳送一第二緩衝工作電壓VL_buf。更詳細地說明,該第一主動負載Mp8的第一端耦接該第一緩衝器13H的該輸出端。並且,該第一主動元件Mn8具有一第一端、一第二端與一第三端,其中該第一端耦接該第六N型MOSFET元件Mn6的該閘極端和所述第七N型MOSFET元件Mn7的該閘極端之間的一第四共接點N4,該第二端耦接該主動負載Mp8的一第二端,且該第三端耦接該接地端GND。另一方面,該第二主動負載Mn9的第一端耦接該第二緩衝器13L的該輸出端。同樣地,該第二主動元件Mp9具有一第一端、一第二端與一第三端,其中該第一端耦接該第三共接點N3,該第二端耦接該第二主動負載Mn9的第二端,且該第三端耦接該電源電壓VDD 。As can be seen from FIG. 3 , N is an odd number greater than or equal to 3, and the
承上述說明,N為大於或等於3的奇數。並且,各所述第一偏置電壓傳送元件具有一第一端、一第二端與一第三端,該第一端耦接該第一主動元件Mn8的第二端,該第二端耦接所述反相器131的第一偏置端(即,高電壓偏置端),且該第三端耦接該第一緩衝器13H的輸出端。同樣地,各所述第二偏置電壓傳送元件具有一第一端、一第二端與一第三端,該第一端耦接該第二主動元件Mp9的第二端,該第二端耦接所述反相器131的該第二偏置端(即,低電壓偏置端),且該第三端耦接該第二緩衝器13L的輸出端。並且,該第三緩衝器133的輸入端耦接第N個所述反相器111的輸出端,且以其一輸出端輸出一時鐘信號CLK。補充說明的是,如圖3所示,該第一主動負載Mp8為一二極體連接形式(Diode-connected)之P型MOSFET元件,且該第二主動負載Mn9亦為一二極體連接形式之N型MOSFET元件。另一方面,該第一主動元件Mn8為一N型MOSFET元件,且該第二主動元件Mp9亦為一P型MOSFET元件。According to the above description, N is an odd number greater than or equal to 3. Moreover, each of the first bias voltage transmission elements has a first end, a second end and a third end, the first end is coupled to the second end of the first active element Mn8, and the second end is coupled to connected to the first bias terminal (ie, high voltage bias terminal) of the
如圖3所示,本發明之環形振盪器電路1的具體工作原理為:電源電壓VDD上電之後,該第三P型MOSFET元件Mp3導通從而使該第五N型MOSFET元件Mn5導通。在導通後,該第五N型MOSFET元件Mn5的汲極端的電位被拉低,使該第五P型MOSFET元件Mp5和該第六P型MOSFET元件Mp6導通,從而完整啟動整個第一偏置單元11。接著,該第四P型MOSFET元件Mp4傳送一偏置電流給該第四N型MOSFET元件Mn4。由於該第四N型MOSFET元件Mn4與該第三N型MOSFET元件Mn3組成一電流鏡,因此該第三N型MOSFET元件Mn3依據該偏置電流而產生一汲極電流,且該汲極電流與該偏置電流的電流值相同。之後,由於該第五N型MOSFET元件Mn5的閘極端的電位被導通的第三N型MOSFET元件Mn3拉低,故使得該第五N型MOSFET元件Mn5關斷。在此情況下,該啟動單元10與該第一偏置單元11之間的電性連繫於是被切斷。As shown in FIG. 3 , the working principle of the
隨後,第七P型MOSFET元件Mp7鏡像第五P型MOSFET元件Mp5和第六P型MOSFET元件Mp6的元件電流並傳輸給第六N型MOSFET元件Mn6。同時,第一P型MOSFET元件Mp1/第二P型MOSFET元件Mp2鏡像第五P型MOSFET元件Mp5/第六P型MOSFET元件Mp6的元件電流並傳輸給第一N型MOSFET元件Mn1/第二N型MOSFET元件Mn2,使該第一N型MOSFET元件Mn1/第二N型MOSFET元件Mn2產生第一工作電壓VH/第二工作電壓VL。Subsequently, the seventh P-type MOSFET element Mp7 mirrors the element currents of the fifth P-type MOSFET element Mp5 and the sixth P-type MOSFET element Mp6 and transfers to the sixth N-type MOSFET element Mn6. At the same time, the first P-type MOSFET element Mp1/second P-type MOSFET element Mp2 mirrors the element current of the fifth P-type MOSFET element Mp5/sixth P-type MOSFET element Mp6 and transmits it to the first N-type MOSFET element Mn1/second N N-type MOSFET element Mn2, so that the first N-type MOSFET element Mn1/second N-type MOSFET element Mn2 generates the first working voltage VH/the second working voltage VL.
接著,該第一緩衝器13H/該第二緩衝器13L將第一工作電壓VH/第二工作電壓VL輸出為第一緩衝工作電壓VH_buf/第二緩衝工作電壓VL_buf。並且,該第一主動元件Mn8鏡像該第六N型MOSFET元件Mn6的元件電流給該第一主動負載Mp8,之後該第一主動負載Mp8再將電流鏡像給N個第一偏置電壓傳送元件(Mp10, Mp11, Mp12)並作為環振電路的“上拉”電流 。同時,該第二主動元件Mp9鏡像該第一偏置單元11的偏置電流並傳輸給第二主動負載Mn9,隨後N個第二偏置電壓傳送元件(Mn10, Mn11, Mn12)鏡像第二主動負載Mn9的電流並作為環形振盪器(即,N個級聯的反相器131)的“下拉”電流。最終,環形振盪器在上拉電流與下拉電流穩定之後進行穩定的周期振盪,從而輸出一時鐘信號CLK。並且,該時鐘信號CLK的頻率可利用下式(1)表示:
······················ (1)
Then, the
並且,該第一偏置單元11的偏置電流可利用下式(2)表示:
······································ (2)
And, the bias current of the
上式(2)中, 為第一BJT元件Q1/第二BJT元件Q2的基極端與射極端的電壓差,VT為熱電壓,m前述之元件數量比。並且,在該第一BJT元件Q1與該第二BJT元件Q2的數量皆為1的情況下,該第一BJT元件Q1和該第二BJT元件Q2之間具有一面積比,且該面積比亦為1:m。忽略第二電阻R2的溫度係數,偏置電流I為正溫度係數電流。換句話說,該時鐘信號CLK的頻率不受溫度係數漂移之影響。 In the above formula (2), is the voltage difference between the base terminal and the emitter terminal of the first BJT element Q1/the second BJT element Q2, VT is the thermal voltage, and m is the aforementioned element quantity ratio. Moreover, in the case where the numbers of the first BJT element Q1 and the second BJT element Q2 are both 1, there is an area ratio between the first BJT element Q1 and the second BJT element Q2, and the area ratio is also is 1:m. Neglecting the temperature coefficient of the second resistor R2, the bias current I is a positive temperature coefficient current. In other words, the frequency of the clock signal CLK is not affected by temperature coefficient drift.
另一方面,在亞閾狀態工作時,MOSFET元件的Vgs可以利用下式(3)表示: ······························ (3) On the other hand, when working in the subthreshold state, the Vgs of the MOSFET element can be expressed by the following formula (3): ····························(3)
上式(3)中,為W和L分別為MOSFET元件的元件寬度和長度,Vth為臨界電壓,n為製程參數,I 0為單位面積擴散電流。令該第一P型MOSFET元件Mp1和該第二P型MOSFET元件Mp2具有相同的寬長比,且令該第一P型MOSFET元件Mp1和該第二P型MOSFET元件Mp2之間的一元件數量比為α/1。如此,則上式(1)之中的VH_buf-VL_buf可利用下式(4)表示: ················ (4) In the above formula (3), W and L are the element width and length of the MOSFET element respectively, Vth is the critical voltage, n is the process parameter, and I 0 is the diffusion current per unit area. Make the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 have the same aspect ratio, and make an element number between the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 The ratio is α/1. In this way, VH_buf-VL_buf in the above formula (1) can be expressed by the following formula (4): ················(4)
因此,上式(1)可以改寫為下式(1.1)表示: ··································· (1.1) Therefore, the above formula (1) can be rewritten as the following formula (1.1):・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ (1.1)
由上式(1.1)可知,該時鐘信號CLK的頻率不受溫度漂移以及電源電壓VDD漂移之影響。It can be known from the above formula (1.1) that the frequency of the clock signal CLK is not affected by temperature drift and power voltage VDD drift.
圖4顯示本發明之環形振盪器電路的第二電路拓樸圖。比較圖4與圖3可知,在第二電路拓樸結構之中,用以產生一第一偏置電壓Vbp與一第二偏置電壓Vbn的該第一偏置單元11係包括:一第五P型MOSFET元件Mp5、一第六N型MOSFET元件Mn6、一第六P型MOSFET元件Mp6、以及至少一第七N型MOSFET元件Mn7。其中,該第六N型MOSFET元件Mn6的汲極端耦接該第五P型MOSFET元件Mp5的汲極端,其源極端耦接該接地端GND,且其閘極端耦接其所述汲極端。另一方面,該第六P型MOSFET元件Mp6的源極端耦接該電源電壓VDD,其閘極端耦接該第五P型MOSFET元件Mp5的閘極端。並且,該第五N型MOSFET元件Mn5的汲極端與該第四P型MOSFET元件Mp4的閘極端之間的一第二共接點N2係耦接至該第六P型MOSFET元件Mp6的閘極端與該第五P型MOSFET元件Mp5的閘極端之間的一第三共接點N3,且該第六P型MOSFET元件Mp6的汲極端耦接該第三共接點N3。如圖4所示,依據本發明之設計,該第六N型MOSFET元件Mn6和所述至少一第七N型MOSFET元件Mn7之間具有一元件數量比,且該元件數量比為1:m。其中,各所述第七N型MOSFET元件Mn7的汲極端耦接該第六P型MOSFET元件Mp6的該汲極端,且其源極端透過一第二電阻R2而耦接該接地端GND。並且,各所述第七N型MOSFET元件Mn7的閘極端耦接該第六N型MOSFET元件Mn6的該閘極端。FIG. 4 shows a second circuit topology of the ring oscillator circuit of the present invention. 4 and FIG. 3, in the second circuit topology, the
依圖4之電路設計,該第一偏置單元11的偏置電流可利用下式(2.1)表示:
·································· (2.a)
According to the circuit design of FIG. 4, the bias current of the
上式(2.1)中,k=μCox為MOSFET元件的製程跨導參數(process transconductance parameter),且m為第六N型MOSFET元件Mn6和所述至少一第七N型MOSFET元件Mn7之間的一數量比。並且,在該第六N型MOSFET元件Mn6和該第七N型MOSFET元件Mn7的數量皆為1的情況下,該第六N型MOSFET元件Mn6和該第七N型MOSFET元件Mn7之間具有一面積比,且該面積比亦為1:m。忽略第二電阻R2的溫度係數,則上式(2.1)可以改寫為下式(2.b)。 …………………(2.b) In the above formula (2.1), k=μCox is a process transconductance parameter (process transconductance parameter) of the MOSFET element, and m is a sixth N-type MOSFET element Mn6 and the at least one seventh N-type MOSFET element Mn7. quantity ratio. Moreover, when the number of the sixth N-type MOSFET element Mn6 and the number of the seventh N-type MOSFET element Mn7 are both 1, there is a gap between the sixth N-type MOSFET element Mn6 and the seventh N-type MOSFET element Mn7. area ratio, and the area ratio is also 1:m. Neglecting the temperature coefficient of the second resistor R2, the above formula (2.1) can be rewritten as the following formula (2.b). ………………(2.b)
上式(2.2)中,I 0為與溫度無關的常數,因此偏置電流I的大小僅與MOSFET元件的製程跨導參數有關。在亞閾狀態工作時,MOSFET元件的Vgs可以利用下式(3.a)表示: ······································· (3.a) In the above formula (2.2), I 0 is a constant that has nothing to do with temperature, so the magnitude of the bias current I is only related to the process transconductance parameters of MOSFET components. When working in the subthreshold state, the Vgs of the MOSFET element can be expressed by the following formula (3.a):・・・・・・・・・・・・・・・・・・・・・・・・・・・・ (3.a)
如此,則上式(1)之中的VH_buf-VL_buf可利用下式(5)表示: ···································· (5) In this way, VH_buf-VL_buf in the above formula (1) can be expressed by the following formula (5): ·································(5)
因此,上式(1)可以改寫為下式(1.a)表示: ··································· (1.a) Therefore, the above formula (1) can be rewritten as the following formula (1.a): ·······························(1.a)
令該第一P型MOSFET元件Mp1和該第二P型MOSFET元件Mp2具有相同的寬長比,且令該第一P型MOSFET元件Mp1和該第二P型MOSFET元件Mp2之間的一元件數量比為λ/1。如此,則上式(5)之中的VH_buf-VL_buf可利用下式(5.a)表示: ································· (5.a) Make the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 have the same aspect ratio, and make an element number between the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 The ratio is λ/1. In this way, VH_buf-VL_buf in the above formula (5) can be expressed by the following formula (5.a): ·····························(5.a)
最終,上式(1.a)可以改寫為下式(1.b)表示: ·································· (1.b) Finally, the above formula (1.a) can be rewritten as the following formula (1.b): ······························(1.b)
由上式(1.b)可知,該時鐘信號CLK的頻率不受溫度漂移以及電源電壓VDD漂移之影響。It can be known from the above formula (1.b) that the frequency of the clock signal CLK is not affected by temperature drift and power supply voltage VDD drift.
實驗例Experimental example
在實驗例中,電源電壓VDD為3.3V。並且, MOSFET元件的基礎參數分別為:W Mp3/L Mp3=1/20μm、W Mn5/L Mn5=0.4/20μm 、W Mp1/L Mp1=8/3μm、W Mp2/L Mp2=8/3μm、W Mp4/L Mp4=8/3μm、W Mp5/L Mp5=8/3μm、W Mp6/L Mp6=8/3μm、W Mp7/L Mp7=8/3μm、W Mp8/L Mp8=8/3μm、W Mp9/L Mp9=8/3μm、W Mp10/L Mp10=8/3μm、W Mp11/L Mp11=8/3μm、W Mp12/L Mp12=8/3μm、W Mn1/L Mn1=2/3μm、W Mn2/L Mn2=2/3μm、W Mn3/L Mn3=4/2μm、W Mn4/L Mn4=4/2μm、W Mn6/L Mn6=4/2μm、W Mn8/L Mn8=4/2μm、W Mn9/L Mn9=4/2μm、W Mn10/L Mn10=4/2μm、W Mn11/L Mn11=4/2μm、W Mn12/L Mn12=4/2μm。並且,R1=1kΩ、R2=30kΩ、該第一P型MOSFET元件Mp1和該第二P型MOSFET元件Mp2之間的元件數量比為20/6,且該第一BJT元件Q1和該第二BJT元件Q2之間的元件數量比為1/8。 In the experimental example, the power supply voltage VDD is 3.3V. Moreover, the basic parameters of MOSFET elements are: W Mp3 /L Mp3 = 1/20μm, W Mn5 /L Mn5 = 0.4/20μm, W Mp1 /L Mp1 = 8/3μm, W Mp2 /L Mp2 = 8/3μm, W Mp4 /L Mp4 = 8/3 μm, W Mp5 /L Mp5 = 8/3 μm, W Mp6 /L Mp6 = 8/3 μm, W Mp7 /L Mp7 = 8/3 μm, W Mp8 /L Mp8 = 8/3 μm, W Mp9 /L Mp9 = 8/3 μm, W Mp10 /L Mp10 = 8/3 μm, W Mp11 /L Mp11 = 8/3 μm, W Mp12 /L Mp12 = 8/3 μm, W Mn1 /L Mn1 = 2/3 μm, W Mn2 /L Mn2 = 2/3 μm, W Mn3 /L Mn3 = 4/2 μm, W Mn4 /L Mn4 = 4/2 μm, W Mn6 /L Mn6 = 4/2 μm, W Mn8 /L Mn8 = 4/2 μm, W Mn9 /L Mn9 =4/2 μm, W Mn10 /L Mn10 =4/2 μm, W Mn11 /L Mn11 =4/2 μm, W Mn12 /L Mn12 =4/2 μm. In addition, R1=1kΩ, R2=30kΩ, the ratio of the number of elements between the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 is 20/6, and the first BJT element Q1 and the second BJT The element number ratio among the elements Q2 is 1/8.
本發明之環形振盪器電路1的實驗例所輸出的時鐘信號CLK的工作頻率f
CLK可利用上式(1.1)計算獲得。電路模擬得到輸出頻率f約為80MHz(不同工藝角通過調節電阻阻值使得輸出頻率接近80Mhz),圖5為本發明之環形振盪器電路在不同工藝角條件下的溫漂曲線,且圖6為本發明之環形振盪器電路在不同工藝角條件下的電源漂移曲線。並且,下表(1)整理了不同工藝角和不同溫度條件之頻率,且表(2)整理了不同工藝角和不同電源電壓之頻率。從結果中可以看出,本發明之環形振盪器電路在不同工藝角下,-40°C到120°C的溫度變化所導致的溫漂係數<±1.99%,其中TT工藝角下<±1.02%。另一方面,電源變化±10%所引起的頻率漂移係數在各個工藝角下均<±0.07%。
The operating frequency f CLK of the clock signal CLK output by the experimental example of the
表(1)
表(2)
如此,上述完整且清楚地說明本發明之一種環形振盪器電路;並且,經由上述可得知本發明具有下列優點:Thus, the above-mentioned complete and clearly illustrates a ring oscillator circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:
(1)本發明揭示一種環形振盪器電路,其基礎上包含一第一偏置單元、一第二偏置單元以及一環形振盪器單元,其中該第一偏置單元依據一電源電壓產生一第一偏置電壓與一第二偏置電壓,且該第二偏置單元依據該電源電壓以及所述第一偏置電壓而產生一第一工作電壓與一第二工作電壓。並且,該環形振盪器單元耦接該電源電壓與該接地端,且同時耦接傳送自該第一偏置單元的該第二偏置電壓以及傳送自該第二偏置單元的該第一工作電壓和該第二工作電壓。依據本發明之設計,該環形振盪器單元包括N個級聯的反相器,且所述第一工作電壓供電至各所述反相器的一第一偏置端,而所述第二工作電壓則供電至各所述反相器的一第二偏置端。如此設計,各所述反相器不由電子晶片的電源電壓所偏置,因此由第N個反相器所輸出的時鐘信號的頻率不受電源電壓和溫度的影響,從而保持時鐘信號的頻率的穩定。(1) The present invention discloses a ring oscillator circuit, which basically includes a first bias unit, a second bias unit and a ring oscillator unit, wherein the first bias unit generates a first bias unit according to a power supply voltage A bias voltage and a second bias voltage, and the second bias unit generates a first operating voltage and a second operating voltage according to the power supply voltage and the first bias voltage. In addition, the ring oscillator unit is coupled to the power supply voltage and the ground terminal, and is simultaneously coupled to the second bias voltage transmitted from the first bias unit and the first working voltage transmitted from the second bias unit. voltage and the second operating voltage. According to the design of the present invention, the ring oscillator unit includes N cascaded inverters, and the first operating voltage supplies power to a first bias terminal of each of the inverters, and the second operating voltage The voltage is then supplied to a second bias terminal of each of the inverters. Designed in this way, each of the inverters is not biased by the power supply voltage of the electronic chip, so the frequency of the clock signal output by the Nth inverter is not affected by the power supply voltage and temperature, thereby maintaining the frequency of the clock signal. Stablize.
(2)本發明同時提供一種資訊處理裝置,其具有至少一電子晶片,且該電子晶片包含如前所述本發明之環形振盪器電路。並且,該資訊處理裝置是選自於由智慧型電視、智慧型手機、智慧型手錶、智慧手環、平板電腦、桌上型電腦、工業電腦、筆記型電腦、一體式電腦、門禁裝置、指紋式打卡裝置、和電子式門鎖所組成群組之中的一種電子裝置。(2) The present invention also provides an information processing device, which has at least one electronic chip, and the electronic chip includes the ring oscillator circuit of the present invention as described above. Moreover, the information processing device is selected from smart TVs, smart phones, smart watches, smart bracelets, tablet computers, desktop computers, industrial computers, notebook computers, all-in-one computers, access control devices, fingerprint A type of electronic device in the group consisting of a card punching device and an electronic door lock.
必須加以強調的是,前述本案所揭示者乃為較佳實施例,舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者,俱不脫本案之專利權範疇。It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment, and all partial changes or modifications derived from the technical ideas of this case and easily deduced by those familiar with the technology are all inseparable from the patent of this case. category of rights.
綜上所陳,本案無論目的、手段與功效,皆顯示其迥異於習知技術,且其首先發明合於實用,確實符合發明之專利要件,懇請 貴審查委員明察,並早日賜予專利俾嘉惠社會,是為至禱。To sum up, the purpose, means and efficacy of this case all show that it is very different from the conventional technology, and its first invention is practical, and indeed meets the patent requirements of the invention. I implore your review committee to be aware and grant a patent as soon as possible to benefit you. Society is for the Most Prayer.
1a:環形振盪器電路
11a:反相器
111a:P型MOSFET元件
112a:N型MOSFET元件
1:環形振盪器電路
10:啟動單元
11:第一偏置單元
111:運算放大器
12:第二偏置單元
13:環形振盪器單元
131:反相器
13H:第一緩衝器
13L:第二緩衝器
133:第三緩衝器
Mp1:第一P型MOSFET元件
Mn1:第一N型MOSFET元件
Mp2:第二P型MOSFET元件
Mn2:第二N型MOSFET元件
Mp3:第三P型MOSFET元件
Mn3:第三N型MOSFET元件
Mp4:第四P型MOSFET元件
Mn4:第四N型MOSFET元件
Mp5:第五P型MOSFET元件
Mn5:第五N型MOSFET元件
Mp6:第六P型MOSFET元件
Mn6:第六N型MOSFET元件
Mp7:第七P型MOSFET元件
Mn7:第七N型MOSFET元件
Mp8:第一主動負載
Mn8:第一主動元件
Mp9:第二主動元件
Mn9:第二主動負載
Mp10、Mp11、Mp12:第一偏置電壓傳送元件
Mn10、Mn11、Mn12:第二偏置電壓傳送元件
Q1:第一BJT元件
Q2:第二BJT元件
1a:
圖1為習知的一種環形振盪器電路的電路拓樸圖; 圖2為本發明之一種環形振盪器電路的方塊圖; 圖3為本發明之環形振盪器電路的第一電路拓樸圖; 圖4為本發明之環形振盪器電路的第二電路拓樸圖; 圖5為本發明之環形振盪器電路在不同工藝角條件下的溫漂曲線;以及 圖6為本發明之環形振盪器電路在不同工藝角條件下的電源漂移曲線。 Fig. 1 is the circuit topology diagram of a known ring oscillator circuit; Fig. 2 is the block diagram of a kind of ring oscillator circuit of the present invention; Fig. 3 is the first circuit topology diagram of the ring oscillator circuit of the present invention; Fig. 4 is the second circuit topology diagram of the ring oscillator circuit of the present invention; Fig. 5 is the temperature drift curve of the ring oscillator circuit of the present invention under different process angle conditions; and FIG. 6 is a power supply drift curve of the ring oscillator circuit of the present invention under different process corner conditions.
1:環形振盪器電路 1: Ring Oscillator Circuit
10:啟動單元 10:Start the unit
11:第一偏置單元 11: The first bias unit
12:第二偏置單元 12: Second bias unit
13:環形振盪器單元 13: Ring oscillator unit
131:反相器 131: Inverter
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US20200044627A1 (en) * | 2018-08-02 | 2020-02-06 | Nxp Usa, Inc. | Fd-soi device calibration circuit and method therefor |
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